drivers/soc/mediatek/mtk-mmsys.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __SOC_MEDIATEK_MTK_MMSYS_H
   4 #define __SOC_MEDIATEK_MTK_MMSYS_H
   5
   6 #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN       0x040
   7 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN       0x044
   8 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN         0x048
   9 #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN      0x04c
  10 #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN       0x050
  11 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN      0x084
  12 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN      0x088
  13 #define DISP_REG_CONFIG_DSIE_SEL_IN             0x0a4
  14 #define DISP_REG_CONFIG_DSIO_SEL_IN             0x0a8
  15 #define DISP_REG_CONFIG_DPI_SEL_IN              0x0ac
  16 #define DISP_REG_CONFIG_DISP_RDMA2_SOUT         0x0b8
  17 #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN      0x0c4
  18 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN      0x0c8
  19 #define DISP_REG_CONFIG_MMSYS_CG_CON0           0x100
  20
  21 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN        0x030
  22 #define DISP_REG_CONFIG_OUT_SEL                 0x04c
  23 #define DISP_REG_CONFIG_DSI_SEL                 0x050
  24 #define DISP_REG_CONFIG_DPI_SEL                 0x064
  25
  26 #define OVL0_MOUT_EN_COLOR0                     0x1
  27 #define OD_MOUT_EN_RDMA0                        0x1
  28 #define OD1_MOUT_EN_RDMA1                       BIT(16)
  29 #define UFOE_MOUT_EN_DSI0                       0x1
  30 #define COLOR0_SEL_IN_OVL0                      0x1
  31 #define OVL1_MOUT_EN_COLOR1                     0x1
  32 #define GAMMA_MOUT_EN_RDMA1                     0x1
  33 #define RDMA0_SOUT_DPI0                         0x2
  34 #define RDMA0_SOUT_DPI1                         0x3
  35 #define RDMA0_SOUT_DSI1                         0x1
  36 #define RDMA0_SOUT_DSI2                         0x4
  37 #define RDMA0_SOUT_DSI3                         0x5
  38 #define RDMA1_SOUT_DPI0                         0x2
  39 #define RDMA1_SOUT_DPI1                         0x3
  40 #define RDMA1_SOUT_DSI1                         0x1
  41 #define RDMA1_SOUT_DSI2                         0x4
  42 #define RDMA1_SOUT_DSI3                         0x5
  43 #define RDMA2_SOUT_DPI0                         0x2
  44 #define RDMA2_SOUT_DPI1                         0x3
  45 #define RDMA2_SOUT_DSI1                         0x1
  46 #define RDMA2_SOUT_DSI2                         0x4
  47 #define RDMA2_SOUT_DSI3                         0x5
  48 #define DPI0_SEL_IN_RDMA1                       0x1
  49 #define DPI0_SEL_IN_RDMA2                       0x3
  50 #define DPI1_SEL_IN_RDMA1                       (0x1 << 8)
  51 #define DPI1_SEL_IN_RDMA2                       (0x3 << 8)
  52 #define DSI0_SEL_IN_RDMA1                       0x1
  53 #define DSI0_SEL_IN_RDMA2                       0x4
  54 #define DSI1_SEL_IN_RDMA1                       0x1
  55 #define DSI1_SEL_IN_RDMA2                       0x4
  56 #define DSI2_SEL_IN_RDMA1                       (0x1 << 16)
  57 #define DSI2_SEL_IN_RDMA2                       (0x4 << 16)
  58 #define DSI3_SEL_IN_RDMA1                       (0x1 << 16)
  59 #define DSI3_SEL_IN_RDMA2                       (0x4 << 16)
  60 #define COLOR1_SEL_IN_OVL1                      0x1
  61
  62 #define OVL_MOUT_EN_RDMA                        0x1
  63 #define BLS_TO_DSI_RDMA1_TO_DPI1                0x8
  64 #define BLS_TO_DPI_RDMA1_TO_DSI                 0x2
  65 #define DSI_SEL_IN_BLS                          0x0
  66 #define DPI_SEL_IN_BLS                          0x0
  67 #define DSI_SEL_IN_RDMA                         0x1
  68
  69 struct mtk_mmsys_routes {
  70         u32 from_comp;
  71         u32 to_comp;
  72         u32 addr;
  73         u32 val;
  74 };
  75
  76 struct mtk_mmsys_driver_data {
  77         const char *clk_driver;
  78         const struct mtk_mmsys_routes *routes;
  79         const unsigned int num_routes;
  80 };
  81
  82 /*
  83  * Routes in mt8173, mt2701, mt2712 are different. That means
  84  * in the same register address, it controls different input/output
  85  * selection for each SoC. But, right now, they use the same table as
  86  * default routes meet their requirements. But we don't have the complete
  87  * route information for these three SoC, so just keep them in the same
  88  * table. After we've more information, we could separate mt2701, mt2712
  89  * to an independent table.
  90  */
  91 static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
  92         {
  93                 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
  94                 DISP_REG_CONFIG_OUT_SEL, BLS_TO_DSI_RDMA1_TO_DPI1
  95         }, {
  96                 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
  97                 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_BLS
  98         }, {
  99                 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
 100                 DISP_REG_CONFIG_OUT_SEL, BLS_TO_DPI_RDMA1_TO_DSI
 101         }, {
 102                 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
 103                 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_RDMA
 104         }, {
 105                 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
 106                 DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_BLS
 107         }, {
 108                 DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
 109                 DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1
 110         }, {
 111                 DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
 112                 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0
 113         }, {
 114                 DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
 115                 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1
 116         }, {
 117                 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
 118                 DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0
 119         }, {
 120                 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
 121                 DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0
 122         }, {
 123                 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
 124                 DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA
 125         }, {
 126                 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
 127                 DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1
 128         }, {
 129                 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
 130                 DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1
 131         }, {
 132                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
 133                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI0
 134         }, {
 135                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
 136                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI1
 137         }, {
 138                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
 139                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI1
 140         }, {
 141                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
 142                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI2
 143         }, {
 144                 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
 145                 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI3
 146         }, {
 147                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
 148                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI0
 149         }, {
 150                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
 151                 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA1
 152         }, {
 153                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
 154                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI1
 155         }, {
 156                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
 157                 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA1
 158         }, {
 159                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
 160                 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA1
 161         }, {
 162                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
 163                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI1
 164         }, {
 165                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
 166                 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA1
 167         }, {
 168                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
 169                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI2
 170         }, {
 171                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
 172                 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA1
 173         }, {
 174                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
 175                 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI3
 176         }, {
 177                 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
 178                 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA1
 179         }, {
 180                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
 181                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI0
 182         }, {
 183                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
 184                 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA2
 185         }, {
 186                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
 187                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI1
 188         }, {
 189                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
 190                 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA2
 191         }, {
 192                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
 193                 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA2
 194         }, {
 195                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
 196                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI1
 197         }, {
 198                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
 199                 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA2
 200         }, {
 201                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
 202                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI2
 203         }, {
 204                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
 205                 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA2
 206         }, {
 207                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
 208                 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI3
 209         }, {
 210                 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
 211                 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA2
 212         }
 213 };
 214
 215 #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */