drivers/scsi/ufs/ufs.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Universal Flash Storage Host controller driver
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  *
   6  * Authors:
   7  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   8  *      Vinayak Holikatti <h.vinayak@samsung.com>
   9  */
  10
  11 #ifndef _UFS_H
  12 #define _UFS_H
  13
  14 #include <linux/mutex.h>
  15 #include <linux/types.h>
  16 #include <uapi/scsi/scsi_bsg_ufs.h>
  17
  18 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
  19 #define QUERY_DESC_MAX_SIZE       255
  20 #define QUERY_DESC_MIN_SIZE       2
  21 #define QUERY_DESC_HDR_SIZE       2
  22 #define QUERY_OSF_SIZE            (GENERAL_UPIU_REQUEST_SIZE - \
  23                                         (sizeof(struct utp_upiu_header)))
  24 #define UFS_SENSE_SIZE  18
  25
  26 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
  27                         cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
  28                          (byte1 << 8) | (byte0))
  29 /*
  30  * UFS device may have standard LUs and LUN id could be from 0x00 to
  31  * 0x7F. Standard LUs use "Peripheral Device Addressing Format".
  32  * UFS device may also have the Well Known LUs (also referred as W-LU)
  33  * which again could be from 0x00 to 0x7F. For W-LUs, device only use
  34  * the "Extended Addressing Format" which means the W-LUNs would be
  35  * from 0xc100 (SCSI_W_LUN_BASE) onwards.
  36  * This means max. LUN number reported from UFS device could be 0xC17F.
  37  */
  38 #define UFS_UPIU_MAX_UNIT_NUM_ID        0x7F
  39 #define UFS_MAX_LUNS            (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
  40 #define UFS_UPIU_WLUN_ID        (1 << 7)
  41 #define UFS_RPMB_UNIT           0xC4
  42
  43 /* WriteBooster buffer is available only for the logical unit from 0 to 7 */
  44 #define UFS_UPIU_MAX_WB_LUN_ID  8
  45
  46 /* Well known logical unit id in LUN field of UPIU */
  47 enum {
  48         UFS_UPIU_REPORT_LUNS_WLUN       = 0x81,
  49         UFS_UPIU_UFS_DEVICE_WLUN        = 0xD0,
  50         UFS_UPIU_BOOT_WLUN              = 0xB0,
  51         UFS_UPIU_RPMB_WLUN              = 0xC4,
  52 };
  53
  54 /*
  55  * UFS Protocol Information Unit related definitions
  56  */
  57
  58 /* Task management functions */
  59 enum {
  60         UFS_ABORT_TASK          = 0x01,
  61         UFS_ABORT_TASK_SET      = 0x02,
  62         UFS_CLEAR_TASK_SET      = 0x04,
  63         UFS_LOGICAL_RESET       = 0x08,
  64         UFS_QUERY_TASK          = 0x80,
  65         UFS_QUERY_TASK_SET      = 0x81,
  66 };
  67
  68 /* UTP UPIU Transaction Codes Initiator to Target */
  69 enum {
  70         UPIU_TRANSACTION_NOP_OUT        = 0x00,
  71         UPIU_TRANSACTION_COMMAND        = 0x01,
  72         UPIU_TRANSACTION_DATA_OUT       = 0x02,
  73         UPIU_TRANSACTION_TASK_REQ       = 0x04,
  74         UPIU_TRANSACTION_QUERY_REQ      = 0x16,
  75 };
  76
  77 /* UTP UPIU Transaction Codes Target to Initiator */
  78 enum {
  79         UPIU_TRANSACTION_NOP_IN         = 0x20,
  80         UPIU_TRANSACTION_RESPONSE       = 0x21,
  81         UPIU_TRANSACTION_DATA_IN        = 0x22,
  82         UPIU_TRANSACTION_TASK_RSP       = 0x24,
  83         UPIU_TRANSACTION_READY_XFER     = 0x31,
  84         UPIU_TRANSACTION_QUERY_RSP      = 0x36,
  85         UPIU_TRANSACTION_REJECT_UPIU    = 0x3F,
  86 };
  87
  88 /* UPIU Read/Write flags */
  89 enum {
  90         UPIU_CMD_FLAGS_NONE     = 0x00,
  91         UPIU_CMD_FLAGS_WRITE    = 0x20,
  92         UPIU_CMD_FLAGS_READ     = 0x40,
  93 };
  94
  95 /* UPIU Task Attributes */
  96 enum {
  97         UPIU_TASK_ATTR_SIMPLE   = 0x00,
  98         UPIU_TASK_ATTR_ORDERED  = 0x01,
  99         UPIU_TASK_ATTR_HEADQ    = 0x02,
 100         UPIU_TASK_ATTR_ACA      = 0x03,
 101 };
 102
 103 /* UPIU Query request function */
 104 enum {
 105         UPIU_QUERY_FUNC_STANDARD_READ_REQUEST           = 0x01,
 106         UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST          = 0x81,
 107 };
 108
 109 /* Flag idn for Query Requests*/
 110 enum flag_idn {
 111         QUERY_FLAG_IDN_FDEVICEINIT                      = 0x01,
 112         QUERY_FLAG_IDN_PERMANENT_WPE                    = 0x02,
 113         QUERY_FLAG_IDN_PWR_ON_WPE                       = 0x03,
 114         QUERY_FLAG_IDN_BKOPS_EN                         = 0x04,
 115         QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE            = 0x05,
 116         QUERY_FLAG_IDN_PURGE_ENABLE                     = 0x06,
 117         QUERY_FLAG_IDN_RESERVED2                        = 0x07,
 118         QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL              = 0x08,
 119         QUERY_FLAG_IDN_BUSY_RTC                         = 0x09,
 120         QUERY_FLAG_IDN_RESERVED3                        = 0x0A,
 121         QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE    = 0x0B,
 122         QUERY_FLAG_IDN_WB_EN                            = 0x0E,
 123         QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN                 = 0x0F,
 124         QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8     = 0x10,
 125 };
 126
 127 /* Attribute idn for Query requests */
 128 enum attr_idn {
 129         QUERY_ATTR_IDN_BOOT_LU_EN               = 0x00,
 130         QUERY_ATTR_IDN_RESERVED                 = 0x01,
 131         QUERY_ATTR_IDN_POWER_MODE               = 0x02,
 132         QUERY_ATTR_IDN_ACTIVE_ICC_LVL           = 0x03,
 133         QUERY_ATTR_IDN_OOO_DATA_EN              = 0x04,
 134         QUERY_ATTR_IDN_BKOPS_STATUS             = 0x05,
 135         QUERY_ATTR_IDN_PURGE_STATUS             = 0x06,
 136         QUERY_ATTR_IDN_MAX_DATA_IN              = 0x07,
 137         QUERY_ATTR_IDN_MAX_DATA_OUT             = 0x08,
 138         QUERY_ATTR_IDN_DYN_CAP_NEEDED           = 0x09,
 139         QUERY_ATTR_IDN_REF_CLK_FREQ             = 0x0A,
 140         QUERY_ATTR_IDN_CONF_DESC_LOCK           = 0x0B,
 141         QUERY_ATTR_IDN_MAX_NUM_OF_RTT           = 0x0C,
 142         QUERY_ATTR_IDN_EE_CONTROL               = 0x0D,
 143         QUERY_ATTR_IDN_EE_STATUS                = 0x0E,
 144         QUERY_ATTR_IDN_SECONDS_PASSED           = 0x0F,
 145         QUERY_ATTR_IDN_CNTX_CONF                = 0x10,
 146         QUERY_ATTR_IDN_CORR_PRG_BLK_NUM         = 0x11,
 147         QUERY_ATTR_IDN_RESERVED2                = 0x12,
 148         QUERY_ATTR_IDN_RESERVED3                = 0x13,
 149         QUERY_ATTR_IDN_FFU_STATUS               = 0x14,
 150         QUERY_ATTR_IDN_PSA_STATE                = 0x15,
 151         QUERY_ATTR_IDN_PSA_DATA_SIZE            = 0x16,
 152         QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
 153         QUERY_ATTR_IDN_WB_FLUSH_STATUS          = 0x1C,
 154         QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE       = 0x1D,
 155         QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST    = 0x1E,
 156         QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE        = 0x1F,
 157 };
 158
 159 /* Descriptor idn for Query requests */
 160 enum desc_idn {
 161         QUERY_DESC_IDN_DEVICE           = 0x0,
 162         QUERY_DESC_IDN_CONFIGURATION    = 0x1,
 163         QUERY_DESC_IDN_UNIT             = 0x2,
 164         QUERY_DESC_IDN_RFU_0            = 0x3,
 165         QUERY_DESC_IDN_INTERCONNECT     = 0x4,
 166         QUERY_DESC_IDN_STRING           = 0x5,
 167         QUERY_DESC_IDN_RFU_1            = 0x6,
 168         QUERY_DESC_IDN_GEOMETRY         = 0x7,
 169         QUERY_DESC_IDN_POWER            = 0x8,
 170         QUERY_DESC_IDN_HEALTH           = 0x9,
 171         QUERY_DESC_IDN_MAX,
 172 };
 173
 174 enum desc_header_offset {
 175         QUERY_DESC_LENGTH_OFFSET        = 0x00,
 176         QUERY_DESC_DESC_TYPE_OFFSET     = 0x01,
 177 };
 178
 179 /* Unit descriptor parameters offsets in bytes*/
 180 enum unit_desc_param {
 181         UNIT_DESC_PARAM_LEN                     = 0x0,
 182         UNIT_DESC_PARAM_TYPE                    = 0x1,
 183         UNIT_DESC_PARAM_UNIT_INDEX              = 0x2,
 184         UNIT_DESC_PARAM_LU_ENABLE               = 0x3,
 185         UNIT_DESC_PARAM_BOOT_LUN_ID             = 0x4,
 186         UNIT_DESC_PARAM_LU_WR_PROTECT           = 0x5,
 187         UNIT_DESC_PARAM_LU_Q_DEPTH              = 0x6,
 188         UNIT_DESC_PARAM_PSA_SENSITIVE           = 0x7,
 189         UNIT_DESC_PARAM_MEM_TYPE                = 0x8,
 190         UNIT_DESC_PARAM_DATA_RELIABILITY        = 0x9,
 191         UNIT_DESC_PARAM_LOGICAL_BLK_SIZE        = 0xA,
 192         UNIT_DESC_PARAM_LOGICAL_BLK_COUNT       = 0xB,
 193         UNIT_DESC_PARAM_ERASE_BLK_SIZE          = 0x13,
 194         UNIT_DESC_PARAM_PROVISIONING_TYPE       = 0x17,
 195         UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT        = 0x18,
 196         UNIT_DESC_PARAM_CTX_CAPABILITIES        = 0x20,
 197         UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1      = 0x22,
 198         UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS      = 0x29,
 199 };
 200
 201 /* Device descriptor parameters offsets in bytes*/
 202 enum device_desc_param {
 203         DEVICE_DESC_PARAM_LEN                   = 0x0,
 204         DEVICE_DESC_PARAM_TYPE                  = 0x1,
 205         DEVICE_DESC_PARAM_DEVICE_TYPE           = 0x2,
 206         DEVICE_DESC_PARAM_DEVICE_CLASS          = 0x3,
 207         DEVICE_DESC_PARAM_DEVICE_SUB_CLASS      = 0x4,
 208         DEVICE_DESC_PARAM_PRTCL                 = 0x5,
 209         DEVICE_DESC_PARAM_NUM_LU                = 0x6,
 210         DEVICE_DESC_PARAM_NUM_WLU               = 0x7,
 211         DEVICE_DESC_PARAM_BOOT_ENBL             = 0x8,
 212         DEVICE_DESC_PARAM_DESC_ACCSS_ENBL       = 0x9,
 213         DEVICE_DESC_PARAM_INIT_PWR_MODE         = 0xA,
 214         DEVICE_DESC_PARAM_HIGH_PR_LUN           = 0xB,
 215         DEVICE_DESC_PARAM_SEC_RMV_TYPE          = 0xC,
 216         DEVICE_DESC_PARAM_SEC_LU                = 0xD,
 217         DEVICE_DESC_PARAM_BKOP_TERM_LT          = 0xE,
 218         DEVICE_DESC_PARAM_ACTVE_ICC_LVL         = 0xF,
 219         DEVICE_DESC_PARAM_SPEC_VER              = 0x10,
 220         DEVICE_DESC_PARAM_MANF_DATE             = 0x12,
 221         DEVICE_DESC_PARAM_MANF_NAME             = 0x14,
 222         DEVICE_DESC_PARAM_PRDCT_NAME            = 0x15,
 223         DEVICE_DESC_PARAM_SN                    = 0x16,
 224         DEVICE_DESC_PARAM_OEM_ID                = 0x17,
 225         DEVICE_DESC_PARAM_MANF_ID               = 0x18,
 226         DEVICE_DESC_PARAM_UD_OFFSET             = 0x1A,
 227         DEVICE_DESC_PARAM_UD_LEN                = 0x1B,
 228         DEVICE_DESC_PARAM_RTT_CAP               = 0x1C,
 229         DEVICE_DESC_PARAM_FRQ_RTC               = 0x1D,
 230         DEVICE_DESC_PARAM_UFS_FEAT              = 0x1F,
 231         DEVICE_DESC_PARAM_FFU_TMT               = 0x20,
 232         DEVICE_DESC_PARAM_Q_DPTH                = 0x21,
 233         DEVICE_DESC_PARAM_DEV_VER               = 0x22,
 234         DEVICE_DESC_PARAM_NUM_SEC_WPA           = 0x24,
 235         DEVICE_DESC_PARAM_PSA_MAX_DATA          = 0x25,
 236         DEVICE_DESC_PARAM_PSA_TMT               = 0x29,
 237         DEVICE_DESC_PARAM_PRDCT_REV             = 0x2A,
 238         DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP   = 0x4F,
 239         DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN   = 0x53,
 240         DEVICE_DESC_PARAM_WB_TYPE               = 0x54,
 241         DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
 242 };
 243
 244 /* Interconnect descriptor parameters offsets in bytes*/
 245 enum interconnect_desc_param {
 246         INTERCONNECT_DESC_PARAM_LEN             = 0x0,
 247         INTERCONNECT_DESC_PARAM_TYPE            = 0x1,
 248         INTERCONNECT_DESC_PARAM_UNIPRO_VER      = 0x2,
 249         INTERCONNECT_DESC_PARAM_MPHY_VER        = 0x4,
 250 };
 251
 252 /* Geometry descriptor parameters offsets in bytes*/
 253 enum geometry_desc_param {
 254         GEOMETRY_DESC_PARAM_LEN                 = 0x0,
 255         GEOMETRY_DESC_PARAM_TYPE                = 0x1,
 256         GEOMETRY_DESC_PARAM_DEV_CAP             = 0x4,
 257         GEOMETRY_DESC_PARAM_MAX_NUM_LUN         = 0xC,
 258         GEOMETRY_DESC_PARAM_SEG_SIZE            = 0xD,
 259         GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE     = 0x11,
 260         GEOMETRY_DESC_PARAM_MIN_BLK_SIZE        = 0x12,
 261         GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE     = 0x13,
 262         GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE     = 0x14,
 263         GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE     = 0x15,
 264         GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE    = 0x16,
 265         GEOMETRY_DESC_PARAM_RPMB_RW_SIZE        = 0x17,
 266         GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC    = 0x18,
 267         GEOMETRY_DESC_PARAM_DATA_ORDER          = 0x19,
 268         GEOMETRY_DESC_PARAM_MAX_NUM_CTX         = 0x1A,
 269         GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE       = 0x1B,
 270         GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE       = 0x1C,
 271         GEOMETRY_DESC_PARAM_SEC_RM_TYPES        = 0x1D,
 272         GEOMETRY_DESC_PARAM_MEM_TYPES           = 0x1E,
 273         GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS   = 0x20,
 274         GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR    = 0x24,
 275         GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS   = 0x26,
 276         GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR    = 0x2A,
 277         GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS  = 0x2C,
 278         GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR   = 0x30,
 279         GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS  = 0x32,
 280         GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR   = 0x36,
 281         GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS  = 0x38,
 282         GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR   = 0x3C,
 283         GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS  = 0x3E,
 284         GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR   = 0x42,
 285         GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE    = 0x44,
 286         GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS  = 0x4F,
 287         GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS      = 0x53,
 288         GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ     = 0x54,
 289         GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE     = 0x55,
 290         GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE      = 0x56,
 291 };
 292
 293 /* Health descriptor parameters offsets in bytes*/
 294 enum health_desc_param {
 295         HEALTH_DESC_PARAM_LEN                   = 0x0,
 296         HEALTH_DESC_PARAM_TYPE                  = 0x1,
 297         HEALTH_DESC_PARAM_EOL_INFO              = 0x2,
 298         HEALTH_DESC_PARAM_LIFE_TIME_EST_A       = 0x3,
 299         HEALTH_DESC_PARAM_LIFE_TIME_EST_B       = 0x4,
 300 };
 301
 302 /* WriteBooster buffer mode */
 303 enum {
 304         WB_BUF_MODE_LU_DEDICATED        = 0x0,
 305         WB_BUF_MODE_SHARED              = 0x1,
 306 };
 307
 308 /*
 309  * Logical Unit Write Protect
 310  * 00h: LU not write protected
 311  * 01h: LU write protected when fPowerOnWPEn =1
 312  * 02h: LU permanently write protected when fPermanentWPEn =1
 313  */
 314 enum ufs_lu_wp_type {
 315         UFS_LU_NO_WP            = 0x00,
 316         UFS_LU_POWER_ON_WP      = 0x01,
 317         UFS_LU_PERM_WP          = 0x02,
 318 };
 319
 320 /* bActiveICCLevel parameter current units */
 321 enum {
 322         UFSHCD_NANO_AMP         = 0,
 323         UFSHCD_MICRO_AMP        = 1,
 324         UFSHCD_MILI_AMP         = 2,
 325         UFSHCD_AMP              = 3,
 326 };
 327
 328 /* Possible values for dExtendedUFSFeaturesSupport */
 329 enum {
 330         UFS_DEV_WRITE_BOOSTER_SUP       = BIT(8),
 331 };
 332
 333 #define POWER_DESC_MAX_SIZE                     0x62
 334 #define POWER_DESC_MAX_ACTV_ICC_LVLS            16
 335
 336 /* Attribute  bActiveICCLevel parameter bit masks definitions */
 337 #define ATTR_ICC_LVL_UNIT_OFFSET        14
 338 #define ATTR_ICC_LVL_UNIT_MASK          (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
 339 #define ATTR_ICC_LVL_VALUE_MASK         0x3FF
 340
 341 /* Power descriptor parameters offsets in bytes */
 342 enum power_desc_param_offset {
 343         PWR_DESC_LEN                    = 0x0,
 344         PWR_DESC_TYPE                   = 0x1,
 345         PWR_DESC_ACTIVE_LVLS_VCC_0      = 0x2,
 346         PWR_DESC_ACTIVE_LVLS_VCCQ_0     = 0x22,
 347         PWR_DESC_ACTIVE_LVLS_VCCQ2_0    = 0x42,
 348 };
 349
 350 /* Exception event mask values */
 351 enum {
 352         MASK_EE_STATUS          = 0xFFFF,
 353         MASK_EE_URGENT_BKOPS    = (1 << 2),
 354 };
 355
 356 /* Background operation status */
 357 enum bkops_status {
 358         BKOPS_STATUS_NO_OP               = 0x0,
 359         BKOPS_STATUS_NON_CRITICAL        = 0x1,
 360         BKOPS_STATUS_PERF_IMPACT         = 0x2,
 361         BKOPS_STATUS_CRITICAL            = 0x3,
 362         BKOPS_STATUS_MAX                 = BKOPS_STATUS_CRITICAL,
 363 };
 364
 365 /* UTP QUERY Transaction Specific Fields OpCode */
 366 enum query_opcode {
 367         UPIU_QUERY_OPCODE_NOP           = 0x0,
 368         UPIU_QUERY_OPCODE_READ_DESC     = 0x1,
 369         UPIU_QUERY_OPCODE_WRITE_DESC    = 0x2,
 370         UPIU_QUERY_OPCODE_READ_ATTR     = 0x3,
 371         UPIU_QUERY_OPCODE_WRITE_ATTR    = 0x4,
 372         UPIU_QUERY_OPCODE_READ_FLAG     = 0x5,
 373         UPIU_QUERY_OPCODE_SET_FLAG      = 0x6,
 374         UPIU_QUERY_OPCODE_CLEAR_FLAG    = 0x7,
 375         UPIU_QUERY_OPCODE_TOGGLE_FLAG   = 0x8,
 376 };
 377
 378 /* bRefClkFreq attribute values */
 379 enum ufs_ref_clk_freq {
 380         REF_CLK_FREQ_19_2_MHZ   = 0,
 381         REF_CLK_FREQ_26_MHZ     = 1,
 382         REF_CLK_FREQ_38_4_MHZ   = 2,
 383         REF_CLK_FREQ_52_MHZ     = 3,
 384         REF_CLK_FREQ_INVAL      = -1,
 385 };
 386
 387 struct ufs_ref_clk {
 388         unsigned long freq_hz;
 389         enum ufs_ref_clk_freq val;
 390 };
 391
 392 /* Query response result code */
 393 enum {
 394         QUERY_RESULT_SUCCESS                    = 0x00,
 395         QUERY_RESULT_NOT_READABLE               = 0xF6,
 396         QUERY_RESULT_NOT_WRITEABLE              = 0xF7,
 397         QUERY_RESULT_ALREADY_WRITTEN            = 0xF8,
 398         QUERY_RESULT_INVALID_LENGTH             = 0xF9,
 399         QUERY_RESULT_INVALID_VALUE              = 0xFA,
 400         QUERY_RESULT_INVALID_SELECTOR           = 0xFB,
 401         QUERY_RESULT_INVALID_INDEX              = 0xFC,
 402         QUERY_RESULT_INVALID_IDN                = 0xFD,
 403         QUERY_RESULT_INVALID_OPCODE             = 0xFE,
 404         QUERY_RESULT_GENERAL_FAILURE            = 0xFF,
 405 };
 406
 407 /* UTP Transfer Request Command Type (CT) */
 408 enum {
 409         UPIU_COMMAND_SET_TYPE_SCSI      = 0x0,
 410         UPIU_COMMAND_SET_TYPE_UFS       = 0x1,
 411         UPIU_COMMAND_SET_TYPE_QUERY     = 0x2,
 412 };
 413
 414 /* UTP Transfer Request Command Offset */
 415 #define UPIU_COMMAND_TYPE_OFFSET        28
 416
 417 /* Offset of the response code in the UPIU header */
 418 #define UPIU_RSP_CODE_OFFSET            8
 419
 420 enum {
 421         MASK_SCSI_STATUS                = 0xFF,
 422         MASK_TASK_RESPONSE              = 0xFF00,
 423         MASK_RSP_UPIU_RESULT            = 0xFFFF,
 424         MASK_QUERY_DATA_SEG_LEN         = 0xFFFF,
 425         MASK_RSP_UPIU_DATA_SEG_LEN      = 0xFFFF,
 426         MASK_RSP_EXCEPTION_EVENT        = 0x10000,
 427         MASK_TM_SERVICE_RESP            = 0xFF,
 428         MASK_TM_FUNC                    = 0xFF,
 429 };
 430
 431 /* Task management service response */
 432 enum {
 433         UPIU_TASK_MANAGEMENT_FUNC_COMPL         = 0x00,
 434         UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
 435         UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED     = 0x08,
 436         UPIU_TASK_MANAGEMENT_FUNC_FAILED        = 0x05,
 437         UPIU_INCORRECT_LOGICAL_UNIT_NO          = 0x09,
 438 };
 439
 440 /* UFS device power modes */
 441 enum ufs_dev_pwr_mode {
 442         UFS_ACTIVE_PWR_MODE     = 1,
 443         UFS_SLEEP_PWR_MODE      = 2,
 444         UFS_POWERDOWN_PWR_MODE  = 3,
 445         UFS_DEEPSLEEP_PWR_MODE  = 4,
 446 };
 447
 448 #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
 449
 450 /**
 451  * struct utp_cmd_rsp - Response UPIU structure
 452  * @residual_transfer_count: Residual transfer count DW-3
 453  * @reserved: Reserved double words DW-4 to DW-7
 454  * @sense_data_len: Sense data length DW-8 U16
 455  * @sense_data: Sense data field DW-8 to DW-12
 456  */
 457 struct utp_cmd_rsp {
 458         __be32 residual_transfer_count;
 459         __be32 reserved[4];
 460         __be16 sense_data_len;
 461         u8 sense_data[UFS_SENSE_SIZE];
 462 };
 463
 464 /**
 465  * struct utp_upiu_rsp - general upiu response structure
 466  * @header: UPIU header structure DW-0 to DW-2
 467  * @sr: fields structure for scsi command DW-3 to DW-12
 468  * @qr: fields structure for query request DW-3 to DW-7
 469  */
 470 struct utp_upiu_rsp {
 471         struct utp_upiu_header header;
 472         union {
 473                 struct utp_cmd_rsp sr;
 474                 struct utp_upiu_query qr;
 475         };
 476 };
 477
 478 /**
 479  * struct ufs_query_req - parameters for building a query request
 480  * @query_func: UPIU header query function
 481  * @upiu_req: the query request data
 482  */
 483 struct ufs_query_req {
 484         u8 query_func;
 485         struct utp_upiu_query upiu_req;
 486 };
 487
 488 /**
 489  * struct ufs_query_resp - UPIU QUERY
 490  * @response: device response code
 491  * @upiu_res: query response data
 492  */
 493 struct ufs_query_res {
 494         u8 response;
 495         struct utp_upiu_query upiu_res;
 496 };
 497
 498 #define UFS_VREG_VCC_MIN_UV        2700000 /* uV */
 499 #define UFS_VREG_VCC_MAX_UV        3600000 /* uV */
 500 #define UFS_VREG_VCC_1P8_MIN_UV    1700000 /* uV */
 501 #define UFS_VREG_VCC_1P8_MAX_UV    1950000 /* uV */
 502 #define UFS_VREG_VCCQ_MIN_UV       1140000 /* uV */
 503 #define UFS_VREG_VCCQ_MAX_UV       1260000 /* uV */
 504 #define UFS_VREG_VCCQ2_MIN_UV      1700000 /* uV */
 505 #define UFS_VREG_VCCQ2_MAX_UV      1950000 /* uV */
 506
 507 /*
 508  * VCCQ & VCCQ2 current requirement when UFS device is in sleep state
 509  * and link is in Hibern8 state.
 510  */
 511 #define UFS_VREG_LPM_LOAD_UA    1000 /* uA */
 512
 513 struct ufs_vreg {
 514         struct regulator *reg;
 515         const char *name;
 516         bool enabled;
 517         int min_uV;
 518         int max_uV;
 519         int max_uA;
 520 };
 521
 522 struct ufs_vreg_info {
 523         struct ufs_vreg *vcc;
 524         struct ufs_vreg *vccq;
 525         struct ufs_vreg *vccq2;
 526         struct ufs_vreg *vdd_hba;
 527 };
 528
 529 struct ufs_dev_info {
 530         bool f_power_on_wp_en;
 531         /* Keeps information if any of the LU is power on write protected */
 532         bool is_lu_power_on_wp;
 533         /* Maximum number of general LU supported by the UFS device */
 534         u8 max_lu_supported;
 535         u8 wb_dedicated_lu;
 536         u16 wmanufacturerid;
 537         /*UFS device Product Name */
 538         u8 *model;
 539         u16 wspecversion;
 540         u32 clk_gating_wait_us;
 541         u32 d_ext_ufs_feature_sup;
 542         u8 b_wb_buffer_type;
 543         u32 d_wb_alloc_units;
 544         bool b_rpm_dev_flush_capable;
 545         u8 b_presrv_uspc_en;
 546 };
 547
 548 /**
 549  * ufs_is_valid_unit_desc_lun - checks if the given LUN has a unit descriptor
 550  * @dev_info: pointer of instance of struct ufs_dev_info
 551  * @lun: LU number to check
 552  * @return: true if the lun has a matching unit descriptor, false otherwise
 553  */
 554 static inline bool ufs_is_valid_unit_desc_lun(struct ufs_dev_info *dev_info,
 555                 u8 lun)
 556 {
 557         if (!dev_info || !dev_info->max_lu_supported) {
 558                 pr_err("Max General LU supported by UFS isn't initialized\n");
 559                 return false;
 560         }
 561
 562         return lun == UFS_UPIU_RPMB_WLUN || (lun < dev_info->max_lu_supported);
 563 }
 564
 565 #endif /* End of Header */