drivers/scsi/ufs/ufs-mediatek.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2019 MediaTek Inc.
   4  */
   5
   6 #ifndef _UFS_MEDIATEK_H
   7 #define _UFS_MEDIATEK_H
   8
   9 #include <linux/bitops.h>
  10 #include <linux/soc/mediatek/mtk_sip_svc.h>
  11
  12 /*
  13  * Vendor specific UFSHCI Registers
  14  */
  15 #define REG_UFS_REFCLK_CTRL         0x144
  16 #define REG_UFS_EXTREG              0x2100
  17 #define REG_UFS_MPHYCTRL            0x2200
  18 #define REG_UFS_REJECT_MON          0x22AC
  19 #define REG_UFS_DEBUG_SEL           0x22C0
  20 #define REG_UFS_PROBE               0x22C8
  21
  22 /*
  23  * Ref-clk control
  24  *
  25  * Values for register REG_UFS_REFCLK_CTRL
  26  */
  27 #define REFCLK_RELEASE              0x0
  28 #define REFCLK_REQUEST              BIT(0)
  29 #define REFCLK_ACK                  BIT(1)
  30
  31 #define REFCLK_REQ_TIMEOUT_US       3000
  32
  33 /*
  34  * Other attributes
  35  */
  36 #define VS_DEBUGCLOCKENABLE         0xD0A1
  37 #define VS_SAVEPOWERCONTROL         0xD0A6
  38 #define VS_UNIPROPOWERDOWNCONTROL   0xD0A8
  39
  40 /*
  41  * Vendor specific link state
  42  */
  43 enum {
  44         VS_LINK_DISABLED            = 0,
  45         VS_LINK_DOWN                = 1,
  46         VS_LINK_UP                  = 2,
  47         VS_LINK_HIBERN8             = 3,
  48         VS_LINK_LOST                = 4,
  49         VS_LINK_CFG                 = 5,
  50 };
  51
  52 /*
  53  * SiP commands
  54  */
  55 #define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)
  56 #define UFS_MTK_SIP_VA09_PWR_CTRL         BIT(0)
  57 #define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
  58 #define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
  59 #define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
  60
  61 /*
  62  * VS_DEBUGCLOCKENABLE
  63  */
  64 enum {
  65         TX_SYMBOL_CLK_REQ_FORCE = 5,
  66 };
  67
  68 /*
  69  * VS_SAVEPOWERCONTROL
  70  */
  71 enum {
  72         RX_SYMBOL_CLK_GATE_EN   = 0,
  73         SYS_CLK_GATE_EN         = 2,
  74         TX_CLK_GATE_EN          = 3,
  75 };
  76
  77 /*
  78  * Host capability
  79  */
  80 enum ufs_mtk_host_caps {
  81         UFS_MTK_CAP_BOOST_CRYPT_ENGINE         = 1 << 0,
  82         UFS_MTK_CAP_VA09_PWR_CTRL              = 1 << 1,
  83         UFS_MTK_CAP_DISABLE_AH8                = 1 << 2,
  84         UFS_MTK_CAP_BROKEN_VCC                 = 1 << 3,
  85 };
  86
  87 struct ufs_mtk_crypt_cfg {
  88         struct regulator *reg_vcore;
  89         struct clk *clk_crypt_perf;
  90         struct clk *clk_crypt_mux;
  91         struct clk *clk_crypt_lp;
  92         int vcore_volt;
  93 };
  94
  95 struct ufs_mtk_hw_ver {
  96         u8 step;
  97         u8 minor;
  98         u8 major;
  99 };
 100
 101 struct ufs_mtk_host {
 102         struct phy *mphy;
 103         struct regulator *reg_va09;
 104         struct reset_control *hci_reset;
 105         struct reset_control *unipro_reset;
 106         struct reset_control *crypto_reset;
 107         struct ufs_hba *hba;
 108         struct ufs_mtk_crypt_cfg *crypt;
 109         struct ufs_mtk_hw_ver hw_ver;
 110         enum ufs_mtk_host_caps caps;
 111         bool mphy_powered_on;
 112         bool unipro_lpm;
 113         bool ref_clk_enabled;
 114         u16 ref_clk_ungating_wait_us;
 115         u16 ref_clk_gating_wait_us;
 116 };
 117
 118 #endif /* !_UFS_MEDIATEK_H */