2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 #include <linux/btree.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport_fc.h>
35 #include <scsi/scsi_bsg_fc.h>
42 #define QLA2XXX_DRIVER_NAME "qla2xxx"
43 #define QLA2XXX_APIDEV "ql2xapidev"
44 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
47 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
48 * but that's fine as we don't look at the last 24 ones for
51 #define MAILBOX_REGISTER_COUNT_2100 8
52 #define MAILBOX_REGISTER_COUNT_2200 24
53 #define MAILBOX_REGISTER_COUNT 32
55 #define QLA2200A_RISC_ROM_VER 4
59 #include "qla_settings.h"
61 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
64 * Data bit definitions
82 #define BIT_16 0x10000
83 #define BIT_17 0x20000
84 #define BIT_18 0x40000
85 #define BIT_19 0x80000
86 #define BIT_20 0x100000
87 #define BIT_21 0x200000
88 #define BIT_22 0x400000
89 #define BIT_23 0x800000
90 #define BIT_24 0x1000000
91 #define BIT_25 0x2000000
92 #define BIT_26 0x4000000
93 #define BIT_27 0x8000000
94 #define BIT_28 0x10000000
95 #define BIT_29 0x20000000
96 #define BIT_30 0x40000000
97 #define BIT_31 0x80000000
99 #define LSB(x) ((uint8_t)(x))
100 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
102 #define LSW(x) ((uint16_t)(x))
103 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
105 #define LSD(x) ((uint32_t)((uint64_t)(x)))
106 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
108 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
114 #define RD_REG_BYTE(addr) readb(addr)
115 #define RD_REG_WORD(addr) readw(addr)
116 #define RD_REG_DWORD(addr) readl(addr)
117 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
118 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
119 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
120 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
121 #define WRT_REG_WORD(addr, data) writew(data,addr)
122 #define WRT_REG_DWORD(addr, data) writel(data,addr)
125 * ISP83XX specific remote register addresses
127 #define QLA83XX_LED_PORT0 0x00201320
128 #define QLA83XX_LED_PORT1 0x00201328
129 #define QLA83XX_IDC_DEV_STATE 0x22102384
130 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
131 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
132 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
133 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
134 #define QLA83XX_IDC_CONTROL 0x22102390
135 #define QLA83XX_IDC_AUDIT 0x22102394
136 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
137 #define QLA83XX_DRIVER_LOCKID 0x22102104
138 #define QLA83XX_DRIVER_LOCK 0x8111c028
139 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
140 #define QLA83XX_FLASH_LOCKID 0x22102100
141 #define QLA83XX_FLASH_LOCK 0x8111c010
142 #define QLA83XX_FLASH_UNLOCK 0x8111c014
143 #define QLA83XX_DEV_PARTINFO1 0x221023e0
144 #define QLA83XX_DEV_PARTINFO2 0x221023e4
145 #define QLA83XX_FW_HEARTBEAT 0x221020b0
146 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
147 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
149 /* 83XX: Macros defining 8200 AEN Reason codes */
150 #define IDC_DEVICE_STATE_CHANGE BIT_0
151 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
152 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
153 #define IDC_HEARTBEAT_FAILURE BIT_3
155 /* 83XX: Macros defining 8200 AEN Error-levels */
156 #define ERR_LEVEL_NON_FATAL 0x1
157 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
158 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
160 /* 83XX: Macros for IDC Version */
161 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
162 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
164 /* 83XX: Macros for scheduling dpc tasks */
165 #define QLA83XX_NIC_CORE_RESET 0x1
166 #define QLA83XX_IDC_STATE_HANDLER 0x2
167 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
169 /* 83XX: Macros for defining IDC-Control bits */
170 #define QLA83XX_IDC_RESET_DISABLED BIT_0
171 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
173 /* 83XX: Macros for different timeouts */
174 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
175 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
176 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
178 /* 83XX: Macros for defining class in DEV-Partition Info register */
179 #define QLA83XX_CLASS_TYPE_NONE 0x0
180 #define QLA83XX_CLASS_TYPE_NIC 0x1
181 #define QLA83XX_CLASS_TYPE_FCOE 0x2
182 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
184 /* 83XX: Macros for IDC Lock-Recovery stages */
185 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
188 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
190 /* 83XX: Macros for IDC Audit type */
191 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
192 * dev-state change to NEED-RESET
195 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
196 * reset-recovery completion is
199 /* ISP2031: Values for laser on/off */
200 #define PORT_0_2031 0x00201340
201 #define PORT_1_2031 0x00201350
202 #define LASER_ON_2031 0x01800100
203 #define LASER_OFF_2031 0x01800180
206 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
209 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
210 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
213 * Fibre Channel device definitions.
215 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
216 #define MAX_FIBRE_DEVICES_2100 512
217 #define MAX_FIBRE_DEVICES_2400 2048
218 #define MAX_FIBRE_DEVICES_LOOP 128
219 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
220 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
221 #define MAX_FIBRE_LUNS 0xFFFF
222 #define MAX_HOST_COUNT 16
225 * Host adapter default definitions.
227 #define MAX_BUSES 1 /* We only have one bus today */
229 #define MAX_LUNS MAX_FIBRE_LUNS
230 #define MAX_CMDS_PER_LUN 255
233 * Fibre Channel device definitions.
235 #define SNS_LAST_LOOP_ID_2100 0xfe
236 #define SNS_LAST_LOOP_ID_2300 0x7ff
238 #define LAST_LOCAL_LOOP_ID 0x7d
239 #define SNS_FL_PORT 0x7e
240 #define FABRIC_CONTROLLER 0x7f
241 #define SIMPLE_NAME_SERVER 0x80
242 #define SNS_FIRST_LOOP_ID 0x81
243 #define MANAGEMENT_SERVER 0xfe
244 #define BROADCAST 0xff
247 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
248 * valid range of an N-PORT id is 0 through 0x7ef.
250 #define NPH_LAST_HANDLE 0x7ee
251 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
252 #define NPH_SNS 0x7fc /* FFFFFC */
253 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
254 #define NPH_F_PORT 0x7fe /* FFFFFE */
255 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
257 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
259 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
262 struct name_list_extended {
263 struct get_name_list_extended *l;
265 struct list_head fcports;
270 * Timeout timer counts in seconds
272 #define PORT_RETRY_TIME 1
273 #define LOOP_DOWN_TIMEOUT 60
274 #define LOOP_DOWN_TIME 255 /* 240 */
275 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
277 #define DEFAULT_OUTSTANDING_COMMANDS 4096
278 #define MIN_OUTSTANDING_COMMANDS 128
280 /* ISP request and response entry counts (37-65535) */
281 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
282 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
283 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
284 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
285 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
286 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
287 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
288 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
289 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
290 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
291 #define FW_DEF_EXCHANGES_CNT 2048
292 #define FW_MAX_EXCHANGES_CNT (32 * 1024)
293 #define REDUCE_EXCHANGES_CNT (8 * 1024)
302 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
303 uint32_t request_sense_length;
304 uint32_t fw_sense_length;
305 uint8_t *request_sense_ptr;
310 * SRB flag definitions
312 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
313 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
314 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
315 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
316 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
317 #define SRB_WAKEUP_ON_COMP BIT_6
318 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
320 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
321 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
324 * 24 bit port ID type definition.
334 #elif defined(__LITTLE_ENDIAN)
339 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
344 #define INVALID_PORT_ID 0xFFFFFF
346 struct els_logo_payload {
351 uint8_t wwpn[WWN_SIZE];
354 struct els_plogi_payload {
367 u32 req_allocated_size;
368 u32 rsp_allocated_size;
381 #define SRB_LOGIN_RETRIED BIT_0
382 #define SRB_LOGIN_COND_PLOGI BIT_1
383 #define SRB_LOGIN_SKIP_PRLI BIT_2
384 #define SRB_LOGIN_NVME_PRLI BIT_3
385 #define SRB_LOGIN_PRLI_ONLY BIT_4
390 #define ELS_DCMD_TIMEOUT 20
391 #define ELS_DCMD_LOGO 0x5
394 struct completion comp;
395 struct els_logo_payload *els_logo_pyld;
396 dma_addr_t els_logo_pyld_dma;
399 #define ELS_DCMD_PLOGI 0x3
402 struct completion comp;
403 struct els_plogi_payload *els_plogi_pyld;
404 struct els_plogi_payload *els_resp_pyld;
407 dma_addr_t els_plogi_pyld_dma;
408 dma_addr_t els_resp_pyld_dma;
409 uint32_t fw_status[3];
415 * Values for flags field below are as
416 * defined in tsk_mgmt_entry struct
417 * for control_flags field in qla_fw.h.
422 struct completion comp;
426 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
427 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
428 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
429 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
430 #define FXDISC_TIMEOUT 20
436 dma_addr_t req_dma_handle;
437 dma_addr_t rsp_dma_handle;
439 __le32 adapter_id_hi;
440 __le16 req_func_type;
442 __le32 req_data_extra;
446 struct completion fxiocb_comp;
454 struct completion comp;
457 #define MAX_IOCB_MB_REG 28
458 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
460 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
461 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
463 dma_addr_t out_dma, in_dma;
464 struct completion comp;
468 struct imm_ntfy_from_isp *ntfy;
472 uint16_t rsp_pyld_len;
476 /* These are only used with ls4 requests */
481 enum nvmefc_fcp_datadir dir;
483 uint32_t timeout_sec;
484 struct list_head entry;
492 struct timer_list timer;
493 void (*timeout)(void *);
496 /* Values for srb_ctx type */
497 #define SRB_LOGIN_CMD 1
498 #define SRB_LOGOUT_CMD 2
499 #define SRB_ELS_CMD_RPT 3
500 #define SRB_ELS_CMD_HST 4
502 #define SRB_ADISC_CMD 6
504 #define SRB_SCSI_CMD 8
505 #define SRB_BIDI_CMD 9
506 #define SRB_FXIOCB_DCMD 10
507 #define SRB_FXIOCB_BCMD 11
508 #define SRB_ABT_CMD 12
509 #define SRB_ELS_DCMD 13
510 #define SRB_MB_IOCB 14
511 #define SRB_CT_PTHRU_CMD 15
512 #define SRB_NACK_PLOGI 16
513 #define SRB_NACK_PRLI 17
514 #define SRB_NACK_LOGO 18
515 #define SRB_NVME_CMD 19
516 #define SRB_NVME_LS 20
517 #define SRB_PRLI_CMD 21
518 #define SRB_CTRL_VP 22
519 #define SRB_PRLO_CMD 23
524 TYPE_TGT_TMCMD, /* task management */
529 * Do not move cmd_type field, it needs to
530 * line up with qla_tgt_cmd->cmd_type
535 wait_queue_head_t nvme_ls_waitq;
536 struct fc_port *fcport;
537 struct scsi_qla_host *vha;
543 struct qla_qpair *qpair;
544 struct list_head elem;
545 u32 gen1; /* scratch */
546 u32 gen2; /* scratch */
549 struct completion *comp;
551 struct srb_iocb iocb_cmd;
552 struct bsg_job *bsg_job;
555 void (*done)(void *, int);
556 void (*free)(void *);
559 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
560 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
561 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
563 #define GET_CMD_SENSE_LEN(sp) \
564 (sp->u.scmd.request_sense_length)
565 #define SET_CMD_SENSE_LEN(sp, len) \
566 (sp->u.scmd.request_sense_length = len)
567 #define GET_CMD_SENSE_PTR(sp) \
568 (sp->u.scmd.request_sense_ptr)
569 #define SET_CMD_SENSE_PTR(sp, ptr) \
570 (sp->u.scmd.request_sense_ptr = ptr)
571 #define GET_FW_SENSE_LEN(sp) \
572 (sp->u.scmd.fw_sense_length)
573 #define SET_FW_SENSE_LEN(sp, len) \
574 (sp->u.scmd.fw_sense_length = len)
582 uint32_t transfer_size;
583 uint32_t iteration_count;
587 * ISP I/O Register Set structure definitions.
589 struct device_reg_2xxx {
590 uint16_t flash_address; /* Flash BIOS address */
591 uint16_t flash_data; /* Flash BIOS data */
592 uint16_t unused_1[1]; /* Gap */
593 uint16_t ctrl_status; /* Control/Status */
594 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
595 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
596 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
598 uint16_t ictrl; /* Interrupt control */
599 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
600 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
602 uint16_t istatus; /* Interrupt status */
603 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
605 uint16_t semaphore; /* Semaphore */
606 uint16_t nvram; /* NVRAM register. */
607 #define NVR_DESELECT 0
608 #define NVR_BUSY BIT_15
609 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
610 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
611 #define NVR_DATA_IN BIT_3
612 #define NVR_DATA_OUT BIT_2
613 #define NVR_SELECT BIT_1
614 #define NVR_CLOCK BIT_0
616 #define NVR_WAIT_CNT 20000
628 uint16_t unused_2[59]; /* Gap */
629 } __attribute__((packed)) isp2100;
632 uint16_t req_q_in; /* In-Pointer */
633 uint16_t req_q_out; /* Out-Pointer */
635 uint16_t rsp_q_in; /* In-Pointer */
636 uint16_t rsp_q_out; /* Out-Pointer */
638 /* RISC to Host Status */
639 uint32_t host_status;
640 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
641 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
643 /* Host to Host Semaphore */
644 uint16_t host_semaphore;
645 uint16_t unused_3[17]; /* Gap */
679 uint16_t unused_4[10]; /* Gap */
680 } __attribute__((packed)) isp2300;
683 uint16_t fpm_diag_config;
684 uint16_t unused_5[0x4]; /* Gap */
686 uint16_t unused_5_1; /* Gap */
687 uint16_t pcr; /* Processor Control Register. */
688 uint16_t unused_6[0x5]; /* Gap */
689 uint16_t mctr; /* Memory Configuration and Timing. */
690 uint16_t unused_7[0x3]; /* Gap */
691 uint16_t fb_cmd_2100; /* Unused on 23XX */
692 uint16_t unused_8[0x3]; /* Gap */
693 uint16_t hccr; /* Host command & control register. */
694 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
695 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
697 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
698 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
699 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
700 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
701 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
702 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
703 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
704 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
706 uint16_t unused_9[5]; /* Gap */
707 uint16_t gpiod; /* GPIO Data register. */
708 uint16_t gpioe; /* GPIO Enable register. */
709 #define GPIO_LED_MASK 0x00C0
710 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
711 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
712 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
713 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
714 #define GPIO_LED_ALL_OFF 0x0000
715 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
716 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
720 uint16_t unused_10[8]; /* Gap */
736 uint16_t mailbox23; /* Also probe reg. */
737 } __attribute__((packed)) isp2200;
741 struct device_reg_25xxmq {
751 struct device_reg_fx00 {
752 uint32_t mailbox0; /* 00 */
753 uint32_t mailbox1; /* 04 */
754 uint32_t mailbox2; /* 08 */
755 uint32_t mailbox3; /* 0C */
756 uint32_t mailbox4; /* 10 */
757 uint32_t mailbox5; /* 14 */
758 uint32_t mailbox6; /* 18 */
759 uint32_t mailbox7; /* 1C */
760 uint32_t mailbox8; /* 20 */
761 uint32_t mailbox9; /* 24 */
762 uint32_t mailbox10; /* 28 */
784 uint32_t aenmailbox0;
785 uint32_t aenmailbox1;
786 uint32_t aenmailbox2;
787 uint32_t aenmailbox3;
788 uint32_t aenmailbox4;
789 uint32_t aenmailbox5;
790 uint32_t aenmailbox6;
791 uint32_t aenmailbox7;
793 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
794 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
795 /* Response Queue. */
796 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
797 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
798 /* Init values shadowed on FW Up Event */
799 uint32_t initval0; /* B0 */
800 uint32_t initval1; /* B4 */
801 uint32_t initval2; /* B8 */
802 uint32_t initval3; /* BC */
803 uint32_t initval4; /* C0 */
804 uint32_t initval5; /* C4 */
805 uint32_t initval6; /* C8 */
806 uint32_t initval7; /* CC */
807 uint32_t fwheartbeat; /* D0 */
808 uint32_t pseudoaen; /* D4 */
814 struct device_reg_2xxx isp;
815 struct device_reg_24xx isp24;
816 struct device_reg_25xxmq isp25mq;
817 struct device_reg_82xx isp82;
818 struct device_reg_fx00 ispfx00;
819 } __iomem device_reg_t;
821 #define ISP_REQ_Q_IN(ha, reg) \
822 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
823 &(reg)->u.isp2100.mailbox4 : \
824 &(reg)->u.isp2300.req_q_in)
825 #define ISP_REQ_Q_OUT(ha, reg) \
826 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
827 &(reg)->u.isp2100.mailbox4 : \
828 &(reg)->u.isp2300.req_q_out)
829 #define ISP_RSP_Q_IN(ha, reg) \
830 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
831 &(reg)->u.isp2100.mailbox5 : \
832 &(reg)->u.isp2300.rsp_q_in)
833 #define ISP_RSP_Q_OUT(ha, reg) \
834 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
835 &(reg)->u.isp2100.mailbox5 : \
836 &(reg)->u.isp2300.rsp_q_out)
838 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
839 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
841 #define MAILBOX_REG(ha, reg, num) \
842 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
844 &(reg)->u.isp2100.mailbox0 + (num) : \
845 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
846 &(reg)->u.isp2300.mailbox0 + (num))
847 #define RD_MAILBOX_REG(ha, reg, num) \
848 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
849 #define WRT_MAILBOX_REG(ha, reg, num, data) \
850 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
852 #define FB_CMD_REG(ha, reg) \
853 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
854 &(reg)->fb_cmd_2100 : \
855 &(reg)->u.isp2300.fb_cmd)
856 #define RD_FB_CMD_REG(ha, reg) \
857 RD_REG_WORD(FB_CMD_REG(ha, reg))
858 #define WRT_FB_CMD_REG(ha, reg, data) \
859 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
862 uint32_t out_mb; /* outbound from driver */
863 uint32_t in_mb; /* Incoming from RISC */
864 uint16_t mb[MAILBOX_REGISTER_COUNT];
869 #define MBX_DMA_IN BIT_0
870 #define MBX_DMA_OUT BIT_1
871 #define IOCTL_CMD BIT_2
875 uint32_t out_mb; /* outbound from driver */
876 uint32_t in_mb; /* Incoming from RISC */
877 uint32_t mb[MAILBOX_REGISTER_COUNT];
882 #define MBX_DMA_IN BIT_0
883 #define MBX_DMA_OUT BIT_1
884 #define IOCTL_CMD BIT_2
888 #define MBX_TOV_SECONDS 30
891 * ISP product identification definitions in mailboxes after reset.
893 #define PROD_ID_1 0x4953
894 #define PROD_ID_2 0x0000
895 #define PROD_ID_2a 0x5020
896 #define PROD_ID_3 0x2020
899 * ISP mailbox Self-Test status codes
901 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
902 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
903 #define MBS_BUSY 4 /* Busy. */
906 * ISP mailbox command complete status codes
908 #define MBS_COMMAND_COMPLETE 0x4000
909 #define MBS_INVALID_COMMAND 0x4001
910 #define MBS_HOST_INTERFACE_ERROR 0x4002
911 #define MBS_TEST_FAILED 0x4003
912 #define MBS_COMMAND_ERROR 0x4005
913 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
914 #define MBS_PORT_ID_USED 0x4007
915 #define MBS_LOOP_ID_USED 0x4008
916 #define MBS_ALL_IDS_IN_USE 0x4009
917 #define MBS_NOT_LOGGED_IN 0x400A
918 #define MBS_LINK_DOWN_ERROR 0x400B
919 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
922 * ISP mailbox asynchronous event status codes
924 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
925 #define MBA_RESET 0x8001 /* Reset Detected. */
926 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
927 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
928 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
929 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
930 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
932 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
933 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
934 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
935 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
936 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
937 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
938 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
939 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
940 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
941 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
942 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
943 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
944 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
945 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
946 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
947 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
949 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
950 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
951 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
952 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
953 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
954 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
955 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
956 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
957 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
958 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
959 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
960 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
961 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
962 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
963 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
964 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
965 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
966 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
967 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
968 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
969 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
970 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
971 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
972 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
974 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
975 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
976 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
977 /* 83XX FCoE specific */
978 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
980 /* Interrupt type codes */
981 #define INTR_ROM_MB_SUCCESS 0x1
982 #define INTR_ROM_MB_FAILED 0x2
983 #define INTR_MB_SUCCESS 0x10
984 #define INTR_MB_FAILED 0x11
985 #define INTR_ASYNC_EVENT 0x12
986 #define INTR_RSP_QUE_UPDATE 0x13
987 #define INTR_RSP_QUE_UPDATE_83XX 0x14
988 #define INTR_ATIO_QUE_UPDATE 0x1C
989 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
990 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
992 /* ISP mailbox loopback echo diagnostic error code */
993 #define MBS_LB_RESET 0x17
995 * Firmware options 1, 2, 3.
997 #define FO1_AE_ON_LIPF8 BIT_0
998 #define FO1_AE_ALL_LIP_RESET BIT_1
999 #define FO1_CTIO_RETRY BIT_3
1000 #define FO1_DISABLE_LIP_F7_SW BIT_4
1001 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1002 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1003 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1004 #define FO1_SET_EMPHASIS_SWING BIT_8
1005 #define FO1_AE_AUTO_BYPASS BIT_9
1006 #define FO1_ENABLE_PURE_IOCB BIT_10
1007 #define FO1_AE_PLOGI_RJT BIT_11
1008 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1009 #define FO1_AE_QUEUE_FULL BIT_13
1011 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1012 #define FO2_REV_LOOPBACK BIT_1
1014 #define FO3_ENABLE_EMERG_IOCB BIT_0
1015 #define FO3_AE_RND_ERROR BIT_1
1017 /* 24XX additional firmware options */
1018 #define ADD_FO_COUNT 3
1019 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
1020 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1022 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1024 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1027 * ISP mailbox commands
1029 #define MBC_LOAD_RAM 1 /* Load RAM. */
1030 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
1031 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
1032 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
1033 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
1034 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1035 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1036 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
1037 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
1038 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1039 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1040 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
1041 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1042 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
1043 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1044 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1045 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1046 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1047 #define MBC_RESET 0x18 /* Reset. */
1048 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
1049 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
1050 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1051 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1052 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1053 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1054 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1055 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
1056 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1057 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1058 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1059 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1060 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1061 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1062 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1063 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
1064 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1065 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1066 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
1067 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1068 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1069 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
1070 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1071 #define MBC_DATA_RATE 0x5d /* Data Rate */
1072 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1073 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1074 /* Initialization Procedure */
1075 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1076 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1077 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1078 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
1079 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1080 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1081 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1082 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1083 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1084 #define MBC_LIP_RESET 0x6c /* LIP reset. */
1085 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1087 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1088 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1089 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1090 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1091 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1092 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1093 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1094 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1095 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1096 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1097 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1100 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1101 * should be defined with MBC_MR_*
1103 #define MBC_MR_DRV_SHUTDOWN 0x6A
1106 * ISP24xx mailbox commands
1108 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1109 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1110 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1111 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1112 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1113 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1114 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1115 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1116 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1117 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1118 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1119 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1120 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1121 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1122 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1123 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1124 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1125 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1126 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1127 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1128 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1129 #define MBC_PORT_RESET 0x120 /* Port Reset */
1130 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1131 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1134 * ISP81xx mailbox commands
1136 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1139 * ISP8044 mailbox commands
1141 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1142 #define HCS_WRITE_SERDES 0x3
1143 #define HCS_READ_SERDES 0x4
1145 /* Firmware return data sizes */
1146 #define FCAL_MAP_SIZE 128
1148 /* Mailbox bit definitions for out_mb and in_mb */
1149 #define MBX_31 BIT_31
1150 #define MBX_30 BIT_30
1151 #define MBX_29 BIT_29
1152 #define MBX_28 BIT_28
1153 #define MBX_27 BIT_27
1154 #define MBX_26 BIT_26
1155 #define MBX_25 BIT_25
1156 #define MBX_24 BIT_24
1157 #define MBX_23 BIT_23
1158 #define MBX_22 BIT_22
1159 #define MBX_21 BIT_21
1160 #define MBX_20 BIT_20
1161 #define MBX_19 BIT_19
1162 #define MBX_18 BIT_18
1163 #define MBX_17 BIT_17
1164 #define MBX_16 BIT_16
1165 #define MBX_15 BIT_15
1166 #define MBX_14 BIT_14
1167 #define MBX_13 BIT_13
1168 #define MBX_12 BIT_12
1169 #define MBX_11 BIT_11
1170 #define MBX_10 BIT_10
1182 #define RNID_TYPE_PORT_LOGIN 0x7
1183 #define RNID_TYPE_SET_VERSION 0x9
1184 #define RNID_TYPE_ASIC_TEMP 0xC
1187 * Firmware state codes from get firmware state mailbox command
1189 #define FSTATE_CONFIG_WAIT 0
1190 #define FSTATE_WAIT_AL_PA 1
1191 #define FSTATE_WAIT_LOGIN 2
1192 #define FSTATE_READY 3
1193 #define FSTATE_LOSS_OF_SYNC 4
1194 #define FSTATE_ERROR 5
1195 #define FSTATE_REINIT 6
1196 #define FSTATE_NON_PART 7
1198 #define FSTATE_CONFIG_CORRECT 0
1199 #define FSTATE_P2P_RCV_LIP 1
1200 #define FSTATE_P2P_CHOOSE_LOOP 2
1201 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1202 #define FSTATE_FATAL_ERROR 4
1203 #define FSTATE_LOOP_BACK_CONN 5
1205 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1206 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1207 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1208 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1209 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1210 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1211 #define QLA27XX_DEFAULT_IMAGE 0
1212 #define QLA27XX_PRIMARY_IMAGE 1
1213 #define QLA27XX_SECONDARY_IMAGE 2
1216 * Port Database structure definition
1217 * Little endian except where noted.
1219 #define PORT_DATABASE_SIZE 128 /* bytes */
1223 uint8_t master_state;
1224 uint8_t slave_state;
1225 uint8_t reserved[2];
1226 uint8_t hard_address;
1229 uint8_t node_name[WWN_SIZE];
1230 uint8_t port_name[WWN_SIZE];
1231 uint16_t execution_throttle;
1232 uint16_t execution_count;
1233 uint8_t reset_count;
1235 uint16_t resource_allocation;
1236 uint16_t current_allocation;
1237 uint16_t queue_head;
1238 uint16_t queue_tail;
1239 uint16_t transmit_execution_list_next;
1240 uint16_t transmit_execution_list_previous;
1241 uint16_t common_features;
1242 uint16_t total_concurrent_sequences;
1243 uint16_t RO_by_information_category;
1246 uint16_t receive_data_size;
1247 uint16_t concurrent_sequences;
1248 uint16_t open_sequences_per_exchange;
1249 uint16_t lun_abort_flags;
1250 uint16_t lun_stop_flags;
1251 uint16_t stop_queue_head;
1252 uint16_t stop_queue_tail;
1253 uint16_t port_retry_timer;
1254 uint16_t next_sequence_id;
1255 uint16_t frame_count;
1256 uint16_t PRLI_payload_length;
1257 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1258 /* Bits 15-0 of word 0 */
1259 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1260 /* Bits 15-0 of word 3 */
1262 uint16_t extended_lun_info_list_pointer;
1263 uint16_t extended_lun_stop_list_pointer;
1267 * Port database slave/master states
1269 #define PD_STATE_DISCOVERY 0
1270 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1271 #define PD_STATE_PORT_LOGIN 2
1272 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1273 #define PD_STATE_PROCESS_LOGIN 4
1274 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1275 #define PD_STATE_PORT_LOGGED_IN 6
1276 #define PD_STATE_PORT_UNAVAILABLE 7
1277 #define PD_STATE_PROCESS_LOGOUT 8
1278 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1279 #define PD_STATE_PORT_LOGOUT 10
1280 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1283 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1284 #define QLA_ZIO_DISABLED 0
1285 #define QLA_ZIO_DEFAULT_TIMER 2
1288 * ISP Initialization Control Block.
1289 * Little endian except where noted.
1291 #define ICB_VERSION 1
1297 * LSB BIT 0 = Enable Hard Loop Id
1298 * LSB BIT 1 = Enable Fairness
1299 * LSB BIT 2 = Enable Full-Duplex
1300 * LSB BIT 3 = Enable Fast Posting
1301 * LSB BIT 4 = Enable Target Mode
1302 * LSB BIT 5 = Disable Initiator Mode
1303 * LSB BIT 6 = Enable ADISC
1304 * LSB BIT 7 = Enable Target Inquiry Data
1306 * MSB BIT 0 = Enable PDBC Notify
1307 * MSB BIT 1 = Non Participating LIP
1308 * MSB BIT 2 = Descending Loop ID Search
1309 * MSB BIT 3 = Acquire Loop ID in LIPA
1310 * MSB BIT 4 = Stop PortQ on Full Status
1311 * MSB BIT 5 = Full Login after LIP
1312 * MSB BIT 6 = Node Name Option
1313 * MSB BIT 7 = Ext IFWCB enable bit
1315 uint8_t firmware_options[2];
1317 uint16_t frame_payload_size;
1318 uint16_t max_iocb_allocation;
1319 uint16_t execution_throttle;
1320 uint8_t retry_count;
1321 uint8_t retry_delay; /* unused */
1322 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1323 uint16_t hard_address;
1324 uint8_t inquiry_data;
1325 uint8_t login_timeout;
1326 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1328 uint16_t request_q_outpointer;
1329 uint16_t response_q_inpointer;
1330 uint16_t request_q_length;
1331 uint16_t response_q_length;
1332 __le64 request_q_address __packed;
1333 __le64 response_q_address __packed;
1335 uint16_t lun_enables;
1336 uint8_t command_resource_count;
1337 uint8_t immediate_notify_resource_count;
1339 uint8_t reserved_2[2];
1342 * LSB BIT 0 = Timer Operation mode bit 0
1343 * LSB BIT 1 = Timer Operation mode bit 1
1344 * LSB BIT 2 = Timer Operation mode bit 2
1345 * LSB BIT 3 = Timer Operation mode bit 3
1346 * LSB BIT 4 = Init Config Mode bit 0
1347 * LSB BIT 5 = Init Config Mode bit 1
1348 * LSB BIT 6 = Init Config Mode bit 2
1349 * LSB BIT 7 = Enable Non part on LIHA failure
1351 * MSB BIT 0 = Enable class 2
1352 * MSB BIT 1 = Enable ACK0
1355 * MSB BIT 4 = FC Tape Enable
1356 * MSB BIT 5 = Enable FC Confirm
1357 * MSB BIT 6 = Enable command queuing in target mode
1358 * MSB BIT 7 = No Logo On Link Down
1360 uint8_t add_firmware_options[2];
1362 uint8_t response_accumulation_timer;
1363 uint8_t interrupt_delay_timer;
1366 * LSB BIT 0 = Enable Read xfr_rdy
1367 * LSB BIT 1 = Soft ID only
1370 * LSB BIT 4 = FCP RSP Payload [0]
1371 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1372 * LSB BIT 6 = Enable Out-of-Order frame handling
1373 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1375 * MSB BIT 0 = Sbus enable - 2300
1379 * MSB BIT 4 = LED mode
1380 * MSB BIT 5 = enable 50 ohm termination
1381 * MSB BIT 6 = Data Rate (2300 only)
1382 * MSB BIT 7 = Data Rate (2300 only)
1384 uint8_t special_options[2];
1386 uint8_t reserved_3[26];
1390 * Get Link Status mailbox command return buffer.
1392 #define GLSO_SEND_RPS BIT_0
1393 #define GLSO_USE_DID BIT_3
1395 struct link_statistics {
1396 uint32_t link_fail_cnt;
1397 uint32_t loss_sync_cnt;
1398 uint32_t loss_sig_cnt;
1399 uint32_t prim_seq_err_cnt;
1400 uint32_t inval_xmit_word_cnt;
1401 uint32_t inval_crc_cnt;
1403 uint32_t link_up_cnt;
1404 uint32_t link_down_loop_init_tmo;
1405 uint32_t link_down_los;
1406 uint32_t link_down_loss_rcv_clk;
1407 uint32_t reserved0[5];
1408 uint32_t port_cfg_chg;
1409 uint32_t reserved1[11];
1410 uint32_t rsp_q_full;
1411 uint32_t atio_q_full;
1413 uint32_t els_proto_err;
1417 uint32_t discarded_frames;
1418 uint32_t dropped_frames;
1421 uint32_t reserved4[4];
1423 uint32_t rcv_exfail;
1425 uint32_t seq_frm_miss;
1428 uint32_t nport_full;
1431 uint32_t fpm_recv_word_cnt_lo;
1432 uint32_t fpm_recv_word_cnt_hi;
1433 uint32_t fpm_disc_word_cnt_lo;
1434 uint32_t fpm_disc_word_cnt_hi;
1435 uint32_t fpm_xmit_word_cnt_lo;
1436 uint32_t fpm_xmit_word_cnt_hi;
1437 uint32_t reserved6[70];
1441 * NVRAM Command values.
1443 #define NV_START_BIT BIT_2
1444 #define NV_WRITE_OP (BIT_26+BIT_24)
1445 #define NV_READ_OP (BIT_26+BIT_25)
1446 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1447 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1448 #define NV_DELAY_COUNT 10
1451 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1458 uint8_t nvram_version;
1462 * NVRAM RISC parameter block
1464 uint8_t parameter_block_version;
1468 * LSB BIT 0 = Enable Hard Loop Id
1469 * LSB BIT 1 = Enable Fairness
1470 * LSB BIT 2 = Enable Full-Duplex
1471 * LSB BIT 3 = Enable Fast Posting
1472 * LSB BIT 4 = Enable Target Mode
1473 * LSB BIT 5 = Disable Initiator Mode
1474 * LSB BIT 6 = Enable ADISC
1475 * LSB BIT 7 = Enable Target Inquiry Data
1477 * MSB BIT 0 = Enable PDBC Notify
1478 * MSB BIT 1 = Non Participating LIP
1479 * MSB BIT 2 = Descending Loop ID Search
1480 * MSB BIT 3 = Acquire Loop ID in LIPA
1481 * MSB BIT 4 = Stop PortQ on Full Status
1482 * MSB BIT 5 = Full Login after LIP
1483 * MSB BIT 6 = Node Name Option
1484 * MSB BIT 7 = Ext IFWCB enable bit
1486 uint8_t firmware_options[2];
1488 uint16_t frame_payload_size;
1489 uint16_t max_iocb_allocation;
1490 uint16_t execution_throttle;
1491 uint8_t retry_count;
1492 uint8_t retry_delay; /* unused */
1493 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1494 uint16_t hard_address;
1495 uint8_t inquiry_data;
1496 uint8_t login_timeout;
1497 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1500 * LSB BIT 0 = Timer Operation mode bit 0
1501 * LSB BIT 1 = Timer Operation mode bit 1
1502 * LSB BIT 2 = Timer Operation mode bit 2
1503 * LSB BIT 3 = Timer Operation mode bit 3
1504 * LSB BIT 4 = Init Config Mode bit 0
1505 * LSB BIT 5 = Init Config Mode bit 1
1506 * LSB BIT 6 = Init Config Mode bit 2
1507 * LSB BIT 7 = Enable Non part on LIHA failure
1509 * MSB BIT 0 = Enable class 2
1510 * MSB BIT 1 = Enable ACK0
1513 * MSB BIT 4 = FC Tape Enable
1514 * MSB BIT 5 = Enable FC Confirm
1515 * MSB BIT 6 = Enable command queuing in target mode
1516 * MSB BIT 7 = No Logo On Link Down
1518 uint8_t add_firmware_options[2];
1520 uint8_t response_accumulation_timer;
1521 uint8_t interrupt_delay_timer;
1524 * LSB BIT 0 = Enable Read xfr_rdy
1525 * LSB BIT 1 = Soft ID only
1528 * LSB BIT 4 = FCP RSP Payload [0]
1529 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1530 * LSB BIT 6 = Enable Out-of-Order frame handling
1531 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1533 * MSB BIT 0 = Sbus enable - 2300
1537 * MSB BIT 4 = LED mode
1538 * MSB BIT 5 = enable 50 ohm termination
1539 * MSB BIT 6 = Data Rate (2300 only)
1540 * MSB BIT 7 = Data Rate (2300 only)
1542 uint8_t special_options[2];
1544 /* Reserved for expanded RISC parameter block */
1545 uint8_t reserved_2[22];
1548 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1549 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1550 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1551 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1552 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1553 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1554 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1555 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1557 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1558 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1559 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1560 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1561 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1562 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1563 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1564 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1566 * LSB BIT 0 = Output Swing 1G bit 0
1567 * LSB BIT 1 = Output Swing 1G bit 1
1568 * LSB BIT 2 = Output Swing 1G bit 2
1569 * LSB BIT 3 = Output Emphasis 1G bit 0
1570 * LSB BIT 4 = Output Emphasis 1G bit 1
1571 * LSB BIT 5 = Output Swing 2G bit 0
1572 * LSB BIT 6 = Output Swing 2G bit 1
1573 * LSB BIT 7 = Output Swing 2G bit 2
1575 * MSB BIT 0 = Output Emphasis 2G bit 0
1576 * MSB BIT 1 = Output Emphasis 2G bit 1
1577 * MSB BIT 2 = Output Enable
1584 uint8_t seriallink_options[4];
1587 * NVRAM host parameter block
1589 * LSB BIT 0 = Enable spinup delay
1590 * LSB BIT 1 = Disable BIOS
1591 * LSB BIT 2 = Enable Memory Map BIOS
1592 * LSB BIT 3 = Enable Selectable Boot
1593 * LSB BIT 4 = Disable RISC code load
1594 * LSB BIT 5 = Set cache line size 1
1595 * LSB BIT 6 = PCI Parity Disable
1596 * LSB BIT 7 = Enable extended logging
1598 * MSB BIT 0 = Enable 64bit addressing
1599 * MSB BIT 1 = Enable lip reset
1600 * MSB BIT 2 = Enable lip full login
1601 * MSB BIT 3 = Enable target reset
1602 * MSB BIT 4 = Enable database storage
1603 * MSB BIT 5 = Enable cache flush read
1604 * MSB BIT 6 = Enable database load
1605 * MSB BIT 7 = Enable alternate WWN
1609 uint8_t boot_node_name[WWN_SIZE];
1610 uint8_t boot_lun_number;
1611 uint8_t reset_delay;
1612 uint8_t port_down_retry_count;
1613 uint8_t boot_id_number;
1614 uint16_t max_luns_per_target;
1615 uint8_t fcode_boot_port_name[WWN_SIZE];
1616 uint8_t alternate_port_name[WWN_SIZE];
1617 uint8_t alternate_node_name[WWN_SIZE];
1620 * BIT 0 = Selective Login
1621 * BIT 1 = Alt-Boot Enable
1623 * BIT 3 = Boot Order List
1625 * BIT 5 = Selective LUN
1629 uint8_t efi_parameters;
1631 uint8_t link_down_timeout;
1633 uint8_t adapter_id[16];
1635 uint8_t alt1_boot_node_name[WWN_SIZE];
1636 uint16_t alt1_boot_lun_number;
1637 uint8_t alt2_boot_node_name[WWN_SIZE];
1638 uint16_t alt2_boot_lun_number;
1639 uint8_t alt3_boot_node_name[WWN_SIZE];
1640 uint16_t alt3_boot_lun_number;
1641 uint8_t alt4_boot_node_name[WWN_SIZE];
1642 uint16_t alt4_boot_lun_number;
1643 uint8_t alt5_boot_node_name[WWN_SIZE];
1644 uint16_t alt5_boot_lun_number;
1645 uint8_t alt6_boot_node_name[WWN_SIZE];
1646 uint16_t alt6_boot_lun_number;
1647 uint8_t alt7_boot_node_name[WWN_SIZE];
1648 uint16_t alt7_boot_lun_number;
1650 uint8_t reserved_3[2];
1652 /* Offset 200-215 : Model Number */
1653 uint8_t model_number[16];
1655 /* OEM related items */
1656 uint8_t oem_specific[16];
1659 * NVRAM Adapter Features offset 232-239
1661 * LSB BIT 0 = External GBIC
1662 * LSB BIT 1 = Risc RAM parity
1663 * LSB BIT 2 = Buffer Plus Module
1664 * LSB BIT 3 = Multi Chip Adapter
1665 * LSB BIT 4 = Internal connector
1679 uint8_t adapter_features[2];
1681 uint8_t reserved_4[16];
1683 /* Subsystem vendor ID for ISP2200 */
1684 uint16_t subsystem_vendor_id_2200;
1686 /* Subsystem device ID for ISP2200 */
1687 uint16_t subsystem_device_id_2200;
1694 * ISP queue - response queue entry definition.
1697 uint8_t entry_type; /* Entry type. */
1698 uint8_t entry_count; /* Entry count. */
1699 uint8_t sys_define; /* System defined. */
1700 uint8_t entry_status; /* Entry Status. */
1701 uint32_t handle; /* System defined handle */
1704 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1708 * ISP queue - ATIO queue entry definition.
1711 uint8_t entry_type; /* Entry type. */
1712 uint8_t entry_count; /* Entry count. */
1713 __le16 attr_n_length;
1716 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1727 #define SET_TARGET_ID(ha, to, from) \
1729 if (HAS_EXTENDED_IDS(ha)) \
1730 to.extended = cpu_to_le16(from); \
1732 to.id.standard = (uint8_t)from; \
1736 * ISP queue - command entry structure definition.
1738 #define COMMAND_TYPE 0x11 /* Command entry */
1740 uint8_t entry_type; /* Entry type. */
1741 uint8_t entry_count; /* Entry count. */
1742 uint8_t sys_define; /* System defined. */
1743 uint8_t entry_status; /* Entry Status. */
1744 uint32_t handle; /* System handle. */
1745 target_id_t target; /* SCSI ID */
1746 uint16_t lun; /* SCSI LUN */
1747 uint16_t control_flags; /* Control flags. */
1748 #define CF_WRITE BIT_6
1749 #define CF_READ BIT_5
1750 #define CF_SIMPLE_TAG BIT_3
1751 #define CF_ORDERED_TAG BIT_2
1752 #define CF_HEAD_TAG BIT_1
1753 uint16_t reserved_1;
1754 uint16_t timeout; /* Command timeout. */
1755 uint16_t dseg_count; /* Data segment count. */
1756 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1757 uint32_t byte_count; /* Total byte count. */
1759 struct dsd32 dsd32[3];
1760 struct dsd64 dsd64[2];
1765 * ISP queue - 64-Bit addressing, command entry structure definition.
1767 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1769 uint8_t entry_type; /* Entry type. */
1770 uint8_t entry_count; /* Entry count. */
1771 uint8_t sys_define; /* System defined. */
1772 uint8_t entry_status; /* Entry Status. */
1773 uint32_t handle; /* System handle. */
1774 target_id_t target; /* SCSI ID */
1775 uint16_t lun; /* SCSI LUN */
1776 uint16_t control_flags; /* Control flags. */
1777 uint16_t reserved_1;
1778 uint16_t timeout; /* Command timeout. */
1779 uint16_t dseg_count; /* Data segment count. */
1780 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1781 uint32_t byte_count; /* Total byte count. */
1782 struct dsd64 dsd[2];
1783 } cmd_a64_entry_t, request_t;
1786 * ISP queue - continuation entry structure definition.
1788 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1790 uint8_t entry_type; /* Entry type. */
1791 uint8_t entry_count; /* Entry count. */
1792 uint8_t sys_define; /* System defined. */
1793 uint8_t entry_status; /* Entry Status. */
1795 struct dsd32 dsd[7];
1799 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1801 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1803 uint8_t entry_type; /* Entry type. */
1804 uint8_t entry_count; /* Entry count. */
1805 uint8_t sys_define; /* System defined. */
1806 uint8_t entry_status; /* Entry Status. */
1807 struct dsd64 dsd[5];
1810 #define PO_MODE_DIF_INSERT 0
1811 #define PO_MODE_DIF_REMOVE 1
1812 #define PO_MODE_DIF_PASS 2
1813 #define PO_MODE_DIF_REPLACE 3
1814 #define PO_MODE_DIF_TCP_CKSUM 6
1815 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1816 #define PO_DISABLE_GUARD_CHECK BIT_4
1817 #define PO_DISABLE_INCR_REF_TAG BIT_5
1818 #define PO_DIS_HEADER_MODE BIT_7
1819 #define PO_ENABLE_DIF_BUNDLING BIT_8
1820 #define PO_DIS_FRAME_MODE BIT_9
1821 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1822 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1824 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1825 #define PO_DIS_REF_TAG_REPL BIT_13
1826 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1827 #define PO_DIS_REF_TAG_VALD BIT_15
1830 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1832 struct crc_context {
1833 uint32_t handle; /* System handle. */
1836 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1837 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1838 __le16 guard_seed; /* Initial Guard Seed */
1839 __le16 prot_opts; /* Requested Data Protection Mode */
1840 __le16 blk_size; /* Data size in bytes */
1841 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1843 __le32 byte_count; /* Total byte count/ total data
1847 uint32_t reserved_1;
1848 uint16_t reserved_2;
1849 uint16_t reserved_3;
1850 uint32_t reserved_4;
1851 struct dsd64 data_dsd;
1852 uint32_t reserved_5[2];
1853 uint32_t reserved_6;
1856 __le32 dif_byte_count; /* Total DIF byte
1858 uint16_t reserved_1;
1859 __le16 dseg_count; /* Data segment count */
1860 uint32_t reserved_2;
1861 struct dsd64 data_dsd;
1862 struct dsd64 dif_dsd;
1866 struct fcp_cmnd fcp_cmnd;
1867 dma_addr_t crc_ctx_dma;
1868 /* List of DMA context transfers */
1869 struct list_head dsd_list;
1871 /* List of DIF Bundling context DMA address */
1872 struct list_head ldif_dsd_list;
1875 struct list_head ldif_dma_hndl_list;
1878 /* This structure should not exceed 512 bytes */
1881 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1882 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1885 * ISP queue - status entry structure definition.
1887 #define STATUS_TYPE 0x03 /* Status entry. */
1889 uint8_t entry_type; /* Entry type. */
1890 uint8_t entry_count; /* Entry count. */
1891 uint8_t sys_define; /* System defined. */
1892 uint8_t entry_status; /* Entry Status. */
1893 uint32_t handle; /* System handle. */
1894 uint16_t scsi_status; /* SCSI status. */
1895 uint16_t comp_status; /* Completion status. */
1896 uint16_t state_flags; /* State flags. */
1897 uint16_t status_flags; /* Status flags. */
1898 uint16_t rsp_info_len; /* Response Info Length. */
1899 uint16_t req_sense_length; /* Request sense data length. */
1900 uint32_t residual_length; /* Residual transfer length. */
1901 uint8_t rsp_info[8]; /* FCP response information. */
1902 uint8_t req_sense_data[32]; /* Request sense data. */
1906 * Status entry entry status
1908 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1909 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1910 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1911 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1912 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1913 #define RF_BUSY BIT_1 /* Busy */
1914 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1915 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1916 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1920 * Status entry SCSI status bit definitions.
1922 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1923 #define SS_RESIDUAL_UNDER BIT_11
1924 #define SS_RESIDUAL_OVER BIT_10
1925 #define SS_SENSE_LEN_VALID BIT_9
1926 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1927 #define SS_SCSI_STATUS_BYTE 0xff
1929 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1930 #define SS_BUSY_CONDITION BIT_3
1931 #define SS_CONDITION_MET BIT_2
1932 #define SS_CHECK_CONDITION BIT_1
1935 * Status entry completion status
1937 #define CS_COMPLETE 0x0 /* No errors */
1938 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1939 #define CS_DMA 0x2 /* A DMA direction error. */
1940 #define CS_TRANSPORT 0x3 /* Transport error. */
1941 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1942 #define CS_ABORTED 0x5 /* System aborted command. */
1943 #define CS_TIMEOUT 0x6 /* Timeout error. */
1944 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1945 #define CS_DIF_ERROR 0xC /* DIF error detected */
1947 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1948 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1949 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1950 /* (selection timeout) */
1951 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1952 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1953 #define CS_PORT_BUSY 0x2B /* Port Busy */
1954 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1955 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
1957 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1958 #define CS_UNKNOWN 0x81 /* Driver defined */
1959 #define CS_RETRY 0x82 /* Driver defined */
1960 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1962 #define CS_BIDIR_RD_OVERRUN 0x700
1963 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1964 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1965 #define CS_BIDIR_RD_UNDERRUN 0x1500
1966 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1967 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1968 #define CS_BIDIR_DMA 0x200
1970 * Status entry status flags
1972 #define SF_ABTS_TERMINATED BIT_10
1973 #define SF_LOGOUT_SENT BIT_13
1976 * ISP queue - status continuation entry structure definition.
1978 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1980 uint8_t entry_type; /* Entry type. */
1981 uint8_t entry_count; /* Entry count. */
1982 uint8_t sys_define; /* System defined. */
1983 uint8_t entry_status; /* Entry Status. */
1984 uint8_t data[60]; /* data */
1988 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1989 * structure definition.
1991 #define STATUS_TYPE_21 0x21 /* Status entry. */
1993 uint8_t entry_type; /* Entry type. */
1994 uint8_t entry_count; /* Entry count. */
1995 uint8_t handle_count; /* Handle count. */
1996 uint8_t entry_status; /* Entry Status. */
1997 uint32_t handle[15]; /* System handles. */
2001 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
2002 * structure definition.
2004 #define STATUS_TYPE_22 0x22 /* Status entry. */
2006 uint8_t entry_type; /* Entry type. */
2007 uint8_t entry_count; /* Entry count. */
2008 uint8_t handle_count; /* Handle count. */
2009 uint8_t entry_status; /* Entry Status. */
2010 uint16_t handle[30]; /* System handles. */
2014 * ISP queue - marker entry structure definition.
2016 #define MARKER_TYPE 0x04 /* Marker entry. */
2018 uint8_t entry_type; /* Entry type. */
2019 uint8_t entry_count; /* Entry count. */
2020 uint8_t handle_count; /* Handle count. */
2021 uint8_t entry_status; /* Entry Status. */
2022 uint32_t sys_define_2; /* System defined. */
2023 target_id_t target; /* SCSI ID */
2024 uint8_t modifier; /* Modifier (7-0). */
2025 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2026 #define MK_SYNC_ID 1 /* Synchronize ID */
2027 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2028 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2029 /* clear port changed, */
2030 /* use sequence number. */
2032 uint16_t sequence_number; /* Sequence number of event */
2033 uint16_t lun; /* SCSI LUN */
2034 uint8_t reserved_2[48];
2038 * ISP queue - Management Server entry structure definition.
2040 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2042 uint8_t entry_type; /* Entry type. */
2043 uint8_t entry_count; /* Entry count. */
2044 uint8_t handle_count; /* Handle count. */
2045 uint8_t entry_status; /* Entry Status. */
2046 uint32_t handle1; /* System handle. */
2047 target_id_t loop_id;
2049 uint16_t control_flags; /* Control flags. */
2052 uint16_t cmd_dsd_count;
2053 uint16_t total_dsd_count;
2059 uint32_t rsp_bytecount;
2060 uint32_t req_bytecount;
2061 struct dsd64 req_dsd;
2062 struct dsd64 rsp_dsd;
2067 * ISP queue - Mailbox Command entry structure definition.
2069 #define MBX_IOCB_TYPE 0x39
2072 uint8_t entry_count;
2073 uint8_t sys_define1;
2074 /* Use sys_define1 for source type */
2075 #define SOURCE_SCSI 0x00
2076 #define SOURCE_IP 0x01
2077 #define SOURCE_VI 0x02
2078 #define SOURCE_SCTP 0x03
2079 #define SOURCE_MP 0x04
2080 #define SOURCE_MPIOCTL 0x05
2081 #define SOURCE_ASYNC_IOCB 0x07
2083 uint8_t entry_status;
2086 target_id_t loop_id;
2089 uint16_t state_flags;
2090 uint16_t status_flags;
2092 uint32_t sys_define2[2];
2102 uint32_t reserved_2[2];
2103 uint8_t node_name[WWN_SIZE];
2104 uint8_t port_name[WWN_SIZE];
2107 #ifndef IMMED_NOTIFY_TYPE
2108 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2110 * ISP queue - immediate notify entry structure definition.
2111 * This is sent by the ISP to the Target driver.
2112 * This IOCB would have report of events sent by the
2113 * initiator, that needs to be handled by the target
2114 * driver immediately.
2116 struct imm_ntfy_from_isp {
2117 uint8_t entry_type; /* Entry type. */
2118 uint8_t entry_count; /* Entry count. */
2119 uint8_t sys_define; /* System defined. */
2120 uint8_t entry_status; /* Entry Status. */
2123 uint32_t sys_define_2; /* System defined. */
2128 uint16_t status_modifier;
2130 uint16_t task_flags;
2133 uint32_t srr_rel_offs;
2135 #define SRR_IU_DATA_IN 0x1
2136 #define SRR_IU_DATA_OUT 0x5
2137 #define SRR_IU_STATUS 0x7
2139 uint8_t reserved_2[28];
2143 uint16_t nport_handle;
2144 uint16_t reserved_2;
2146 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2147 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2150 uint8_t status_subcode;
2152 uint32_t exchange_address;
2153 uint32_t srr_rel_offs;
2158 uint8_t node_name[8];
2159 } plogi; /* PLOGI/ADISC/PDISC */
2161 /* PRLI word 3 bit 0-15 */
2168 uint16_t nport_handle;
2172 uint8_t port_name[8];
2175 uint32_t reserved_5;
2180 uint16_t reserved_7;
2186 * ISP request and response queue entry sizes
2188 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2189 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2194 * Switch info gathering structure.
2198 uint8_t node_name[WWN_SIZE];
2199 uint8_t port_name[WWN_SIZE];
2200 uint8_t fabric_port_name[WWN_SIZE];
2203 uint8_t fc4f_nvme; /* nvme fc4 feature bits */
2207 #define FC4_TYPE_FCP_SCSI 0x08
2208 #define FC4_TYPE_NVME 0x28
2209 #define FC4_TYPE_OTHER 0x0
2210 #define FC4_TYPE_UNKNOWN 0xff
2212 /* mailbox command 4G & above */
2213 struct mbx_24xx_entry {
2215 uint8_t entry_count;
2216 uint8_t sys_define1;
2217 uint8_t entry_status;
2222 #define IOCB_SIZE 64
2225 * Fibre channel port type.
2234 FCT_NVME_INITIATOR = 0x10,
2235 FCT_NVME_TARGET = 0x20,
2236 FCT_NVME_DISCOVERY = 0x40,
2240 enum qla_sess_deletion {
2241 QLA_SESS_DELETION_NONE = 0,
2242 QLA_SESS_DELETION_IN_PROGRESS,
2246 enum qlt_plogi_link_t {
2247 QLT_PLOGI_LINK_SAME_WWN,
2248 QLT_PLOGI_LINK_CONFLICT,
2252 struct qlt_plogi_ack_t {
2253 struct list_head list;
2254 struct imm_ntfy_from_isp iocb;
2260 struct ct_sns_desc {
2261 struct ct_sns_pkt *ct_sns;
2262 dma_addr_t ct_sns_dma;
2265 enum discovery_state {
2278 enum login_state { /* FW control Target side */
2279 DSC_LS_LLIOCB_SENT = 2,
2284 DSC_LS_PORT_UNAVAIL,
2285 DSC_LS_PRLO_PEND = 9,
2289 enum fcport_mgt_event {
2292 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */
2302 FCME_ELS_PLOGI_DONE,
2305 enum rscn_addr_format {
2313 * Fibre channel port structure.
2315 typedef struct fc_port {
2316 struct list_head list;
2317 struct scsi_qla_host *vha;
2319 uint8_t node_name[WWN_SIZE];
2320 uint8_t port_name[WWN_SIZE];
2323 uint16_t old_loop_id;
2325 unsigned int conf_compl_supported:1;
2326 unsigned int deleted:2;
2327 unsigned int free_pending:1;
2328 unsigned int local:1;
2329 unsigned int logout_on_delete:1;
2330 unsigned int logo_ack_needed:1;
2331 unsigned int keep_nport_handle:1;
2332 unsigned int send_els_logo:1;
2333 unsigned int login_pause:1;
2334 unsigned int login_succ:1;
2335 unsigned int query:1;
2336 unsigned int id_changed:1;
2337 unsigned int scan_needed:1;
2339 struct work_struct nvme_del_work;
2340 struct completion nvme_del_done;
2341 uint32_t nvme_prli_service_param;
2342 #define NVME_PRLI_SP_CONF BIT_7
2343 #define NVME_PRLI_SP_INITIATOR BIT_5
2344 #define NVME_PRLI_SP_TARGET BIT_4
2345 #define NVME_PRLI_SP_DISCOVERY BIT_3
2346 #define NVME_PRLI_SP_FIRST_BURST BIT_0
2348 uint32_t nvme_first_burst_size;
2349 #define NVME_FLAG_REGISTERED 4
2350 #define NVME_FLAG_DELETING 2
2351 #define NVME_FLAG_RESETTING 1
2353 struct fc_port *conflict;
2354 unsigned char logout_completed;
2357 struct se_session *se_sess;
2358 struct kref sess_kref;
2359 struct qla_tgt *tgt;
2360 unsigned long expires;
2361 struct list_head del_list_entry;
2362 struct work_struct free_work;
2363 struct work_struct reg_work;
2364 uint64_t jiffies_at_registration;
2365 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2368 uint16_t old_tgt_id;
2369 uint16_t sec_since_registration;
2373 uint8_t fabric_port_name[WWN_SIZE];
2376 fc_port_type_t port_type;
2383 struct fc_rport *rport, *drport;
2384 u32 supported_classes;
2391 unsigned long last_queue_full;
2392 unsigned long last_ramp_up;
2396 struct nvme_fc_remote_port *nvme_remote_port;
2398 unsigned long retry_delay_timestamp;
2399 struct qla_tgt_sess *tgt_session;
2400 struct ct_sns_desc ct_desc;
2401 enum discovery_state disc_state;
2402 enum discovery_state next_disc_state;
2403 enum login_state fw_login_state;
2404 unsigned long dm_login_expire;
2405 unsigned long plogi_nack_done_deadline;
2407 u32 login_gen, last_login_gen;
2408 u32 rscn_gen, last_rscn_gen;
2410 struct list_head gnl_entry;
2411 struct work_struct del_work;
2413 u8 current_login_state;
2414 u8 last_login_state;
2415 u16 n2n_link_reset_cnt;
2419 #define QLA_FCPORT_SCAN 1
2420 #define QLA_FCPORT_FOUND 2
2423 enum fcport_mgt_event event;
2428 u8 port_name[WWN_SIZE];
2435 * Fibre channel port/lun states.
2437 #define FCS_UNCONFIGURED 1
2438 #define FCS_DEVICE_DEAD 2
2439 #define FCS_DEVICE_LOST 3
2440 #define FCS_ONLINE 4
2442 extern const char *const port_state_str[5];
2447 #define FCF_FABRIC_DEVICE BIT_0
2448 #define FCF_LOGIN_NEEDED BIT_1
2449 #define FCF_FCP2_DEVICE BIT_2
2450 #define FCF_ASYNC_SENT BIT_3
2451 #define FCF_CONF_COMP_SUPPORTED BIT_4
2452 #define FCF_ASYNC_ACTIVE BIT_5
2454 /* No loop ID flag. */
2455 #define FC_NO_LOOP_ID 0x1000
2460 * NOTE: All structures are big-endian in form.
2463 #define CT_REJECT_RESPONSE 0x8001
2464 #define CT_ACCEPT_RESPONSE 0x8002
2465 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2466 #define CT_REASON_CANNOT_PERFORM 0x09
2467 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2468 #define CT_EXPL_ALREADY_REGISTERED 0x10
2469 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2470 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2471 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2472 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2473 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2474 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2475 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2476 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2477 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2478 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2479 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2481 #define NS_N_PORT_TYPE 0x01
2482 #define NS_NL_PORT_TYPE 0x02
2483 #define NS_NX_PORT_TYPE 0x7F
2485 #define GA_NXT_CMD 0x100
2486 #define GA_NXT_REQ_SIZE (16 + 4)
2487 #define GA_NXT_RSP_SIZE (16 + 620)
2489 #define GPN_FT_CMD 0x172
2490 #define GPN_FT_REQ_SIZE (16 + 4)
2491 #define GNN_FT_CMD 0x173
2492 #define GNN_FT_REQ_SIZE (16 + 4)
2494 #define GID_PT_CMD 0x1A1
2495 #define GID_PT_REQ_SIZE (16 + 4)
2497 #define GPN_ID_CMD 0x112
2498 #define GPN_ID_REQ_SIZE (16 + 4)
2499 #define GPN_ID_RSP_SIZE (16 + 8)
2501 #define GNN_ID_CMD 0x113
2502 #define GNN_ID_REQ_SIZE (16 + 4)
2503 #define GNN_ID_RSP_SIZE (16 + 8)
2505 #define GFT_ID_CMD 0x117
2506 #define GFT_ID_REQ_SIZE (16 + 4)
2507 #define GFT_ID_RSP_SIZE (16 + 32)
2509 #define GID_PN_CMD 0x121
2510 #define GID_PN_REQ_SIZE (16 + 8)
2511 #define GID_PN_RSP_SIZE (16 + 4)
2513 #define RFT_ID_CMD 0x217
2514 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2515 #define RFT_ID_RSP_SIZE 16
2517 #define RFF_ID_CMD 0x21F
2518 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2519 #define RFF_ID_RSP_SIZE 16
2521 #define RNN_ID_CMD 0x213
2522 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2523 #define RNN_ID_RSP_SIZE 16
2525 #define RSNN_NN_CMD 0x239
2526 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2527 #define RSNN_NN_RSP_SIZE 16
2529 #define GFPN_ID_CMD 0x11C
2530 #define GFPN_ID_REQ_SIZE (16 + 4)
2531 #define GFPN_ID_RSP_SIZE (16 + 8)
2533 #define GPSC_CMD 0x127
2534 #define GPSC_REQ_SIZE (16 + 8)
2535 #define GPSC_RSP_SIZE (16 + 2 + 2)
2537 #define GFF_ID_CMD 0x011F
2538 #define GFF_ID_REQ_SIZE (16 + 4)
2539 #define GFF_ID_RSP_SIZE (16 + 128)
2542 * HBA attribute types.
2544 #define FDMI_HBA_ATTR_COUNT 9
2545 #define FDMIV2_HBA_ATTR_COUNT 17
2546 #define FDMI_HBA_NODE_NAME 0x1
2547 #define FDMI_HBA_MANUFACTURER 0x2
2548 #define FDMI_HBA_SERIAL_NUMBER 0x3
2549 #define FDMI_HBA_MODEL 0x4
2550 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2551 #define FDMI_HBA_HARDWARE_VERSION 0x6
2552 #define FDMI_HBA_DRIVER_VERSION 0x7
2553 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2554 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2555 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2556 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2557 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2558 #define FDMI_HBA_VENDOR_ID 0xd
2559 #define FDMI_HBA_NUM_PORTS 0xe
2560 #define FDMI_HBA_FABRIC_NAME 0xf
2561 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2562 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2564 struct ct_fdmi_hba_attr {
2568 uint8_t node_name[WWN_SIZE];
2569 uint8_t manufacturer[64];
2570 uint8_t serial_num[32];
2571 uint8_t model[16+1];
2572 uint8_t model_desc[80];
2573 uint8_t hw_version[32];
2574 uint8_t driver_version[32];
2575 uint8_t orom_version[16];
2576 uint8_t fw_version[32];
2577 uint8_t os_version[128];
2578 uint32_t max_ct_len;
2582 struct ct_fdmi_hba_attributes {
2584 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2587 struct ct_fdmiv2_hba_attr {
2591 uint8_t node_name[WWN_SIZE];
2592 uint8_t manufacturer[64];
2593 uint8_t serial_num[32];
2594 uint8_t model[16+1];
2595 uint8_t model_desc[80];
2596 uint8_t hw_version[16];
2597 uint8_t driver_version[32];
2598 uint8_t orom_version[16];
2599 uint8_t fw_version[32];
2600 uint8_t os_version[128];
2601 uint32_t max_ct_len;
2602 uint8_t sym_name[256];
2605 uint8_t fabric_name[WWN_SIZE];
2606 uint8_t bios_name[32];
2607 uint8_t vendor_identifier[8];
2611 struct ct_fdmiv2_hba_attributes {
2613 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2617 * Port attribute types.
2619 #define FDMI_PORT_ATTR_COUNT 6
2620 #define FDMIV2_PORT_ATTR_COUNT 16
2621 #define FDMI_PORT_FC4_TYPES 0x1
2622 #define FDMI_PORT_SUPPORT_SPEED 0x2
2623 #define FDMI_PORT_CURRENT_SPEED 0x3
2624 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2625 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2626 #define FDMI_PORT_HOST_NAME 0x6
2627 #define FDMI_PORT_NODE_NAME 0x7
2628 #define FDMI_PORT_NAME 0x8
2629 #define FDMI_PORT_SYM_NAME 0x9
2630 #define FDMI_PORT_TYPE 0xa
2631 #define FDMI_PORT_SUPP_COS 0xb
2632 #define FDMI_PORT_FABRIC_NAME 0xc
2633 #define FDMI_PORT_FC4_TYPE 0xd
2634 #define FDMI_PORT_STATE 0x101
2635 #define FDMI_PORT_COUNT 0x102
2636 #define FDMI_PORT_ID 0x103
2638 #define FDMI_PORT_SPEED_1GB 0x1
2639 #define FDMI_PORT_SPEED_2GB 0x2
2640 #define FDMI_PORT_SPEED_10GB 0x4
2641 #define FDMI_PORT_SPEED_4GB 0x8
2642 #define FDMI_PORT_SPEED_8GB 0x10
2643 #define FDMI_PORT_SPEED_16GB 0x20
2644 #define FDMI_PORT_SPEED_32GB 0x40
2645 #define FDMI_PORT_SPEED_64GB 0x80
2646 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2648 #define FC_CLASS_2 0x04
2649 #define FC_CLASS_3 0x08
2650 #define FC_CLASS_2_3 0x0C
2652 struct ct_fdmiv2_port_attr {
2656 uint8_t fc4_types[32];
2659 uint32_t max_frame_size;
2660 uint8_t os_dev_name[32];
2661 uint8_t host_name[256];
2662 uint8_t node_name[WWN_SIZE];
2663 uint8_t port_name[WWN_SIZE];
2664 uint8_t port_sym_name[128];
2666 uint32_t port_supported_cos;
2667 uint8_t fabric_name[WWN_SIZE];
2668 uint8_t port_fc4_type[32];
2669 uint32_t port_state;
2676 * Port Attribute Block.
2678 struct ct_fdmiv2_port_attributes {
2680 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2683 struct ct_fdmi_port_attr {
2687 uint8_t fc4_types[32];
2690 uint32_t max_frame_size;
2691 uint8_t os_dev_name[32];
2692 uint8_t host_name[256];
2696 struct ct_fdmi_port_attributes {
2698 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2701 /* FDMI definitions. */
2702 #define GRHL_CMD 0x100
2703 #define GHAT_CMD 0x101
2704 #define GRPL_CMD 0x102
2705 #define GPAT_CMD 0x110
2707 #define RHBA_CMD 0x200
2708 #define RHBA_RSP_SIZE 16
2710 #define RHAT_CMD 0x201
2711 #define RPRT_CMD 0x210
2713 #define RPA_CMD 0x211
2714 #define RPA_RSP_SIZE 16
2716 #define DHBA_CMD 0x300
2717 #define DHBA_REQ_SIZE (16 + 8)
2718 #define DHBA_RSP_SIZE 16
2720 #define DHAT_CMD 0x301
2721 #define DPRT_CMD 0x310
2722 #define DPA_CMD 0x311
2724 /* CT command header -- request/response common fields */
2734 /* CT command request */
2736 struct ct_cmd_hdr header;
2738 uint16_t max_rsp_size;
2739 uint8_t fragment_id;
2740 uint8_t reserved[3];
2743 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2766 uint8_t fc4_types[32];
2773 uint8_t fc4_feature;
2780 uint8_t node_name[8];
2784 uint8_t node_name[8];
2786 uint8_t sym_node_name[255];
2790 uint8_t hba_identifier[8];
2794 uint8_t hba_identifier[8];
2795 uint32_t entry_count;
2796 uint8_t port_name[8];
2797 struct ct_fdmi_hba_attributes attrs;
2801 uint8_t hba_identifier[8];
2802 uint32_t entry_count;
2803 uint8_t port_name[8];
2804 struct ct_fdmiv2_hba_attributes attrs;
2808 uint8_t hba_identifier[8];
2809 struct ct_fdmi_hba_attributes attrs;
2813 uint8_t port_name[8];
2814 struct ct_fdmi_port_attributes attrs;
2818 uint8_t port_name[8];
2819 struct ct_fdmiv2_port_attributes attrs;
2823 uint8_t port_name[8];
2827 uint8_t port_name[8];
2831 uint8_t port_name[8];
2835 uint8_t port_name[8];
2839 uint8_t port_name[8];
2848 uint8_t port_name[8];
2853 /* CT command response header */
2855 struct ct_cmd_hdr header;
2858 uint8_t fragment_id;
2859 uint8_t reason_code;
2860 uint8_t explanation_code;
2861 uint8_t vendor_unique;
2864 struct ct_sns_gid_pt_data {
2865 uint8_t control_byte;
2869 /* It's the same for both GPN_FT and GNN_FT */
2870 struct ct_sns_gpnft_rsp {
2872 struct ct_cmd_hdr header;
2875 uint8_t fragment_id;
2876 uint8_t reason_code;
2877 uint8_t explanation_code;
2878 uint8_t vendor_unique;
2880 /* Assume the largest number of targets for the union */
2881 struct ct_sns_gpn_ft_data {
2889 /* CT command response */
2891 struct ct_rsp_hdr header;
2897 uint8_t port_name[8];
2898 uint8_t sym_port_name_len;
2899 uint8_t sym_port_name[255];
2900 uint8_t node_name[8];
2901 uint8_t sym_node_name_len;
2902 uint8_t sym_node_name[255];
2903 uint8_t init_proc_assoc[8];
2904 uint8_t node_ip_addr[16];
2905 uint8_t class_of_service[4];
2906 uint8_t fc4_types[32];
2907 uint8_t ip_address[16];
2908 uint8_t fabric_port_name[8];
2910 uint8_t hard_address[3];
2914 /* Assume the largest number of targets for the union */
2915 struct ct_sns_gid_pt_data
2916 entries[MAX_FIBRE_DEVICES_MAX];
2920 uint8_t port_name[8];
2924 uint8_t node_name[8];
2928 uint8_t fc4_types[32];
2932 uint32_t entry_count;
2933 uint8_t port_name[8];
2934 struct ct_fdmi_hba_attributes attrs;
2938 uint8_t port_name[8];
2946 #define GFF_FCP_SCSI_OFFSET 7
2947 #define GFF_NVME_OFFSET 23 /* type = 28h */
2949 uint8_t fc4_features[128];
2960 struct ct_sns_req req;
2961 struct ct_sns_rsp rsp;
2965 struct ct_sns_gpnft_pkt {
2967 struct ct_sns_req req;
2968 struct ct_sns_gpnft_rsp rsp;
2973 SF_SCANNING = BIT_0,
2978 FS_FC4TYPE_FCP = BIT_0,
2979 FS_FC4TYPE_NVME = BIT_1,
2982 struct fab_scan_rp {
2984 enum fc4type_t fc4type;
2990 struct fab_scan_rp *l;
2993 #define MAX_SCAN_RETRIES 5
2994 enum scan_flags_t scan_flags;
2995 struct delayed_work scan_work;
2999 * SNS command structures -- for 2200 compatibility.
3001 #define RFT_ID_SNS_SCMD_LEN 22
3002 #define RFT_ID_SNS_CMD_SIZE 60
3003 #define RFT_ID_SNS_DATA_SIZE 16
3005 #define RNN_ID_SNS_SCMD_LEN 10
3006 #define RNN_ID_SNS_CMD_SIZE 36
3007 #define RNN_ID_SNS_DATA_SIZE 16
3009 #define GA_NXT_SNS_SCMD_LEN 6
3010 #define GA_NXT_SNS_CMD_SIZE 28
3011 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
3013 #define GID_PT_SNS_SCMD_LEN 6
3014 #define GID_PT_SNS_CMD_SIZE 28
3016 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
3019 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3021 #define GPN_ID_SNS_SCMD_LEN 6
3022 #define GPN_ID_SNS_CMD_SIZE 28
3023 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
3025 #define GNN_ID_SNS_SCMD_LEN 6
3026 #define GNN_ID_SNS_CMD_SIZE 28
3027 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
3029 struct sns_cmd_pkt {
3032 uint16_t buffer_length;
3033 uint16_t reserved_1;
3034 __le64 buffer_address __packed;
3035 uint16_t subcommand_length;
3036 uint16_t reserved_2;
3037 uint16_t subcommand;
3039 uint32_t reserved_3;
3043 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3044 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3045 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3046 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3047 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3048 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3055 const struct firmware *fw;
3058 /* Return data from MBC_GET_ID_LIST call. */
3059 struct gid_list_info {
3063 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
3064 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3065 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
3069 typedef struct vport_info {
3070 uint8_t port_name[WWN_SIZE];
3071 uint8_t node_name[WWN_SIZE];
3074 unsigned long host_no;
3079 typedef struct vport_params {
3080 uint8_t port_name[WWN_SIZE];
3081 uint8_t node_name[WWN_SIZE];
3083 #define VP_OPTS_RETRY_ENABLE BIT_0
3084 #define VP_OPTS_VP_DISABLE BIT_1
3087 /* NPIV - return codes of VP create and modify */
3088 #define VP_RET_CODE_OK 0
3089 #define VP_RET_CODE_FATAL 1
3090 #define VP_RET_CODE_WRONG_ID 2
3091 #define VP_RET_CODE_WWPN 3
3092 #define VP_RET_CODE_RESOURCES 4
3093 #define VP_RET_CODE_NO_MEM 5
3094 #define VP_RET_CODE_NOT_FOUND 6
3101 struct isp_operations {
3103 int (*pci_config) (struct scsi_qla_host *);
3104 int (*reset_chip)(struct scsi_qla_host *);
3105 int (*chip_diag) (struct scsi_qla_host *);
3106 void (*config_rings) (struct scsi_qla_host *);
3107 int (*reset_adapter)(struct scsi_qla_host *);
3108 int (*nvram_config) (struct scsi_qla_host *);
3109 void (*update_fw_options) (struct scsi_qla_host *);
3110 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3112 char * (*pci_info_str) (struct scsi_qla_host *, char *);
3113 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3115 irq_handler_t intr_handler;
3116 void (*enable_intrs) (struct qla_hw_data *);
3117 void (*disable_intrs) (struct qla_hw_data *);
3119 int (*abort_command) (srb_t *);
3120 int (*target_reset) (struct fc_port *, uint64_t, int);
3121 int (*lun_reset) (struct fc_port *, uint64_t, int);
3122 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3123 uint8_t, uint8_t, uint16_t *, uint8_t);
3124 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3127 uint16_t (*calc_req_entries) (uint16_t);
3128 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3129 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3130 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3133 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3134 uint32_t, uint32_t);
3135 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3138 void (*fw_dump) (struct scsi_qla_host *, int);
3140 int (*beacon_on) (struct scsi_qla_host *);
3141 int (*beacon_off) (struct scsi_qla_host *);
3142 void (*beacon_blink) (struct scsi_qla_host *);
3144 void *(*read_optrom)(struct scsi_qla_host *, void *,
3145 uint32_t, uint32_t);
3146 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3149 int (*get_flash_version) (struct scsi_qla_host *, void *);
3150 int (*start_scsi) (srb_t *);
3151 int (*start_scsi_mq) (srb_t *);
3152 int (*abort_isp) (struct scsi_qla_host *);
3153 int (*iospace_config)(struct qla_hw_data *);
3154 int (*initialize_adapter)(struct scsi_qla_host *);
3157 /* MSI-X Support *************************************************************/
3159 #define QLA_MSIX_CHIP_REV_24XX 3
3160 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3161 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3163 #define QLA_BASE_VECTORS 2 /* default + RSP */
3164 #define QLA_MSIX_RSP_Q 0x01
3165 #define QLA_ATIO_VECTOR 0x02
3166 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3168 #define QLA_MIDX_DEFAULT 0
3169 #define QLA_MIDX_RSP_Q 1
3170 #define QLA_PCI_MSIX_CONTROL 0xa2
3171 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3173 struct scsi_qla_host;
3176 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3178 struct qla_msix_entry {
3188 #define WATCH_INTERVAL 1 /* number of seconds */
3191 enum qla_work_type {
3194 QLA_EVT_ASYNC_LOGIN,
3195 QLA_EVT_ASYNC_LOGOUT,
3196 QLA_EVT_ASYNC_LOGOUT_DONE,
3197 QLA_EVT_ASYNC_ADISC,
3210 QLA_EVT_ASYNC_PRLO_DONE,
3222 struct qla_work_evt {
3223 struct list_head list;
3224 enum qla_work_type type;
3226 #define QLA_EVT_FLAG_FREE 0x1
3230 enum fc_host_event_code code;
3234 #define QLA_IDC_ACK_REGS 7
3235 uint16_t mb[QLA_IDC_ACK_REGS];
3238 struct fc_port *fcport;
3239 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3244 #define QLA_UEVENT_CODE_FW_DUMP 0
3264 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3280 struct qla_chip_state_84xx {
3281 struct list_head list;
3285 spinlock_t access_lock;
3286 struct mutex fw_update_mutex;
3288 uint32_t op_fw_version;
3289 uint32_t op_fw_size;
3290 uint32_t op_fw_seq_size;
3291 uint32_t diag_fw_version;
3292 uint32_t gold_fw_version;
3295 struct qla_dif_statistics {
3296 uint64_t dif_input_bytes;
3297 uint64_t dif_output_bytes;
3298 uint64_t dif_input_requests;
3299 uint64_t dif_output_requests;
3300 uint32_t dif_guard_err;
3301 uint32_t dif_ref_tag_err;
3302 uint32_t dif_app_tag_err;
3305 struct qla_statistics {
3306 uint32_t total_isp_aborts;
3307 uint64_t input_bytes;
3308 uint64_t output_bytes;
3309 uint64_t input_requests;
3310 uint64_t output_requests;
3311 uint32_t control_requests;
3313 uint64_t jiffies_at_last_reset;
3314 uint32_t stat_max_pend_cmds;
3315 uint32_t stat_max_qfull_cmds_alloc;
3316 uint32_t stat_max_qfull_cmds_dropped;
3318 struct qla_dif_statistics qla_dif_stats;
3321 struct bidi_statistics {
3322 unsigned long long io_count;
3323 unsigned long long transfer_bytes;
3326 struct qla_tc_param {
3327 struct scsi_qla_host *vha;
3330 struct scatterlist *sg;
3331 struct scatterlist *prot_sg;
3332 struct crc_context *ctx;
3333 uint8_t *ctx_dsd_alloced;
3336 /* Multi queue support */
3337 #define MBC_INITIALIZE_MULTIQ 0x1f
3338 #define QLA_QUE_PAGE 0X1000
3339 #define QLA_MQ_SIZE 32
3340 #define QLA_MAX_QUEUES 256
3341 #define ISP_QUE_REG(ha, id) \
3342 ((ha->mqenable || IS_QLA83XX(ha) || \
3343 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3344 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3345 ((void __iomem *)ha->iobase))
3346 #define QLA_REQ_QUE_ID(tag) \
3347 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3348 #define QLA_DEFAULT_QUE_QOS 5
3349 #define QLA_PRECONFIG_VPORTS 32
3350 #define QLA_MAX_VPORTS_QLA24XX 128
3351 #define QLA_MAX_VPORTS_QLA25XX 256
3353 struct qla_tgt_counters {
3354 uint64_t qla_core_sbt_cmd;
3355 uint64_t core_qla_que_buf;
3356 uint64_t qla_core_ret_ctio;
3357 uint64_t core_qla_snd_status;
3358 uint64_t qla_core_ret_sta_ctio;
3359 uint64_t core_qla_free_cmd;
3360 uint64_t num_q_full_sent;
3361 uint64_t num_alloc_iocb_failed;
3362 uint64_t num_term_xchg_sent;
3367 /* Response queue data structure */
3371 response_t *ring_ptr;
3372 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
3373 uint32_t __iomem *rsp_q_out;
3374 uint16_t ring_index;
3376 uint16_t *in_ptr; /* queue shadow in index */
3382 struct qla_hw_data *hw;
3383 struct qla_msix_entry *msix;
3384 struct req_que *req;
3385 srb_t *status_srb; /* status continuation entry */
3386 struct qla_qpair *qpair;
3388 dma_addr_t dma_fx00;
3389 response_t *ring_fx00;
3390 uint16_t length_fx00;
3391 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3394 /* Request queue data structure */
3398 request_t *ring_ptr;
3399 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
3400 uint32_t __iomem *req_q_out;
3401 uint16_t ring_index;
3403 uint16_t *out_ptr; /* queue shadow out index */
3411 struct rsp_que *rsp;
3412 srb_t **outstanding_cmds;
3413 uint32_t current_outstanding_cmd;
3414 uint16_t num_outstanding_cmds;
3417 dma_addr_t dma_fx00;
3418 request_t *ring_fx00;
3419 uint16_t length_fx00;
3420 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3423 /*Queue pair data structure */
3429 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3430 * legacy code. For other Qpair(s), it will point at qp_lock.
3432 spinlock_t *qp_lock_ptr;
3433 struct scsi_qla_host *vha;
3436 /* distill these fields down to 'online=0/1'
3437 * ha->flags.eeh_busy
3438 * ha->flags.pci_channel_io_perm_failure
3439 * base_vha->loop_state
3442 /* move vha->flags.difdix_supported here */
3443 uint32_t difdix_supported:1;
3444 uint32_t delete_in_progress:1;
3445 uint32_t fw_started:1;
3446 uint32_t enable_class_2:1;
3447 uint32_t enable_explicit_conf:1;
3448 uint32_t use_shadow_reg:1;
3450 uint16_t id; /* qp number used with FW */
3451 uint16_t vp_idx; /* vport ID */
3452 mempool_t *srb_mempool;
3454 struct pci_dev *pdev;
3455 void (*reqq_start_iocbs)(struct qla_qpair *);
3457 /* to do: New driver: move queues to here instead of pointers */
3458 struct req_que *req;
3459 struct rsp_que *rsp;
3460 struct atio_que *atio;
3461 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3462 struct qla_hw_data *hw;
3463 struct work_struct q_work;
3464 struct list_head qp_list_elem; /* vha->qp_list */
3465 struct list_head hints_list;
3467 uint16_t retry_term_cnt;
3468 uint32_t retry_term_exchg_addr;
3469 uint64_t retry_term_jiff;
3470 struct qla_tgt_counters tgt_counters;
3473 /* Place holder for FW buffer parameters */
3480 struct scsi_qlt_host {
3481 void *target_lport_ptr;
3482 struct mutex tgt_mutex;
3483 struct mutex tgt_host_action_mutex;
3484 struct qla_tgt *qla_tgt;
3487 struct qlt_hw_data {
3488 /* Protected by hw lock */
3489 uint32_t node_name_set:1;
3491 dma_addr_t atio_dma; /* Physical address. */
3492 struct atio *atio_ring; /* Base virtual address */
3493 struct atio *atio_ring_ptr; /* Current address. */
3494 uint16_t atio_ring_index; /* Current index. */
3495 uint16_t atio_q_length;
3496 uint32_t __iomem *atio_q_in;
3497 uint32_t __iomem *atio_q_out;
3499 struct qla_tgt_func_tmpl *tgt_ops;
3500 struct qla_tgt_vp_map *tgt_vp_map;
3503 uint16_t saved_exchange_count;
3504 uint32_t saved_firmware_options_1;
3505 uint32_t saved_firmware_options_2;
3506 uint32_t saved_firmware_options_3;
3507 uint8_t saved_firmware_options[2];
3508 uint8_t saved_add_firmware_options[2];
3510 uint8_t tgt_node_name[WWN_SIZE];
3512 struct dentry *dfs_tgt_sess;
3513 struct dentry *dfs_tgt_port_database;
3514 struct dentry *dfs_naqp;
3516 struct list_head q_full_list;
3517 uint32_t num_pend_cmds;
3518 uint32_t num_qfull_cmds_alloc;
3519 uint32_t num_qfull_cmds_dropped;
3520 spinlock_t q_full_lock;
3521 uint32_t leak_exchg_thresh_hold;
3522 spinlock_t sess_lock;
3524 #define DEFAULT_NAQP 2
3525 spinlock_t atio_lock ____cacheline_aligned;
3526 struct btree_head32 host_map;
3529 #define MAX_QFULL_CMDS_ALLOC 8192
3530 #define Q_FULL_THRESH_HOLD_PERCENT 90
3531 #define Q_FULL_THRESH_HOLD(ha) \
3532 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3534 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3537 * Qlogic host adapter specific data structure.
3539 struct qla_hw_data {
3540 struct pci_dev *pdev;
3542 #define SRB_MIN_REQ 128
3543 mempool_t *srb_mempool;
3546 uint32_t mbox_int :1;
3547 uint32_t mbox_busy :1;
3548 uint32_t disable_risc_code_load :1;
3549 uint32_t enable_64bit_addressing :1;
3550 uint32_t enable_lip_reset :1;
3551 uint32_t enable_target_reset :1;
3552 uint32_t enable_lip_full_login :1;
3553 uint32_t enable_led_scheme :1;
3555 uint32_t msi_enabled :1;
3556 uint32_t msix_enabled :1;
3557 uint32_t disable_serdes :1;
3558 uint32_t gpsc_supported :1;
3559 uint32_t npiv_supported :1;
3560 uint32_t pci_channel_io_perm_failure :1;
3561 uint32_t fce_enabled :1;
3562 uint32_t fac_supported :1;
3564 uint32_t chip_reset_done :1;
3565 uint32_t running_gold_fw :1;
3566 uint32_t eeh_busy :1;
3567 uint32_t disable_msix_handshake :1;
3568 uint32_t fcp_prio_enabled :1;
3569 uint32_t isp82xx_fw_hung:1;
3570 uint32_t nic_core_hung:1;
3572 uint32_t quiesce_owner:1;
3573 uint32_t nic_core_reset_hdlr_active:1;
3574 uint32_t nic_core_reset_owner:1;
3575 uint32_t isp82xx_no_md_cap:1;
3576 uint32_t host_shutting_down:1;
3577 uint32_t idc_compl_status:1;
3578 uint32_t mr_reset_hdlr_active:1;
3579 uint32_t mr_intr_valid:1;
3581 uint32_t dport_enabled:1;
3582 uint32_t fawwpn_enabled:1;
3583 uint32_t exlogins_enabled:1;
3584 uint32_t exchoffld_enabled:1;
3588 uint32_t fw_started:1;
3589 uint32_t fw_init_done:1;
3591 uint32_t detected_lr_sfp:1;
3592 uint32_t using_lr_setting:1;
3593 uint32_t rida_fmt2:1;
3594 uint32_t purge_mbox:1;
3595 uint32_t n2n_bigger:1;
3596 uint32_t secure_adapter:1;
3597 uint32_t secure_fw:1;
3601 uint16_t long_range_distance; /* 32G & above */
3602 #define LR_DISTANCE_5K 1
3603 #define LR_DISTANCE_10K 0
3605 /* This spinlock is used to protect "io transactions", you must
3606 * acquire it before doing any IO to the card, eg with RD_REG*() and
3607 * WRT_REG*() for the duration of your entire commandtransaction.
3609 * This spinlock is of lower priority than the io request lock.
3612 spinlock_t hardware_lock ____cacheline_aligned;
3615 device_reg_t *iobase; /* Base I/O address */
3616 resource_size_t pio_address;
3618 #define MIN_IOBASE_LEN 0x100
3619 dma_addr_t bar0_hdl;
3621 void __iomem *cregbase;
3622 dma_addr_t bar2_hdl;
3623 #define BAR0_LEN_FX00 (1024 * 1024)
3624 #define BAR2_LEN_FX00 (128 * 1024)
3626 uint32_t rqstq_intr_code;
3627 uint32_t mbx_intr_code;
3628 uint32_t req_que_len;
3629 uint32_t rsp_que_len;
3630 uint32_t req_que_off;
3631 uint32_t rsp_que_off;
3633 /* Multi queue data structs */
3634 device_reg_t *mqiobase;
3635 device_reg_t *msixbase;
3636 uint16_t msix_count;
3638 struct req_que **req_q_map;
3639 struct rsp_que **rsp_q_map;
3640 struct qla_qpair **queue_pair_map;
3641 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3642 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3643 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3644 / sizeof(unsigned long)];
3645 uint8_t max_req_queues;
3646 uint8_t max_rsp_queues;
3649 struct qla_qpair *base_qpair;
3650 struct qla_npiv_entry *npiv_info;
3651 uint16_t nvram_npiv_size;
3653 uint16_t switch_cap;
3654 #define FLOGI_SEQ_DEL BIT_8
3655 #define FLOGI_MID_SUPPORT BIT_10
3656 #define FLOGI_VSAN_SUPPORT BIT_12
3657 #define FLOGI_SP_SUPPORT BIT_13
3659 uint8_t port_no; /* Physical port of adapter */
3660 uint8_t exch_starvation;
3662 /* Timeout timers. */
3663 uint8_t loop_down_abort_time; /* port down timer */
3664 atomic_t loop_down_timer; /* loop down timer */
3665 uint8_t link_down_timeout; /* link down timeout */
3666 uint16_t max_loop_id;
3667 uint16_t max_fibre_devices; /* Maximum number of targets */
3670 uint16_t min_external_loopid; /* First external loop Id */
3672 #define PORT_SPEED_UNKNOWN 0xFFFF
3673 #define PORT_SPEED_1GB 0x00
3674 #define PORT_SPEED_2GB 0x01
3675 #define PORT_SPEED_AUTO 0x02
3676 #define PORT_SPEED_4GB 0x03
3677 #define PORT_SPEED_8GB 0x04
3678 #define PORT_SPEED_16GB 0x05
3679 #define PORT_SPEED_32GB 0x06
3680 #define PORT_SPEED_64GB 0x07
3681 #define PORT_SPEED_10GB 0x13
3682 uint16_t link_data_rate; /* F/W operating speed */
3683 uint16_t set_data_rate; /* Set by user */
3685 uint8_t current_topology;
3686 uint8_t prev_topology;
3687 #define ISP_CFG_NL 1
3689 #define ISP_CFG_FL 4
3692 uint8_t operating_mode; /* F/W operating mode */
3697 uint8_t interrupts_on;
3698 uint32_t isp_abort_cnt;
3699 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3700 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3701 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3702 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3703 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3704 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3705 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3706 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3707 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
3708 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
3709 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
3710 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
3711 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
3714 #define DT_ISP2100 BIT_0
3715 #define DT_ISP2200 BIT_1
3716 #define DT_ISP2300 BIT_2
3717 #define DT_ISP2312 BIT_3
3718 #define DT_ISP2322 BIT_4
3719 #define DT_ISP6312 BIT_5
3720 #define DT_ISP6322 BIT_6
3721 #define DT_ISP2422 BIT_7
3722 #define DT_ISP2432 BIT_8
3723 #define DT_ISP5422 BIT_9
3724 #define DT_ISP5432 BIT_10
3725 #define DT_ISP2532 BIT_11
3726 #define DT_ISP8432 BIT_12
3727 #define DT_ISP8001 BIT_13
3728 #define DT_ISP8021 BIT_14
3729 #define DT_ISP2031 BIT_15
3730 #define DT_ISP8031 BIT_16
3731 #define DT_ISPFX00 BIT_17
3732 #define DT_ISP8044 BIT_18
3733 #define DT_ISP2071 BIT_19
3734 #define DT_ISP2271 BIT_20
3735 #define DT_ISP2261 BIT_21
3736 #define DT_ISP2061 BIT_22
3737 #define DT_ISP2081 BIT_23
3738 #define DT_ISP2089 BIT_24
3739 #define DT_ISP2281 BIT_25
3740 #define DT_ISP2289 BIT_26
3741 #define DT_ISP_LAST (DT_ISP2289 << 1)
3743 uint32_t device_type;
3744 #define DT_T10_PI BIT_25
3745 #define DT_IIDMA BIT_26
3746 #define DT_FWI2 BIT_27
3747 #define DT_ZIO_SUPPORTED BIT_28
3748 #define DT_OEM_001 BIT_29
3749 #define DT_ISP2200A BIT_30
3750 #define DT_EXTENDED_IDS BIT_31
3752 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3753 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3754 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3755 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3756 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3757 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3758 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3759 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3760 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3761 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3762 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3763 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3764 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3765 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3766 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3767 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3768 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3769 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3770 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3771 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3772 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3773 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3774 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3775 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3776 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
3777 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
3779 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3780 IS_QLA6312(ha) || IS_QLA6322(ha))
3781 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3782 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3783 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3784 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3785 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3786 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3787 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
3788 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3790 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3791 IS_QLA8031(ha) || IS_QLA8044(ha))
3792 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3793 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3794 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3795 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3796 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
3798 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3799 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3800 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3801 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3802 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3803 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3804 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3805 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3807 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3808 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3809 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3810 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3811 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3812 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3813 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3814 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3815 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3816 #define IS_BIDI_CAPABLE(ha) \
3817 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3818 /* Bit 21 of fw_attributes decides the MCTP capabilities */
3819 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3820 ((ha)->fw_attributes_ext[0] & BIT_0))
3821 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3822 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3823 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3824 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3826 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3827 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3828 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3830 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3831 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
3832 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3834 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3836 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
3837 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3838 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3839 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3840 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3841 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
3842 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3844 /* HBA serial number */
3849 /* NVRAM configuration data */
3850 #define MAX_NVRAM_SIZE 4096
3851 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
3852 uint16_t nvram_size;
3853 uint16_t nvram_base;
3859 uint16_t loop_reset_delay;
3860 uint8_t retry_count;
3861 uint8_t login_timeout;
3863 int port_down_retry_count;
3865 uint8_t aen_mbx_count;
3866 atomic_t num_pend_mbx_stage1;
3867 atomic_t num_pend_mbx_stage2;
3868 atomic_t num_pend_mbx_stage3;
3869 uint16_t frame_payload_size;
3871 uint32_t login_retry_count;
3872 /* SNS command interfaces. */
3873 ms_iocb_entry_t *ms_iocb;
3874 dma_addr_t ms_iocb_dma;
3875 struct ct_sns_pkt *ct_sns;
3876 dma_addr_t ct_sns_dma;
3877 /* SNS command interfaces for 2200. */
3878 struct sns_cmd_pkt *sns_cmd;
3879 dma_addr_t sns_cmd_dma;
3881 #define SFP_DEV_SIZE 512
3882 #define SFP_BLOCK_SIZE 64
3884 dma_addr_t sfp_data_dma;
3889 #define XGMAC_DATA_SIZE 4096
3891 dma_addr_t xgmac_data_dma;
3893 #define DCBX_TLV_DATA_SIZE 4096
3895 dma_addr_t dcbx_tlv_dma;
3897 struct task_struct *dpc_thread;
3898 uint8_t dpc_active; /* DPC routine is active */
3900 dma_addr_t gid_list_dma;
3901 struct gid_list_info *gid_list;
3902 int gid_list_info_size;
3904 /* Small DMA pool allocations -- maximum 256 bytes in length. */
3905 #define DMA_POOL_SIZE 256
3906 struct dma_pool *s_dma_pool;
3908 dma_addr_t init_cb_dma;
3911 dma_addr_t ex_init_cb_dma;
3912 struct ex_init_cb_81xx *ex_init_cb;
3915 dma_addr_t async_pd_dma;
3917 #define ENABLE_EXTENDED_LOGIN BIT_7
3919 /* Extended Logins */
3921 dma_addr_t exlogin_buf_dma;
3924 #define ENABLE_EXCHANGE_OFFLD BIT_2
3926 /* Exchange Offload */
3927 void *exchoffld_buf;
3928 dma_addr_t exchoffld_buf_dma;
3930 int exchoffld_count;
3933 struct els_plogi_payload plogi_els_payld;
3937 /* These are used by mailbox operations. */
3938 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3939 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3940 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3943 struct mbx_cmd_32 *mcp32;
3945 unsigned long mbx_cmd_flags;
3946 #define MBX_INTERRUPT 1
3947 #define MBX_INTR_WAIT 2
3948 #define MBX_UPDATE_FLASH_ACTIVE 3
3950 struct mutex vport_lock; /* Virtual port synchronization */
3951 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
3952 struct mutex mq_lock; /* multi-queue synchronization */
3953 struct completion mbx_cmd_comp; /* Serialize mbx access */
3954 struct completion mbx_intr_comp; /* Used for completion notification */
3955 struct completion dcbx_comp; /* For set port config notification */
3956 struct completion lb_portup_comp; /* Used to wait for link up during
3958 #define DCBX_COMP_TIMEOUT 20
3959 #define LB_PORTUP_COMP_TIMEOUT 10
3961 int notify_dcbx_comp;
3962 int notify_lb_portup_comp;
3963 struct mutex selflogin_lock;
3965 /* Basic firmware related information. */
3966 uint16_t fw_major_version;
3967 uint16_t fw_minor_version;
3968 uint16_t fw_subminor_version;
3969 uint16_t fw_attributes;
3970 uint16_t fw_attributes_h;
3971 #define FW_ATTR_H_NVME_FBURST BIT_1
3972 #define FW_ATTR_H_NVME BIT_10
3973 #define FW_ATTR_H_NVME_UPDATED BIT_14
3975 uint16_t fw_attributes_ext[2];
3976 uint32_t fw_memory_size;
3977 uint32_t fw_transfer_size;
3978 uint32_t fw_srisc_address;
3979 #define RISC_START_ADDRESS_2100 0x1000
3980 #define RISC_START_ADDRESS_2300 0x800
3981 #define RISC_START_ADDRESS_2400 0x100000
3983 uint16_t orig_fw_tgt_xcb_count;
3984 uint16_t cur_fw_tgt_xcb_count;
3985 uint16_t orig_fw_xcb_count;
3986 uint16_t cur_fw_xcb_count;
3987 uint16_t orig_fw_iocb_count;
3988 uint16_t cur_fw_iocb_count;
3989 uint16_t fw_max_fcf_count;
3991 uint32_t fw_shared_ram_start;
3992 uint32_t fw_shared_ram_end;
3993 uint32_t fw_ddr_ram_start;
3994 uint32_t fw_ddr_ram_end;
3996 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3997 uint8_t fw_seriallink_options[4];
3998 uint16_t fw_seriallink_options24[4];
4000 uint8_t serdes_version[3];
4001 uint8_t mpi_version[3];
4002 uint32_t mpi_capabilities;
4003 uint8_t phy_version[3];
4004 uint8_t pep_version[3];
4006 /* Firmware dump template */
4012 struct qla2xxx_fw_dump *fw_dump;
4013 uint32_t fw_dump_len;
4014 u32 fw_dump_alloc_len;
4017 unsigned long fw_dump_cap_flags;
4018 #define RISC_PAUSE_CMPL 0
4019 #define DMA_SHUTDOWN_CMPL 1
4020 #define ISP_RESET_CMPL 2
4021 #define RISC_RDY_AFT_RESET 3
4022 #define RISC_SRAM_DUMP_CMPL 4
4023 #define RISC_EXT_MEM_DUMP_CMPL 5
4024 #define ISP_MBX_RDY 6
4025 #define ISP_SOFT_RESET_CMPL 7
4026 int fw_dump_reading;
4027 int prev_minidump_failed;
4030 /* Current size of mctp dump is 0x086064 bytes */
4031 #define MCTP_DUMP_SIZE 0x086064
4032 dma_addr_t mctp_dump_dma;
4035 int mctp_dump_reading;
4036 uint32_t chain_offset;
4037 struct dentry *dfs_dir;
4038 struct dentry *dfs_fce;
4039 struct dentry *dfs_tgt_counters;
4040 struct dentry *dfs_fw_resource_cnt;
4046 uint64_t fce_wr, fce_rd;
4047 struct mutex fce_mutex;
4050 uint16_t chip_revision;
4052 uint16_t product_id[4];
4054 uint8_t model_number[16+1];
4055 char model_desc[80];
4056 uint8_t adapter_id[16+1];
4058 /* Option ROM information. */
4059 char *optrom_buffer;
4060 uint32_t optrom_size;
4062 #define QLA_SWAITING 0
4063 #define QLA_SREADING 1
4064 #define QLA_SWRITING 2
4065 uint32_t optrom_region_start;
4066 uint32_t optrom_region_size;
4067 struct mutex optrom_mutex;
4069 /* PCI expansion ROM image information. */
4070 #define ROM_CODE_TYPE_BIOS 0
4071 #define ROM_CODE_TYPE_FCODE 1
4072 #define ROM_CODE_TYPE_EFI 3
4073 uint8_t bios_revision[2];
4074 uint8_t efi_revision[2];
4075 uint8_t fcode_revision[16];
4076 uint32_t fw_revision[4];
4078 uint32_t gold_fw_version[4];
4080 /* Offsets for flash/nvram access (set to ~0 if not used). */
4081 uint32_t flash_conf_off;
4082 uint32_t flash_data_off;
4083 uint32_t nvram_conf_off;
4084 uint32_t nvram_data_off;
4086 uint32_t fdt_wrt_disable;
4087 uint32_t fdt_wrt_enable;
4088 uint32_t fdt_erase_cmd;
4089 uint32_t fdt_block_size;
4090 uint32_t fdt_unprotect_sec_cmd;
4091 uint32_t fdt_protect_sec_cmd;
4092 uint32_t fdt_wrt_sts_reg_cmd;
4095 uint32_t flt_region_flt;
4096 uint32_t flt_region_fdt;
4097 uint32_t flt_region_boot;
4098 uint32_t flt_region_boot_sec;
4099 uint32_t flt_region_fw;
4100 uint32_t flt_region_fw_sec;
4101 uint32_t flt_region_vpd_nvram;
4102 uint32_t flt_region_vpd_nvram_sec;
4103 uint32_t flt_region_vpd;
4104 uint32_t flt_region_vpd_sec;
4105 uint32_t flt_region_nvram;
4106 uint32_t flt_region_nvram_sec;
4107 uint32_t flt_region_npiv_conf;
4108 uint32_t flt_region_gold_fw;
4109 uint32_t flt_region_fcp_prio;
4110 uint32_t flt_region_bootload;
4111 uint32_t flt_region_img_status_pri;
4112 uint32_t flt_region_img_status_sec;
4113 uint32_t flt_region_aux_img_status_pri;
4114 uint32_t flt_region_aux_img_status_sec;
4116 uint8_t active_image;
4118 /* Needed for BEACON */
4119 uint16_t beacon_blink_led;
4120 uint8_t beacon_color_state;
4121 #define QLA_LED_GRN_ON 0x01
4122 #define QLA_LED_YLW_ON 0x02
4123 #define QLA_LED_ABR_ON 0x04
4124 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
4125 /* ISP2322: red, green, amber. */
4129 struct qla_msix_entry *msix_entries;
4131 struct list_head vp_list; /* list of VP */
4132 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4133 sizeof(unsigned long)];
4134 uint16_t num_vhosts; /* number of vports created */
4135 uint16_t num_vsans; /* number of vsan created */
4136 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
4137 int cur_vport_count;
4139 struct qla_chip_state_84xx *cs84xx;
4140 struct isp_operations *isp_ops;
4141 struct workqueue_struct *wq;
4142 struct qlfc_fw fw_buf;
4144 /* FCP_CMND priority support */
4145 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4147 struct dma_pool *dl_dma_pool;
4148 #define DSD_LIST_DMA_POOL_SIZE 512
4150 struct dma_pool *fcp_cmnd_dma_pool;
4151 mempool_t *ctx_mempool;
4152 #define FCP_CMND_DMA_POOL_SIZE 512
4154 void __iomem *nx_pcibase; /* Base I/O address */
4155 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
4156 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
4159 uint32_t curr_window;
4160 uint32_t ddr_mn_window;
4161 unsigned long mn_win_crb;
4162 unsigned long ms_win_crb;
4164 uint32_t fcoe_dev_init_timeout;
4165 uint32_t fcoe_reset_timeout;
4167 uint16_t portnum; /* port number */
4169 struct fw_blob *hablob;
4170 struct qla82xx_legacy_intr_set nx_legacy_intr;
4172 uint16_t gbl_dsd_inuse;
4173 uint16_t gbl_dsd_avail;
4174 struct list_head gbl_dsd_list;
4175 #define NUM_DSD_CHAIN 4096
4178 __le32 file_prd_off; /* File firmware product offset */
4180 uint32_t md_template_size;
4182 dma_addr_t md_tmplt_hdr_dma;
4184 uint32_t md_dump_size;
4188 /* QLA83XX IDC specific fields */
4189 uint32_t idc_audit_ts;
4190 uint32_t idc_extend_tmo;
4192 /* DPC low-priority workqueue */
4193 struct workqueue_struct *dpc_lp_wq;
4194 struct work_struct idc_aen;
4195 /* DPC high-priority workqueue */
4196 struct workqueue_struct *dpc_hp_wq;
4197 struct work_struct nic_core_reset;
4198 struct work_struct idc_state_handler;
4199 struct work_struct nic_core_unrecoverable;
4200 struct work_struct board_disable;
4202 struct mr_data_fx00 mr;
4203 uint32_t chip_reset;
4205 struct qlt_hw_data tgt;
4206 int allow_cna_fw_dump;
4207 uint32_t fw_ability_mask;
4208 uint16_t min_supported_speed;
4209 uint16_t max_supported_speed;
4211 /* DMA pool for the DIF bundling buffers */
4212 struct dma_pool *dif_bundl_pool;
4213 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4216 struct list_head head;
4220 struct list_head head;
4225 unsigned long long dif_bundle_crossed_pages;
4226 unsigned long long dif_bundle_reads;
4227 unsigned long long dif_bundle_writes;
4228 unsigned long long dif_bundle_kallocs;
4229 unsigned long long dif_bundle_dma_allocs;
4231 atomic_t nvme_active_aen_cnt;
4232 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
4234 atomic_t zio_threshold;
4235 uint16_t last_zio_threshold;
4237 #define DEFAULT_ZIO_THRESHOLD 5
4240 struct active_regions {
4243 uint8_t board_config;
4245 uint8_t npiv_config_0_1;
4246 uint8_t npiv_config_2_3;
4250 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4251 #define FW_ABILITY_MAX_SPEED_16G 0x0
4252 #define FW_ABILITY_MAX_SPEED_32G 0x1
4253 #define FW_ABILITY_MAX_SPEED(ha) \
4254 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4256 #define QLA_GET_DATA_RATE 0
4257 #define QLA_SET_DATA_RATE_NOLR 1
4258 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
4261 * Qlogic scsi host structure
4263 typedef struct scsi_qla_host {
4264 struct list_head list;
4265 struct list_head vp_fcports; /* list of fcports */
4266 struct list_head work_list;
4267 spinlock_t work_lock;
4268 struct work_struct iocb_work;
4270 /* Commonly used flags and state information. */
4271 struct Scsi_Host *host;
4272 unsigned long host_no;
4273 uint8_t host_str[16];
4276 uint32_t init_done :1;
4278 uint32_t reset_active :1;
4280 uint32_t management_server_logged_in :1;
4281 uint32_t process_response_queue :1;
4282 uint32_t difdix_supported:1;
4283 uint32_t delete_progress:1;
4285 uint32_t fw_tgt_reported:1;
4286 uint32_t bbcr_enable:1;
4287 uint32_t qpairs_available:1;
4288 uint32_t qpairs_req_created:1;
4289 uint32_t qpairs_rsp_created:1;
4290 uint32_t nvme_enabled:1;
4291 uint32_t nvme_first_burst:1;
4294 atomic_t loop_state;
4295 #define LOOP_TIMEOUT 1
4298 #define LOOP_UPDATE 4
4299 #define LOOP_READY 5
4302 unsigned long relogin_jif;
4303 unsigned long dpc_flags;
4304 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4305 #define RESET_ACTIVE 1
4306 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4307 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4308 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4309 #define LOOP_RESYNC_ACTIVE 5
4310 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4311 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4312 #define RELOGIN_NEEDED 8
4313 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4314 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4315 #define BEACON_BLINK_NEEDED 11
4316 #define REGISTER_FDMI_NEEDED 12
4317 #define FCPORT_UPDATE_NEEDED 13
4318 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4319 #define UNLOADING 15
4320 #define NPIV_CONFIG_NEEDED 16
4321 #define ISP_UNRECOVERABLE 17
4322 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4323 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4324 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4325 #define N2N_LINK_RESET 21
4326 #define PORT_UPDATE_NEEDED 22
4327 #define FX00_RESET_RECOVERY 23
4328 #define FX00_TARGET_SCAN 24
4329 #define FX00_CRITEMP_RECOVERY 25
4330 #define FX00_HOST_INFO_RESEND 26
4331 #define QPAIR_ONLINE_CHECK_NEEDED 27
4332 #define SET_NVME_ZIO_THRESHOLD_NEEDED 28
4333 #define DETECT_SFP_CHANGE 29
4334 #define N2N_LOGIN_NEEDED 30
4335 #define IOCB_WORK_ACTIVE 31
4336 #define SET_ZIO_THRESHOLD_NEEDED 32
4337 #define ISP_ABORT_TO_ROM 33
4339 unsigned long pci_flags;
4340 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4341 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4342 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4344 uint32_t device_flags;
4345 #define SWITCH_FOUND BIT_0
4346 #define DFLG_NO_CABLE BIT_1
4347 #define DFLG_DEV_FAILED BIT_5
4349 /* ISP configuration data. */
4350 uint16_t loop_id; /* Host adapter loop id */
4351 uint16_t self_login_loop_id; /* host adapter loop id
4352 * get it on self login
4354 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4355 * no need of allocating it for
4359 port_id_t d_id; /* Host adapter port id */
4360 uint8_t marker_needed;
4361 uint16_t mgmt_svr_loop_id;
4365 /* Timeout timers. */
4366 uint8_t loop_down_abort_time; /* port down timer */
4367 atomic_t loop_down_timer; /* loop down timer */
4368 uint8_t link_down_timeout; /* link down timeout */
4370 uint32_t timer_active;
4371 struct timer_list timer;
4373 uint8_t node_name[WWN_SIZE];
4374 uint8_t port_name[WWN_SIZE];
4375 uint8_t fabric_node_name[WWN_SIZE];
4377 struct nvme_fc_local_port *nvme_local_port;
4378 struct completion nvme_del_done;
4379 struct list_head nvme_rport_list;
4381 uint16_t fcoe_vlan_id;
4382 uint16_t fcoe_fcf_idx;
4383 uint8_t fcoe_vn_port_mac[6];
4385 /* list of commands waiting on workqueue */
4386 struct list_head qla_cmd_list;
4387 struct list_head qla_sess_op_cmd_list;
4388 struct list_head unknown_atio_list;
4389 spinlock_t cmd_list_lock;
4390 struct delayed_work unknown_atio_work;
4392 /* Counter to detect races between ELS and RSCN events */
4393 atomic_t generation_tick;
4394 /* Time when global fcport update has been scheduled */
4395 int total_fcport_update_gen;
4396 /* List of pending LOGOs, protected by tgt_mutex */
4397 struct list_head logo_list;
4398 /* List of pending PLOGI acks, protected by hw lock */
4399 struct list_head plogi_ack_list;
4401 struct list_head qp_list;
4403 uint32_t vp_abort_cnt;
4405 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4406 uint16_t vp_idx; /* vport ID */
4407 struct qla_qpair *qpair; /* base qpair */
4409 unsigned long vp_flags;
4410 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4411 #define VP_CREATE_NEEDED 1
4412 #define VP_BIND_NEEDED 2
4413 #define VP_DELETE_NEEDED 3
4414 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4415 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4417 #define VP_OFFLINE 0
4420 // #define VP_DISABLE 3
4421 uint16_t vp_err_state;
4422 uint16_t vp_prev_err_state;
4423 #define VP_ERR_UNKWN 0
4424 #define VP_ERR_PORTDWN 1
4425 #define VP_ERR_FAB_UNSUPPORTED 2
4426 #define VP_ERR_FAB_NORESOURCES 3
4427 #define VP_ERR_FAB_LOGOUT 4
4428 #define VP_ERR_ADAP_NORESOURCES 5
4429 struct qla_hw_data *hw;
4430 struct scsi_qlt_host vha_tgt;
4431 struct req_que *req;
4432 int fw_heartbeat_counter;
4433 int seconds_since_last_heartbeat;
4434 struct fc_host_statistics fc_host_stat;
4435 struct qla_statistics qla_stats;
4436 struct bidi_statistics bidi_stats;
4437 atomic_t vref_count;
4438 struct qla8044_reset_template reset_tmplt;
4441 uint16_t u_ql2xexchoffld;
4442 uint16_t u_ql2xiniexchg;
4443 uint16_t qlini_mode;
4444 uint16_t ql2xexchoffld;
4445 uint16_t ql2xiniexchg;
4447 struct name_list_extended gnl;
4448 /* Count of active session/fcport */
4450 wait_queue_head_t fcport_waitQ;
4451 wait_queue_head_t vref_waitq;
4452 uint8_t min_supported_speed;
4453 uint8_t n2n_node_name[WWN_SIZE];
4454 uint8_t n2n_port_name[WWN_SIZE];
4456 struct list_head gpnid_list;
4457 struct fab_scan scan;
4459 unsigned int irq_offset;
4462 struct qla27xx_image_status {
4463 uint8_t image_status_mask;
4464 uint16_t generation;
4467 uint8_t bitmap; /* 28xx only */
4468 uint8_t reserved[2];
4473 /* 28xx aux image status bimap values */
4474 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
4475 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
4476 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
4477 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
4479 #define SET_VP_IDX 1
4481 #define RESET_VP_IDX 3
4482 #define RESET_AL_PA 4
4483 struct qla_tgt_vp_map {
4485 scsi_qla_host_t *vha;
4489 dma_addr_t dma_addr; /* OUT */
4490 uint32_t dma_len; /* OUT */
4492 uint32_t tot_bytes; /* IN */
4493 struct scatterlist *cur_sg; /* IN */
4495 /* for book keeping, bzero on initial invocation */
4496 uint32_t bytes_consumed;
4498 uint32_t tot_partial;
4505 #define QLA_FW_STARTED(_ha) { \
4507 _ha->flags.fw_started = 1; \
4508 _ha->base_qpair->fw_started = 1; \
4509 for (i = 0; i < _ha->max_qpairs; i++) { \
4510 if (_ha->queue_pair_map[i]) \
4511 _ha->queue_pair_map[i]->fw_started = 1; \
4515 #define QLA_FW_STOPPED(_ha) { \
4517 _ha->flags.fw_started = 0; \
4518 _ha->base_qpair->fw_started = 0; \
4519 for (i = 0; i < _ha->max_qpairs; i++) { \
4520 if (_ha->queue_pair_map[i]) \
4521 _ha->queue_pair_map[i]->fw_started = 0; \
4526 #define SFUB_CHECKSUM_SIZE 4
4528 struct secure_flash_update_block {
4529 uint32_t block_info;
4530 uint32_t signature_lo;
4531 uint32_t signature_hi;
4532 uint32_t signature_upper[0x3e];
4535 struct secure_flash_update_block_pk {
4536 uint32_t block_info;
4537 uint32_t signature_lo;
4538 uint32_t signature_hi;
4539 uint32_t signature_upper[0x3e];
4540 uint32_t public_key[0x41];
4544 * Macros to help code, maintain, etc.
4546 #define LOOP_TRANSITION(ha) \
4547 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4548 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4549 atomic_read(&ha->loop_state) == LOOP_DOWN)
4551 #define STATE_TRANSITION(ha) \
4552 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4553 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4555 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4556 atomic_inc(&__vha->vref_count); \
4558 if (__vha->flags.delete_progress) { \
4559 atomic_dec(&__vha->vref_count); \
4560 wake_up(&__vha->vref_waitq); \
4567 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4568 atomic_dec(&__vha->vref_count); \
4569 wake_up(&__vha->vref_waitq); \
4572 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4573 atomic_inc(&__qpair->ref_count); \
4575 if (__qpair->delete_in_progress) { \
4576 atomic_dec(&__qpair->ref_count); \
4583 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4584 atomic_dec(&__qpair->ref_count); \
4587 #define QLA_ENA_CONF(_ha) {\
4589 _ha->base_qpair->enable_explicit_conf = 1; \
4590 for (i = 0; i < _ha->max_qpairs; i++) { \
4591 if (_ha->queue_pair_map[i]) \
4592 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4596 #define QLA_DIS_CONF(_ha) {\
4598 _ha->base_qpair->enable_explicit_conf = 0; \
4599 for (i = 0; i < _ha->max_qpairs; i++) { \
4600 if (_ha->queue_pair_map[i]) \
4601 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4606 * qla2x00 local function return status codes
4608 #define MBS_MASK 0x3fff
4610 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4611 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4612 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4613 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4614 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4615 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4616 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4617 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4618 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4619 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4621 #define QLA_FUNCTION_TIMEOUT 0x100
4622 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
4623 #define QLA_FUNCTION_FAILED 0x102
4624 #define QLA_MEMORY_ALLOC_FAILED 0x103
4625 #define QLA_LOCK_TIMEOUT 0x104
4626 #define QLA_ABORTED 0x105
4627 #define QLA_SUSPENDED 0x106
4628 #define QLA_BUSY 0x107
4629 #define QLA_ALREADY_REGISTERED 0x109
4631 #define NVRAM_DELAY() udelay(10)
4634 * Flash support definitions
4636 #define OPTROM_SIZE_2300 0x20000
4637 #define OPTROM_SIZE_2322 0x100000
4638 #define OPTROM_SIZE_24XX 0x100000
4639 #define OPTROM_SIZE_25XX 0x200000
4640 #define OPTROM_SIZE_81XX 0x400000
4641 #define OPTROM_SIZE_82XX 0x800000
4642 #define OPTROM_SIZE_83XX 0x1000000
4643 #define OPTROM_SIZE_28XX 0x2000000
4645 #define OPTROM_BURST_SIZE 0x1000
4646 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4648 #define QLA_DSDS_PER_IOCB 37
4650 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4652 #define QLA_SG_ALL 1024
4654 enum nexus_wait_type {
4660 /* Refer to SNIA SFF 8247 */
4661 struct sff_8247_a0 {
4662 u8 txid; /* transceiver id */
4665 /* compliance code */
4666 u8 eth_infi_cc3; /* ethernet, inifiband */
4670 #define FC_LL_VL BIT_7 /* very long */
4671 #define FC_LL_S BIT_6 /* Short */
4672 #define FC_LL_I BIT_5 /* Intermidiate*/
4673 #define FC_LL_L BIT_4 /* Long */
4674 #define FC_LL_M BIT_3 /* Medium */
4675 #define FC_LL_SA BIT_2 /* ShortWave laser */
4676 #define FC_LL_LC BIT_1 /* LongWave laser */
4677 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
4680 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
4681 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
4682 #define FC_TEC_SL BIT_5 /* short wave with OFC */
4683 #define FC_TEC_LL BIT_4 /* Longwave Laser */
4684 #define FC_TEC_ACT BIT_3 /* Active cable */
4685 #define FC_TEC_PAS BIT_2 /* Passive cable */
4687 /* Transmission Media */
4688 #define FC_MED_TW BIT_7 /* Twin Ax */
4689 #define FC_MED_TP BIT_6 /* Twited Pair */
4690 #define FC_MED_MI BIT_5 /* Min Coax */
4691 #define FC_MED_TV BIT_4 /* Video Coax */
4692 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
4693 #define FC_MED_M5 BIT_2 /* Multimode, 50um */
4694 #define FC_MED_SM BIT_0 /* Single Mode */
4696 /* speed FC_SP_12: 12*100M = 1200 MB/s */
4697 #define FC_SP_12 BIT_7
4698 #define FC_SP_8 BIT_6
4699 #define FC_SP_16 BIT_5
4700 #define FC_SP_4 BIT_4
4701 #define FC_SP_32 BIT_3
4702 #define FC_SP_2 BIT_2
4703 #define FC_SP_1 BIT_0
4708 u8 length_km; /* offset 14/eh */
4714 #define SFF_VEN_NAME_LEN 16
4715 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
4718 #define SFF_PART_NAME_LEN 16
4719 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
4724 u8 options[2]; /* offset 64 */
4733 u8 vendor_specific[32];
4737 #define AUTO_DETECT_SFP_SUPPORT(_vha)\
4738 (ql2xautodetectsfp && !_vha->vp_idx && \
4739 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\
4740 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw) || \
4741 IS_QLA28XX(_vha->hw)))
4743 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
4745 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4746 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
4748 #define SAVE_TOPO(_ha) { \
4749 if (_ha->current_topology) \
4750 _ha->prev_topology = _ha->current_topology; \
4753 #define N2N_TOPO(ha) \
4754 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
4755 ha->current_topology == ISP_CFG_N || \
4756 !ha->current_topology)
4758 #include "qla_target.h"
4759 #include "qla_gbl.h"
4760 #include "qla_dbg.h"
4761 #include "qla_inline.h"