drivers/pwm/pwm-mtk-disp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * MediaTek display pulse-width-modulation controller driver.
   4  * Copyright (c) 2015 MediaTek Inc.
   5  * Author: YH Huang <yh.huang@mediatek.com>
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/err.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pwm.h>
  17 #include <linux/slab.h>
  18
  19 #define DISP_PWM_EN             0x00
  20
  21 #define PWM_CLKDIV_SHIFT        16
  22 #define PWM_CLKDIV_MAX          0x3ff
  23 #define PWM_CLKDIV_MASK         (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
  24
  25 #define PWM_PERIOD_BIT_WIDTH    12
  26 #define PWM_PERIOD_MASK         ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
  27
  28 #define PWM_HIGH_WIDTH_SHIFT    16
  29 #define PWM_HIGH_WIDTH_MASK     (0x1fff << PWM_HIGH_WIDTH_SHIFT)
  30
  31 struct mtk_pwm_data {
  32         u32 enable_mask;
  33         unsigned int con0;
  34         u32 con0_sel;
  35         unsigned int con1;
  36
  37         bool has_commit;
  38         unsigned int commit;
  39         unsigned int commit_mask;
  40
  41         unsigned int bls_debug;
  42         u32 bls_debug_mask;
  43 };
  44
  45 struct mtk_disp_pwm {
  46         struct pwm_chip chip;
  47         const struct mtk_pwm_data *data;
  48         struct clk *clk_main;
  49         struct clk *clk_mm;
  50         void __iomem *base;
  51         bool enabled;
  52 };
  53
  54 static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
  55 {
  56         return container_of(chip, struct mtk_disp_pwm, chip);
  57 }
  58
  59 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
  60                                      u32 mask, u32 data)
  61 {
  62         void __iomem *address = mdp->base + offset;
  63         u32 value;
  64
  65         value = readl(address);
  66         value &= ~mask;
  67         value |= data;
  68         writel(value, address);
  69 }
  70
  71 static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  72                               const struct pwm_state *state)
  73 {
  74         struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
  75         u32 clk_div, period, high_width, value;
  76         u64 div, rate;
  77         int err;
  78
  79         if (state->polarity != PWM_POLARITY_NORMAL)
  80                 return -EINVAL;
  81
  82         if (!state->enabled) {
  83                 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
  84                                          0x0);
  85
  86                 if (mdp->enabled) {
  87                         clk_disable_unprepare(mdp->clk_mm);
  88                         clk_disable_unprepare(mdp->clk_main);
  89                 }
  90
  91                 mdp->enabled = false;
  92                 return 0;
  93         }
  94
  95         if (!mdp->enabled) {
  96                 err = clk_prepare_enable(mdp->clk_main);
  97                 if (err < 0) {
  98                         dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
  99                                 ERR_PTR(err));
 100                         return err;
 101                 }
 102
 103                 err = clk_prepare_enable(mdp->clk_mm);
 104                 if (err < 0) {
 105                         dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
 106                                 ERR_PTR(err));
 107                         clk_disable_unprepare(mdp->clk_main);
 108                         return err;
 109                 }
 110         }
 111
 112         /*
 113          * Find period, high_width and clk_div to suit duty_ns and period_ns.
 114          * Calculate proper div value to keep period value in the bound.
 115          *
 116          * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
 117          * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
 118          *
 119          * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
 120          * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
 121          */
 122         rate = clk_get_rate(mdp->clk_main);
 123         clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
 124                           PWM_PERIOD_BIT_WIDTH;
 125         if (clk_div > PWM_CLKDIV_MAX) {
 126                 if (!mdp->enabled) {
 127                         clk_disable_unprepare(mdp->clk_mm);
 128                         clk_disable_unprepare(mdp->clk_main);
 129                 }
 130                 return -EINVAL;
 131         }
 132
 133         div = NSEC_PER_SEC * (clk_div + 1);
 134         period = mul_u64_u64_div_u64(state->period, rate, div);
 135         if (period > 0)
 136                 period--;
 137
 138         high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
 139         value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
 140
 141         mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
 142                                  PWM_CLKDIV_MASK,
 143                                  clk_div << PWM_CLKDIV_SHIFT);
 144         mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
 145                                  PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
 146                                  value);
 147
 148         if (mdp->data->has_commit) {
 149                 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
 150                                          mdp->data->commit_mask,
 151                                          mdp->data->commit_mask);
 152                 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
 153                                          mdp->data->commit_mask,
 154                                          0x0);
 155         } else {
 156                 /*
 157                  * For MT2701, disable double buffer before writing register
 158                  * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
 159                  */
 160                 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
 161                                          mdp->data->bls_debug_mask,
 162                                          mdp->data->bls_debug_mask);
 163                 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
 164                                          mdp->data->con0_sel,
 165                                          mdp->data->con0_sel);
 166         }
 167
 168         mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
 169                                  mdp->data->enable_mask);
 170         mdp->enabled = true;
 171
 172         return 0;
 173 }
 174
 175 static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
 176                                    struct pwm_device *pwm,
 177                                    struct pwm_state *state)
 178 {
 179         struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
 180         u64 rate, period, high_width;
 181         u32 clk_div, con0, con1;
 182         int err;
 183
 184         err = clk_prepare_enable(mdp->clk_main);
 185         if (err < 0) {
 186                 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
 187                 return;
 188         }
 189
 190         err = clk_prepare_enable(mdp->clk_mm);
 191         if (err < 0) {
 192                 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
 193                 clk_disable_unprepare(mdp->clk_main);
 194                 return;
 195         }
 196
 197         rate = clk_get_rate(mdp->clk_main);
 198         con0 = readl(mdp->base + mdp->data->con0);
 199         con1 = readl(mdp->base + mdp->data->con1);
 200         state->enabled = !!(con0 & BIT(0));
 201         clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
 202         period = FIELD_GET(PWM_PERIOD_MASK, con1);
 203         /*
 204          * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
 205          * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
 206          */
 207         state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
 208         high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
 209         state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
 210                                                rate);
 211         state->polarity = PWM_POLARITY_NORMAL;
 212         clk_disable_unprepare(mdp->clk_mm);
 213         clk_disable_unprepare(mdp->clk_main);
 214 }
 215
 216 static const struct pwm_ops mtk_disp_pwm_ops = {
 217         .apply = mtk_disp_pwm_apply,
 218         .get_state = mtk_disp_pwm_get_state,
 219         .owner = THIS_MODULE,
 220 };
 221
 222 static int mtk_disp_pwm_probe(struct platform_device *pdev)
 223 {
 224         struct mtk_disp_pwm *mdp;
 225         int ret;
 226
 227         mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
 228         if (!mdp)
 229                 return -ENOMEM;
 230
 231         mdp->data = of_device_get_match_data(&pdev->dev);
 232
 233         mdp->base = devm_platform_ioremap_resource(pdev, 0);
 234         if (IS_ERR(mdp->base))
 235                 return PTR_ERR(mdp->base);
 236
 237         mdp->clk_main = devm_clk_get(&pdev->dev, "main");
 238         if (IS_ERR(mdp->clk_main))
 239                 return PTR_ERR(mdp->clk_main);
 240
 241         mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
 242         if (IS_ERR(mdp->clk_mm))
 243                 return PTR_ERR(mdp->clk_mm);
 244
 245         mdp->chip.dev = &pdev->dev;
 246         mdp->chip.ops = &mtk_disp_pwm_ops;
 247         mdp->chip.npwm = 1;
 248
 249         ret = pwmchip_add(&mdp->chip);
 250         if (ret < 0) {
 251                 dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
 252                 return ret;
 253         }
 254
 255         platform_set_drvdata(pdev, mdp);
 256
 257         return 0;
 258 }
 259
 260 static int mtk_disp_pwm_remove(struct platform_device *pdev)
 261 {
 262         struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
 263
 264         pwmchip_remove(&mdp->chip);
 265
 266         return 0;
 267 }
 268
 269 static const struct mtk_pwm_data mt2701_pwm_data = {
 270         .enable_mask = BIT(16),
 271         .con0 = 0xa8,
 272         .con0_sel = 0x2,
 273         .con1 = 0xac,
 274         .has_commit = false,
 275         .bls_debug = 0xb0,
 276         .bls_debug_mask = 0x3,
 277 };
 278
 279 static const struct mtk_pwm_data mt8173_pwm_data = {
 280         .enable_mask = BIT(0),
 281         .con0 = 0x10,
 282         .con0_sel = 0x0,
 283         .con1 = 0x14,
 284         .has_commit = true,
 285         .commit = 0x8,
 286         .commit_mask = 0x1,
 287 };
 288
 289 static const struct mtk_pwm_data mt8183_pwm_data = {
 290         .enable_mask = BIT(0),
 291         .con0 = 0x18,
 292         .con0_sel = 0x0,
 293         .con1 = 0x1c,
 294         .has_commit = false,
 295         .bls_debug = 0x80,
 296         .bls_debug_mask = 0x3,
 297 };
 298
 299 static const struct of_device_id mtk_disp_pwm_of_match[] = {
 300         { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
 301         { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
 302         { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
 303         { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
 304         { }
 305 };
 306 MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
 307
 308 static struct platform_driver mtk_disp_pwm_driver = {
 309         .driver = {
 310                 .name = "mediatek-disp-pwm",
 311                 .of_match_table = mtk_disp_pwm_of_match,
 312         },
 313         .probe = mtk_disp_pwm_probe,
 314         .remove = mtk_disp_pwm_remove,
 315 };
 316 module_platform_driver(mtk_disp_pwm_driver);
 317
 318 MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
 319 MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
 320 MODULE_LICENSE("GPL v2");