1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/platform_device.h>
33 #include <linux/seq_file.h>
34 #include <linux/slab.h>
35 #include <linux/spinlock.h>
36 #include <linux/types.h>
37 #include <dt-bindings/pinctrl/bcm2835.h>
39 #define MODULE_NAME "pinctrl-bcm2835"
40 #define BCM2835_NUM_GPIOS 54
41 #define BCM2711_NUM_GPIOS 58
42 #define BCM2835_NUM_BANKS 2
43 #define BCM2835_NUM_IRQS 3
45 /* GPIO register offsets */
46 #define GPFSEL0 0x0 /* Function Select */
47 #define GPSET0 0x1c /* Pin Output Set */
48 #define GPCLR0 0x28 /* Pin Output Clear */
49 #define GPLEV0 0x34 /* Pin Level */
50 #define GPEDS0 0x40 /* Pin Event Detect Status */
51 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
52 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
53 #define GPHEN0 0x64 /* Pin High Detect Enable */
54 #define GPLEN0 0x70 /* Pin Low Detect Enable */
55 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
56 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
57 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
58 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
59 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
61 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
62 #define FSEL_SHIFT(p) (((p) % 10) * 3)
63 #define GPIO_REG_OFFSET(p) ((p) / 32)
64 #define GPIO_REG_SHIFT(p) ((p) % 32)
66 #define PUD_2711_MASK 0x3
67 #define PUD_2711_REG_OFFSET(p) ((p) / 16)
68 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
70 /* argument: bcm2835_pinconf_pull */
71 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
73 #define BCM2711_PULL_NONE 0x0
74 #define BCM2711_PULL_UP 0x1
75 #define BCM2711_PULL_DOWN 0x2
77 struct bcm2835_pinctrl {
82 /* note: locking assumes each bank will have its own unsigned long */
83 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
84 unsigned int irq_type[BCM2711_NUM_GPIOS];
86 struct pinctrl_dev *pctl_dev;
87 struct gpio_chip gpio_chip;
88 struct pinctrl_desc pctl_desc;
89 struct pinctrl_gpio_range gpio_range;
91 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
94 /* pins are just named GPIO0..GPIO53 */
95 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
96 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
107 BCM2835_GPIO_PIN(10),
108 BCM2835_GPIO_PIN(11),
109 BCM2835_GPIO_PIN(12),
110 BCM2835_GPIO_PIN(13),
111 BCM2835_GPIO_PIN(14),
112 BCM2835_GPIO_PIN(15),
113 BCM2835_GPIO_PIN(16),
114 BCM2835_GPIO_PIN(17),
115 BCM2835_GPIO_PIN(18),
116 BCM2835_GPIO_PIN(19),
117 BCM2835_GPIO_PIN(20),
118 BCM2835_GPIO_PIN(21),
119 BCM2835_GPIO_PIN(22),
120 BCM2835_GPIO_PIN(23),
121 BCM2835_GPIO_PIN(24),
122 BCM2835_GPIO_PIN(25),
123 BCM2835_GPIO_PIN(26),
124 BCM2835_GPIO_PIN(27),
125 BCM2835_GPIO_PIN(28),
126 BCM2835_GPIO_PIN(29),
127 BCM2835_GPIO_PIN(30),
128 BCM2835_GPIO_PIN(31),
129 BCM2835_GPIO_PIN(32),
130 BCM2835_GPIO_PIN(33),
131 BCM2835_GPIO_PIN(34),
132 BCM2835_GPIO_PIN(35),
133 BCM2835_GPIO_PIN(36),
134 BCM2835_GPIO_PIN(37),
135 BCM2835_GPIO_PIN(38),
136 BCM2835_GPIO_PIN(39),
137 BCM2835_GPIO_PIN(40),
138 BCM2835_GPIO_PIN(41),
139 BCM2835_GPIO_PIN(42),
140 BCM2835_GPIO_PIN(43),
141 BCM2835_GPIO_PIN(44),
142 BCM2835_GPIO_PIN(45),
143 BCM2835_GPIO_PIN(46),
144 BCM2835_GPIO_PIN(47),
145 BCM2835_GPIO_PIN(48),
146 BCM2835_GPIO_PIN(49),
147 BCM2835_GPIO_PIN(50),
148 BCM2835_GPIO_PIN(51),
149 BCM2835_GPIO_PIN(52),
150 BCM2835_GPIO_PIN(53),
151 BCM2835_GPIO_PIN(54),
152 BCM2835_GPIO_PIN(55),
153 BCM2835_GPIO_PIN(56),
154 BCM2835_GPIO_PIN(57),
157 /* one pin per group */
158 static const char * const bcm2835_gpio_groups[] = {
220 BCM2835_FSEL_COUNT = 8,
221 BCM2835_FSEL_MASK = 0x7,
224 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
225 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
226 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
227 [BCM2835_FSEL_ALT0] = "alt0",
228 [BCM2835_FSEL_ALT1] = "alt1",
229 [BCM2835_FSEL_ALT2] = "alt2",
230 [BCM2835_FSEL_ALT3] = "alt3",
231 [BCM2835_FSEL_ALT4] = "alt4",
232 [BCM2835_FSEL_ALT5] = "alt5",
235 static const char * const irq_type_names[] = {
236 [IRQ_TYPE_NONE] = "none",
237 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
238 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
239 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
240 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
241 [IRQ_TYPE_LEVEL_LOW] = "level-low",
244 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
246 return readl(pc->base + reg);
249 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
252 writel(val, pc->base + reg);
255 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
258 reg += GPIO_REG_OFFSET(bit) * 4;
259 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
262 /* note NOT a read/modify/write cycle */
263 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
264 unsigned reg, unsigned bit)
266 reg += GPIO_REG_OFFSET(bit) * 4;
267 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
270 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
271 struct bcm2835_pinctrl *pc, unsigned pin)
273 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
274 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
276 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
277 bcm2835_functions[status]);
282 static inline void bcm2835_pinctrl_fsel_set(
283 struct bcm2835_pinctrl *pc, unsigned pin,
284 enum bcm2835_fsel fsel)
286 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
287 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
289 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
290 bcm2835_functions[cur]);
295 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
296 /* always transition through GPIO_IN */
297 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
298 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
300 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
301 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
302 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
305 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
306 val |= fsel << FSEL_SHIFT(pin);
308 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
309 bcm2835_functions[fsel]);
310 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
313 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
315 return pinctrl_gpio_direction_input(chip->base + offset);
318 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
320 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
322 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
325 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
327 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
328 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
330 /* Alternative function doesn't clearly provide a direction */
331 if (fsel > BCM2835_FSEL_GPIO_OUT)
334 if (fsel == BCM2835_FSEL_GPIO_IN)
335 return GPIO_LINE_DIRECTION_IN;
337 return GPIO_LINE_DIRECTION_OUT;
340 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
342 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
344 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
347 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
348 unsigned offset, int value)
350 bcm2835_gpio_set(chip, offset, value);
351 return pinctrl_gpio_direction_output(chip->base + offset);
354 static const struct gpio_chip bcm2835_gpio_chip = {
355 .label = MODULE_NAME,
356 .owner = THIS_MODULE,
357 .request = gpiochip_generic_request,
358 .free = gpiochip_generic_free,
359 .direction_input = bcm2835_gpio_direction_input,
360 .direction_output = bcm2835_gpio_direction_output,
361 .get_direction = bcm2835_gpio_get_direction,
362 .get = bcm2835_gpio_get,
363 .set = bcm2835_gpio_set,
364 .set_config = gpiochip_generic_config,
366 .ngpio = BCM2835_NUM_GPIOS,
370 static const struct gpio_chip bcm2711_gpio_chip = {
371 .label = "pinctrl-bcm2711",
372 .owner = THIS_MODULE,
373 .request = gpiochip_generic_request,
374 .free = gpiochip_generic_free,
375 .direction_input = bcm2835_gpio_direction_input,
376 .direction_output = bcm2835_gpio_direction_output,
377 .get_direction = bcm2835_gpio_get_direction,
378 .get = bcm2835_gpio_get,
379 .set = bcm2835_gpio_set,
380 .set_config = gpiochip_generic_config,
382 .ngpio = BCM2711_NUM_GPIOS,
386 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
387 unsigned int bank, u32 mask)
389 unsigned long events;
393 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
395 events &= pc->enabled_irq_map[bank];
396 for_each_set_bit(offset, &events, 32) {
397 gpio = (32 * bank) + offset;
398 generic_handle_domain_irq(pc->gpio_chip.irq.domain,
403 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
405 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
406 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
407 struct irq_chip *host_chip = irq_desc_get_chip(desc);
408 int irq = irq_desc_get_irq(desc);
412 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
413 if (chip->irq.parents[i] == irq) {
418 /* This should not happen, every IRQ has a bank */
419 BUG_ON(i == BCM2835_NUM_IRQS);
421 chained_irq_enter(host_chip, desc);
424 case 0: /* IRQ0 covers GPIOs 0-27 */
425 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
427 case 1: /* IRQ1 covers GPIOs 28-45 */
428 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
429 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
431 case 2: /* IRQ2 covers GPIOs 46-57 */
432 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
436 chained_irq_exit(host_chip, desc);
439 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
444 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
445 unsigned reg, unsigned offset, bool enable)
448 reg += GPIO_REG_OFFSET(offset) * 4;
449 value = bcm2835_gpio_rd(pc, reg);
451 value |= BIT(GPIO_REG_SHIFT(offset));
453 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
454 bcm2835_gpio_wr(pc, reg, value);
457 /* fast path for IRQ handler */
458 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
459 unsigned offset, bool enable)
461 switch (pc->irq_type[offset]) {
462 case IRQ_TYPE_EDGE_RISING:
463 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
466 case IRQ_TYPE_EDGE_FALLING:
467 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
470 case IRQ_TYPE_EDGE_BOTH:
471 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
472 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
475 case IRQ_TYPE_LEVEL_HIGH:
476 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
479 case IRQ_TYPE_LEVEL_LOW:
480 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
485 static void bcm2835_gpio_irq_enable(struct irq_data *data)
487 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
488 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
489 unsigned gpio = irqd_to_hwirq(data);
490 unsigned offset = GPIO_REG_SHIFT(gpio);
491 unsigned bank = GPIO_REG_OFFSET(gpio);
494 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
495 set_bit(offset, &pc->enabled_irq_map[bank]);
496 bcm2835_gpio_irq_config(pc, gpio, true);
497 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
500 static void bcm2835_gpio_irq_disable(struct irq_data *data)
502 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
503 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
504 unsigned gpio = irqd_to_hwirq(data);
505 unsigned offset = GPIO_REG_SHIFT(gpio);
506 unsigned bank = GPIO_REG_OFFSET(gpio);
509 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
510 bcm2835_gpio_irq_config(pc, gpio, false);
511 /* Clear events that were latched prior to clearing event sources */
512 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
513 clear_bit(offset, &pc->enabled_irq_map[bank]);
514 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
517 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
518 unsigned offset, unsigned int type)
522 case IRQ_TYPE_EDGE_RISING:
523 case IRQ_TYPE_EDGE_FALLING:
524 case IRQ_TYPE_EDGE_BOTH:
525 case IRQ_TYPE_LEVEL_HIGH:
526 case IRQ_TYPE_LEVEL_LOW:
527 pc->irq_type[offset] = type;
536 /* slower path for reconfiguring IRQ type */
537 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
538 unsigned offset, unsigned int type)
542 if (pc->irq_type[offset] != type) {
543 bcm2835_gpio_irq_config(pc, offset, false);
544 pc->irq_type[offset] = type;
548 case IRQ_TYPE_EDGE_RISING:
549 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
550 /* RISING already enabled, disable FALLING */
551 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
552 bcm2835_gpio_irq_config(pc, offset, false);
553 pc->irq_type[offset] = type;
554 } else if (pc->irq_type[offset] != type) {
555 bcm2835_gpio_irq_config(pc, offset, false);
556 pc->irq_type[offset] = type;
557 bcm2835_gpio_irq_config(pc, offset, true);
561 case IRQ_TYPE_EDGE_FALLING:
562 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
563 /* FALLING already enabled, disable RISING */
564 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
565 bcm2835_gpio_irq_config(pc, offset, false);
566 pc->irq_type[offset] = type;
567 } else if (pc->irq_type[offset] != type) {
568 bcm2835_gpio_irq_config(pc, offset, false);
569 pc->irq_type[offset] = type;
570 bcm2835_gpio_irq_config(pc, offset, true);
574 case IRQ_TYPE_EDGE_BOTH:
575 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
576 /* RISING already enabled, enable FALLING too */
577 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
578 bcm2835_gpio_irq_config(pc, offset, true);
579 pc->irq_type[offset] = type;
580 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
581 /* FALLING already enabled, enable RISING too */
582 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
583 bcm2835_gpio_irq_config(pc, offset, true);
584 pc->irq_type[offset] = type;
585 } else if (pc->irq_type[offset] != type) {
586 bcm2835_gpio_irq_config(pc, offset, false);
587 pc->irq_type[offset] = type;
588 bcm2835_gpio_irq_config(pc, offset, true);
592 case IRQ_TYPE_LEVEL_HIGH:
593 case IRQ_TYPE_LEVEL_LOW:
594 if (pc->irq_type[offset] != type) {
595 bcm2835_gpio_irq_config(pc, offset, false);
596 pc->irq_type[offset] = type;
597 bcm2835_gpio_irq_config(pc, offset, true);
607 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
609 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
610 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
611 unsigned gpio = irqd_to_hwirq(data);
612 unsigned offset = GPIO_REG_SHIFT(gpio);
613 unsigned bank = GPIO_REG_OFFSET(gpio);
617 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
619 if (test_bit(offset, &pc->enabled_irq_map[bank]))
620 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
622 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
624 if (type & IRQ_TYPE_EDGE_BOTH)
625 irq_set_handler_locked(data, handle_edge_irq);
627 irq_set_handler_locked(data, handle_level_irq);
629 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
634 static void bcm2835_gpio_irq_ack(struct irq_data *data)
636 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
637 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
638 unsigned gpio = irqd_to_hwirq(data);
640 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
643 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
645 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
646 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
647 unsigned gpio = irqd_to_hwirq(data);
648 unsigned int irqgroup;
656 else if (gpio >= 28 && gpio <= 45)
658 else if (gpio >= 46 && gpio <= 57)
664 ret = enable_irq_wake(pc->wake_irq[irqgroup]);
666 ret = disable_irq_wake(pc->wake_irq[irqgroup]);
671 static struct irq_chip bcm2835_gpio_irq_chip = {
673 .irq_enable = bcm2835_gpio_irq_enable,
674 .irq_disable = bcm2835_gpio_irq_disable,
675 .irq_set_type = bcm2835_gpio_irq_set_type,
676 .irq_ack = bcm2835_gpio_irq_ack,
677 .irq_mask = bcm2835_gpio_irq_disable,
678 .irq_unmask = bcm2835_gpio_irq_enable,
679 .irq_set_wake = bcm2835_gpio_irq_set_wake,
680 .flags = IRQCHIP_MASK_ON_SUSPEND,
683 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
685 return BCM2835_NUM_GPIOS;
688 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
691 return bcm2835_gpio_groups[selector];
694 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
696 const unsigned **pins,
699 *pins = &bcm2835_gpio_pins[selector].number;
705 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
709 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
710 struct gpio_chip *chip = &pc->gpio_chip;
711 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
712 const char *fname = bcm2835_functions[fsel];
713 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
714 int irq = irq_find_mapping(chip->irq.domain, offset);
716 seq_printf(s, "function %s in %s; irq %d (%s)",
717 fname, value ? "hi" : "lo",
718 irq, irq_type_names[pc->irq_type[offset]]);
721 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
722 struct pinctrl_map *maps, unsigned num_maps)
726 for (i = 0; i < num_maps; i++)
727 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
728 kfree(maps[i].data.configs.configs);
733 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
734 struct device_node *np, u32 pin, u32 fnum,
735 struct pinctrl_map **maps)
737 struct pinctrl_map *map = *maps;
739 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
740 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
744 map->type = PIN_MAP_TYPE_MUX_GROUP;
745 map->data.mux.group = bcm2835_gpio_groups[pin];
746 map->data.mux.function = bcm2835_functions[fnum];
752 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
753 struct device_node *np, u32 pin, u32 pull,
754 struct pinctrl_map **maps)
756 struct pinctrl_map *map = *maps;
757 unsigned long *configs;
760 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
764 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
767 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
769 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
770 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
771 map->data.configs.configs = configs;
772 map->data.configs.num_configs = 1;
778 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
779 struct device_node *np,
780 struct pinctrl_map **map, unsigned int *num_maps)
782 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
783 struct property *pins, *funcs, *pulls;
784 int num_pins, num_funcs, num_pulls, maps_per_pin;
785 struct pinctrl_map *maps, *cur_map;
789 /* Check for generic binding in this node */
790 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
791 if (err || *num_maps)
794 /* Generic binding did not find anything continue with legacy parse */
795 pins = of_find_property(np, "brcm,pins", NULL);
797 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
801 funcs = of_find_property(np, "brcm,function", NULL);
802 pulls = of_find_property(np, "brcm,pull", NULL);
804 if (!funcs && !pulls) {
806 "%pOF: neither brcm,function nor brcm,pull specified\n",
811 num_pins = pins->length / 4;
812 num_funcs = funcs ? (funcs->length / 4) : 0;
813 num_pulls = pulls ? (pulls->length / 4) : 0;
815 if (num_funcs > 1 && num_funcs != num_pins) {
817 "%pOF: brcm,function must have 1 or %d entries\n",
822 if (num_pulls > 1 && num_pulls != num_pins) {
824 "%pOF: brcm,pull must have 1 or %d entries\n",
834 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
839 for (i = 0; i < num_pins; i++) {
840 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
843 if (pin >= pc->pctl_desc.npins) {
844 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
851 err = of_property_read_u32_index(np, "brcm,function",
852 (num_funcs > 1) ? i : 0, &func);
855 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
861 err = of_property_read_u32_index(np, "brcm,pull",
862 (num_pulls > 1) ? i : 0, &pull);
865 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
873 *num_maps = num_pins * maps_per_pin;
878 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
882 static const struct pinctrl_ops bcm2835_pctl_ops = {
883 .get_groups_count = bcm2835_pctl_get_groups_count,
884 .get_group_name = bcm2835_pctl_get_group_name,
885 .get_group_pins = bcm2835_pctl_get_group_pins,
886 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
887 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
888 .dt_free_map = bcm2835_pctl_dt_free_map,
891 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
894 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
896 /* disable by setting to GPIO_IN */
897 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
901 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
903 return BCM2835_FSEL_COUNT;
906 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
909 return bcm2835_functions[selector];
912 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
914 const char * const **groups,
915 unsigned * const num_groups)
917 /* every pin can do every function */
918 *groups = bcm2835_gpio_groups;
919 *num_groups = BCM2835_NUM_GPIOS;
924 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
925 unsigned func_selector,
926 unsigned group_selector)
928 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
930 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
935 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
936 struct pinctrl_gpio_range *range,
939 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
941 /* disable by setting to GPIO_IN */
942 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
945 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
946 struct pinctrl_gpio_range *range,
950 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
951 enum bcm2835_fsel fsel = input ?
952 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
954 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
959 static const struct pinmux_ops bcm2835_pmx_ops = {
960 .free = bcm2835_pmx_free,
961 .get_functions_count = bcm2835_pmx_get_functions_count,
962 .get_function_name = bcm2835_pmx_get_function_name,
963 .get_function_groups = bcm2835_pmx_get_function_groups,
964 .set_mux = bcm2835_pmx_set,
965 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
966 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
969 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
970 unsigned pin, unsigned long *config)
972 /* No way to read back config in HW */
976 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
977 unsigned int pin, unsigned int arg)
981 off = GPIO_REG_OFFSET(pin);
982 bit = GPIO_REG_SHIFT(pin);
984 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
986 * BCM2835 datasheet say to wait 150 cycles, but not of what.
987 * But the VideoCore firmware delay for this operation
988 * based nearly on the same amount of VPU cycles and this clock
992 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
994 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
997 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
998 unsigned int pin, unsigned long *configs,
999 unsigned int num_configs)
1001 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1005 for (i = 0; i < num_configs; i++) {
1006 param = pinconf_to_config_param(configs[i]);
1007 arg = pinconf_to_config_argument(configs[i]);
1010 /* Set legacy brcm,pull */
1011 case BCM2835_PINCONF_PARAM_PULL:
1012 bcm2835_pull_config_set(pc, pin, arg);
1015 /* Set pull generic bindings */
1016 case PIN_CONFIG_BIAS_DISABLE:
1017 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1020 case PIN_CONFIG_BIAS_PULL_DOWN:
1021 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1024 case PIN_CONFIG_BIAS_PULL_UP:
1025 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1028 /* Set output-high or output-low */
1029 case PIN_CONFIG_OUTPUT:
1030 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1036 } /* switch param type */
1037 } /* for each config */
1042 static const struct pinconf_ops bcm2835_pinconf_ops = {
1044 .pin_config_get = bcm2835_pinconf_get,
1045 .pin_config_set = bcm2835_pinconf_set,
1048 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1049 unsigned int pin, unsigned int arg)
1055 off = PUD_2711_REG_OFFSET(pin);
1056 shifter = PUD_2711_REG_SHIFT(pin);
1058 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1059 value &= ~(PUD_2711_MASK << shifter);
1060 value |= (arg << shifter);
1061 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1064 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1065 unsigned int pin, unsigned long *configs,
1066 unsigned int num_configs)
1068 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1072 for (i = 0; i < num_configs; i++) {
1073 param = pinconf_to_config_param(configs[i]);
1074 arg = pinconf_to_config_argument(configs[i]);
1077 /* convert legacy brcm,pull */
1078 case BCM2835_PINCONF_PARAM_PULL:
1079 if (arg == BCM2835_PUD_UP)
1080 arg = BCM2711_PULL_UP;
1081 else if (arg == BCM2835_PUD_DOWN)
1082 arg = BCM2711_PULL_DOWN;
1084 arg = BCM2711_PULL_NONE;
1086 bcm2711_pull_config_set(pc, pin, arg);
1089 /* Set pull generic bindings */
1090 case PIN_CONFIG_BIAS_DISABLE:
1091 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1093 case PIN_CONFIG_BIAS_PULL_DOWN:
1094 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1096 case PIN_CONFIG_BIAS_PULL_UP:
1097 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1100 /* Set output-high or output-low */
1101 case PIN_CONFIG_OUTPUT:
1102 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1108 } /* for each config */
1113 static const struct pinconf_ops bcm2711_pinconf_ops = {
1115 .pin_config_get = bcm2835_pinconf_get,
1116 .pin_config_set = bcm2711_pinconf_set,
1119 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1120 .name = MODULE_NAME,
1121 .pins = bcm2835_gpio_pins,
1122 .npins = BCM2835_NUM_GPIOS,
1123 .pctlops = &bcm2835_pctl_ops,
1124 .pmxops = &bcm2835_pmx_ops,
1125 .confops = &bcm2835_pinconf_ops,
1126 .owner = THIS_MODULE,
1129 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1130 .name = "pinctrl-bcm2711",
1131 .pins = bcm2835_gpio_pins,
1132 .npins = BCM2711_NUM_GPIOS,
1133 .pctlops = &bcm2835_pctl_ops,
1134 .pmxops = &bcm2835_pmx_ops,
1135 .confops = &bcm2711_pinconf_ops,
1136 .owner = THIS_MODULE,
1139 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1140 .name = MODULE_NAME,
1141 .npins = BCM2835_NUM_GPIOS,
1144 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1145 .name = "pinctrl-bcm2711",
1146 .npins = BCM2711_NUM_GPIOS,
1149 struct bcm_plat_data {
1150 const struct gpio_chip *gpio_chip;
1151 const struct pinctrl_desc *pctl_desc;
1152 const struct pinctrl_gpio_range *gpio_range;
1155 static const struct bcm_plat_data bcm2835_plat_data = {
1156 .gpio_chip = &bcm2835_gpio_chip,
1157 .pctl_desc = &bcm2835_pinctrl_desc,
1158 .gpio_range = &bcm2835_pinctrl_gpio_range,
1161 static const struct bcm_plat_data bcm2711_plat_data = {
1162 .gpio_chip = &bcm2711_gpio_chip,
1163 .pctl_desc = &bcm2711_pinctrl_desc,
1164 .gpio_range = &bcm2711_pinctrl_gpio_range,
1167 static const struct of_device_id bcm2835_pinctrl_match[] = {
1169 .compatible = "brcm,bcm2835-gpio",
1170 .data = &bcm2835_plat_data,
1173 .compatible = "brcm,bcm2711-gpio",
1174 .data = &bcm2711_plat_data,
1177 .compatible = "brcm,bcm7211-gpio",
1178 .data = &bcm2711_plat_data,
1183 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1185 struct device *dev = &pdev->dev;
1186 struct device_node *np = dev->of_node;
1187 const struct bcm_plat_data *pdata;
1188 struct bcm2835_pinctrl *pc;
1189 struct gpio_irq_chip *girq;
1190 struct resource iomem;
1192 const struct of_device_id *match;
1195 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1196 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1198 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1202 platform_set_drvdata(pdev, pc);
1205 err = of_address_to_resource(np, 0, &iomem);
1207 dev_err(dev, "could not get IO memory\n");
1211 pc->base = devm_ioremap_resource(dev, &iomem);
1212 if (IS_ERR(pc->base))
1213 return PTR_ERR(pc->base);
1215 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1219 pdata = match->data;
1220 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1222 pc->gpio_chip = *pdata->gpio_chip;
1223 pc->gpio_chip.parent = dev;
1224 pc->gpio_chip.of_node = np;
1226 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1227 unsigned long events;
1230 /* clear event detection flags */
1231 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1232 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1233 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1234 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1235 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1236 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1238 /* clear all the events */
1239 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1240 for_each_set_bit(offset, &events, 32)
1241 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1243 raw_spin_lock_init(&pc->irq_lock[i]);
1246 girq = &pc->gpio_chip.irq;
1247 girq->chip = &bcm2835_gpio_irq_chip;
1248 girq->parent_handler = bcm2835_gpio_irq_handler;
1249 girq->num_parents = BCM2835_NUM_IRQS;
1250 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1251 sizeof(*girq->parents),
1257 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1258 sizeof(*pc->wake_irq),
1265 * Use the same handler for all groups: this is necessary
1266 * since we use one gpiochip to cover all lines - the
1267 * irq handler then needs to figure out which group and
1268 * bank that was firing the IRQ and look up the per-group
1271 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1275 girq->parents[i] = irq_of_parse_and_map(np, i);
1277 if (!girq->parents[i]) {
1278 girq->num_parents = i;
1283 /* Skip over the all banks interrupts */
1284 pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1285 BCM2835_NUM_IRQS + 1);
1287 len = strlen(dev_name(pc->dev)) + 16;
1288 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1292 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1294 /* These are optional interrupts */
1295 err = devm_request_irq(dev, pc->wake_irq[i],
1296 bcm2835_gpio_wake_irq_handler,
1297 IRQF_SHARED, name, pc);
1299 dev_warn(dev, "unable to request wake IRQ %d\n",
1303 girq->default_type = IRQ_TYPE_NONE;
1304 girq->handler = handle_level_irq;
1306 err = gpiochip_add_data(&pc->gpio_chip, pc);
1308 dev_err(dev, "could not add GPIO chip\n");
1312 pc->pctl_desc = *pdata->pctl_desc;
1313 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1314 if (IS_ERR(pc->pctl_dev)) {
1315 gpiochip_remove(&pc->gpio_chip);
1316 return PTR_ERR(pc->pctl_dev);
1319 pc->gpio_range = *pdata->gpio_range;
1320 pc->gpio_range.base = pc->gpio_chip.base;
1321 pc->gpio_range.gc = &pc->gpio_chip;
1322 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1327 static struct platform_driver bcm2835_pinctrl_driver = {
1328 .probe = bcm2835_pinctrl_probe,
1330 .name = MODULE_NAME,
1331 .of_match_table = bcm2835_pinctrl_match,
1332 .suppress_bind_attrs = true,
1335 builtin_platform_driver(bcm2835_pinctrl_driver);