drivers/phy/st/phy-stm32-usbphyc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * STMicroelectronics STM32 USB PHY Controller driver
   4  *
   5  * Copyright (C) 2018 STMicroelectronics
   6  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
   7  */
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/delay.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/reset.h>
  18 #include <linux/units.h>
  19
  20 #define STM32_USBPHYC_PLL       0x0
  21 #define STM32_USBPHYC_MISC      0x8
  22 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
  23 #define STM32_USBPHYC_VERSION   0x3F4
  24
  25 /* STM32_USBPHYC_PLL bit fields */
  26 #define PLLNDIV                 GENMASK(6, 0)
  27 #define PLLFRACIN               GENMASK(25, 10)
  28 #define PLLEN                   BIT(26)
  29 #define PLLSTRB                 BIT(27)
  30 #define PLLSTRBYP               BIT(28)
  31 #define PLLFRACCTL              BIT(29)
  32 #define PLLDITHEN0              BIT(30)
  33 #define PLLDITHEN1              BIT(31)
  34
  35 /* STM32_USBPHYC_MISC bit fields */
  36 #define SWITHOST                BIT(0)
  37
  38 /* STM32_USBPHYC_MONITOR bit fields */
  39 #define STM32_USBPHYC_MON_OUT   GENMASK(3, 0)
  40 #define STM32_USBPHYC_MON_SEL   GENMASK(8, 4)
  41 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
  42 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
  43
  44 /* STM32_USBPHYC_VERSION bit fields */
  45 #define MINREV                  GENMASK(3, 0)
  46 #define MAJREV                  GENMASK(7, 4)
  47
  48 #define PLL_FVCO_MHZ            2880
  49 #define PLL_INFF_MIN_RATE_HZ    19200000
  50 #define PLL_INFF_MAX_RATE_HZ    38400000
  51
  52 struct pll_params {
  53         u8 ndiv;
  54         u16 frac;
  55 };
  56
  57 struct stm32_usbphyc_phy {
  58         struct phy *phy;
  59         struct stm32_usbphyc *usbphyc;
  60         struct regulator *vbus;
  61         u32 index;
  62         bool active;
  63 };
  64
  65 struct stm32_usbphyc {
  66         struct device *dev;
  67         void __iomem *base;
  68         struct clk *clk;
  69         struct reset_control *rst;
  70         struct stm32_usbphyc_phy **phys;
  71         int nphys;
  72         struct regulator *vdda1v1;
  73         struct regulator *vdda1v8;
  74         atomic_t n_pll_cons;
  75         struct clk_hw clk48_hw;
  76         int switch_setup;
  77 };
  78
  79 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
  80 {
  81         writel_relaxed(readl_relaxed(reg) | bits, reg);
  82 }
  83
  84 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
  85 {
  86         writel_relaxed(readl_relaxed(reg) & ~bits, reg);
  87 }
  88
  89 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
  90 {
  91         int ret;
  92
  93         ret = regulator_enable(usbphyc->vdda1v1);
  94         if (ret)
  95                 return ret;
  96
  97         ret = regulator_enable(usbphyc->vdda1v8);
  98         if (ret)
  99                 goto vdda1v1_disable;
 100
 101         return 0;
 102
 103 vdda1v1_disable:
 104         regulator_disable(usbphyc->vdda1v1);
 105
 106         return ret;
 107 }
 108
 109 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
 110 {
 111         int ret;
 112
 113         ret = regulator_disable(usbphyc->vdda1v8);
 114         if (ret)
 115                 return ret;
 116
 117         ret = regulator_disable(usbphyc->vdda1v1);
 118         if (ret)
 119                 return ret;
 120
 121         return 0;
 122 }
 123
 124 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
 125                                          struct pll_params *pll_params)
 126 {
 127         unsigned long long fvco, ndiv, frac;
 128
 129         /*    _
 130          *   | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
 131          *   | FVCO = 2880MHz
 132          *  <
 133          *   | NDIV = integer part of input bits to set the LDF
 134          *   |_FRACT = fractional part of input bits to set the LDF
 135          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
 136          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
 137          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
 138          */
 139         fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
 140
 141         ndiv = fvco;
 142         do_div(ndiv, (clk_rate * 2));
 143         pll_params->ndiv = (u8)ndiv;
 144
 145         frac = fvco * (1 << 16);
 146         do_div(frac, (clk_rate * 2));
 147         frac = frac - (ndiv * (1 << 16));
 148         pll_params->frac = (u16)frac;
 149 }
 150
 151 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
 152 {
 153         struct pll_params pll_params;
 154         u32 clk_rate = clk_get_rate(usbphyc->clk);
 155         u32 ndiv, frac;
 156         u32 usbphyc_pll;
 157
 158         if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
 159             (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
 160                 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
 161                         clk_rate);
 162                 return -EINVAL;
 163         }
 164
 165         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 166         ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
 167         frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
 168
 169         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
 170
 171         if (pll_params.frac)
 172                 usbphyc_pll |= PLLFRACCTL | frac;
 173
 174         writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 175
 176         dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
 177                 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
 178                 FIELD_GET(PLLFRACIN, usbphyc_pll));
 179
 180         return 0;
 181 }
 182
 183 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 184 {
 185         void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
 186         u32 pllen;
 187
 188         stm32_usbphyc_clr_bits(pll_reg, PLLEN);
 189
 190         /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
 191         if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
 192                 dev_err(usbphyc->dev, "PLL not reset\n");
 193
 194         return stm32_usbphyc_regulators_disable(usbphyc);
 195 }
 196
 197 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 198 {
 199         /* Check if a phy port is still active or clk48 in use */
 200         if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
 201                 return 0;
 202
 203         return __stm32_usbphyc_pll_disable(usbphyc);
 204 }
 205
 206 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
 207 {
 208         void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
 209         bool pllen = readl_relaxed(pll_reg) & PLLEN;
 210         int ret;
 211
 212         /*
 213          * Check if a phy port or clk48 prepare has configured the pll
 214          * and ensure the PLL is enabled
 215          */
 216         if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
 217                 return 0;
 218
 219         if (pllen) {
 220                 /*
 221                  * PLL shouldn't be enabled without known consumer,
 222                  * disable it and reinit n_pll_cons
 223                  */
 224                 dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
 225
 226                 ret = __stm32_usbphyc_pll_disable(usbphyc);
 227                 if (ret)
 228                         return ret;
 229         }
 230
 231         ret = stm32_usbphyc_regulators_enable(usbphyc);
 232         if (ret)
 233                 goto dec_n_pll_cons;
 234
 235         ret = stm32_usbphyc_pll_init(usbphyc);
 236         if (ret)
 237                 goto reg_disable;
 238
 239         stm32_usbphyc_set_bits(pll_reg, PLLEN);
 240
 241         return 0;
 242
 243 reg_disable:
 244         stm32_usbphyc_regulators_disable(usbphyc);
 245
 246 dec_n_pll_cons:
 247         atomic_dec(&usbphyc->n_pll_cons);
 248
 249         return ret;
 250 }
 251
 252 static int stm32_usbphyc_phy_init(struct phy *phy)
 253 {
 254         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 255         struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
 256         u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
 257         u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
 258                                 STM32_USBPHYC_MON_SEL_LOCKP);
 259         u32 monout;
 260         int ret;
 261
 262         ret = stm32_usbphyc_pll_enable(usbphyc);
 263         if (ret)
 264                 return ret;
 265
 266         /* Check that PLL Lock input to PHY is High */
 267         writel_relaxed(monsel, usbphyc->base + reg_mon);
 268         ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
 269                                          (monout & STM32_USBPHYC_MON_OUT_LOCKP),
 270                                          100, 1000);
 271         if (ret) {
 272                 dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
 273                         (u32)(monout & STM32_USBPHYC_MON_OUT));
 274                 goto pll_disable;
 275         }
 276
 277         usbphyc_phy->active = true;
 278
 279         return 0;
 280
 281 pll_disable:
 282         return stm32_usbphyc_pll_disable(usbphyc);
 283 }
 284
 285 static int stm32_usbphyc_phy_exit(struct phy *phy)
 286 {
 287         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 288         struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
 289
 290         usbphyc_phy->active = false;
 291
 292         return stm32_usbphyc_pll_disable(usbphyc);
 293 }
 294
 295 static int stm32_usbphyc_phy_power_on(struct phy *phy)
 296 {
 297         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 298
 299         if (usbphyc_phy->vbus)
 300                 return regulator_enable(usbphyc_phy->vbus);
 301
 302         return 0;
 303 }
 304
 305 static int stm32_usbphyc_phy_power_off(struct phy *phy)
 306 {
 307         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 308
 309         if (usbphyc_phy->vbus)
 310                 return regulator_disable(usbphyc_phy->vbus);
 311
 312         return 0;
 313 }
 314
 315 static const struct phy_ops stm32_usbphyc_phy_ops = {
 316         .init = stm32_usbphyc_phy_init,
 317         .exit = stm32_usbphyc_phy_exit,
 318         .power_on = stm32_usbphyc_phy_power_on,
 319         .power_off = stm32_usbphyc_phy_power_off,
 320         .owner = THIS_MODULE,
 321 };
 322
 323 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
 324 {
 325         struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
 326
 327         return stm32_usbphyc_pll_enable(usbphyc);
 328 }
 329
 330 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
 331 {
 332         struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
 333
 334         stm32_usbphyc_pll_disable(usbphyc);
 335 }
 336
 337 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 338 {
 339         return 48000000;
 340 }
 341
 342 static const struct clk_ops usbphyc_clk48_ops = {
 343         .prepare = stm32_usbphyc_clk48_prepare,
 344         .unprepare = stm32_usbphyc_clk48_unprepare,
 345         .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
 346 };
 347
 348 static void stm32_usbphyc_clk48_unregister(void *data)
 349 {
 350         struct stm32_usbphyc *usbphyc = data;
 351
 352         of_clk_del_provider(usbphyc->dev->of_node);
 353         clk_hw_unregister(&usbphyc->clk48_hw);
 354 }
 355
 356 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
 357 {
 358         struct device_node *node = usbphyc->dev->of_node;
 359         struct clk_init_data init = { };
 360         int ret = 0;
 361
 362         init.name = "ck_usbo_48m";
 363         init.ops = &usbphyc_clk48_ops;
 364
 365         usbphyc->clk48_hw.init = &init;
 366
 367         ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
 368         if (ret)
 369                 return ret;
 370
 371         ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
 372         if (ret)
 373                 clk_hw_unregister(&usbphyc->clk48_hw);
 374
 375         return ret;
 376 }
 377
 378 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
 379                                        u32 utmi_switch)
 380 {
 381         if (!utmi_switch)
 382                 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
 383                                        SWITHOST);
 384         else
 385                 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
 386                                        SWITHOST);
 387         usbphyc->switch_setup = utmi_switch;
 388 }
 389
 390 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
 391                                           struct of_phandle_args *args)
 392 {
 393         struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
 394         struct stm32_usbphyc_phy *usbphyc_phy = NULL;
 395         struct device_node *phynode = args->np;
 396         int port = 0;
 397
 398         for (port = 0; port < usbphyc->nphys; port++) {
 399                 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
 400                         usbphyc_phy = usbphyc->phys[port];
 401                         break;
 402                 }
 403         }
 404         if (!usbphyc_phy) {
 405                 dev_err(dev, "failed to find phy\n");
 406                 return ERR_PTR(-EINVAL);
 407         }
 408
 409         if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
 410             ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
 411                 dev_err(dev, "invalid number of cells for phy port%d\n",
 412                         usbphyc_phy->index);
 413                 return ERR_PTR(-EINVAL);
 414         }
 415
 416         /* Configure the UTMI switch for PHY port#2 */
 417         if (usbphyc_phy->index == 1) {
 418                 if (usbphyc->switch_setup < 0) {
 419                         stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
 420                 } else {
 421                         if (args->args[0] != usbphyc->switch_setup) {
 422                                 dev_err(dev, "phy port1 already used\n");
 423                                 return ERR_PTR(-EBUSY);
 424                         }
 425                 }
 426         }
 427
 428         return usbphyc_phy->phy;
 429 }
 430
 431 static int stm32_usbphyc_probe(struct platform_device *pdev)
 432 {
 433         struct stm32_usbphyc *usbphyc;
 434         struct device *dev = &pdev->dev;
 435         struct device_node *child, *np = dev->of_node;
 436         struct phy_provider *phy_provider;
 437         u32 pllen, version;
 438         int ret, port = 0;
 439
 440         usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
 441         if (!usbphyc)
 442                 return -ENOMEM;
 443         usbphyc->dev = dev;
 444         dev_set_drvdata(dev, usbphyc);
 445
 446         usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
 447         if (IS_ERR(usbphyc->base))
 448                 return PTR_ERR(usbphyc->base);
 449
 450         usbphyc->clk = devm_clk_get(dev, NULL);
 451         if (IS_ERR(usbphyc->clk))
 452                 return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
 453
 454         ret = clk_prepare_enable(usbphyc->clk);
 455         if (ret) {
 456                 dev_err(dev, "clk enable failed: %d\n", ret);
 457                 return ret;
 458         }
 459
 460         usbphyc->rst = devm_reset_control_get(dev, NULL);
 461         if (!IS_ERR(usbphyc->rst)) {
 462                 reset_control_assert(usbphyc->rst);
 463                 udelay(2);
 464                 reset_control_deassert(usbphyc->rst);
 465         } else {
 466                 ret = PTR_ERR(usbphyc->rst);
 467                 if (ret == -EPROBE_DEFER)
 468                         goto clk_disable;
 469
 470                 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 471         }
 472
 473         /*
 474          * Wait for minimum width of powerdown pulse (ENABLE = Low):
 475          * we have to ensure the PLL is disabled before phys initialization.
 476          */
 477         if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
 478                                        pllen, !(pllen & PLLEN), 5, 50)) {
 479                 dev_warn(usbphyc->dev, "PLL not reset\n");
 480                 ret = -EPROBE_DEFER;
 481                 goto clk_disable;
 482         }
 483
 484         usbphyc->switch_setup = -EINVAL;
 485         usbphyc->nphys = of_get_child_count(np);
 486         usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
 487                                      sizeof(*usbphyc->phys), GFP_KERNEL);
 488         if (!usbphyc->phys) {
 489                 ret = -ENOMEM;
 490                 goto clk_disable;
 491         }
 492
 493         usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
 494         if (IS_ERR(usbphyc->vdda1v1)) {
 495                 ret = PTR_ERR(usbphyc->vdda1v1);
 496                 if (ret != -EPROBE_DEFER)
 497                         dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
 498                 goto clk_disable;
 499         }
 500
 501         usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
 502         if (IS_ERR(usbphyc->vdda1v8)) {
 503                 ret = PTR_ERR(usbphyc->vdda1v8);
 504                 if (ret != -EPROBE_DEFER)
 505                         dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
 506                 goto clk_disable;
 507         }
 508
 509         for_each_child_of_node(np, child) {
 510                 struct stm32_usbphyc_phy *usbphyc_phy;
 511                 struct phy *phy;
 512                 u32 index;
 513
 514                 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
 515                 if (IS_ERR(phy)) {
 516                         ret = PTR_ERR(phy);
 517                         if (ret != -EPROBE_DEFER)
 518                                 dev_err(dev, "failed to create phy%d: %d\n",
 519                                         port, ret);
 520                         goto put_child;
 521                 }
 522
 523                 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
 524                                            GFP_KERNEL);
 525                 if (!usbphyc_phy) {
 526                         ret = -ENOMEM;
 527                         goto put_child;
 528                 }
 529
 530                 ret = of_property_read_u32(child, "reg", &index);
 531                 if (ret || index > usbphyc->nphys) {
 532                         dev_err(&phy->dev, "invalid reg property: %d\n", ret);
 533                         goto put_child;
 534                 }
 535
 536                 usbphyc->phys[port] = usbphyc_phy;
 537                 phy_set_bus_width(phy, 8);
 538                 phy_set_drvdata(phy, usbphyc_phy);
 539
 540                 usbphyc->phys[port]->phy = phy;
 541                 usbphyc->phys[port]->usbphyc = usbphyc;
 542                 usbphyc->phys[port]->index = index;
 543                 usbphyc->phys[port]->active = false;
 544
 545                 usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
 546                 if (IS_ERR(usbphyc->phys[port]->vbus)) {
 547                         ret = PTR_ERR(usbphyc->phys[port]->vbus);
 548                         if (ret == -EPROBE_DEFER)
 549                                 goto put_child;
 550                         usbphyc->phys[port]->vbus = NULL;
 551                 }
 552
 553                 port++;
 554         }
 555
 556         phy_provider = devm_of_phy_provider_register(dev,
 557                                                      stm32_usbphyc_of_xlate);
 558         if (IS_ERR(phy_provider)) {
 559                 ret = PTR_ERR(phy_provider);
 560                 dev_err(dev, "failed to register phy provider: %d\n", ret);
 561                 goto clk_disable;
 562         }
 563
 564         ret = stm32_usbphyc_clk48_register(usbphyc);
 565         if (ret) {
 566                 dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
 567                 goto clk_disable;
 568         }
 569
 570         version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
 571         dev_info(dev, "registered rev:%lu.%lu\n",
 572                  FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
 573
 574         return 0;
 575
 576 put_child:
 577         of_node_put(child);
 578 clk_disable:
 579         clk_disable_unprepare(usbphyc->clk);
 580
 581         return ret;
 582 }
 583
 584 static int stm32_usbphyc_remove(struct platform_device *pdev)
 585 {
 586         struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
 587         int port;
 588
 589         /* Ensure PHYs are not active, to allow PLL disabling */
 590         for (port = 0; port < usbphyc->nphys; port++)
 591                 if (usbphyc->phys[port]->active)
 592                         stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 593
 594         stm32_usbphyc_clk48_unregister(usbphyc);
 595
 596         clk_disable_unprepare(usbphyc->clk);
 597
 598         return 0;
 599 }
 600
 601 static const struct of_device_id stm32_usbphyc_of_match[] = {
 602         { .compatible = "st,stm32mp1-usbphyc", },
 603         { },
 604 };
 605 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
 606
 607 static struct platform_driver stm32_usbphyc_driver = {
 608         .probe = stm32_usbphyc_probe,
 609         .remove = stm32_usbphyc_remove,
 610         .driver = {
 611                 .of_match_table = stm32_usbphyc_of_match,
 612                 .name = "stm32-usbphyc",
 613         }
 614 };
 615 module_platform_driver(stm32_usbphyc_driver);
 616
 617 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
 618 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
 619 MODULE_LICENSE("GPL v2");