1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe host controller driver
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
8 * Author: Jingoo Han <jg1.han@samsung.com>
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/msi.h>
14 #include <linux/of_address.h>
15 #include <linux/of_pci.h>
16 #include <linux/pci_regs.h>
17 #include <linux/platform_device.h>
19 #include "../../pci.h"
20 #include "pcie-designware.h"
22 static struct pci_ops dw_pcie_ops;
23 static struct pci_ops dw_child_pcie_ops;
25 static void dw_msi_ack_irq(struct irq_data *d)
27 irq_chip_ack_parent(d);
30 static void dw_msi_mask_irq(struct irq_data *d)
33 irq_chip_mask_parent(d);
36 static void dw_msi_unmask_irq(struct irq_data *d)
38 pci_msi_unmask_irq(d);
39 irq_chip_unmask_parent(d);
42 static struct irq_chip dw_pcie_msi_irq_chip = {
44 .irq_ack = dw_msi_ack_irq,
45 .irq_mask = dw_msi_mask_irq,
46 .irq_unmask = dw_msi_unmask_irq,
49 static struct msi_domain_info dw_pcie_msi_domain_info = {
50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
52 .chip = &dw_pcie_msi_irq_chip,
56 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
60 u32 status, num_ctrls;
61 irqreturn_t ret = IRQ_NONE;
62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
66 for (i = 0; i < num_ctrls; i++) {
67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
68 (i * MSI_REG_CTRL_BLOCK_SIZE));
75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
76 pos)) != MAX_MSI_IRQS_PER_CTRL) {
77 irq = irq_find_mapping(pp->irq_domain,
78 (i * MAX_MSI_IRQS_PER_CTRL) +
80 generic_handle_irq(irq);
88 /* Chained MSI interrupt service routine */
89 static void dw_chained_msi_isr(struct irq_desc *desc)
91 struct irq_chip *chip = irq_desc_get_chip(desc);
94 chained_irq_enter(chip, desc);
96 pp = irq_desc_get_handler_data(desc);
97 dw_handle_msi_irq(pp);
99 chained_irq_exit(chip, desc);
102 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
104 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
105 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
108 msi_target = (u64)pp->msi_data;
110 msg->address_lo = lower_32_bits(msi_target);
111 msg->address_hi = upper_32_bits(msi_target);
113 msg->data = d->hwirq;
115 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
116 (int)d->hwirq, msg->address_hi, msg->address_lo);
119 static int dw_pci_msi_set_affinity(struct irq_data *d,
120 const struct cpumask *mask, bool force)
125 static void dw_pci_bottom_mask(struct irq_data *d)
127 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
128 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
129 unsigned int res, bit, ctrl;
132 raw_spin_lock_irqsave(&pp->lock, flags);
134 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
135 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
136 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
138 pp->irq_mask[ctrl] |= BIT(bit);
139 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
141 raw_spin_unlock_irqrestore(&pp->lock, flags);
144 static void dw_pci_bottom_unmask(struct irq_data *d)
146 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
147 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
148 unsigned int res, bit, ctrl;
151 raw_spin_lock_irqsave(&pp->lock, flags);
153 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
154 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
155 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
157 pp->irq_mask[ctrl] &= ~BIT(bit);
158 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
160 raw_spin_unlock_irqrestore(&pp->lock, flags);
163 static void dw_pci_bottom_ack(struct irq_data *d)
165 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
166 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
167 unsigned int res, bit, ctrl;
169 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
170 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
171 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
173 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
176 static struct irq_chip dw_pci_msi_bottom_irq_chip = {
178 .irq_ack = dw_pci_bottom_ack,
179 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
180 .irq_set_affinity = dw_pci_msi_set_affinity,
181 .irq_mask = dw_pci_bottom_mask,
182 .irq_unmask = dw_pci_bottom_unmask,
185 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
186 unsigned int virq, unsigned int nr_irqs,
189 struct pcie_port *pp = domain->host_data;
194 raw_spin_lock_irqsave(&pp->lock, flags);
196 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
197 order_base_2(nr_irqs));
199 raw_spin_unlock_irqrestore(&pp->lock, flags);
204 for (i = 0; i < nr_irqs; i++)
205 irq_domain_set_info(domain, virq + i, bit + i,
213 static void dw_pcie_irq_domain_free(struct irq_domain *domain,
214 unsigned int virq, unsigned int nr_irqs)
216 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
217 struct pcie_port *pp = domain->host_data;
220 raw_spin_lock_irqsave(&pp->lock, flags);
222 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
223 order_base_2(nr_irqs));
225 raw_spin_unlock_irqrestore(&pp->lock, flags);
228 static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
229 .alloc = dw_pcie_irq_domain_alloc,
230 .free = dw_pcie_irq_domain_free,
233 int dw_pcie_allocate_domains(struct pcie_port *pp)
235 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
236 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
238 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
239 &dw_pcie_msi_domain_ops, pp);
240 if (!pp->irq_domain) {
241 dev_err(pci->dev, "Failed to create IRQ domain\n");
245 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
247 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
248 &dw_pcie_msi_domain_info,
250 if (!pp->msi_domain) {
251 dev_err(pci->dev, "Failed to create MSI domain\n");
252 irq_domain_remove(pp->irq_domain);
259 static void dw_pcie_free_msi(struct pcie_port *pp)
262 irq_set_chained_handler(pp->msi_irq, NULL);
263 irq_set_handler_data(pp->msi_irq, NULL);
266 irq_domain_remove(pp->msi_domain);
267 irq_domain_remove(pp->irq_domain);
270 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
271 struct device *dev = pci->dev;
273 dma_unmap_single_attrs(dev, pp->msi_data, sizeof(pp->msi_msg),
274 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
278 static void dw_pcie_msi_init(struct pcie_port *pp)
280 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
281 u64 msi_target = (u64)pp->msi_data;
283 if (!pci_msi_enabled() || !pp->has_msi_ctrl)
286 /* Program the msi_data */
287 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
288 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
291 int dw_pcie_host_init(struct pcie_port *pp)
293 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
294 struct device *dev = pci->dev;
295 struct device_node *np = dev->of_node;
296 struct platform_device *pdev = to_platform_device(dev);
297 struct resource_entry *win;
298 struct pci_host_bridge *bridge;
299 struct resource *cfg_res;
302 raw_spin_lock_init(&pci->pp.lock);
304 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
306 pp->cfg0_size = resource_size(cfg_res);
307 pp->cfg0_base = cfg_res->start;
308 } else if (!pp->va_cfg0_base) {
309 dev_err(dev, "Missing *config* reg space\n");
312 if (!pci->dbi_base) {
313 struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
314 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
315 if (IS_ERR(pci->dbi_base))
316 return PTR_ERR(pci->dbi_base);
319 bridge = devm_pci_alloc_host_bridge(dev, 0);
325 /* Get the I/O and memory ranges from DT */
326 resource_list_for_each_entry(win, &bridge->windows) {
327 switch (resource_type(win->res)) {
329 pp->io_size = resource_size(win->res);
330 pp->io_bus_addr = win->res->start - win->offset;
331 pp->io_base = pci_pio_to_address(win->res->start);
334 dev_err(dev, "Missing *config* reg space\n");
335 pp->cfg0_size = resource_size(win->res);
336 pp->cfg0_base = win->res->start;
337 if (!pci->dbi_base) {
338 pci->dbi_base = devm_pci_remap_cfgspace(dev,
341 if (!pci->dbi_base) {
342 dev_err(dev, "Error with ioremap\n");
350 if (!pp->va_cfg0_base) {
351 pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
352 pp->cfg0_base, pp->cfg0_size);
353 if (!pp->va_cfg0_base) {
354 dev_err(dev, "Error with ioremap in function\n");
359 if (pci->link_gen < 1)
360 pci->link_gen = of_pci_get_max_link_speed(np);
362 if (pci_msi_enabled()) {
363 pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
364 of_property_read_bool(np, "msi-parent") ||
365 of_property_read_bool(np, "msi-map"));
367 if (!pp->num_vectors) {
368 pp->num_vectors = MSI_DEF_NUM_VECTORS;
369 } else if (pp->num_vectors > MAX_MSI_IRQS) {
370 dev_err(dev, "Invalid number of vectors\n");
374 if (pp->ops->msi_host_init) {
375 ret = pp->ops->msi_host_init(pp);
378 } else if (pp->has_msi_ctrl) {
380 pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
381 if (pp->msi_irq < 0) {
382 pp->msi_irq = platform_get_irq(pdev, 0);
388 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
390 ret = dw_pcie_allocate_domains(pp);
395 irq_set_chained_handler_and_data(pp->msi_irq,
399 pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
402 DMA_ATTR_SKIP_CPU_SYNC);
403 if (dma_mapping_error(pci->dev, pp->msi_data)) {
404 dev_err(pci->dev, "Failed to map MSI data\n");
411 /* Set default bus ops */
412 bridge->ops = &dw_pcie_ops;
413 bridge->child_ops = &dw_child_pcie_ops;
415 if (pp->ops->host_init) {
416 ret = pp->ops->host_init(pp);
421 dw_pcie_setup_rc(pp);
422 dw_pcie_msi_init(pp);
424 if (!dw_pcie_link_up(pci) && pci->ops->start_link) {
425 ret = pci->ops->start_link(pci);
430 /* Ignore errors, the link may come up later */
431 dw_pcie_wait_for_link(pci);
433 bridge->sysdata = pp;
435 ret = pci_host_probe(bridge);
440 if (pp->has_msi_ctrl)
441 dw_pcie_free_msi(pp);
444 EXPORT_SYMBOL_GPL(dw_pcie_host_init);
446 void dw_pcie_host_deinit(struct pcie_port *pp)
448 pci_stop_root_bus(pp->bridge->bus);
449 pci_remove_root_bus(pp->bridge->bus);
450 if (pp->has_msi_ctrl)
451 dw_pcie_free_msi(pp);
453 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
455 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
456 unsigned int devfn, int where)
460 struct pcie_port *pp = bus->sysdata;
461 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
464 * Checking whether the link is up here is a last line of defense
465 * against platforms that forward errors on the system bus as
466 * SError upon PCI configuration transactions issued when the link
467 * is down. This check is racy by definition and does not stop
468 * the system from triggering an SError if the link goes down
469 * after this check is performed.
471 if (!dw_pcie_link_up(pci))
474 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
475 PCIE_ATU_FUNC(PCI_FUNC(devfn));
477 if (pci_is_root_bus(bus->parent))
478 type = PCIE_ATU_TYPE_CFG0;
480 type = PCIE_ATU_TYPE_CFG1;
483 dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, pp->cfg0_size);
485 return pp->va_cfg0_base + where;
488 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
489 int where, int size, u32 *val)
492 struct pcie_port *pp = bus->sysdata;
493 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
495 ret = pci_generic_config_read(bus, devfn, where, size, val);
497 if (!ret && pci->io_cfg_atu_shared)
498 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
499 pp->io_bus_addr, pp->io_size);
504 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
505 int where, int size, u32 val)
508 struct pcie_port *pp = bus->sysdata;
509 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
511 ret = pci_generic_config_write(bus, devfn, where, size, val);
513 if (!ret && pci->io_cfg_atu_shared)
514 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
515 pp->io_bus_addr, pp->io_size);
520 static struct pci_ops dw_child_pcie_ops = {
521 .map_bus = dw_pcie_other_conf_map_bus,
522 .read = dw_pcie_rd_other_conf,
523 .write = dw_pcie_wr_other_conf,
526 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
528 struct pcie_port *pp = bus->sysdata;
529 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
531 if (PCI_SLOT(devfn) > 0)
534 return pci->dbi_base + where;
536 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
538 static struct pci_ops dw_pcie_ops = {
539 .map_bus = dw_pcie_own_conf_map_bus,
540 .read = pci_generic_config_read,
541 .write = pci_generic_config_write,
544 void dw_pcie_setup_rc(struct pcie_port *pp)
547 u32 val, ctrl, num_ctrls;
548 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
551 * Enable DBI read-only registers for writing/updating configuration.
552 * Write permission gets disabled towards the end of this function.
554 dw_pcie_dbi_ro_wr_en(pci);
558 if (pp->has_msi_ctrl) {
559 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
561 /* Initialize IRQ Status array */
562 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
563 pp->irq_mask[ctrl] = ~0;
564 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
565 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
567 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
568 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
574 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
575 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
577 /* Setup interrupt pins */
578 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
581 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
583 /* Setup bus numbers */
584 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
587 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
589 /* Setup command register */
590 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
592 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
593 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
594 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
596 /* Ensure all outbound windows are disabled so there are multiple matches */
597 for (i = 0; i < pci->num_ob_windows; i++)
598 dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
601 * If the platform provides its own child bus config accesses, it means
602 * the platform uses its own address translation component rather than
603 * ATU, so we should not program the ATU here.
605 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
607 struct resource_entry *entry;
609 /* Get last memory resource entry */
610 resource_list_for_each_entry(entry, &pp->bridge->windows) {
611 if (resource_type(entry->res) != IORESOURCE_MEM)
614 if (pci->num_ob_windows <= ++atu_idx)
617 dw_pcie_prog_outbound_atu(pci, atu_idx,
618 PCIE_ATU_TYPE_MEM, entry->res->start,
619 entry->res->start - entry->offset,
620 resource_size(entry->res));
624 if (pci->num_ob_windows > ++atu_idx)
625 dw_pcie_prog_outbound_atu(pci, atu_idx,
626 PCIE_ATU_TYPE_IO, pp->io_base,
627 pp->io_bus_addr, pp->io_size);
629 pci->io_cfg_atu_shared = true;
632 if (pci->num_ob_windows <= atu_idx)
633 dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)",
634 pci->num_ob_windows);
637 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
639 /* Program correct class for RC */
640 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
642 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
643 val |= PORT_LOGIC_SPEED_CHANGE;
644 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
646 dw_pcie_dbi_ro_wr_dis(pci);
648 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);