1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Freescale i.MX6 SoCs
5 * Copyright (C) 2013 Kosagi
6 * https://www.kosagi.com
8 * Author: Sean Cross <xobs@kosagi.com>
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/gpio.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
19 #include <linux/module.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_device.h>
22 #include <linux/of_address.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/resource.h>
28 #include <linux/signal.h>
29 #include <linux/types.h>
30 #include <linux/interrupt.h>
31 #include <linux/reset.h>
32 #include <linux/pm_domain.h>
33 #include <linux/pm_runtime.h>
35 #include "pcie-designware.h"
37 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
38 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
39 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
40 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
41 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
43 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
45 enum imx6_pcie_variants {
53 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
54 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
55 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
57 struct imx6_pcie_drvdata {
58 enum imx6_pcie_variants variant;
66 bool gpio_active_high;
69 struct clk *pcie_inbound_axi;
72 struct regmap *iomuxc_gpr;
74 struct reset_control *pciephy_reset;
75 struct reset_control *apps_reset;
76 struct reset_control *turnoff_reset;
78 u32 tx_deemph_gen2_3p5db;
79 u32 tx_deemph_gen2_6db;
82 struct regulator *vpcie;
83 void __iomem *phy_base;
85 /* power domain for pcie */
86 struct device *pd_pcie;
87 /* power domain for pcie phy */
88 struct device *pd_pcie_phy;
89 const struct imx6_pcie_drvdata *drvdata;
92 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
93 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
94 #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
96 /* PCIe Port Logic registers (memory-mapped) */
97 #define PL_OFFSET 0x700
99 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
100 #define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x))
101 #define PCIE_PHY_CTRL_CAP_ADR BIT(16)
102 #define PCIE_PHY_CTRL_CAP_DAT BIT(17)
103 #define PCIE_PHY_CTRL_WR BIT(18)
104 #define PCIE_PHY_CTRL_RD BIT(19)
106 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
107 #define PCIE_PHY_STAT_ACK BIT(16)
109 /* PHY registers (not memory-mapped) */
110 #define PCIE_PHY_ATEOVRD 0x10
111 #define PCIE_PHY_ATEOVRD_EN BIT(2)
112 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0
113 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1
115 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11
116 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2
117 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f
118 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9)
120 #define PCIE_PHY_RX_ASIC_OUT 0x100D
121 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
123 /* iMX7 PCIe PHY registers */
124 #define PCIE_PHY_CMN_REG4 0x14
125 /* These are probably the bits that *aren't* DCC_FB_EN */
126 #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29
128 #define PCIE_PHY_CMN_REG15 0x54
129 #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2)
130 #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5)
131 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7)
133 #define PCIE_PHY_CMN_REG24 0x90
134 #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6)
135 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3)
137 #define PCIE_PHY_CMN_REG26 0x98
138 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC
140 #define PHY_RX_OVRD_IN_LO 0x1005
141 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
142 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
144 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
146 struct dw_pcie *pci = imx6_pcie->pci;
148 u32 max_iterations = 10;
149 u32 wait_counter = 0;
152 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
160 } while (wait_counter < max_iterations);
165 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
167 struct dw_pcie *pci = imx6_pcie->pci;
171 val = PCIE_PHY_CTRL_DATA(addr);
172 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
174 val |= PCIE_PHY_CTRL_CAP_ADR;
175 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
177 ret = pcie_phy_poll_ack(imx6_pcie, true);
181 val = PCIE_PHY_CTRL_DATA(addr);
182 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
184 return pcie_phy_poll_ack(imx6_pcie, false);
187 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
188 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
190 struct dw_pcie *pci = imx6_pcie->pci;
194 ret = pcie_phy_wait_ack(imx6_pcie, addr);
198 /* assert Read signal */
199 phy_ctl = PCIE_PHY_CTRL_RD;
200 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
202 ret = pcie_phy_poll_ack(imx6_pcie, true);
206 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
208 /* deassert Read signal */
209 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
211 return pcie_phy_poll_ack(imx6_pcie, false);
214 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
216 struct dw_pcie *pci = imx6_pcie->pci;
222 ret = pcie_phy_wait_ack(imx6_pcie, addr);
226 var = PCIE_PHY_CTRL_DATA(data);
227 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
230 var |= PCIE_PHY_CTRL_CAP_DAT;
231 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
233 ret = pcie_phy_poll_ack(imx6_pcie, true);
237 /* deassert cap data */
238 var = PCIE_PHY_CTRL_DATA(data);
239 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
241 /* wait for ack de-assertion */
242 ret = pcie_phy_poll_ack(imx6_pcie, false);
246 /* assert wr signal */
247 var = PCIE_PHY_CTRL_WR;
248 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
251 ret = pcie_phy_poll_ack(imx6_pcie, true);
255 /* deassert wr signal */
256 var = PCIE_PHY_CTRL_DATA(data);
257 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
259 /* wait for ack de-assertion */
260 ret = pcie_phy_poll_ack(imx6_pcie, false);
264 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
269 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
273 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
276 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
277 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
278 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
279 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
281 usleep_range(2000, 3000);
283 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
284 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
285 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
286 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
290 /* Added for PCI abort handling */
291 static int imx6q_pcie_abort_handler(unsigned long addr,
292 unsigned int fsr, struct pt_regs *regs)
294 unsigned long pc = instruction_pointer(regs);
295 unsigned long instr = *(unsigned long *)pc;
296 int reg = (instr >> 12) & 15;
299 * If the instruction being executed was a read,
300 * make it look like it read all-ones.
302 if ((instr & 0x0c100000) == 0x04100000) {
305 if (instr & 0x00400000)
310 regs->uregs[reg] = val;
315 if ((instr & 0x0e100090) == 0x00100090) {
316 regs->uregs[reg] = -1;
325 static int imx6_pcie_attach_pd(struct device *dev)
327 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
328 struct device_link *link;
330 /* Do nothing when in a single power domain */
334 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
335 if (IS_ERR(imx6_pcie->pd_pcie))
336 return PTR_ERR(imx6_pcie->pd_pcie);
337 /* Do nothing when power domain missing */
338 if (!imx6_pcie->pd_pcie)
340 link = device_link_add(dev, imx6_pcie->pd_pcie,
345 dev_err(dev, "Failed to add device_link to pcie pd.\n");
349 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
350 if (IS_ERR(imx6_pcie->pd_pcie_phy))
351 return PTR_ERR(imx6_pcie->pd_pcie_phy);
353 link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
358 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n");
365 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
367 struct device *dev = imx6_pcie->pci->dev;
369 switch (imx6_pcie->drvdata->variant) {
372 reset_control_assert(imx6_pcie->pciephy_reset);
373 reset_control_assert(imx6_pcie->apps_reset);
376 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
377 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
378 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
379 /* Force PCIe PHY reset */
380 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
381 IMX6SX_GPR5_PCIE_BTNRST_RESET,
382 IMX6SX_GPR5_PCIE_BTNRST_RESET);
385 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
386 IMX6Q_GPR1_PCIE_SW_RST,
387 IMX6Q_GPR1_PCIE_SW_RST);
390 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
391 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
392 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
393 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
397 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
398 int ret = regulator_disable(imx6_pcie->vpcie);
401 dev_err(dev, "failed to disable vpcie regulator: %d\n",
406 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
408 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
409 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
412 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
414 struct dw_pcie *pci = imx6_pcie->pci;
415 struct device *dev = pci->dev;
419 switch (imx6_pcie->drvdata->variant) {
421 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
423 dev_err(dev, "unable to enable pcie_axi clock\n");
427 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
428 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
432 /* power up core phy and enable ref clock */
433 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
434 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
436 * the async reset input need ref clock to sync internally,
437 * when the ref clock comes after reset, internal synced
438 * reset time is too short, cannot meet the requirement.
439 * add one ~10us delay here.
441 usleep_range(10, 100);
442 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
443 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
448 ret = clk_prepare_enable(imx6_pcie->pcie_aux);
450 dev_err(dev, "unable to enable pcie_aux clock\n");
454 offset = imx6_pcie_grp_offset(imx6_pcie);
456 * Set the over ride low and enabled
457 * make sure that REF_CLK is turned on.
459 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
460 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
462 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
463 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
464 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
471 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
474 struct device *dev = imx6_pcie->pci->dev;
476 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
478 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
479 PHY_PLL_LOCK_WAIT_USLEEP_MAX,
480 PHY_PLL_LOCK_WAIT_TIMEOUT))
481 dev_err(dev, "PCIe PLL lock timeout\n");
484 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
486 struct dw_pcie *pci = imx6_pcie->pci;
487 struct device *dev = pci->dev;
490 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
491 ret = regulator_enable(imx6_pcie->vpcie);
493 dev_err(dev, "failed to enable vpcie regulator: %d\n",
499 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
501 dev_err(dev, "unable to enable pcie_phy clock\n");
505 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
507 dev_err(dev, "unable to enable pcie_bus clock\n");
511 ret = clk_prepare_enable(imx6_pcie->pcie);
513 dev_err(dev, "unable to enable pcie clock\n");
517 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
519 dev_err(dev, "unable to enable pcie ref clock\n");
523 /* allow the clocks to stabilize */
524 usleep_range(200, 500);
526 /* Some boards don't have PCIe reset GPIO. */
527 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
528 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
529 imx6_pcie->gpio_active_high);
531 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
532 !imx6_pcie->gpio_active_high);
535 switch (imx6_pcie->drvdata->variant) {
537 reset_control_deassert(imx6_pcie->pciephy_reset);
540 reset_control_deassert(imx6_pcie->pciephy_reset);
542 /* Workaround for ERR010728, failure of PCI-e PLL VCO to
543 * oscillate, especially when cold. This turns off "Duty-cycle
544 * Corrector" and other mysterious undocumented things.
546 if (likely(imx6_pcie->phy_base)) {
547 /* De-assert DCC_FB_EN */
548 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
549 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
550 /* Assert RX_EQS and RX_EQS_SEL */
551 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
552 | PCIE_PHY_CMN_REG24_RX_EQ,
553 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
554 /* Assert ATT_MODE */
555 writel(PCIE_PHY_CMN_REG26_ATT_MODE,
556 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
558 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
561 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
564 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
565 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
568 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
569 IMX6Q_GPR1_PCIE_SW_RST, 0);
571 usleep_range(200, 500);
573 case IMX6Q: /* Nothing to do */
580 clk_disable_unprepare(imx6_pcie->pcie);
582 clk_disable_unprepare(imx6_pcie->pcie_bus);
584 clk_disable_unprepare(imx6_pcie->pcie_phy);
586 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
587 ret = regulator_disable(imx6_pcie->vpcie);
589 dev_err(dev, "failed to disable vpcie regulator: %d\n",
594 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
596 unsigned int mask, val;
598 if (imx6_pcie->drvdata->variant == IMX8MQ &&
599 imx6_pcie->controller_id == 1) {
600 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
601 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
602 PCI_EXP_TYPE_ROOT_PORT);
604 mask = IMX6Q_GPR12_DEVICE_TYPE;
605 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
606 PCI_EXP_TYPE_ROOT_PORT);
609 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
612 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
614 switch (imx6_pcie->drvdata->variant) {
617 * TODO: Currently this code assumes external
618 * oscillator is being used
620 regmap_update_bits(imx6_pcie->iomuxc_gpr,
621 imx6_pcie_grp_offset(imx6_pcie),
622 IMX8MQ_GPR_PCIE_REF_USE_PAD,
623 IMX8MQ_GPR_PCIE_REF_USE_PAD);
626 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
627 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
630 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
631 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
632 IMX6SX_GPR12_PCIE_RX_EQ_2);
635 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
636 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
638 /* configure constant input signal to the pcie ctrl and phy */
639 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
640 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
642 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
643 IMX6Q_GPR8_TX_DEEMPH_GEN1,
644 imx6_pcie->tx_deemph_gen1 << 0);
645 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
646 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
647 imx6_pcie->tx_deemph_gen2_3p5db << 6);
648 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
649 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
650 imx6_pcie->tx_deemph_gen2_6db << 12);
651 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
652 IMX6Q_GPR8_TX_SWING_FULL,
653 imx6_pcie->tx_swing_full << 18);
654 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
655 IMX6Q_GPR8_TX_SWING_LOW,
656 imx6_pcie->tx_swing_low << 25);
660 imx6_pcie_configure_type(imx6_pcie);
663 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
665 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
669 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
675 * The default settings of the MPLL are for a 125MHz input
676 * clock, so no need to reconfigure anything in that case.
688 dev_err(imx6_pcie->pci->dev,
689 "Unsupported PHY reference clock rate %lu\n", phy_rate);
693 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
694 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
695 PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
696 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
697 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
698 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
700 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
701 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
702 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
703 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
704 val |= PCIE_PHY_ATEOVRD_EN;
705 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
710 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
712 struct dw_pcie *pci = imx6_pcie->pci;
713 struct device *dev = pci->dev;
715 unsigned int retries;
717 for (retries = 0; retries < 200; retries++) {
718 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
719 /* Test if the speed change finished. */
720 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
722 usleep_range(100, 1000);
725 dev_err(dev, "Speed change timeout\n");
729 static void imx6_pcie_ltssm_enable(struct device *dev)
731 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
733 switch (imx6_pcie->drvdata->variant) {
737 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
738 IMX6Q_GPR12_PCIE_CTL_2,
739 IMX6Q_GPR12_PCIE_CTL_2);
743 reset_control_deassert(imx6_pcie->apps_reset);
748 static int imx6_pcie_start_link(struct dw_pcie *pci)
750 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
751 struct device *dev = pci->dev;
752 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
757 * Force Gen1 operation when starting the link. In case the link is
758 * started in Gen2 mode, there is a possibility the devices on the
759 * bus will not be detected at all. This happens with PCIe switches.
761 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
762 tmp &= ~PCI_EXP_LNKCAP_SLS;
763 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
764 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
767 imx6_pcie_ltssm_enable(dev);
769 ret = dw_pcie_wait_for_link(pci);
773 if (pci->link_gen == 2) {
774 /* Allow Gen2 mode after the link is up. */
775 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
776 tmp &= ~PCI_EXP_LNKCAP_SLS;
777 tmp |= PCI_EXP_LNKCAP_SLS_5_0GB;
778 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
781 * Start Directed Speed Change so the best possible
782 * speed both link partners support can be negotiated.
784 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
785 tmp |= PORT_LOGIC_SPEED_CHANGE;
786 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
788 if (imx6_pcie->drvdata->flags &
789 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
791 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
792 * from i.MX6 family when no link speed transition
793 * occurs and we go Gen1 -> yep, Gen1. The difference
794 * is that, in such case, it will not be cleared by HW
795 * which will cause the following code to report false
799 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
801 dev_err(dev, "Failed to bring link up!\n");
806 /* Make sure link training is finished as well! */
807 ret = dw_pcie_wait_for_link(pci);
809 dev_err(dev, "Failed to bring link up!\n");
813 dev_info(dev, "Link: Gen2 disabled\n");
816 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
817 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
821 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
822 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
823 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
824 imx6_pcie_reset_phy(imx6_pcie);
828 static int imx6_pcie_host_init(struct pcie_port *pp)
830 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
831 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
833 imx6_pcie_assert_core_reset(imx6_pcie);
834 imx6_pcie_init_phy(imx6_pcie);
835 imx6_pcie_deassert_core_reset(imx6_pcie);
836 imx6_setup_phy_mpll(imx6_pcie);
841 static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
842 .host_init = imx6_pcie_host_init,
845 static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
846 struct platform_device *pdev)
848 struct dw_pcie *pci = imx6_pcie->pci;
849 struct pcie_port *pp = &pci->pp;
850 struct device *dev = &pdev->dev;
853 pp->ops = &imx6_pcie_host_ops;
855 ret = dw_pcie_host_init(pp);
857 dev_err(dev, "failed to initialize host\n");
864 static const struct dw_pcie_ops dw_pcie_ops = {
865 .start_link = imx6_pcie_start_link,
868 #ifdef CONFIG_PM_SLEEP
869 static void imx6_pcie_ltssm_disable(struct device *dev)
871 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
873 switch (imx6_pcie->drvdata->variant) {
876 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
877 IMX6Q_GPR12_PCIE_CTL_2, 0);
880 reset_control_assert(imx6_pcie->apps_reset);
883 dev_err(dev, "ltssm_disable not supported\n");
887 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
889 struct device *dev = imx6_pcie->pci->dev;
891 /* Some variants have a turnoff reset in DT */
892 if (imx6_pcie->turnoff_reset) {
893 reset_control_assert(imx6_pcie->turnoff_reset);
894 reset_control_deassert(imx6_pcie->turnoff_reset);
895 goto pm_turnoff_sleep;
898 /* Others poke directly at IOMUXC registers */
899 switch (imx6_pcie->drvdata->variant) {
901 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
902 IMX6SX_GPR12_PCIE_PM_TURN_OFF,
903 IMX6SX_GPR12_PCIE_PM_TURN_OFF);
904 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
905 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
908 dev_err(dev, "PME_Turn_Off not implemented\n");
913 * Components with an upstream port must respond to
914 * PME_Turn_Off with PME_TO_Ack but we can't check.
916 * The standard recommends a 1-10ms timeout after which to
917 * proceed anyway as if acks were received.
920 usleep_range(1000, 10000);
923 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
925 clk_disable_unprepare(imx6_pcie->pcie);
926 clk_disable_unprepare(imx6_pcie->pcie_phy);
927 clk_disable_unprepare(imx6_pcie->pcie_bus);
929 switch (imx6_pcie->drvdata->variant) {
931 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
934 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
935 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
936 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
939 clk_disable_unprepare(imx6_pcie->pcie_aux);
946 static int imx6_pcie_suspend_noirq(struct device *dev)
948 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
950 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
953 imx6_pcie_pm_turnoff(imx6_pcie);
954 imx6_pcie_clk_disable(imx6_pcie);
955 imx6_pcie_ltssm_disable(dev);
960 static int imx6_pcie_resume_noirq(struct device *dev)
963 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
964 struct pcie_port *pp = &imx6_pcie->pci->pp;
966 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
969 imx6_pcie_assert_core_reset(imx6_pcie);
970 imx6_pcie_init_phy(imx6_pcie);
971 imx6_pcie_deassert_core_reset(imx6_pcie);
972 dw_pcie_setup_rc(pp);
974 ret = imx6_pcie_start_link(imx6_pcie->pci);
976 dev_info(dev, "pcie link is down after resume.\n");
982 static const struct dev_pm_ops imx6_pcie_pm_ops = {
983 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
984 imx6_pcie_resume_noirq)
987 static int imx6_pcie_probe(struct platform_device *pdev)
989 struct device *dev = &pdev->dev;
991 struct imx6_pcie *imx6_pcie;
992 struct device_node *np;
993 struct resource *dbi_base;
994 struct device_node *node = dev->of_node;
998 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
1002 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1007 pci->ops = &dw_pcie_ops;
1009 imx6_pcie->pci = pci;
1010 imx6_pcie->drvdata = of_device_get_match_data(dev);
1012 /* Find the PHY if one is defined, only imx7d uses it */
1013 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1015 struct resource res;
1017 ret = of_address_to_resource(np, 0, &res);
1019 dev_err(dev, "Unable to map PCIe PHY\n");
1022 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
1023 if (IS_ERR(imx6_pcie->phy_base)) {
1024 dev_err(dev, "Unable to map PCIe PHY\n");
1025 return PTR_ERR(imx6_pcie->phy_base);
1029 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1030 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
1031 if (IS_ERR(pci->dbi_base))
1032 return PTR_ERR(pci->dbi_base);
1035 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
1036 imx6_pcie->gpio_active_high = of_property_read_bool(node,
1037 "reset-gpio-active-high");
1038 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
1039 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
1040 imx6_pcie->gpio_active_high ?
1041 GPIOF_OUT_INIT_HIGH :
1045 dev_err(dev, "unable to get reset gpio\n");
1048 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
1049 return imx6_pcie->reset_gpio;
1053 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
1054 if (IS_ERR(imx6_pcie->pcie_phy))
1055 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
1056 "pcie_phy clock source missing or invalid\n");
1058 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
1059 if (IS_ERR(imx6_pcie->pcie_bus))
1060 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
1061 "pcie_bus clock source missing or invalid\n");
1063 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1064 if (IS_ERR(imx6_pcie->pcie))
1065 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
1066 "pcie clock source missing or invalid\n");
1068 switch (imx6_pcie->drvdata->variant) {
1070 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
1071 "pcie_inbound_axi");
1072 if (IS_ERR(imx6_pcie->pcie_inbound_axi))
1073 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi),
1074 "pcie_inbound_axi clock missing or invalid\n");
1077 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1078 if (IS_ERR(imx6_pcie->pcie_aux))
1079 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1080 "pcie_aux clock source missing or invalid\n");
1083 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1084 imx6_pcie->controller_id = 1;
1086 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
1088 if (IS_ERR(imx6_pcie->pciephy_reset)) {
1089 dev_err(dev, "Failed to get PCIEPHY reset control\n");
1090 return PTR_ERR(imx6_pcie->pciephy_reset);
1093 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1095 if (IS_ERR(imx6_pcie->apps_reset)) {
1096 dev_err(dev, "Failed to get PCIE APPS reset control\n");
1097 return PTR_ERR(imx6_pcie->apps_reset);
1104 /* Grab turnoff reset */
1105 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1106 if (IS_ERR(imx6_pcie->turnoff_reset)) {
1107 dev_err(dev, "Failed to get TURNOFF reset control\n");
1108 return PTR_ERR(imx6_pcie->turnoff_reset);
1111 /* Grab GPR config register range */
1112 imx6_pcie->iomuxc_gpr =
1113 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
1114 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1115 dev_err(dev, "unable to find iomuxc registers\n");
1116 return PTR_ERR(imx6_pcie->iomuxc_gpr);
1119 /* Grab PCIe PHY Tx Settings */
1120 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
1121 &imx6_pcie->tx_deemph_gen1))
1122 imx6_pcie->tx_deemph_gen1 = 0;
1124 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
1125 &imx6_pcie->tx_deemph_gen2_3p5db))
1126 imx6_pcie->tx_deemph_gen2_3p5db = 0;
1128 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
1129 &imx6_pcie->tx_deemph_gen2_6db))
1130 imx6_pcie->tx_deemph_gen2_6db = 20;
1132 if (of_property_read_u32(node, "fsl,tx-swing-full",
1133 &imx6_pcie->tx_swing_full))
1134 imx6_pcie->tx_swing_full = 127;
1136 if (of_property_read_u32(node, "fsl,tx-swing-low",
1137 &imx6_pcie->tx_swing_low))
1138 imx6_pcie->tx_swing_low = 127;
1140 /* Limit link speed */
1142 ret = of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
1144 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1145 if (IS_ERR(imx6_pcie->vpcie)) {
1146 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
1147 return PTR_ERR(imx6_pcie->vpcie);
1148 imx6_pcie->vpcie = NULL;
1151 platform_set_drvdata(pdev, imx6_pcie);
1153 ret = imx6_pcie_attach_pd(dev);
1157 ret = imx6_add_pcie_port(imx6_pcie, pdev);
1161 if (pci_msi_enabled()) {
1162 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
1163 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
1164 val |= PCI_MSI_FLAGS_ENABLE;
1165 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
1171 static void imx6_pcie_shutdown(struct platform_device *pdev)
1173 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
1175 /* bring down link, so bootloader gets clean state in case of reboot */
1176 imx6_pcie_assert_core_reset(imx6_pcie);
1179 static const struct imx6_pcie_drvdata drvdata[] = {
1182 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1183 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1184 .dbi_length = 0x200,
1188 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1189 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
1190 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1194 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1195 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1199 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1206 static const struct of_device_id imx6_pcie_of_match[] = {
1207 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1208 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1209 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1210 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1211 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
1215 static struct platform_driver imx6_pcie_driver = {
1217 .name = "imx6q-pcie",
1218 .of_match_table = imx6_pcie_of_match,
1219 .suppress_bind_attrs = true,
1220 .pm = &imx6_pcie_pm_ops,
1221 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1223 .probe = imx6_pcie_probe,
1224 .shutdown = imx6_pcie_shutdown,
1227 static void imx6_pcie_quirk(struct pci_dev *dev)
1229 struct pci_bus *bus = dev->bus;
1230 struct pcie_port *pp = bus->sysdata;
1232 /* Bus parent is the PCI bridge, its parent is this platform driver */
1233 if (!bus->dev.parent || !bus->dev.parent->parent)
1236 /* Make sure we only quirk devices associated with this driver */
1237 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
1240 if (pci_is_root_bus(bus)) {
1241 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1242 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
1245 * Limit config length to avoid the kernel reading beyond
1246 * the register set and causing an abort on i.MX 6Quad
1248 if (imx6_pcie->drvdata->dbi_length) {
1249 dev->cfg_size = imx6_pcie->drvdata->dbi_length;
1250 dev_info(&dev->dev, "Limiting cfg_size to %d\n",
1255 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
1256 PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
1258 static int __init imx6_pcie_init(void)
1262 * Since probe() can be deferred we need to make sure that
1263 * hook_fault_code is not called after __init memory is freed
1264 * by kernel and since imx6q_pcie_abort_handler() is a no-op,
1265 * we can install the handler here without risking it
1266 * accessing some uninitialized driver state.
1268 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1269 "external abort on non-linefetch");
1272 return platform_driver_register(&imx6_pcie_driver);
1274 device_initcall(imx6_pcie_init);