drivers/ntb/hw/intel/ntb_hw_gen4.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */
   3 #include <linux/debugfs.h>
   4 #include <linux/delay.h>
   5 #include <linux/init.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/module.h>
   8 #include <linux/pci.h>
   9 #include <linux/random.h>
  10 #include <linux/slab.h>
  11 #include <linux/ntb.h>
  12 #include <linux/log2.h>
  13
  14 #include "ntb_hw_intel.h"
  15 #include "ntb_hw_gen1.h"
  16 #include "ntb_hw_gen3.h"
  17 #include "ntb_hw_gen4.h"
  18
  19 static int gen4_poll_link(struct intel_ntb_dev *ndev);
  20 static int gen4_link_is_up(struct intel_ntb_dev *ndev);
  21
  22 static const struct intel_ntb_reg gen4_reg = {
  23         .poll_link              = gen4_poll_link,
  24         .link_is_up             = gen4_link_is_up,
  25         .db_ioread              = gen3_db_ioread,
  26         .db_iowrite             = gen3_db_iowrite,
  27         .db_size                = sizeof(u32),
  28         .ntb_ctl                = GEN4_NTBCNTL_OFFSET,
  29         .mw_bar                 = {2, 4},
  30 };
  31
  32 static const struct intel_ntb_alt_reg gen4_pri_reg = {
  33         .db_clear               = GEN4_IM_INT_STATUS_OFFSET,
  34         .db_mask                = GEN4_IM_INT_DISABLE_OFFSET,
  35         .spad                   = GEN4_IM_SPAD_OFFSET,
  36 };
  37
  38 static const struct intel_ntb_xlat_reg gen4_sec_xlat = {
  39         .bar2_limit             = GEN4_IM23XLMT_OFFSET,
  40         .bar2_xlat              = GEN4_IM23XBASE_OFFSET,
  41         .bar2_idx               = GEN4_IM23XBASEIDX_OFFSET,
  42 };
  43
  44 static const struct intel_ntb_alt_reg gen4_b2b_reg = {
  45         .db_bell                = GEN4_IM_DOORBELL_OFFSET,
  46         .spad                   = GEN4_EM_SPAD_OFFSET,
  47 };
  48
  49 static int gen4_poll_link(struct intel_ntb_dev *ndev)
  50 {
  51         u16 reg_val;
  52
  53         /*
  54          * We need to write to DLLSCS bit in the SLOTSTS before we
  55          * can clear the hardware link interrupt on ICX NTB.
  56          */
  57         iowrite16(GEN4_SLOTSTS_DLLSCS, ndev->self_mmio + GEN4_SLOTSTS);
  58         ndev->reg->db_iowrite(ndev->db_link_mask,
  59                               ndev->self_mmio +
  60                               ndev->self_reg->db_clear);
  61
  62         reg_val = ioread16(ndev->self_mmio + GEN4_LINK_STATUS_OFFSET);
  63         if (reg_val == ndev->lnk_sta)
  64                 return 0;
  65
  66         ndev->lnk_sta = reg_val;
  67
  68         return 1;
  69 }
  70
  71 static int gen4_link_is_up(struct intel_ntb_dev *ndev)
  72 {
  73         return NTB_LNK_STA_ACTIVE(ndev->lnk_sta);
  74 }
  75
  76 static int gen4_init_isr(struct intel_ntb_dev *ndev)
  77 {
  78         int i;
  79
  80         /*
  81          * The MSIX vectors and the interrupt status bits are not lined up
  82          * on Gen3 (Skylake) and Gen4. By default the link status bit is bit
  83          * 32, however it is by default MSIX vector0. We need to fixup to
  84          * line them up. The vectors at reset is 1-32,0. We need to reprogram
  85          * to 0-32.
  86          */
  87         for (i = 0; i < GEN4_DB_MSIX_VECTOR_COUNT; i++)
  88                 iowrite8(i, ndev->self_mmio + GEN4_INTVEC_OFFSET + i);
  89
  90         return ndev_init_isr(ndev, GEN4_DB_MSIX_VECTOR_COUNT,
  91                              GEN4_DB_MSIX_VECTOR_COUNT,
  92                              GEN4_DB_MSIX_VECTOR_SHIFT,
  93                              GEN4_DB_TOTAL_SHIFT);
  94 }
  95
  96 static int gen4_setup_b2b_mw(struct intel_ntb_dev *ndev,
  97                             const struct intel_b2b_addr *addr,
  98                             const struct intel_b2b_addr *peer_addr)
  99 {
 100         struct pci_dev *pdev;
 101         void __iomem *mmio;
 102         phys_addr_t bar_addr;
 103
 104         pdev = ndev->ntb.pdev;
 105         mmio = ndev->self_mmio;
 106
 107         /* setup incoming bar limits == base addrs (zero length windows) */
 108         bar_addr = addr->bar2_addr64;
 109         iowrite64(bar_addr, mmio + GEN4_IM23XLMT_OFFSET);
 110         bar_addr = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
 111         dev_dbg(&pdev->dev, "IM23XLMT %#018llx\n", bar_addr);
 112
 113         bar_addr = addr->bar4_addr64;
 114         iowrite64(bar_addr, mmio + GEN4_IM45XLMT_OFFSET);
 115         bar_addr = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
 116         dev_dbg(&pdev->dev, "IM45XLMT %#018llx\n", bar_addr);
 117
 118         /* zero incoming translation addrs */
 119         iowrite64(0, mmio + GEN4_IM23XBASE_OFFSET);
 120         iowrite64(0, mmio + GEN4_IM45XBASE_OFFSET);
 121
 122         ndev->peer_mmio = ndev->self_mmio;
 123
 124         return 0;
 125 }
 126
 127 static int gen4_init_ntb(struct intel_ntb_dev *ndev)
 128 {
 129         int rc;
 130
 131
 132         ndev->mw_count = XEON_MW_COUNT;
 133         ndev->spad_count = GEN4_SPAD_COUNT;
 134         ndev->db_count = GEN4_DB_COUNT;
 135         ndev->db_link_mask = GEN4_DB_LINK_BIT;
 136
 137         ndev->self_reg = &gen4_pri_reg;
 138         ndev->xlat_reg = &gen4_sec_xlat;
 139         ndev->peer_reg = &gen4_b2b_reg;
 140
 141         if (ndev->ntb.topo == NTB_TOPO_B2B_USD)
 142                 rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_dsd_addr,
 143                                 &xeon_b2b_usd_addr);
 144         else
 145                 rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_usd_addr,
 146                                 &xeon_b2b_dsd_addr);
 147         if (rc)
 148                 return rc;
 149
 150         ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
 151
 152         ndev->reg->db_iowrite(ndev->db_valid_mask,
 153                               ndev->self_mmio +
 154                               ndev->self_reg->db_mask);
 155
 156         return 0;
 157 }
 158
 159 static enum ntb_topo gen4_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
 160 {
 161         switch (ppd & GEN4_PPD_TOPO_MASK) {
 162         case GEN4_PPD_TOPO_B2B_USD:
 163                 return NTB_TOPO_B2B_USD;
 164         case GEN4_PPD_TOPO_B2B_DSD:
 165                 return NTB_TOPO_B2B_DSD;
 166         }
 167
 168         return NTB_TOPO_NONE;
 169 }
 170
 171 int gen4_init_dev(struct intel_ntb_dev *ndev)
 172 {
 173         struct pci_dev *pdev = ndev->ntb.pdev;
 174         u32 ppd1/*, ppd0*/;
 175         u16 lnkctl;
 176         int rc;
 177
 178         ndev->reg = &gen4_reg;
 179
 180         if (pdev_is_ICX(pdev)) {
 181                 ndev->hwerr_flags |= NTB_HWERR_BAR_ALIGN;
 182                 ndev->hwerr_flags |= NTB_HWERR_LTR_BAD;
 183         }
 184
 185         ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);
 186         ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);
 187         dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1,
 188                 ntb_topo_string(ndev->ntb.topo));
 189         if (ndev->ntb.topo == NTB_TOPO_NONE)
 190                 return -EINVAL;
 191
 192         rc = gen4_init_ntb(ndev);
 193         if (rc)
 194                 return rc;
 195
 196         /* init link setup */
 197         lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 198         lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE;
 199         iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 200
 201         return gen4_init_isr(ndev);
 202 }
 203
 204 ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
 205                                       size_t count, loff_t *offp)
 206 {
 207         struct intel_ntb_dev *ndev;
 208         void __iomem *mmio;
 209         char *buf;
 210         size_t buf_size;
 211         ssize_t ret, off;
 212         union { u64 v64; u32 v32; u16 v16; } u;
 213
 214         ndev = filp->private_data;
 215         mmio = ndev->self_mmio;
 216
 217         buf_size = min(count, 0x800ul);
 218
 219         buf = kmalloc(buf_size, GFP_KERNEL);
 220         if (!buf)
 221                 return -ENOMEM;
 222
 223         off = 0;
 224
 225         off += scnprintf(buf + off, buf_size - off,
 226                          "NTB Device Information:\n");
 227
 228         off += scnprintf(buf + off, buf_size - off,
 229                          "Connection Topology -\t%s\n",
 230                          ntb_topo_string(ndev->ntb.topo));
 231
 232         off += scnprintf(buf + off, buf_size - off,
 233                          "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);
 234         off += scnprintf(buf + off, buf_size - off,
 235                          "LNK STA (cached) -\t\t%#06x\n", ndev->lnk_sta);
 236
 237         if (!ndev->reg->link_is_up(ndev))
 238                 off += scnprintf(buf + off, buf_size - off,
 239                                  "Link Status -\t\tDown\n");
 240         else {
 241                 off += scnprintf(buf + off, buf_size - off,
 242                                  "Link Status -\t\tUp\n");
 243                 off += scnprintf(buf + off, buf_size - off,
 244                                  "Link Speed -\t\tPCI-E Gen %u\n",
 245                                  NTB_LNK_STA_SPEED(ndev->lnk_sta));
 246                 off += scnprintf(buf + off, buf_size - off,
 247                                  "Link Width -\t\tx%u\n",
 248                                  NTB_LNK_STA_WIDTH(ndev->lnk_sta));
 249         }
 250
 251         off += scnprintf(buf + off, buf_size - off,
 252                          "Memory Window Count -\t%u\n", ndev->mw_count);
 253         off += scnprintf(buf + off, buf_size - off,
 254                          "Scratchpad Count -\t%u\n", ndev->spad_count);
 255         off += scnprintf(buf + off, buf_size - off,
 256                          "Doorbell Count -\t%u\n", ndev->db_count);
 257         off += scnprintf(buf + off, buf_size - off,
 258                          "Doorbell Vector Count -\t%u\n", ndev->db_vec_count);
 259         off += scnprintf(buf + off, buf_size - off,
 260                          "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);
 261
 262         off += scnprintf(buf + off, buf_size - off,
 263                          "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);
 264         off += scnprintf(buf + off, buf_size - off,
 265                          "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);
 266         off += scnprintf(buf + off, buf_size - off,
 267                          "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);
 268
 269         u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);
 270         off += scnprintf(buf + off, buf_size - off,
 271                          "Doorbell Mask -\t\t%#llx\n", u.v64);
 272
 273         off += scnprintf(buf + off, buf_size - off,
 274                          "\nNTB Incoming XLAT:\n");
 275
 276         u.v64 = ioread64(mmio + GEN4_IM23XBASE_OFFSET);
 277         off += scnprintf(buf + off, buf_size - off,
 278                          "IM23XBASE -\t\t%#018llx\n", u.v64);
 279
 280         u.v64 = ioread64(mmio + GEN4_IM45XBASE_OFFSET);
 281         off += scnprintf(buf + off, buf_size - off,
 282                          "IM45XBASE -\t\t%#018llx\n", u.v64);
 283
 284         u.v64 = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
 285         off += scnprintf(buf + off, buf_size - off,
 286                          "IM23XLMT -\t\t\t%#018llx\n", u.v64);
 287
 288         u.v64 = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
 289         off += scnprintf(buf + off, buf_size - off,
 290                          "IM45XLMT -\t\t\t%#018llx\n", u.v64);
 291
 292         off += scnprintf(buf + off, buf_size - off,
 293                          "\nNTB Statistics:\n");
 294
 295         off += scnprintf(buf + off, buf_size - off,
 296                          "\nNTB Hardware Errors:\n");
 297
 298         if (!pci_read_config_word(ndev->ntb.pdev,
 299                                   GEN4_DEVSTS_OFFSET, &u.v16))
 300                 off += scnprintf(buf + off, buf_size - off,
 301                                 "DEVSTS -\t\t%#06x\n", u.v16);
 302
 303         u.v16 = ioread16(mmio + GEN4_LINK_STATUS_OFFSET);
 304         off += scnprintf(buf + off, buf_size - off,
 305                         "LNKSTS -\t\t%#06x\n", u.v16);
 306
 307         if (!pci_read_config_dword(ndev->ntb.pdev,
 308                                    GEN4_UNCERRSTS_OFFSET, &u.v32))
 309                 off += scnprintf(buf + off, buf_size - off,
 310                                  "UNCERRSTS -\t\t%#06x\n", u.v32);
 311
 312         if (!pci_read_config_dword(ndev->ntb.pdev,
 313                                    GEN4_CORERRSTS_OFFSET, &u.v32))
 314                 off += scnprintf(buf + off, buf_size - off,
 315                                  "CORERRSTS -\t\t%#06x\n", u.v32);
 316
 317         ret = simple_read_from_buffer(ubuf, count, offp, buf, off);
 318         kfree(buf);
 319         return ret;
 320 }
 321
 322 static int intel_ntb4_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
 323                                    dma_addr_t addr, resource_size_t size)
 324 {
 325         struct intel_ntb_dev *ndev = ntb_ndev(ntb);
 326         unsigned long xlat_reg, limit_reg, idx_reg;
 327         unsigned short base_idx, reg_val16;
 328         resource_size_t bar_size, mw_size;
 329         void __iomem *mmio;
 330         u64 base, limit, reg_val;
 331         int bar;
 332
 333         if (pidx != NTB_DEF_PEER_IDX)
 334                 return -EINVAL;
 335
 336         if (idx >= ndev->b2b_idx && !ndev->b2b_off)
 337                 idx += 1;
 338
 339         bar = ndev_mw_to_bar(ndev, idx);
 340         if (bar < 0)
 341                 return bar;
 342
 343         bar_size = pci_resource_len(ndev->ntb.pdev, bar);
 344
 345         if (idx == ndev->b2b_idx)
 346                 mw_size = bar_size - ndev->b2b_off;
 347         else
 348                 mw_size = bar_size;
 349
 350         if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {
 351                 /* hardware requires that addr is aligned to bar size */
 352                 if (addr & (bar_size - 1))
 353                         return -EINVAL;
 354         } else {
 355                 if (addr & (PAGE_SIZE - 1))
 356                         return -EINVAL;
 357         }
 358
 359         /* make sure the range fits in the usable mw size */
 360         if (size > mw_size)
 361                 return -EINVAL;
 362
 363         mmio = ndev->self_mmio;
 364         xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10);
 365         limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10);
 366         base = pci_resource_start(ndev->ntb.pdev, bar);
 367
 368         /* Set the limit if supported, if size is not mw_size */
 369         if (limit_reg && size != mw_size) {
 370                 limit = base + size;
 371                 base_idx = __ilog2_u64(size);
 372         } else {
 373                 limit = base + mw_size;
 374                 base_idx = __ilog2_u64(mw_size);
 375         }
 376
 377
 378         /* set and verify setting the translation address */
 379         iowrite64(addr, mmio + xlat_reg);
 380         reg_val = ioread64(mmio + xlat_reg);
 381         if (reg_val != addr) {
 382                 iowrite64(0, mmio + xlat_reg);
 383                 return -EIO;
 384         }
 385
 386         dev_dbg(&ntb->pdev->dev, "BAR %d IMXBASE: %#Lx\n", bar, reg_val);
 387
 388         /* set and verify setting the limit */
 389         iowrite64(limit, mmio + limit_reg);
 390         reg_val = ioread64(mmio + limit_reg);
 391         if (reg_val != limit) {
 392                 iowrite64(base, mmio + limit_reg);
 393                 iowrite64(0, mmio + xlat_reg);
 394                 return -EIO;
 395         }
 396
 397         dev_dbg(&ntb->pdev->dev, "BAR %d IMXLMT: %#Lx\n", bar, reg_val);
 398
 399         if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {
 400                 idx_reg = ndev->xlat_reg->bar2_idx + (idx * 0x2);
 401                 iowrite16(base_idx, mmio + idx_reg);
 402                 reg_val16 = ioread16(mmio + idx_reg);
 403                 if (reg_val16 != base_idx) {
 404                         iowrite64(base, mmio + limit_reg);
 405                         iowrite64(0, mmio + xlat_reg);
 406                         iowrite16(0, mmio + idx_reg);
 407                         return -EIO;
 408                 }
 409                 dev_dbg(&ntb->pdev->dev, "BAR %d IMBASEIDX: %#x\n", bar, reg_val16);
 410         }
 411
 412
 413         return 0;
 414 }
 415
 416 static int intel_ntb4_link_enable(struct ntb_dev *ntb,
 417                 enum ntb_speed max_speed, enum ntb_width max_width)
 418 {
 419         struct intel_ntb_dev *ndev;
 420         u32 ntb_ctl, ppd0;
 421         u16 lnkctl;
 422
 423         ndev = container_of(ntb, struct intel_ntb_dev, ntb);
 424
 425         dev_dbg(&ntb->pdev->dev,
 426                         "Enabling link with max_speed %d max_width %d\n",
 427                         max_speed, max_width);
 428
 429         if (max_speed != NTB_SPEED_AUTO)
 430                 dev_dbg(&ntb->pdev->dev,
 431                                 "ignoring max_speed %d\n", max_speed);
 432         if (max_width != NTB_WIDTH_AUTO)
 433                 dev_dbg(&ntb->pdev->dev,
 434                                 "ignoring max_width %d\n", max_width);
 435
 436         if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD)) {
 437                 u32 ltr;
 438
 439                 /* Setup active snoop LTR values */
 440                 ltr = NTB_LTR_ACTIVE_REQMNT | NTB_LTR_ACTIVE_VAL | NTB_LTR_ACTIVE_LATSCALE;
 441                 /* Setup active non-snoop values */
 442                 ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr;
 443                 iowrite32(ltr, ndev->self_mmio + GEN4_LTR_ACTIVE_OFFSET);
 444
 445                 /* Setup idle snoop LTR values */
 446                 ltr = NTB_LTR_IDLE_VAL | NTB_LTR_IDLE_LATSCALE | NTB_LTR_IDLE_REQMNT;
 447                 /* Setup idle non-snoop values */
 448                 ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr;
 449                 iowrite32(ltr, ndev->self_mmio + GEN4_LTR_IDLE_OFFSET);
 450
 451                 /* setup PCIe LTR to active */
 452                 iowrite8(NTB_LTR_SWSEL_ACTIVE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET);
 453         }
 454
 455         ntb_ctl = NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP;
 456         ntb_ctl |= NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP;
 457         iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);
 458
 459         lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 460         lnkctl &= ~GEN4_LINK_CTRL_LINK_DISABLE;
 461         iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 462
 463         /* start link training in PPD0 */
 464         ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET);
 465         ppd0 |= GEN4_PPD_LINKTRN;
 466         iowrite32(ppd0, ndev->self_mmio + GEN4_PPD0_OFFSET);
 467
 468         /* make sure link training has started */
 469         ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET);
 470         if (!(ppd0 & GEN4_PPD_LINKTRN)) {
 471                 dev_warn(&ntb->pdev->dev, "Link is not training\n");
 472                 return -ENXIO;
 473         }
 474
 475         ndev->dev_up = 1;
 476
 477         return 0;
 478 }
 479
 480 static int intel_ntb4_link_disable(struct ntb_dev *ntb)
 481 {
 482         struct intel_ntb_dev *ndev;
 483         u32 ntb_cntl;
 484         u16 lnkctl;
 485
 486         ndev = container_of(ntb, struct intel_ntb_dev, ntb);
 487
 488         dev_dbg(&ntb->pdev->dev, "Disabling link\n");
 489
 490         /* clear the snoop bits */
 491         ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
 492         ntb_cntl &= ~(NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP);
 493         ntb_cntl &= ~(NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP);
 494         iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl);
 495
 496         lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 497         lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE;
 498         iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 499
 500         /* set LTR to idle */
 501         if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD))
 502                 iowrite8(NTB_LTR_SWSEL_IDLE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET);
 503
 504         ndev->dev_up = 0;
 505
 506         return 0;
 507 }
 508
 509 static int intel_ntb4_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,
 510                                    resource_size_t *addr_align,
 511                                    resource_size_t *size_align,
 512                                    resource_size_t *size_max)
 513 {
 514         struct intel_ntb_dev *ndev = ntb_ndev(ntb);
 515         resource_size_t bar_size, mw_size;
 516         int bar;
 517
 518         if (pidx != NTB_DEF_PEER_IDX)
 519                 return -EINVAL;
 520
 521         if (idx >= ndev->b2b_idx && !ndev->b2b_off)
 522                 idx += 1;
 523
 524         bar = ndev_mw_to_bar(ndev, idx);
 525         if (bar < 0)
 526                 return bar;
 527
 528         bar_size = pci_resource_len(ndev->ntb.pdev, bar);
 529
 530         if (idx == ndev->b2b_idx)
 531                 mw_size = bar_size - ndev->b2b_off;
 532         else
 533                 mw_size = bar_size;
 534
 535         if (addr_align) {
 536                 if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN)
 537                         *addr_align = pci_resource_len(ndev->ntb.pdev, bar);
 538                 else
 539                         *addr_align = PAGE_SIZE;
 540         }
 541
 542         if (size_align)
 543                 *size_align = 1;
 544
 545         if (size_max)
 546                 *size_max = mw_size;
 547
 548         return 0;
 549 }
 550
 551 const struct ntb_dev_ops intel_ntb4_ops = {
 552         .mw_count               = intel_ntb_mw_count,
 553         .mw_get_align           = intel_ntb4_mw_get_align,
 554         .mw_set_trans           = intel_ntb4_mw_set_trans,
 555         .peer_mw_count          = intel_ntb_peer_mw_count,
 556         .peer_mw_get_addr       = intel_ntb_peer_mw_get_addr,
 557         .link_is_up             = intel_ntb_link_is_up,
 558         .link_enable            = intel_ntb4_link_enable,
 559         .link_disable           = intel_ntb4_link_disable,
 560         .db_valid_mask          = intel_ntb_db_valid_mask,
 561         .db_vector_count        = intel_ntb_db_vector_count,
 562         .db_vector_mask         = intel_ntb_db_vector_mask,
 563         .db_read                = intel_ntb3_db_read,
 564         .db_clear               = intel_ntb3_db_clear,
 565         .db_set_mask            = intel_ntb_db_set_mask,
 566         .db_clear_mask          = intel_ntb_db_clear_mask,
 567         .peer_db_addr           = intel_ntb3_peer_db_addr,
 568         .peer_db_set            = intel_ntb3_peer_db_set,
 569         .spad_is_unsafe         = intel_ntb_spad_is_unsafe,
 570         .spad_count             = intel_ntb_spad_count,
 571         .spad_read              = intel_ntb_spad_read,
 572         .spad_write             = intel_ntb_spad_write,
 573         .peer_spad_addr         = intel_ntb_peer_spad_addr,
 574         .peer_spad_read         = intel_ntb_peer_spad_read,
 575         .peer_spad_write        = intel_ntb_peer_spad_write,
 576 };
 577