drivers/ntb/hw/intel/ntb_hw_gen4.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */
   3 #include <linux/debugfs.h>
   4 #include <linux/delay.h>
   5 #include <linux/init.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/module.h>
   8 #include <linux/pci.h>
   9 #include <linux/random.h>
  10 #include <linux/slab.h>
  11 #include <linux/ntb.h>
  12 #include <linux/log2.h>
  13
  14 #include "ntb_hw_intel.h"
  15 #include "ntb_hw_gen1.h"
  16 #include "ntb_hw_gen3.h"
  17 #include "ntb_hw_gen4.h"
  18
  19 static int gen4_poll_link(struct intel_ntb_dev *ndev);
  20 static int gen4_link_is_up(struct intel_ntb_dev *ndev);
  21
  22 static const struct intel_ntb_reg gen4_reg = {
  23         .poll_link              = gen4_poll_link,
  24         .link_is_up             = gen4_link_is_up,
  25         .db_ioread              = gen3_db_ioread,
  26         .db_iowrite             = gen3_db_iowrite,
  27         .db_size                = sizeof(u32),
  28         .ntb_ctl                = GEN4_NTBCNTL_OFFSET,
  29         .mw_bar                 = {2, 4},
  30 };
  31
  32 static const struct intel_ntb_alt_reg gen4_pri_reg = {
  33         .db_clear               = GEN4_IM_INT_STATUS_OFFSET,
  34         .db_mask                = GEN4_IM_INT_DISABLE_OFFSET,
  35         .spad                   = GEN4_IM_SPAD_OFFSET,
  36 };
  37
  38 static const struct intel_ntb_xlat_reg gen4_sec_xlat = {
  39         .bar2_limit             = GEN4_IM23XLMT_OFFSET,
  40         .bar2_xlat              = GEN4_IM23XBASE_OFFSET,
  41         .bar2_idx               = GEN4_IM23XBASEIDX_OFFSET,
  42 };
  43
  44 static const struct intel_ntb_alt_reg gen4_b2b_reg = {
  45         .db_bell                = GEN4_IM_DOORBELL_OFFSET,
  46         .spad                   = GEN4_EM_SPAD_OFFSET,
  47 };
  48
  49 static int gen4_poll_link(struct intel_ntb_dev *ndev)
  50 {
  51         u16 reg_val;
  52
  53         /*
  54          * We need to write to DLLSCS bit in the SLOTSTS before we
  55          * can clear the hardware link interrupt on ICX NTB.
  56          */
  57         iowrite16(GEN4_SLOTSTS_DLLSCS, ndev->self_mmio + GEN4_SLOTSTS);
  58         ndev->reg->db_iowrite(ndev->db_link_mask,
  59                               ndev->self_mmio +
  60                               ndev->self_reg->db_clear);
  61
  62         reg_val = ioread16(ndev->self_mmio + GEN4_LINK_STATUS_OFFSET);
  63         if (reg_val == ndev->lnk_sta)
  64                 return 0;
  65
  66         ndev->lnk_sta = reg_val;
  67
  68         return 1;
  69 }
  70
  71 static int gen4_link_is_up(struct intel_ntb_dev *ndev)
  72 {
  73         return NTB_LNK_STA_ACTIVE(ndev->lnk_sta);
  74 }
  75
  76 static int gen4_init_isr(struct intel_ntb_dev *ndev)
  77 {
  78         int i;
  79
  80         /*
  81          * The MSIX vectors and the interrupt status bits are not lined up
  82          * on Gen3 (Skylake) and Gen4. By default the link status bit is bit
  83          * 32, however it is by default MSIX vector0. We need to fixup to
  84          * line them up. The vectors at reset is 1-32,0. We need to reprogram
  85          * to 0-32.
  86          */
  87         for (i = 0; i < GEN4_DB_MSIX_VECTOR_COUNT; i++)
  88                 iowrite8(i, ndev->self_mmio + GEN4_INTVEC_OFFSET + i);
  89
  90         return ndev_init_isr(ndev, GEN4_DB_MSIX_VECTOR_COUNT,
  91                              GEN4_DB_MSIX_VECTOR_COUNT,
  92                              GEN4_DB_MSIX_VECTOR_SHIFT,
  93                              GEN4_DB_TOTAL_SHIFT);
  94 }
  95
  96 static int gen4_setup_b2b_mw(struct intel_ntb_dev *ndev,
  97                             const struct intel_b2b_addr *addr,
  98                             const struct intel_b2b_addr *peer_addr)
  99 {
 100         struct pci_dev *pdev;
 101         void __iomem *mmio;
 102         phys_addr_t bar_addr;
 103
 104         pdev = ndev->ntb.pdev;
 105         mmio = ndev->self_mmio;
 106
 107         /* setup incoming bar limits == base addrs (zero length windows) */
 108         bar_addr = addr->bar2_addr64;
 109         iowrite64(bar_addr, mmio + GEN4_IM23XLMT_OFFSET);
 110         bar_addr = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
 111         dev_dbg(&pdev->dev, "IM23XLMT %#018llx\n", bar_addr);
 112
 113         bar_addr = addr->bar4_addr64;
 114         iowrite64(bar_addr, mmio + GEN4_IM45XLMT_OFFSET);
 115         bar_addr = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
 116         dev_dbg(&pdev->dev, "IM45XLMT %#018llx\n", bar_addr);
 117
 118         /* zero incoming translation addrs */
 119         iowrite64(0, mmio + GEN4_IM23XBASE_OFFSET);
 120         iowrite64(0, mmio + GEN4_IM45XBASE_OFFSET);
 121
 122         ndev->peer_mmio = ndev->self_mmio;
 123
 124         return 0;
 125 }
 126
 127 static int gen4_init_ntb(struct intel_ntb_dev *ndev)
 128 {
 129         int rc;
 130
 131
 132         ndev->mw_count = XEON_MW_COUNT;
 133         ndev->spad_count = GEN4_SPAD_COUNT;
 134         ndev->db_count = GEN4_DB_COUNT;
 135         ndev->db_link_mask = GEN4_DB_LINK_BIT;
 136
 137         ndev->self_reg = &gen4_pri_reg;
 138         ndev->xlat_reg = &gen4_sec_xlat;
 139         ndev->peer_reg = &gen4_b2b_reg;
 140
 141         if (ndev->ntb.topo == NTB_TOPO_B2B_USD)
 142                 rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_dsd_addr,
 143                                 &xeon_b2b_usd_addr);
 144         else
 145                 rc = gen4_setup_b2b_mw(ndev, &xeon_b2b_usd_addr,
 146                                 &xeon_b2b_dsd_addr);
 147         if (rc)
 148                 return rc;
 149
 150         ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
 151
 152         ndev->reg->db_iowrite(ndev->db_valid_mask,
 153                               ndev->self_mmio +
 154                               ndev->self_reg->db_mask);
 155
 156         return 0;
 157 }
 158
 159 static enum ntb_topo gen4_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
 160 {
 161         switch (ppd & GEN4_PPD_TOPO_MASK) {
 162         case GEN4_PPD_TOPO_B2B_USD:
 163                 return NTB_TOPO_B2B_USD;
 164         case GEN4_PPD_TOPO_B2B_DSD:
 165                 return NTB_TOPO_B2B_DSD;
 166         }
 167
 168         return NTB_TOPO_NONE;
 169 }
 170
 171 int gen4_init_dev(struct intel_ntb_dev *ndev)
 172 {
 173         struct pci_dev *pdev = ndev->ntb.pdev;
 174         u32 ppd1/*, ppd0*/;
 175         u16 lnkctl;
 176         int rc;
 177
 178         ndev->reg = &gen4_reg;
 179
 180         if (pdev_is_ICX(pdev))
 181                 ndev->hwerr_flags |= NTB_HWERR_BAR_ALIGN;
 182
 183         ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);
 184         ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);
 185         dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1,
 186                 ntb_topo_string(ndev->ntb.topo));
 187         if (ndev->ntb.topo == NTB_TOPO_NONE)
 188                 return -EINVAL;
 189
 190         rc = gen4_init_ntb(ndev);
 191         if (rc)
 192                 return rc;
 193
 194         /* init link setup */
 195         lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 196         lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE;
 197         iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 198
 199         return gen4_init_isr(ndev);
 200 }
 201
 202 ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
 203                                       size_t count, loff_t *offp)
 204 {
 205         struct intel_ntb_dev *ndev;
 206         void __iomem *mmio;
 207         char *buf;
 208         size_t buf_size;
 209         ssize_t ret, off;
 210         union { u64 v64; u32 v32; u16 v16; } u;
 211
 212         ndev = filp->private_data;
 213         mmio = ndev->self_mmio;
 214
 215         buf_size = min(count, 0x800ul);
 216
 217         buf = kmalloc(buf_size, GFP_KERNEL);
 218         if (!buf)
 219                 return -ENOMEM;
 220
 221         off = 0;
 222
 223         off += scnprintf(buf + off, buf_size - off,
 224                          "NTB Device Information:\n");
 225
 226         off += scnprintf(buf + off, buf_size - off,
 227                          "Connection Topology -\t%s\n",
 228                          ntb_topo_string(ndev->ntb.topo));
 229
 230         off += scnprintf(buf + off, buf_size - off,
 231                          "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);
 232         off += scnprintf(buf + off, buf_size - off,
 233                          "LNK STA (cached) -\t\t%#06x\n", ndev->lnk_sta);
 234
 235         if (!ndev->reg->link_is_up(ndev))
 236                 off += scnprintf(buf + off, buf_size - off,
 237                                  "Link Status -\t\tDown\n");
 238         else {
 239                 off += scnprintf(buf + off, buf_size - off,
 240                                  "Link Status -\t\tUp\n");
 241                 off += scnprintf(buf + off, buf_size - off,
 242                                  "Link Speed -\t\tPCI-E Gen %u\n",
 243                                  NTB_LNK_STA_SPEED(ndev->lnk_sta));
 244                 off += scnprintf(buf + off, buf_size - off,
 245                                  "Link Width -\t\tx%u\n",
 246                                  NTB_LNK_STA_WIDTH(ndev->lnk_sta));
 247         }
 248
 249         off += scnprintf(buf + off, buf_size - off,
 250                          "Memory Window Count -\t%u\n", ndev->mw_count);
 251         off += scnprintf(buf + off, buf_size - off,
 252                          "Scratchpad Count -\t%u\n", ndev->spad_count);
 253         off += scnprintf(buf + off, buf_size - off,
 254                          "Doorbell Count -\t%u\n", ndev->db_count);
 255         off += scnprintf(buf + off, buf_size - off,
 256                          "Doorbell Vector Count -\t%u\n", ndev->db_vec_count);
 257         off += scnprintf(buf + off, buf_size - off,
 258                          "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);
 259
 260         off += scnprintf(buf + off, buf_size - off,
 261                          "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);
 262         off += scnprintf(buf + off, buf_size - off,
 263                          "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);
 264         off += scnprintf(buf + off, buf_size - off,
 265                          "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);
 266
 267         u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);
 268         off += scnprintf(buf + off, buf_size - off,
 269                          "Doorbell Mask -\t\t%#llx\n", u.v64);
 270
 271         off += scnprintf(buf + off, buf_size - off,
 272                          "\nNTB Incoming XLAT:\n");
 273
 274         u.v64 = ioread64(mmio + GEN4_IM23XBASE_OFFSET);
 275         off += scnprintf(buf + off, buf_size - off,
 276                          "IM23XBASE -\t\t%#018llx\n", u.v64);
 277
 278         u.v64 = ioread64(mmio + GEN4_IM45XBASE_OFFSET);
 279         off += scnprintf(buf + off, buf_size - off,
 280                          "IM45XBASE -\t\t%#018llx\n", u.v64);
 281
 282         u.v64 = ioread64(mmio + GEN4_IM23XLMT_OFFSET);
 283         off += scnprintf(buf + off, buf_size - off,
 284                          "IM23XLMT -\t\t\t%#018llx\n", u.v64);
 285
 286         u.v64 = ioread64(mmio + GEN4_IM45XLMT_OFFSET);
 287         off += scnprintf(buf + off, buf_size - off,
 288                          "IM45XLMT -\t\t\t%#018llx\n", u.v64);
 289
 290         off += scnprintf(buf + off, buf_size - off,
 291                          "\nNTB Statistics:\n");
 292
 293         off += scnprintf(buf + off, buf_size - off,
 294                          "\nNTB Hardware Errors:\n");
 295
 296         if (!pci_read_config_word(ndev->ntb.pdev,
 297                                   GEN4_DEVSTS_OFFSET, &u.v16))
 298                 off += scnprintf(buf + off, buf_size - off,
 299                                 "DEVSTS -\t\t%#06x\n", u.v16);
 300
 301         u.v16 = ioread16(mmio + GEN4_LINK_STATUS_OFFSET);
 302         off += scnprintf(buf + off, buf_size - off,
 303                         "LNKSTS -\t\t%#06x\n", u.v16);
 304
 305         if (!pci_read_config_dword(ndev->ntb.pdev,
 306                                    GEN4_UNCERRSTS_OFFSET, &u.v32))
 307                 off += scnprintf(buf + off, buf_size - off,
 308                                  "UNCERRSTS -\t\t%#06x\n", u.v32);
 309
 310         if (!pci_read_config_dword(ndev->ntb.pdev,
 311                                    GEN4_CORERRSTS_OFFSET, &u.v32))
 312                 off += scnprintf(buf + off, buf_size - off,
 313                                  "CORERRSTS -\t\t%#06x\n", u.v32);
 314
 315         ret = simple_read_from_buffer(ubuf, count, offp, buf, off);
 316         kfree(buf);
 317         return ret;
 318 }
 319
 320 static int intel_ntb4_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
 321                                    dma_addr_t addr, resource_size_t size)
 322 {
 323         struct intel_ntb_dev *ndev = ntb_ndev(ntb);
 324         unsigned long xlat_reg, limit_reg, idx_reg;
 325         unsigned short base_idx, reg_val16;
 326         resource_size_t bar_size, mw_size;
 327         void __iomem *mmio;
 328         u64 base, limit, reg_val;
 329         int bar;
 330
 331         if (pidx != NTB_DEF_PEER_IDX)
 332                 return -EINVAL;
 333
 334         if (idx >= ndev->b2b_idx && !ndev->b2b_off)
 335                 idx += 1;
 336
 337         bar = ndev_mw_to_bar(ndev, idx);
 338         if (bar < 0)
 339                 return bar;
 340
 341         bar_size = pci_resource_len(ndev->ntb.pdev, bar);
 342
 343         if (idx == ndev->b2b_idx)
 344                 mw_size = bar_size - ndev->b2b_off;
 345         else
 346                 mw_size = bar_size;
 347
 348         if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {
 349                 /* hardware requires that addr is aligned to bar size */
 350                 if (addr & (bar_size - 1))
 351                         return -EINVAL;
 352         } else {
 353                 if (addr & (PAGE_SIZE - 1))
 354                         return -EINVAL;
 355         }
 356
 357         /* make sure the range fits in the usable mw size */
 358         if (size > mw_size)
 359                 return -EINVAL;
 360
 361         mmio = ndev->self_mmio;
 362         xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10);
 363         limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10);
 364         base = pci_resource_start(ndev->ntb.pdev, bar);
 365
 366         /* Set the limit if supported, if size is not mw_size */
 367         if (limit_reg && size != mw_size) {
 368                 limit = base + size;
 369                 base_idx = __ilog2_u64(size);
 370         } else {
 371                 limit = base + mw_size;
 372                 base_idx = __ilog2_u64(mw_size);
 373         }
 374
 375
 376         /* set and verify setting the translation address */
 377         iowrite64(addr, mmio + xlat_reg);
 378         reg_val = ioread64(mmio + xlat_reg);
 379         if (reg_val != addr) {
 380                 iowrite64(0, mmio + xlat_reg);
 381                 return -EIO;
 382         }
 383
 384         dev_dbg(&ntb->pdev->dev, "BAR %d IMXBASE: %#Lx\n", bar, reg_val);
 385
 386         /* set and verify setting the limit */
 387         iowrite64(limit, mmio + limit_reg);
 388         reg_val = ioread64(mmio + limit_reg);
 389         if (reg_val != limit) {
 390                 iowrite64(base, mmio + limit_reg);
 391                 iowrite64(0, mmio + xlat_reg);
 392                 return -EIO;
 393         }
 394
 395         dev_dbg(&ntb->pdev->dev, "BAR %d IMXLMT: %#Lx\n", bar, reg_val);
 396
 397         if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN) {
 398                 idx_reg = ndev->xlat_reg->bar2_idx + (idx * 0x2);
 399                 iowrite16(base_idx, mmio + idx_reg);
 400                 reg_val16 = ioread16(mmio + idx_reg);
 401                 if (reg_val16 != base_idx) {
 402                         iowrite64(base, mmio + limit_reg);
 403                         iowrite64(0, mmio + xlat_reg);
 404                         iowrite16(0, mmio + idx_reg);
 405                         return -EIO;
 406                 }
 407                 dev_dbg(&ntb->pdev->dev, "BAR %d IMBASEIDX: %#x\n", bar, reg_val16);
 408         }
 409
 410
 411         return 0;
 412 }
 413
 414 static int intel_ntb4_link_enable(struct ntb_dev *ntb,
 415                 enum ntb_speed max_speed, enum ntb_width max_width)
 416 {
 417         struct intel_ntb_dev *ndev;
 418         u32 ntb_ctl, ppd0;
 419         u16 lnkctl;
 420
 421         ndev = container_of(ntb, struct intel_ntb_dev, ntb);
 422
 423         dev_dbg(&ntb->pdev->dev,
 424                         "Enabling link with max_speed %d max_width %d\n",
 425                         max_speed, max_width);
 426
 427         if (max_speed != NTB_SPEED_AUTO)
 428                 dev_dbg(&ntb->pdev->dev,
 429                                 "ignoring max_speed %d\n", max_speed);
 430         if (max_width != NTB_WIDTH_AUTO)
 431                 dev_dbg(&ntb->pdev->dev,
 432                                 "ignoring max_width %d\n", max_width);
 433
 434         ntb_ctl = NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP;
 435         ntb_ctl |= NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP;
 436         iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);
 437
 438         lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 439         lnkctl &= ~GEN4_LINK_CTRL_LINK_DISABLE;
 440         iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 441
 442         /* start link training in PPD0 */
 443         ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET);
 444         ppd0 |= GEN4_PPD_LINKTRN;
 445         iowrite32(ppd0, ndev->self_mmio + GEN4_PPD0_OFFSET);
 446
 447         /* make sure link training has started */
 448         ppd0 = ioread32(ndev->self_mmio + GEN4_PPD0_OFFSET);
 449         if (!(ppd0 & GEN4_PPD_LINKTRN)) {
 450                 dev_warn(&ntb->pdev->dev, "Link is not training\n");
 451                 return -ENXIO;
 452         }
 453
 454         ndev->dev_up = 1;
 455
 456         return 0;
 457 }
 458
 459 static int intel_ntb4_link_disable(struct ntb_dev *ntb)
 460 {
 461         struct intel_ntb_dev *ndev;
 462         u32 ntb_cntl;
 463         u16 lnkctl;
 464
 465         ndev = container_of(ntb, struct intel_ntb_dev, ntb);
 466
 467         dev_dbg(&ntb->pdev->dev, "Disabling link\n");
 468
 469         /* clear the snoop bits */
 470         ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
 471         ntb_cntl &= ~(NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP);
 472         ntb_cntl &= ~(NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP);
 473         iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl);
 474
 475         lnkctl = ioread16(ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 476         lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE;
 477         iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET);
 478
 479         ndev->dev_up = 0;
 480
 481         return 0;
 482 }
 483
 484 static int intel_ntb4_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,
 485                                    resource_size_t *addr_align,
 486                                    resource_size_t *size_align,
 487                                    resource_size_t *size_max)
 488 {
 489         struct intel_ntb_dev *ndev = ntb_ndev(ntb);
 490         resource_size_t bar_size, mw_size;
 491         int bar;
 492
 493         if (pidx != NTB_DEF_PEER_IDX)
 494                 return -EINVAL;
 495
 496         if (idx >= ndev->b2b_idx && !ndev->b2b_off)
 497                 idx += 1;
 498
 499         bar = ndev_mw_to_bar(ndev, idx);
 500         if (bar < 0)
 501                 return bar;
 502
 503         bar_size = pci_resource_len(ndev->ntb.pdev, bar);
 504
 505         if (idx == ndev->b2b_idx)
 506                 mw_size = bar_size - ndev->b2b_off;
 507         else
 508                 mw_size = bar_size;
 509
 510         if (addr_align) {
 511                 if (ndev->hwerr_flags & NTB_HWERR_BAR_ALIGN)
 512                         *addr_align = pci_resource_len(ndev->ntb.pdev, bar);
 513                 else
 514                         *addr_align = PAGE_SIZE;
 515         }
 516
 517         if (size_align)
 518                 *size_align = 1;
 519
 520         if (size_max)
 521                 *size_max = mw_size;
 522
 523         return 0;
 524 }
 525
 526 const struct ntb_dev_ops intel_ntb4_ops = {
 527         .mw_count               = intel_ntb_mw_count,
 528         .mw_get_align           = intel_ntb4_mw_get_align,
 529         .mw_set_trans           = intel_ntb4_mw_set_trans,
 530         .peer_mw_count          = intel_ntb_peer_mw_count,
 531         .peer_mw_get_addr       = intel_ntb_peer_mw_get_addr,
 532         .link_is_up             = intel_ntb_link_is_up,
 533         .link_enable            = intel_ntb4_link_enable,
 534         .link_disable           = intel_ntb4_link_disable,
 535         .db_valid_mask          = intel_ntb_db_valid_mask,
 536         .db_vector_count        = intel_ntb_db_vector_count,
 537         .db_vector_mask         = intel_ntb_db_vector_mask,
 538         .db_read                = intel_ntb3_db_read,
 539         .db_clear               = intel_ntb3_db_clear,
 540         .db_set_mask            = intel_ntb_db_set_mask,
 541         .db_clear_mask          = intel_ntb_db_clear_mask,
 542         .peer_db_addr           = intel_ntb3_peer_db_addr,
 543         .peer_db_set            = intel_ntb3_peer_db_set,
 544         .spad_is_unsafe         = intel_ntb_spad_is_unsafe,
 545         .spad_count             = intel_ntb_spad_count,
 546         .spad_read              = intel_ntb_spad_read,
 547         .spad_write             = intel_ntb_spad_write,
 548         .peer_spad_addr         = intel_ntb_peer_spad_addr,
 549         .peer_spad_read         = intel_ntb_peer_spad_read,
 550         .peer_spad_write        = intel_ntb_peer_spad_write,
 551 };
 552