drivers/net/ethernet/xilinx/ll_temac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Xilinx TEMAC Ethernet device
   4  *
   5  * Copyright (c) 2008 Nissin Systems Co., Ltd.,  Yoshio Kashiwagi
   6  * Copyright (c) 2005-2008 DLA Systems,  David H. Lynch Jr. <dhlii@dlasys.net>
   7  * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
   8  *
   9  * This is a driver for the Xilinx ll_temac ipcore which is often used
  10  * in the Virtex and Spartan series of chips.
  11  *
  12  * Notes:
  13  * - The ll_temac hardware uses indirect access for many of the TEMAC
  14  *   registers, include the MDIO bus.  However, indirect access to MDIO
  15  *   registers take considerably more clock cycles than to TEMAC registers.
  16  *   MDIO accesses are long, so threads doing them should probably sleep
  17  *   rather than busywait.  However, since only one indirect access can be
  18  *   in progress at any given time, that means that *all* indirect accesses
  19  *   could end up sleeping (to wait for an MDIO access to complete).
  20  *   Fortunately none of the indirect accesses are on the 'hot' path for tx
  21  *   or rx, so this should be okay.
  22  *
  23  * TODO:
  24  * - Factor out locallink DMA code into separate driver
  25  * - Fix support for hardware checksumming.
  26  * - Testing.  Lots and lots of testing.
  27  *
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/mii.h>
  33 #include <linux/module.h>
  34 #include <linux/mutex.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/if_ether.h>
  37 #include <linux/of.h>
  38 #include <linux/of_device.h>
  39 #include <linux/of_irq.h>
  40 #include <linux/of_mdio.h>
  41 #include <linux/of_net.h>
  42 #include <linux/of_platform.h>
  43 #include <linux/of_address.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/spinlock.h>
  46 #include <linux/tcp.h>      /* needed for sizeof(tcphdr) */
  47 #include <linux/udp.h>      /* needed for sizeof(udphdr) */
  48 #include <linux/phy.h>
  49 #include <linux/in.h>
  50 #include <linux/io.h>
  51 #include <linux/ip.h>
  52 #include <linux/slab.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/workqueue.h>
  55 #include <linux/dma-mapping.h>
  56 #include <linux/processor.h>
  57 #include <linux/platform_data/xilinx-ll-temac.h>
  58
  59 #include "ll_temac.h"
  60
  61 /* Descriptors defines for Tx and Rx DMA */
  62 #define TX_BD_NUM_DEFAULT               64
  63 #define RX_BD_NUM_DEFAULT               1024
  64 #define TX_BD_NUM_MAX                   4096
  65 #define RX_BD_NUM_MAX                   4096
  66
  67 /* ---------------------------------------------------------------------
  68  * Low level register access functions
  69  */
  70
  71 static u32 _temac_ior_be(struct temac_local *lp, int offset)
  72 {
  73         return ioread32be(lp->regs + offset);
  74 }
  75
  76 static void _temac_iow_be(struct temac_local *lp, int offset, u32 value)
  77 {
  78         return iowrite32be(value, lp->regs + offset);
  79 }
  80
  81 static u32 _temac_ior_le(struct temac_local *lp, int offset)
  82 {
  83         return ioread32(lp->regs + offset);
  84 }
  85
  86 static void _temac_iow_le(struct temac_local *lp, int offset, u32 value)
  87 {
  88         return iowrite32(value, lp->regs + offset);
  89 }
  90
  91 static bool hard_acs_rdy(struct temac_local *lp)
  92 {
  93         return temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK;
  94 }
  95
  96 static bool hard_acs_rdy_or_timeout(struct temac_local *lp, ktime_t timeout)
  97 {
  98         ktime_t cur = ktime_get();
  99
 100         return hard_acs_rdy(lp) || ktime_after(cur, timeout);
 101 }
 102
 103 /* Poll for maximum 20 ms.  This is similar to the 2 jiffies @ 100 Hz
 104  * that was used before, and should cover MDIO bus speed down to 3200
 105  * Hz.
 106  */
 107 #define HARD_ACS_RDY_POLL_NS (20 * NSEC_PER_MSEC)
 108
 109 /*
 110  * temac_indirect_busywait - Wait for current indirect register access
 111  * to complete.
 112  */
 113 int temac_indirect_busywait(struct temac_local *lp)
 114 {
 115         ktime_t timeout = ktime_add_ns(ktime_get(), HARD_ACS_RDY_POLL_NS);
 116
 117         spin_until_cond(hard_acs_rdy_or_timeout(lp, timeout));
 118         if (WARN_ON(!hard_acs_rdy(lp)))
 119                 return -ETIMEDOUT;
 120         else
 121                 return 0;
 122 }
 123
 124 /*
 125  * temac_indirect_in32 - Indirect register read access.  This function
 126  * must be called without lp->indirect_lock being held.
 127  */
 128 u32 temac_indirect_in32(struct temac_local *lp, int reg)
 129 {
 130         unsigned long flags;
 131         int val;
 132
 133         spin_lock_irqsave(lp->indirect_lock, flags);
 134         val = temac_indirect_in32_locked(lp, reg);
 135         spin_unlock_irqrestore(lp->indirect_lock, flags);
 136         return val;
 137 }
 138
 139 /*
 140  * temac_indirect_in32_locked - Indirect register read access.  This
 141  * function must be called with lp->indirect_lock being held.  Use
 142  * this together with spin_lock_irqsave/spin_lock_irqrestore to avoid
 143  * repeated lock/unlock and to ensure uninterrupted access to indirect
 144  * registers.
 145  */
 146 u32 temac_indirect_in32_locked(struct temac_local *lp, int reg)
 147 {
 148         /* This initial wait should normally not spin, as we always
 149          * try to wait for indirect access to complete before
 150          * releasing the indirect_lock.
 151          */
 152         if (WARN_ON(temac_indirect_busywait(lp)))
 153                 return -ETIMEDOUT;
 154         /* Initiate read from indirect register */
 155         temac_iow(lp, XTE_CTL0_OFFSET, reg);
 156         /* Wait for indirect register access to complete.  We really
 157          * should not see timeouts, and could even end up causing
 158          * problem for following indirect access, so let's make a bit
 159          * of WARN noise.
 160          */
 161         if (WARN_ON(temac_indirect_busywait(lp)))
 162                 return -ETIMEDOUT;
 163         /* Value is ready now */
 164         return temac_ior(lp, XTE_LSW0_OFFSET);
 165 }
 166
 167 /*
 168  * temac_indirect_out32 - Indirect register write access.  This function
 169  * must be called without lp->indirect_lock being held.
 170  */
 171 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
 172 {
 173         unsigned long flags;
 174
 175         spin_lock_irqsave(lp->indirect_lock, flags);
 176         temac_indirect_out32_locked(lp, reg, value);
 177         spin_unlock_irqrestore(lp->indirect_lock, flags);
 178 }
 179
 180 /*
 181  * temac_indirect_out32_locked - Indirect register write access.  This
 182  * function must be called with lp->indirect_lock being held.  Use
 183  * this together with spin_lock_irqsave/spin_lock_irqrestore to avoid
 184  * repeated lock/unlock and to ensure uninterrupted access to indirect
 185  * registers.
 186  */
 187 void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value)
 188 {
 189         /* As in temac_indirect_in32_locked(), we should normally not
 190          * spin here.  And if it happens, we actually end up silently
 191          * ignoring the write request.  Ouch.
 192          */
 193         if (WARN_ON(temac_indirect_busywait(lp)))
 194                 return;
 195         /* Initiate write to indirect register */
 196         temac_iow(lp, XTE_LSW0_OFFSET, value);
 197         temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
 198         /* As in temac_indirect_in32_locked(), we should not see timeouts
 199          * here.  And if it happens, we continue before the write has
 200          * completed.  Not good.
 201          */
 202         WARN_ON(temac_indirect_busywait(lp));
 203 }
 204
 205 /*
 206  * temac_dma_in32_* - Memory mapped DMA read, these function expects a
 207  * register input that is based on DCR word addresses which are then
 208  * converted to memory mapped byte addresses.  To be assigned to
 209  * lp->dma_in32.
 210  */
 211 static u32 temac_dma_in32_be(struct temac_local *lp, int reg)
 212 {
 213         return ioread32be(lp->sdma_regs + (reg << 2));
 214 }
 215
 216 static u32 temac_dma_in32_le(struct temac_local *lp, int reg)
 217 {
 218         return ioread32(lp->sdma_regs + (reg << 2));
 219 }
 220
 221 /*
 222  * temac_dma_out32_* - Memory mapped DMA read, these function expects
 223  * a register input that is based on DCR word addresses which are then
 224  * converted to memory mapped byte addresses.  To be assigned to
 225  * lp->dma_out32.
 226  */
 227 static void temac_dma_out32_be(struct temac_local *lp, int reg, u32 value)
 228 {
 229         iowrite32be(value, lp->sdma_regs + (reg << 2));
 230 }
 231
 232 static void temac_dma_out32_le(struct temac_local *lp, int reg, u32 value)
 233 {
 234         iowrite32(value, lp->sdma_regs + (reg << 2));
 235 }
 236
 237 /* DMA register access functions can be DCR based or memory mapped.
 238  * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
 239  * memory mapped.
 240  */
 241 #ifdef CONFIG_PPC_DCR
 242
 243 /*
 244  * temac_dma_dcr_in32 - DCR based DMA read
 245  */
 246 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
 247 {
 248         return dcr_read(lp->sdma_dcrs, reg);
 249 }
 250
 251 /*
 252  * temac_dma_dcr_out32 - DCR based DMA write
 253  */
 254 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
 255 {
 256         dcr_write(lp->sdma_dcrs, reg, value);
 257 }
 258
 259 /*
 260  * temac_dcr_setup - If the DMA is DCR based, then setup the address and
 261  * I/O  functions
 262  */
 263 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
 264                                 struct device_node *np)
 265 {
 266         unsigned int dcrs;
 267
 268         /* setup the dcr address mapping if it's in the device tree */
 269
 270         dcrs = dcr_resource_start(np, 0);
 271         if (dcrs != 0) {
 272                 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
 273                 lp->dma_in = temac_dma_dcr_in;
 274                 lp->dma_out = temac_dma_dcr_out;
 275                 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
 276                 return 0;
 277         }
 278         /* no DCR in the device tree, indicate a failure */
 279         return -1;
 280 }
 281
 282 #else
 283
 284 /*
 285  * temac_dcr_setup - This is a stub for when DCR is not supported,
 286  * such as with MicroBlaze and x86
 287  */
 288 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
 289                                 struct device_node *np)
 290 {
 291         return -1;
 292 }
 293
 294 #endif
 295
 296 /*
 297  * temac_dma_bd_release - Release buffer descriptor rings
 298  */
 299 static void temac_dma_bd_release(struct net_device *ndev)
 300 {
 301         struct temac_local *lp = netdev_priv(ndev);
 302         int i;
 303
 304         /* Reset Local Link (DMA) */
 305         lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
 306
 307         for (i = 0; i < lp->rx_bd_num; i++) {
 308                 if (!lp->rx_skb[i])
 309                         break;
 310                 else {
 311                         dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
 312                                         XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
 313                         dev_kfree_skb(lp->rx_skb[i]);
 314                 }
 315         }
 316         if (lp->rx_bd_v)
 317                 dma_free_coherent(ndev->dev.parent,
 318                                   sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
 319                                   lp->rx_bd_v, lp->rx_bd_p);
 320         if (lp->tx_bd_v)
 321                 dma_free_coherent(ndev->dev.parent,
 322                                   sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
 323                                   lp->tx_bd_v, lp->tx_bd_p);
 324 }
 325
 326 /*
 327  * temac_dma_bd_init - Setup buffer descriptor rings
 328  */
 329 static int temac_dma_bd_init(struct net_device *ndev)
 330 {
 331         struct temac_local *lp = netdev_priv(ndev);
 332         struct sk_buff *skb;
 333         dma_addr_t skb_dma_addr;
 334         int i;
 335
 336         lp->rx_skb = devm_kcalloc(&ndev->dev, lp->rx_bd_num,
 337                                   sizeof(*lp->rx_skb), GFP_KERNEL);
 338         if (!lp->rx_skb)
 339                 goto out;
 340
 341         /* allocate the tx and rx ring buffer descriptors. */
 342         /* returns a virtual address and a physical address. */
 343         lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 344                                          sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
 345                                          &lp->tx_bd_p, GFP_KERNEL);
 346         if (!lp->tx_bd_v)
 347                 goto out;
 348
 349         lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 350                                          sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
 351                                          &lp->rx_bd_p, GFP_KERNEL);
 352         if (!lp->rx_bd_v)
 353                 goto out;
 354
 355         for (i = 0; i < lp->tx_bd_num; i++) {
 356                 lp->tx_bd_v[i].next = cpu_to_be32(lp->tx_bd_p
 357                         + sizeof(*lp->tx_bd_v) * ((i + 1) % lp->tx_bd_num));
 358         }
 359
 360         for (i = 0; i < lp->rx_bd_num; i++) {
 361                 lp->rx_bd_v[i].next = cpu_to_be32(lp->rx_bd_p
 362                         + sizeof(*lp->rx_bd_v) * ((i + 1) % lp->rx_bd_num));
 363
 364                 skb = netdev_alloc_skb_ip_align(ndev,
 365                                                 XTE_MAX_JUMBO_FRAME_SIZE);
 366                 if (!skb)
 367                         goto out;
 368
 369                 lp->rx_skb[i] = skb;
 370                 /* returns physical address of skb->data */
 371                 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
 372                                               XTE_MAX_JUMBO_FRAME_SIZE,
 373                                               DMA_FROM_DEVICE);
 374                 if (dma_mapping_error(ndev->dev.parent, skb_dma_addr))
 375                         goto out;
 376                 lp->rx_bd_v[i].phys = cpu_to_be32(skb_dma_addr);
 377                 lp->rx_bd_v[i].len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
 378                 lp->rx_bd_v[i].app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
 379         }
 380
 381         /* Configure DMA channel (irq setup) */
 382         lp->dma_out(lp, TX_CHNL_CTRL,
 383                     lp->coalesce_delay_tx << 24 | lp->coalesce_count_tx << 16 |
 384                     0x00000400 | // Use 1 Bit Wide Counters. Currently Not Used!
 385                     CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
 386                     CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
 387         lp->dma_out(lp, RX_CHNL_CTRL,
 388                     lp->coalesce_delay_rx << 24 | lp->coalesce_count_rx << 16 |
 389                     CHNL_CTRL_IRQ_IOE |
 390                     CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
 391                     CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
 392
 393         /* Init descriptor indexes */
 394         lp->tx_bd_ci = 0;
 395         lp->tx_bd_tail = 0;
 396         lp->rx_bd_ci = 0;
 397         lp->rx_bd_tail = lp->rx_bd_num - 1;
 398
 399         /* Enable RX DMA transfers */
 400         wmb();
 401         lp->dma_out(lp, RX_CURDESC_PTR,  lp->rx_bd_p);
 402         lp->dma_out(lp, RX_TAILDESC_PTR,
 403                        lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * lp->rx_bd_tail));
 404
 405         /* Prepare for TX DMA transfer */
 406         lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
 407
 408         return 0;
 409
 410 out:
 411         temac_dma_bd_release(ndev);
 412         return -ENOMEM;
 413 }
 414
 415 /* ---------------------------------------------------------------------
 416  * net_device_ops
 417  */
 418
 419 static void temac_do_set_mac_address(struct net_device *ndev)
 420 {
 421         struct temac_local *lp = netdev_priv(ndev);
 422         unsigned long flags;
 423
 424         /* set up unicast MAC address filter set its mac address */
 425         spin_lock_irqsave(lp->indirect_lock, flags);
 426         temac_indirect_out32_locked(lp, XTE_UAW0_OFFSET,
 427                                     (ndev->dev_addr[0]) |
 428                                     (ndev->dev_addr[1] << 8) |
 429                                     (ndev->dev_addr[2] << 16) |
 430                                     (ndev->dev_addr[3] << 24));
 431         /* There are reserved bits in EUAW1
 432          * so don't affect them Set MAC bits [47:32] in EUAW1 */
 433         temac_indirect_out32_locked(lp, XTE_UAW1_OFFSET,
 434                                     (ndev->dev_addr[4] & 0x000000ff) |
 435                                     (ndev->dev_addr[5] << 8));
 436         spin_unlock_irqrestore(lp->indirect_lock, flags);
 437 }
 438
 439 static int temac_init_mac_address(struct net_device *ndev, const void *address)
 440 {
 441         memcpy(ndev->dev_addr, address, ETH_ALEN);
 442         if (!is_valid_ether_addr(ndev->dev_addr))
 443                 eth_hw_addr_random(ndev);
 444         temac_do_set_mac_address(ndev);
 445         return 0;
 446 }
 447
 448 static int temac_set_mac_address(struct net_device *ndev, void *p)
 449 {
 450         struct sockaddr *addr = p;
 451
 452         if (!is_valid_ether_addr(addr->sa_data))
 453                 return -EADDRNOTAVAIL;
 454         memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
 455         temac_do_set_mac_address(ndev);
 456         return 0;
 457 }
 458
 459 static void temac_set_multicast_list(struct net_device *ndev)
 460 {
 461         struct temac_local *lp = netdev_priv(ndev);
 462         u32 multi_addr_msw, multi_addr_lsw;
 463         int i = 0;
 464         unsigned long flags;
 465         bool promisc_mode_disabled = false;
 466
 467         if (ndev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
 468             (netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM)) {
 469                 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
 470                 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
 471                 return;
 472         }
 473
 474         spin_lock_irqsave(lp->indirect_lock, flags);
 475
 476         if (!netdev_mc_empty(ndev)) {
 477                 struct netdev_hw_addr *ha;
 478
 479                 netdev_for_each_mc_addr(ha, ndev) {
 480                         if (WARN_ON(i >= MULTICAST_CAM_TABLE_NUM))
 481                                 break;
 482                         multi_addr_msw = ((ha->addr[3] << 24) |
 483                                           (ha->addr[2] << 16) |
 484                                           (ha->addr[1] << 8) |
 485                                           (ha->addr[0]));
 486                         temac_indirect_out32_locked(lp, XTE_MAW0_OFFSET,
 487                                                     multi_addr_msw);
 488                         multi_addr_lsw = ((ha->addr[5] << 8) |
 489                                           (ha->addr[4]) | (i << 16));
 490                         temac_indirect_out32_locked(lp, XTE_MAW1_OFFSET,
 491                                                     multi_addr_lsw);
 492                         i++;
 493                 }
 494         }
 495
 496         /* Clear all or remaining/unused address table entries */
 497         while (i < MULTICAST_CAM_TABLE_NUM) {
 498                 temac_indirect_out32_locked(lp, XTE_MAW0_OFFSET, 0);
 499                 temac_indirect_out32_locked(lp, XTE_MAW1_OFFSET, i << 16);
 500                 i++;
 501         }
 502
 503         /* Enable address filter block if currently disabled */
 504         if (temac_indirect_in32_locked(lp, XTE_AFM_OFFSET)
 505             & XTE_AFM_EPPRM_MASK) {
 506                 temac_indirect_out32_locked(lp, XTE_AFM_OFFSET, 0);
 507                 promisc_mode_disabled = true;
 508         }
 509
 510         spin_unlock_irqrestore(lp->indirect_lock, flags);
 511
 512         if (promisc_mode_disabled)
 513                 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
 514 }
 515
 516 static struct temac_option {
 517         int flg;
 518         u32 opt;
 519         u32 reg;
 520         u32 m_or;
 521         u32 m_and;
 522 } temac_options[] = {
 523         /* Turn on jumbo packet support for both Rx and Tx */
 524         {
 525                 .opt = XTE_OPTION_JUMBO,
 526                 .reg = XTE_TXC_OFFSET,
 527                 .m_or = XTE_TXC_TXJMBO_MASK,
 528         },
 529         {
 530                 .opt = XTE_OPTION_JUMBO,
 531                 .reg = XTE_RXC1_OFFSET,
 532                 .m_or =XTE_RXC1_RXJMBO_MASK,
 533         },
 534         /* Turn on VLAN packet support for both Rx and Tx */
 535         {
 536                 .opt = XTE_OPTION_VLAN,
 537                 .reg = XTE_TXC_OFFSET,
 538                 .m_or =XTE_TXC_TXVLAN_MASK,
 539         },
 540         {
 541                 .opt = XTE_OPTION_VLAN,
 542                 .reg = XTE_RXC1_OFFSET,
 543                 .m_or =XTE_RXC1_RXVLAN_MASK,
 544         },
 545         /* Turn on FCS stripping on receive packets */
 546         {
 547                 .opt = XTE_OPTION_FCS_STRIP,
 548                 .reg = XTE_RXC1_OFFSET,
 549                 .m_or =XTE_RXC1_RXFCS_MASK,
 550         },
 551         /* Turn on FCS insertion on transmit packets */
 552         {
 553                 .opt = XTE_OPTION_FCS_INSERT,
 554                 .reg = XTE_TXC_OFFSET,
 555                 .m_or =XTE_TXC_TXFCS_MASK,
 556         },
 557         /* Turn on length/type field checking on receive packets */
 558         {
 559                 .opt = XTE_OPTION_LENTYPE_ERR,
 560                 .reg = XTE_RXC1_OFFSET,
 561                 .m_or =XTE_RXC1_RXLT_MASK,
 562         },
 563         /* Turn on flow control */
 564         {
 565                 .opt = XTE_OPTION_FLOW_CONTROL,
 566                 .reg = XTE_FCC_OFFSET,
 567                 .m_or =XTE_FCC_RXFLO_MASK,
 568         },
 569         /* Turn on flow control */
 570         {
 571                 .opt = XTE_OPTION_FLOW_CONTROL,
 572                 .reg = XTE_FCC_OFFSET,
 573                 .m_or =XTE_FCC_TXFLO_MASK,
 574         },
 575         /* Turn on promiscuous frame filtering (all frames are received ) */
 576         {
 577                 .opt = XTE_OPTION_PROMISC,
 578                 .reg = XTE_AFM_OFFSET,
 579                 .m_or =XTE_AFM_EPPRM_MASK,
 580         },
 581         /* Enable transmitter if not already enabled */
 582         {
 583                 .opt = XTE_OPTION_TXEN,
 584                 .reg = XTE_TXC_OFFSET,
 585                 .m_or =XTE_TXC_TXEN_MASK,
 586         },
 587         /* Enable receiver? */
 588         {
 589                 .opt = XTE_OPTION_RXEN,
 590                 .reg = XTE_RXC1_OFFSET,
 591                 .m_or =XTE_RXC1_RXEN_MASK,
 592         },
 593         {}
 594 };
 595
 596 /*
 597  * temac_setoptions
 598  */
 599 static u32 temac_setoptions(struct net_device *ndev, u32 options)
 600 {
 601         struct temac_local *lp = netdev_priv(ndev);
 602         struct temac_option *tp = &temac_options[0];
 603         int reg;
 604         unsigned long flags;
 605
 606         spin_lock_irqsave(lp->indirect_lock, flags);
 607         while (tp->opt) {
 608                 reg = temac_indirect_in32_locked(lp, tp->reg) & ~tp->m_or;
 609                 if (options & tp->opt) {
 610                         reg |= tp->m_or;
 611                         temac_indirect_out32_locked(lp, tp->reg, reg);
 612                 }
 613                 tp++;
 614         }
 615         spin_unlock_irqrestore(lp->indirect_lock, flags);
 616         lp->options |= options;
 617
 618         return 0;
 619 }
 620
 621 /* Initialize temac */
 622 static void temac_device_reset(struct net_device *ndev)
 623 {
 624         struct temac_local *lp = netdev_priv(ndev);
 625         u32 timeout;
 626         u32 val;
 627         unsigned long flags;
 628
 629         /* Perform a software reset */
 630
 631         /* 0x300 host enable bit ? */
 632         /* reset PHY through control register ?:1 */
 633
 634         dev_dbg(&ndev->dev, "%s()\n", __func__);
 635
 636         /* Reset the receiver and wait for it to finish reset */
 637         temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
 638         timeout = 1000;
 639         while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
 640                 udelay(1);
 641                 if (--timeout == 0) {
 642                         dev_err(&ndev->dev,
 643                                 "temac_device_reset RX reset timeout!!\n");
 644                         break;
 645                 }
 646         }
 647
 648         /* Reset the transmitter and wait for it to finish reset */
 649         temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
 650         timeout = 1000;
 651         while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
 652                 udelay(1);
 653                 if (--timeout == 0) {
 654                         dev_err(&ndev->dev,
 655                                 "temac_device_reset TX reset timeout!!\n");
 656                         break;
 657                 }
 658         }
 659
 660         /* Disable the receiver */
 661         spin_lock_irqsave(lp->indirect_lock, flags);
 662         val = temac_indirect_in32_locked(lp, XTE_RXC1_OFFSET);
 663         temac_indirect_out32_locked(lp, XTE_RXC1_OFFSET,
 664                                     val & ~XTE_RXC1_RXEN_MASK);
 665         spin_unlock_irqrestore(lp->indirect_lock, flags);
 666
 667         /* Reset Local Link (DMA) */
 668         lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
 669         timeout = 1000;
 670         while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
 671                 udelay(1);
 672                 if (--timeout == 0) {
 673                         dev_err(&ndev->dev,
 674                                 "temac_device_reset DMA reset timeout!!\n");
 675                         break;
 676                 }
 677         }
 678         lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
 679
 680         if (temac_dma_bd_init(ndev)) {
 681                 dev_err(&ndev->dev,
 682                                 "temac_device_reset descriptor allocation failed\n");
 683         }
 684
 685         spin_lock_irqsave(lp->indirect_lock, flags);
 686         temac_indirect_out32_locked(lp, XTE_RXC0_OFFSET, 0);
 687         temac_indirect_out32_locked(lp, XTE_RXC1_OFFSET, 0);
 688         temac_indirect_out32_locked(lp, XTE_TXC_OFFSET, 0);
 689         temac_indirect_out32_locked(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
 690         spin_unlock_irqrestore(lp->indirect_lock, flags);
 691
 692         /* Sync default options with HW
 693          * but leave receiver and transmitter disabled.  */
 694         temac_setoptions(ndev,
 695                          lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
 696
 697         temac_do_set_mac_address(ndev);
 698
 699         /* Set address filter table */
 700         temac_set_multicast_list(ndev);
 701         if (temac_setoptions(ndev, lp->options))
 702                 dev_err(&ndev->dev, "Error setting TEMAC options\n");
 703
 704         /* Init Driver variable */
 705         netif_trans_update(ndev); /* prevent tx timeout */
 706 }
 707
 708 static void temac_adjust_link(struct net_device *ndev)
 709 {
 710         struct temac_local *lp = netdev_priv(ndev);
 711         struct phy_device *phy = ndev->phydev;
 712         u32 mii_speed;
 713         int link_state;
 714         unsigned long flags;
 715
 716         /* hash together the state values to decide if something has changed */
 717         link_state = phy->speed | (phy->duplex << 1) | phy->link;
 718
 719         if (lp->last_link != link_state) {
 720                 spin_lock_irqsave(lp->indirect_lock, flags);
 721                 mii_speed = temac_indirect_in32_locked(lp, XTE_EMCFG_OFFSET);
 722                 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
 723
 724                 switch (phy->speed) {
 725                 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
 726                 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
 727                 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
 728                 }
 729
 730                 /* Write new speed setting out to TEMAC */
 731                 temac_indirect_out32_locked(lp, XTE_EMCFG_OFFSET, mii_speed);
 732                 spin_unlock_irqrestore(lp->indirect_lock, flags);
 733
 734                 lp->last_link = link_state;
 735                 phy_print_status(phy);
 736         }
 737 }
 738
 739 #ifdef CONFIG_64BIT
 740
 741 static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
 742 {
 743         bd->app3 = (u32)(((u64)p) >> 32);
 744         bd->app4 = (u32)((u64)p & 0xFFFFFFFF);
 745 }
 746
 747 static void *ptr_from_txbd(struct cdmac_bd *bd)
 748 {
 749         return (void *)(((u64)(bd->app3) << 32) | bd->app4);
 750 }
 751
 752 #else
 753
 754 static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
 755 {
 756         bd->app4 = (u32)p;
 757 }
 758
 759 static void *ptr_from_txbd(struct cdmac_bd *bd)
 760 {
 761         return (void *)(bd->app4);
 762 }
 763
 764 #endif
 765
 766 static void temac_start_xmit_done(struct net_device *ndev)
 767 {
 768         struct temac_local *lp = netdev_priv(ndev);
 769         struct cdmac_bd *cur_p;
 770         unsigned int stat = 0;
 771         struct sk_buff *skb;
 772
 773         cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
 774         stat = be32_to_cpu(cur_p->app0);
 775
 776         while (stat & STS_CTRL_APP0_CMPLT) {
 777                 /* Make sure that the other fields are read after bd is
 778                  * released by dma
 779                  */
 780                 rmb();
 781                 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),
 782                                  be32_to_cpu(cur_p->len), DMA_TO_DEVICE);
 783                 skb = (struct sk_buff *)ptr_from_txbd(cur_p);
 784                 if (skb)
 785                         dev_consume_skb_irq(skb);
 786                 cur_p->app1 = 0;
 787                 cur_p->app2 = 0;
 788                 cur_p->app3 = 0;
 789                 cur_p->app4 = 0;
 790
 791                 ndev->stats.tx_packets++;
 792                 ndev->stats.tx_bytes += be32_to_cpu(cur_p->len);
 793
 794                 /* app0 must be visible last, as it is used to flag
 795                  * availability of the bd
 796                  */
 797                 smp_mb();
 798                 cur_p->app0 = 0;
 799
 800                 lp->tx_bd_ci++;
 801                 if (lp->tx_bd_ci >= lp->tx_bd_num)
 802                         lp->tx_bd_ci = 0;
 803
 804                 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
 805                 stat = be32_to_cpu(cur_p->app0);
 806         }
 807
 808         /* Matches barrier in temac_start_xmit */
 809         smp_mb();
 810
 811         netif_wake_queue(ndev);
 812 }
 813
 814 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
 815 {
 816         struct cdmac_bd *cur_p;
 817         int tail;
 818
 819         tail = lp->tx_bd_tail;
 820         cur_p = &lp->tx_bd_v[tail];
 821
 822         do {
 823                 if (cur_p->app0)
 824                         return NETDEV_TX_BUSY;
 825
 826                 /* Make sure to read next bd app0 after this one */
 827                 rmb();
 828
 829                 tail++;
 830                 if (tail >= lp->tx_bd_num)
 831                         tail = 0;
 832
 833                 cur_p = &lp->tx_bd_v[tail];
 834                 num_frag--;
 835         } while (num_frag >= 0);
 836
 837         return 0;
 838 }
 839
 840 static netdev_tx_t
 841 temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 842 {
 843         struct temac_local *lp = netdev_priv(ndev);
 844         struct cdmac_bd *cur_p;
 845         dma_addr_t tail_p, skb_dma_addr;
 846         int ii;
 847         unsigned long num_frag;
 848         skb_frag_t *frag;
 849
 850         num_frag = skb_shinfo(skb)->nr_frags;
 851         frag = &skb_shinfo(skb)->frags[0];
 852         cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 853
 854         if (temac_check_tx_bd_space(lp, num_frag + 1)) {
 855                 if (netif_queue_stopped(ndev))
 856                         return NETDEV_TX_BUSY;
 857
 858                 netif_stop_queue(ndev);
 859
 860                 /* Matches barrier in temac_start_xmit_done */
 861                 smp_mb();
 862
 863                 /* Space might have just been freed - check again */
 864                 if (temac_check_tx_bd_space(lp, num_frag + 1))
 865                         return NETDEV_TX_BUSY;
 866
 867                 netif_wake_queue(ndev);
 868         }
 869
 870         cur_p->app0 = 0;
 871         if (skb->ip_summed == CHECKSUM_PARTIAL) {
 872                 unsigned int csum_start_off = skb_checksum_start_offset(skb);
 873                 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
 874
 875                 cur_p->app0 |= cpu_to_be32(0x000001); /* TX Checksum Enabled */
 876                 cur_p->app1 = cpu_to_be32((csum_start_off << 16)
 877                                           | csum_index_off);
 878                 cur_p->app2 = 0;  /* initial checksum seed */
 879         }
 880
 881         cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_SOP);
 882         skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
 883                                       skb_headlen(skb), DMA_TO_DEVICE);
 884         cur_p->len = cpu_to_be32(skb_headlen(skb));
 885         if (WARN_ON_ONCE(dma_mapping_error(ndev->dev.parent, skb_dma_addr))) {
 886                 dev_kfree_skb_any(skb);
 887                 ndev->stats.tx_dropped++;
 888                 return NETDEV_TX_OK;
 889         }
 890         cur_p->phys = cpu_to_be32(skb_dma_addr);
 891
 892         for (ii = 0; ii < num_frag; ii++) {
 893                 if (++lp->tx_bd_tail >= lp->tx_bd_num)
 894                         lp->tx_bd_tail = 0;
 895
 896                 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 897                 skb_dma_addr = dma_map_single(ndev->dev.parent,
 898                                               skb_frag_address(frag),
 899                                               skb_frag_size(frag),
 900                                               DMA_TO_DEVICE);
 901                 if (dma_mapping_error(ndev->dev.parent, skb_dma_addr)) {
 902                         if (--lp->tx_bd_tail < 0)
 903                                 lp->tx_bd_tail = lp->tx_bd_num - 1;
 904                         cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 905                         while (--ii >= 0) {
 906                                 --frag;
 907                                 dma_unmap_single(ndev->dev.parent,
 908                                                  be32_to_cpu(cur_p->phys),
 909                                                  skb_frag_size(frag),
 910                                                  DMA_TO_DEVICE);
 911                                 if (--lp->tx_bd_tail < 0)
 912                                         lp->tx_bd_tail = lp->tx_bd_num - 1;
 913                                 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 914                         }
 915                         dma_unmap_single(ndev->dev.parent,
 916                                          be32_to_cpu(cur_p->phys),
 917                                          skb_headlen(skb), DMA_TO_DEVICE);
 918                         dev_kfree_skb_any(skb);
 919                         ndev->stats.tx_dropped++;
 920                         return NETDEV_TX_OK;
 921                 }
 922                 cur_p->phys = cpu_to_be32(skb_dma_addr);
 923                 cur_p->len = cpu_to_be32(skb_frag_size(frag));
 924                 cur_p->app0 = 0;
 925                 frag++;
 926         }
 927         cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_EOP);
 928
 929         /* Mark last fragment with skb address, so it can be consumed
 930          * in temac_start_xmit_done()
 931          */
 932         ptr_to_txbd((void *)skb, cur_p);
 933
 934         tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
 935         lp->tx_bd_tail++;
 936         if (lp->tx_bd_tail >= lp->tx_bd_num)
 937                 lp->tx_bd_tail = 0;
 938
 939         skb_tx_timestamp(skb);
 940
 941         /* Kick off the transfer */
 942         wmb();
 943         lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
 944
 945         if (temac_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1)) {
 946                 netdev_info(ndev, "%s -> netif_stop_queue\n", __func__);
 947                 netif_stop_queue(ndev);
 948         }
 949
 950         return NETDEV_TX_OK;
 951 }
 952
 953 static int ll_temac_recv_buffers_available(struct temac_local *lp)
 954 {
 955         int available;
 956
 957         if (!lp->rx_skb[lp->rx_bd_ci])
 958                 return 0;
 959         available = 1 + lp->rx_bd_tail - lp->rx_bd_ci;
 960         if (available <= 0)
 961                 available += lp->rx_bd_num;
 962         return available;
 963 }
 964
 965 static void ll_temac_recv(struct net_device *ndev)
 966 {
 967         struct temac_local *lp = netdev_priv(ndev);
 968         unsigned long flags;
 969         int rx_bd;
 970         bool update_tail = false;
 971
 972         spin_lock_irqsave(&lp->rx_lock, flags);
 973
 974         /* Process all received buffers, passing them on network
 975          * stack.  After this, the buffer descriptors will be in an
 976          * un-allocated stage, where no skb is allocated for it, and
 977          * they are therefore not available for TEMAC/DMA.
 978          */
 979         do {
 980                 struct cdmac_bd *bd = &lp->rx_bd_v[lp->rx_bd_ci];
 981                 struct sk_buff *skb = lp->rx_skb[lp->rx_bd_ci];
 982                 unsigned int bdstat = be32_to_cpu(bd->app0);
 983                 int length;
 984
 985                 /* While this should not normally happen, we can end
 986                  * here when GFP_ATOMIC allocations fail, and we
 987                  * therefore have un-allocated buffers.
 988                  */
 989                 if (!skb)
 990                         break;
 991
 992                 /* Loop over all completed buffer descriptors */
 993                 if (!(bdstat & STS_CTRL_APP0_CMPLT))
 994                         break;
 995
 996                 dma_unmap_single(ndev->dev.parent, be32_to_cpu(bd->phys),
 997                                  XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
 998                 /* The buffer is not valid for DMA anymore */
 999                 bd->phys = 0;
1000                 bd->len = 0;
1001
1002                 length = be32_to_cpu(bd->app4) & 0x3FFF;
1003                 skb_put(skb, length);
1004                 skb->protocol = eth_type_trans(skb, ndev);
1005                 skb_checksum_none_assert(skb);
1006
1007                 /* if we're doing rx csum offload, set it up */
1008                 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
1009                     (skb->protocol == htons(ETH_P_IP)) &&
1010                     (skb->len > 64)) {
1011
1012                         /* Convert from device endianness (be32) to cpu
1013                          * endiannes, and if necessary swap the bytes
1014                          * (back) for proper IP checksum byte order
1015                          * (be16).
1016                          */
1017                         skb->csum = htons(be32_to_cpu(bd->app3) & 0xFFFF);
1018                         skb->ip_summed = CHECKSUM_COMPLETE;
1019                 }
1020
1021                 if (!skb_defer_rx_timestamp(skb))
1022                         netif_rx(skb);
1023                 /* The skb buffer is now owned by network stack above */
1024                 lp->rx_skb[lp->rx_bd_ci] = NULL;
1025
1026                 ndev->stats.rx_packets++;
1027                 ndev->stats.rx_bytes += length;
1028
1029                 rx_bd = lp->rx_bd_ci;
1030                 if (++lp->rx_bd_ci >= lp->rx_bd_num)
1031                         lp->rx_bd_ci = 0;
1032         } while (rx_bd != lp->rx_bd_tail);
1033
1034         /* DMA operations will halt when the last buffer descriptor is
1035          * processed (ie. the one pointed to by RX_TAILDESC_PTR).
1036          * When that happens, no more interrupt events will be
1037          * generated.  No IRQ_COAL or IRQ_DLY, and not even an
1038          * IRQ_ERR.  To avoid stalling, we schedule a delayed work
1039          * when there is a potential risk of that happening.  The work
1040          * will call this function, and thus re-schedule itself until
1041          * enough buffers are available again.
1042          */
1043         if (ll_temac_recv_buffers_available(lp) < lp->coalesce_count_rx)
1044                 schedule_delayed_work(&lp->restart_work, HZ / 1000);
1045
1046         /* Allocate new buffers for those buffer descriptors that were
1047          * passed to network stack.  Note that GFP_ATOMIC allocations
1048          * can fail (e.g. when a larger burst of GFP_ATOMIC
1049          * allocations occurs), so while we try to allocate all
1050          * buffers in the same interrupt where they were processed, we
1051          * continue with what we could get in case of allocation
1052          * failure.  Allocation of remaining buffers will be retried
1053          * in following calls.
1054          */
1055         while (1) {
1056                 struct sk_buff *skb;
1057                 struct cdmac_bd *bd;
1058                 dma_addr_t skb_dma_addr;
1059
1060                 rx_bd = lp->rx_bd_tail + 1;
1061                 if (rx_bd >= lp->rx_bd_num)
1062                         rx_bd = 0;
1063                 bd = &lp->rx_bd_v[rx_bd];
1064
1065                 if (bd->phys)
1066                         break;  /* All skb's allocated */
1067
1068                 skb = netdev_alloc_skb_ip_align(ndev, XTE_MAX_JUMBO_FRAME_SIZE);
1069                 if (!skb) {
1070                         dev_warn(&ndev->dev, "skb alloc failed\n");
1071                         break;
1072                 }
1073
1074                 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
1075                                               XTE_MAX_JUMBO_FRAME_SIZE,
1076                                               DMA_FROM_DEVICE);
1077                 if (WARN_ON_ONCE(dma_mapping_error(ndev->dev.parent,
1078                                                    skb_dma_addr))) {
1079                         dev_kfree_skb_any(skb);
1080                         break;
1081                 }
1082
1083                 bd->phys = cpu_to_be32(skb_dma_addr);
1084                 bd->len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
1085                 bd->app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
1086                 lp->rx_skb[rx_bd] = skb;
1087
1088                 lp->rx_bd_tail = rx_bd;
1089                 update_tail = true;
1090         }
1091
1092         /* Move tail pointer when buffers have been allocated */
1093         if (update_tail) {
1094                 lp->dma_out(lp, RX_TAILDESC_PTR,
1095                         lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_tail);
1096         }
1097
1098         spin_unlock_irqrestore(&lp->rx_lock, flags);
1099 }
1100
1101 /* Function scheduled to ensure a restart in case of DMA halt
1102  * condition caused by running out of buffer descriptors.
1103  */
1104 static void ll_temac_restart_work_func(struct work_struct *work)
1105 {
1106         struct temac_local *lp = container_of(work, struct temac_local,
1107                                               restart_work.work);
1108         struct net_device *ndev = lp->ndev;
1109
1110         ll_temac_recv(ndev);
1111 }
1112
1113 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
1114 {
1115         struct net_device *ndev = _ndev;
1116         struct temac_local *lp = netdev_priv(ndev);
1117         unsigned int status;
1118
1119         status = lp->dma_in(lp, TX_IRQ_REG);
1120         lp->dma_out(lp, TX_IRQ_REG, status);
1121
1122         if (status & (IRQ_COAL | IRQ_DLY))
1123                 temac_start_xmit_done(lp->ndev);
1124         if (status & (IRQ_ERR | IRQ_DMAERR))
1125                 dev_err_ratelimited(&ndev->dev,
1126                                     "TX error 0x%x TX_CHNL_STS=0x%08x\n",
1127                                     status, lp->dma_in(lp, TX_CHNL_STS));
1128
1129         return IRQ_HANDLED;
1130 }
1131
1132 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
1133 {
1134         struct net_device *ndev = _ndev;
1135         struct temac_local *lp = netdev_priv(ndev);
1136         unsigned int status;
1137
1138         /* Read and clear the status registers */
1139         status = lp->dma_in(lp, RX_IRQ_REG);
1140         lp->dma_out(lp, RX_IRQ_REG, status);
1141
1142         if (status & (IRQ_COAL | IRQ_DLY))
1143                 ll_temac_recv(lp->ndev);
1144         if (status & (IRQ_ERR | IRQ_DMAERR))
1145                 dev_err_ratelimited(&ndev->dev,
1146                                     "RX error 0x%x RX_CHNL_STS=0x%08x\n",
1147                                     status, lp->dma_in(lp, RX_CHNL_STS));
1148
1149         return IRQ_HANDLED;
1150 }
1151
1152 static int temac_open(struct net_device *ndev)
1153 {
1154         struct temac_local *lp = netdev_priv(ndev);
1155         struct phy_device *phydev = NULL;
1156         int rc;
1157
1158         dev_dbg(&ndev->dev, "temac_open()\n");
1159
1160         if (lp->phy_node) {
1161                 phydev = of_phy_connect(lp->ndev, lp->phy_node,
1162                                         temac_adjust_link, 0, 0);
1163                 if (!phydev) {
1164                         dev_err(lp->dev, "of_phy_connect() failed\n");
1165                         return -ENODEV;
1166                 }
1167                 phy_start(phydev);
1168         } else if (strlen(lp->phy_name) > 0) {
1169                 phydev = phy_connect(lp->ndev, lp->phy_name, temac_adjust_link,
1170                                      lp->phy_interface);
1171                 if (IS_ERR(phydev)) {
1172                         dev_err(lp->dev, "phy_connect() failed\n");
1173                         return PTR_ERR(phydev);
1174                 }
1175                 phy_start(phydev);
1176         }
1177
1178         temac_device_reset(ndev);
1179
1180         rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
1181         if (rc)
1182                 goto err_tx_irq;
1183         rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
1184         if (rc)
1185                 goto err_rx_irq;
1186
1187         return 0;
1188
1189  err_rx_irq:
1190         free_irq(lp->tx_irq, ndev);
1191  err_tx_irq:
1192         if (phydev)
1193                 phy_disconnect(phydev);
1194         dev_err(lp->dev, "request_irq() failed\n");
1195         return rc;
1196 }
1197
1198 static int temac_stop(struct net_device *ndev)
1199 {
1200         struct temac_local *lp = netdev_priv(ndev);
1201         struct phy_device *phydev = ndev->phydev;
1202
1203         dev_dbg(&ndev->dev, "temac_close()\n");
1204
1205         cancel_delayed_work_sync(&lp->restart_work);
1206
1207         free_irq(lp->tx_irq, ndev);
1208         free_irq(lp->rx_irq, ndev);
1209
1210         if (phydev)
1211                 phy_disconnect(phydev);
1212
1213         temac_dma_bd_release(ndev);
1214
1215         return 0;
1216 }
1217
1218 #ifdef CONFIG_NET_POLL_CONTROLLER
1219 static void
1220 temac_poll_controller(struct net_device *ndev)
1221 {
1222         struct temac_local *lp = netdev_priv(ndev);
1223
1224         disable_irq(lp->tx_irq);
1225         disable_irq(lp->rx_irq);
1226
1227         ll_temac_rx_irq(lp->tx_irq, ndev);
1228         ll_temac_tx_irq(lp->rx_irq, ndev);
1229
1230         enable_irq(lp->tx_irq);
1231         enable_irq(lp->rx_irq);
1232 }
1233 #endif
1234
1235 static const struct net_device_ops temac_netdev_ops = {
1236         .ndo_open = temac_open,
1237         .ndo_stop = temac_stop,
1238         .ndo_start_xmit = temac_start_xmit,
1239         .ndo_set_rx_mode = temac_set_multicast_list,
1240         .ndo_set_mac_address = temac_set_mac_address,
1241         .ndo_validate_addr = eth_validate_addr,
1242         .ndo_do_ioctl = phy_do_ioctl_running,
1243 #ifdef CONFIG_NET_POLL_CONTROLLER
1244         .ndo_poll_controller = temac_poll_controller,
1245 #endif
1246 };
1247
1248 /* ---------------------------------------------------------------------
1249  * SYSFS device attributes
1250  */
1251 static ssize_t temac_show_llink_regs(struct device *dev,
1252                                      struct device_attribute *attr, char *buf)
1253 {
1254         struct net_device *ndev = dev_get_drvdata(dev);
1255         struct temac_local *lp = netdev_priv(ndev);
1256         int i, len = 0;
1257
1258         for (i = 0; i < 0x11; i++)
1259                 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
1260                                (i % 8) == 7 ? "\n" : " ");
1261         len += sprintf(buf + len, "\n");
1262
1263         return len;
1264 }
1265
1266 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
1267
1268 static struct attribute *temac_device_attrs[] = {
1269         &dev_attr_llink_regs.attr,
1270         NULL,
1271 };
1272
1273 static const struct attribute_group temac_attr_group = {
1274         .attrs = temac_device_attrs,
1275 };
1276
1277 /* ---------------------------------------------------------------------
1278  * ethtool support
1279  */
1280
1281 static void ll_temac_ethtools_get_ringparam(struct net_device *ndev,
1282                                             struct ethtool_ringparam *ering)
1283 {
1284         struct temac_local *lp = netdev_priv(ndev);
1285
1286         ering->rx_max_pending = RX_BD_NUM_MAX;
1287         ering->rx_mini_max_pending = 0;
1288         ering->rx_jumbo_max_pending = 0;
1289         ering->tx_max_pending = TX_BD_NUM_MAX;
1290         ering->rx_pending = lp->rx_bd_num;
1291         ering->rx_mini_pending = 0;
1292         ering->rx_jumbo_pending = 0;
1293         ering->tx_pending = lp->tx_bd_num;
1294 }
1295
1296 static int ll_temac_ethtools_set_ringparam(struct net_device *ndev,
1297                                            struct ethtool_ringparam *ering)
1298 {
1299         struct temac_local *lp = netdev_priv(ndev);
1300
1301         if (ering->rx_pending > RX_BD_NUM_MAX ||
1302             ering->rx_mini_pending ||
1303             ering->rx_jumbo_pending ||
1304             ering->rx_pending > TX_BD_NUM_MAX)
1305                 return -EINVAL;
1306
1307         if (netif_running(ndev))
1308                 return -EBUSY;
1309
1310         lp->rx_bd_num = ering->rx_pending;
1311         lp->tx_bd_num = ering->tx_pending;
1312         return 0;
1313 }
1314
1315 static int ll_temac_ethtools_get_coalesce(struct net_device *ndev,
1316                                           struct ethtool_coalesce *ec)
1317 {
1318         struct temac_local *lp = netdev_priv(ndev);
1319
1320         ec->rx_max_coalesced_frames = lp->coalesce_count_rx;
1321         ec->tx_max_coalesced_frames = lp->coalesce_count_tx;
1322         ec->rx_coalesce_usecs = (lp->coalesce_delay_rx * 512) / 100;
1323         ec->tx_coalesce_usecs = (lp->coalesce_delay_tx * 512) / 100;
1324         return 0;
1325 }
1326
1327 static int ll_temac_ethtools_set_coalesce(struct net_device *ndev,
1328                                           struct ethtool_coalesce *ec)
1329 {
1330         struct temac_local *lp = netdev_priv(ndev);
1331
1332         if (netif_running(ndev)) {
1333                 netdev_err(ndev,
1334                            "Please stop netif before applying configuration\n");
1335                 return -EFAULT;
1336         }
1337
1338         if (ec->rx_max_coalesced_frames)
1339                 lp->coalesce_count_rx = ec->rx_max_coalesced_frames;
1340         if (ec->tx_max_coalesced_frames)
1341                 lp->coalesce_count_tx = ec->tx_max_coalesced_frames;
1342         /* With typical LocalLink clock speed of 200 MHz and
1343          * C_PRESCALAR=1023, each delay count corresponds to 5.12 us.
1344          */
1345         if (ec->rx_coalesce_usecs)
1346                 lp->coalesce_delay_rx =
1347                         min(255U, (ec->rx_coalesce_usecs * 100) / 512);
1348         if (ec->tx_coalesce_usecs)
1349                 lp->coalesce_delay_tx =
1350                         min(255U, (ec->tx_coalesce_usecs * 100) / 512);
1351
1352         return 0;
1353 }
1354
1355 static const struct ethtool_ops temac_ethtool_ops = {
1356         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1357                                      ETHTOOL_COALESCE_MAX_FRAMES,
1358         .nway_reset = phy_ethtool_nway_reset,
1359         .get_link = ethtool_op_get_link,
1360         .get_ts_info = ethtool_op_get_ts_info,
1361         .get_link_ksettings = phy_ethtool_get_link_ksettings,
1362         .set_link_ksettings = phy_ethtool_set_link_ksettings,
1363         .get_ringparam  = ll_temac_ethtools_get_ringparam,
1364         .set_ringparam  = ll_temac_ethtools_set_ringparam,
1365         .get_coalesce   = ll_temac_ethtools_get_coalesce,
1366         .set_coalesce   = ll_temac_ethtools_set_coalesce,
1367 };
1368
1369 static int temac_probe(struct platform_device *pdev)
1370 {
1371         struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1372         struct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np;
1373         struct temac_local *lp;
1374         struct net_device *ndev;
1375         u8 addr[ETH_ALEN];
1376         __be32 *p;
1377         bool little_endian;
1378         int rc = 0;
1379
1380         /* Init network device structure */
1381         ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp));
1382         if (!ndev)
1383                 return -ENOMEM;
1384
1385         platform_set_drvdata(pdev, ndev);
1386         SET_NETDEV_DEV(ndev, &pdev->dev);
1387         ndev->features = NETIF_F_SG;
1388         ndev->netdev_ops = &temac_netdev_ops;
1389         ndev->ethtool_ops = &temac_ethtool_ops;
1390 #if 0
1391         ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1392         ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1393         ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1394         ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1395         ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1396         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1397         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1398         ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1399         ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1400         ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1401         ndev->features |= NETIF_F_LRO; /* large receive offload */
1402 #endif
1403
1404         /* setup temac private info structure */
1405         lp = netdev_priv(ndev);
1406         lp->ndev = ndev;
1407         lp->dev = &pdev->dev;
1408         lp->options = XTE_OPTION_DEFAULTS;
1409         lp->rx_bd_num = RX_BD_NUM_DEFAULT;
1410         lp->tx_bd_num = TX_BD_NUM_DEFAULT;
1411         spin_lock_init(&lp->rx_lock);
1412         INIT_DELAYED_WORK(&lp->restart_work, ll_temac_restart_work_func);
1413
1414         /* Setup mutex for synchronization of indirect register access */
1415         if (pdata) {
1416                 if (!pdata->indirect_lock) {
1417                         dev_err(&pdev->dev,
1418                                 "indirect_lock missing in platform_data\n");
1419                         return -EINVAL;
1420                 }
1421                 lp->indirect_lock = pdata->indirect_lock;
1422         } else {
1423                 lp->indirect_lock = devm_kmalloc(&pdev->dev,
1424                                                  sizeof(*lp->indirect_lock),
1425                                                  GFP_KERNEL);
1426                 spin_lock_init(lp->indirect_lock);
1427         }
1428
1429         /* map device registers */
1430         lp->regs = devm_platform_ioremap_resource_byname(pdev, 0);
1431         if (IS_ERR(lp->regs)) {
1432                 dev_err(&pdev->dev, "could not map TEMAC registers\n");
1433                 return -ENOMEM;
1434         }
1435
1436         /* Select register access functions with the specified
1437          * endianness mode.  Default for OF devices is big-endian.
1438          */
1439         little_endian = false;
1440         if (temac_np) {
1441                 if (of_get_property(temac_np, "little-endian", NULL))
1442                         little_endian = true;
1443         } else if (pdata) {
1444                 little_endian = pdata->reg_little_endian;
1445         }
1446         if (little_endian) {
1447                 lp->temac_ior = _temac_ior_le;
1448                 lp->temac_iow = _temac_iow_le;
1449         } else {
1450                 lp->temac_ior = _temac_ior_be;
1451                 lp->temac_iow = _temac_iow_be;
1452         }
1453
1454         /* Setup checksum offload, but default to off if not specified */
1455         lp->temac_features = 0;
1456         if (temac_np) {
1457                 p = (__be32 *)of_get_property(temac_np, "xlnx,txcsum", NULL);
1458                 if (p && be32_to_cpu(*p))
1459                         lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1460                 p = (__be32 *)of_get_property(temac_np, "xlnx,rxcsum", NULL);
1461                 if (p && be32_to_cpu(*p))
1462                         lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1463         } else if (pdata) {
1464                 if (pdata->txcsum)
1465                         lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1466                 if (pdata->rxcsum)
1467                         lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1468         }
1469         if (lp->temac_features & TEMAC_FEATURE_TX_CSUM)
1470                 /* Can checksum TCP/UDP over IPv4. */
1471                 ndev->features |= NETIF_F_IP_CSUM;
1472
1473         /* Defaults for IRQ delay/coalescing setup.  These are
1474          * configuration values, so does not belong in device-tree.
1475          */
1476         lp->coalesce_delay_tx = 0x10;
1477         lp->coalesce_count_tx = 0x22;
1478         lp->coalesce_delay_rx = 0xff;
1479         lp->coalesce_count_rx = 0x07;
1480
1481         /* Setup LocalLink DMA */
1482         if (temac_np) {
1483                 /* Find the DMA node, map the DMA registers, and
1484                  * decode the DMA IRQs.
1485                  */
1486                 dma_np = of_parse_phandle(temac_np, "llink-connected", 0);
1487                 if (!dma_np) {
1488                         dev_err(&pdev->dev, "could not find DMA node\n");
1489                         return -ENODEV;
1490                 }
1491
1492                 /* Setup the DMA register accesses, could be DCR or
1493                  * memory mapped.
1494                  */
1495                 if (temac_dcr_setup(lp, pdev, dma_np)) {
1496                         /* no DCR in the device tree, try non-DCR */
1497                         lp->sdma_regs = devm_of_iomap(&pdev->dev, dma_np, 0,
1498                                                       NULL);
1499                         if (IS_ERR(lp->sdma_regs)) {
1500                                 dev_err(&pdev->dev,
1501                                         "unable to map DMA registers\n");
1502                                 of_node_put(dma_np);
1503                                 return PTR_ERR(lp->sdma_regs);
1504                         }
1505                         if (of_get_property(dma_np, "little-endian", NULL)) {
1506                                 lp->dma_in = temac_dma_in32_le;
1507                                 lp->dma_out = temac_dma_out32_le;
1508                         } else {
1509                                 lp->dma_in = temac_dma_in32_be;
1510                                 lp->dma_out = temac_dma_out32_be;
1511                         }
1512                         dev_dbg(&pdev->dev, "MEM base: %p\n", lp->sdma_regs);
1513                 }
1514
1515                 /* Get DMA RX and TX interrupts */
1516                 lp->rx_irq = irq_of_parse_and_map(dma_np, 0);
1517                 lp->tx_irq = irq_of_parse_and_map(dma_np, 1);
1518
1519                 /* Finished with the DMA node; drop the reference */
1520                 of_node_put(dma_np);
1521         } else if (pdata) {
1522                 /* 2nd memory resource specifies DMA registers */
1523                 lp->sdma_regs = devm_platform_ioremap_resource(pdev, 1);
1524                 if (IS_ERR(lp->sdma_regs)) {
1525                         dev_err(&pdev->dev,
1526                                 "could not map DMA registers\n");
1527                         return PTR_ERR(lp->sdma_regs);
1528                 }
1529                 if (pdata->dma_little_endian) {
1530                         lp->dma_in = temac_dma_in32_le;
1531                         lp->dma_out = temac_dma_out32_le;
1532                 } else {
1533                         lp->dma_in = temac_dma_in32_be;
1534                         lp->dma_out = temac_dma_out32_be;
1535                 }
1536
1537                 /* Get DMA RX and TX interrupts */
1538                 lp->rx_irq = platform_get_irq(pdev, 0);
1539                 lp->tx_irq = platform_get_irq(pdev, 1);
1540
1541                 /* IRQ delay/coalescing setup */
1542                 if (pdata->tx_irq_timeout || pdata->tx_irq_count) {
1543                         lp->coalesce_delay_tx = pdata->tx_irq_timeout;
1544                         lp->coalesce_count_tx = pdata->tx_irq_count;
1545                 }
1546                 if (pdata->rx_irq_timeout || pdata->rx_irq_count) {
1547                         lp->coalesce_delay_rx = pdata->rx_irq_timeout;
1548                         lp->coalesce_count_rx = pdata->rx_irq_count;
1549                 }
1550         }
1551
1552         /* Error handle returned DMA RX and TX interrupts */
1553         if (lp->rx_irq < 0) {
1554                 if (lp->rx_irq != -EPROBE_DEFER)
1555                         dev_err(&pdev->dev, "could not get DMA RX irq\n");
1556                 return lp->rx_irq;
1557         }
1558         if (lp->tx_irq < 0) {
1559                 if (lp->tx_irq != -EPROBE_DEFER)
1560                         dev_err(&pdev->dev, "could not get DMA TX irq\n");
1561                 return lp->tx_irq;
1562         }
1563
1564         if (temac_np) {
1565                 /* Retrieve the MAC address */
1566                 rc = of_get_mac_address(temac_np, addr);
1567                 if (rc) {
1568                         dev_err(&pdev->dev, "could not find MAC address\n");
1569                         return -ENODEV;
1570                 }
1571                 temac_init_mac_address(ndev, addr);
1572         } else if (pdata) {
1573                 temac_init_mac_address(ndev, pdata->mac_addr);
1574         }
1575
1576         rc = temac_mdio_setup(lp, pdev);
1577         if (rc)
1578                 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1579
1580         if (temac_np) {
1581                 lp->phy_node = of_parse_phandle(temac_np, "phy-handle", 0);
1582                 if (lp->phy_node)
1583                         dev_dbg(lp->dev, "using PHY node %pOF\n", temac_np);
1584         } else if (pdata) {
1585                 snprintf(lp->phy_name, sizeof(lp->phy_name),
1586                          PHY_ID_FMT, lp->mii_bus->id, pdata->phy_addr);
1587                 lp->phy_interface = pdata->phy_interface;
1588         }
1589
1590         /* Add the device attributes */
1591         rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1592         if (rc) {
1593                 dev_err(lp->dev, "Error creating sysfs files\n");
1594                 goto err_sysfs_create;
1595         }
1596
1597         rc = register_netdev(lp->ndev);
1598         if (rc) {
1599                 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1600                 goto err_register_ndev;
1601         }
1602
1603         return 0;
1604
1605 err_register_ndev:
1606         sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1607 err_sysfs_create:
1608         if (lp->phy_node)
1609                 of_node_put(lp->phy_node);
1610         temac_mdio_teardown(lp);
1611         return rc;
1612 }
1613
1614 static int temac_remove(struct platform_device *pdev)
1615 {
1616         struct net_device *ndev = platform_get_drvdata(pdev);
1617         struct temac_local *lp = netdev_priv(ndev);
1618
1619         unregister_netdev(ndev);
1620         sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1621         if (lp->phy_node)
1622                 of_node_put(lp->phy_node);
1623         temac_mdio_teardown(lp);
1624         return 0;
1625 }
1626
1627 static const struct of_device_id temac_of_match[] = {
1628         { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1629         { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1630         { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1631         { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1632         {},
1633 };
1634 MODULE_DEVICE_TABLE(of, temac_of_match);
1635
1636 static struct platform_driver temac_driver = {
1637         .probe = temac_probe,
1638         .remove = temac_remove,
1639         .driver = {
1640                 .name = "xilinx_temac",
1641                 .of_match_table = temac_of_match,
1642         },
1643 };
1644
1645 module_platform_driver(temac_driver);
1646
1647 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1648 MODULE_AUTHOR("Yoshio Kashiwagi");
1649 MODULE_LICENSE("GPL");