2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
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6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/irq.h>
37 #include "en/xsk/rx.h"
38 #include "en/xsk/tx.h"
40 static inline bool mlx5e_channel_no_affinity_change(struct mlx5e_channel *c)
42 int current_cpu = smp_processor_id();
44 return cpumask_test_cpu(current_cpu, c->aff_mask);
47 static void mlx5e_handle_tx_dim(struct mlx5e_txqsq *sq)
49 struct mlx5e_sq_stats *stats = sq->stats;
50 struct dim_sample dim_sample = {};
52 if (unlikely(!test_bit(MLX5E_SQ_STATE_AM, &sq->state)))
55 dim_update_sample(sq->cq.event_ctr, stats->packets, stats->bytes, &dim_sample);
56 net_dim(&sq->dim, dim_sample);
59 static void mlx5e_handle_rx_dim(struct mlx5e_rq *rq)
61 struct mlx5e_rq_stats *stats = rq->stats;
62 struct dim_sample dim_sample = {};
64 if (unlikely(!test_bit(MLX5E_RQ_STATE_AM, &rq->state)))
67 dim_update_sample(rq->cq.event_ctr, stats->packets, stats->bytes, &dim_sample);
68 net_dim(&rq->dim, dim_sample);
71 void mlx5e_trigger_irq(struct mlx5e_icosq *sq)
73 struct mlx5_wq_cyc *wq = &sq->wq;
74 struct mlx5e_tx_wqe *nopwqe;
75 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
77 sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) {
78 .wqe_type = MLX5E_ICOSQ_WQE_NOP,
82 nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
83 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
86 static bool mlx5e_napi_xsk_post(struct mlx5e_xdpsq *xsksq, struct mlx5e_rq *xskrq)
88 bool busy_xsk = false, xsk_rx_alloc_err;
90 /* Handle the race between the application querying need_wakeup and the
92 * 1. Update need_wakeup both before and after the TX. If it goes to
93 * "yes", it can only happen with the first update.
94 * 2. If the application queried need_wakeup before we set it, the
95 * packets will be transmitted anyway, even w/o a wakeup.
96 * 3. Give a chance to clear need_wakeup after new packets were queued
99 mlx5e_xsk_update_tx_wakeup(xsksq);
100 busy_xsk |= mlx5e_xsk_tx(xsksq, MLX5E_TX_XSK_POLL_BUDGET);
101 mlx5e_xsk_update_tx_wakeup(xsksq);
103 xsk_rx_alloc_err = INDIRECT_CALL_2(xskrq->post_wqes,
104 mlx5e_post_rx_mpwqes,
107 busy_xsk |= mlx5e_xsk_update_rx_wakeup(xskrq, xsk_rx_alloc_err);
112 int mlx5e_napi_poll(struct napi_struct *napi, int budget)
114 struct mlx5e_channel *c = container_of(napi, struct mlx5e_channel,
116 struct mlx5e_ch_stats *ch_stats = c->stats;
117 struct mlx5e_xdpsq *xsksq = &c->xsksq;
118 struct mlx5e_rq *xskrq = &c->xskrq;
119 struct mlx5e_rq *rq = &c->rq;
120 bool aff_change = false;
121 bool busy_xsk = false;
129 xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
133 for (i = 0; i < c->num_tc; i++)
134 busy |= mlx5e_poll_tx_cq(&c->sq[i].cq, budget);
136 busy |= mlx5e_poll_xdpsq_cq(&c->xdpsq.cq);
139 busy |= mlx5e_poll_xdpsq_cq(&c->rq_xdpsq.cq);
141 if (likely(budget)) { /* budget=0 means: don't poll rx rings */
143 work_done = mlx5e_poll_rx_cq(&xskrq->cq, budget);
145 if (likely(budget - work_done))
146 work_done += mlx5e_poll_rx_cq(&rq->cq, budget - work_done);
148 busy |= work_done == budget;
151 mlx5e_poll_ico_cq(&c->icosq.cq);
152 if (mlx5e_poll_ico_cq(&c->async_icosq.cq))
153 /* Don't clear the flag if nothing was polled to prevent
154 * queueing more WQEs and overflowing the async ICOSQ.
156 clear_bit(MLX5E_SQ_STATE_PENDING_XSK_TX, &c->async_icosq.state);
158 busy |= INDIRECT_CALL_2(rq->post_wqes,
159 mlx5e_post_rx_mpwqes,
163 busy |= mlx5e_poll_xdpsq_cq(&xsksq->cq);
164 busy_xsk |= mlx5e_napi_xsk_post(xsksq, xskrq);
170 if (likely(mlx5e_channel_no_affinity_change(c))) {
174 ch_stats->aff_change++;
176 if (budget && work_done == budget)
180 if (unlikely(!napi_complete_done(napi, work_done)))
185 for (i = 0; i < c->num_tc; i++) {
186 mlx5e_handle_tx_dim(&c->sq[i]);
187 mlx5e_cq_arm(&c->sq[i].cq);
190 mlx5e_handle_rx_dim(rq);
192 mlx5e_cq_arm(&rq->cq);
193 mlx5e_cq_arm(&c->icosq.cq);
194 mlx5e_cq_arm(&c->async_icosq.cq);
195 mlx5e_cq_arm(&c->xdpsq.cq);
198 mlx5e_handle_rx_dim(xskrq);
199 mlx5e_cq_arm(&xsksq->cq);
200 mlx5e_cq_arm(&xskrq->cq);
203 if (unlikely(aff_change && busy_xsk)) {
204 mlx5e_trigger_irq(&c->icosq);
205 ch_stats->force_irq++;
214 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe)
216 struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
218 napi_schedule(cq->napi);
220 cq->ch_stats->events++;
223 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event)
225 struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
226 struct net_device *netdev = cq->netdev;
228 netdev_err(netdev, "%s: cqn=0x%.6x event=0x%.2x\n",
229 __func__, mcq->cqn, event);