drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68
  69 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  70 {
  71         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  72                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  73                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  74         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  75         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  76
  77         if (!striding_rq_umr)
  78                 return false;
  79         if (!inline_umr) {
  80                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  81                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  82                 return false;
  83         }
  84         return true;
  85 }
  86
  87 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  88                                struct mlx5e_params *params)
  89 {
  90         params->log_rq_mtu_frames = is_kdump_kernel() ?
  91                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  92                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  93
  94         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  95                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  96                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  97                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  98                        BIT(params->log_rq_mtu_frames),
  99                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
 100                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 101 }
 102
 103 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 104                                 struct mlx5e_params *params)
 105 {
 106         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 107                 return false;
 108
 109         if (MLX5_IPSEC_DEV(mdev))
 110                 return false;
 111
 112         if (params->xdp_prog) {
 113                 /* XSK params are not considered here. If striding RQ is in use,
 114                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 115                  * be called with the known XSK params.
 116                  */
 117                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 118                         return false;
 119         }
 120
 121         return true;
 122 }
 123
 124 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 125 {
 126         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 127                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 128                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 129                 MLX5_WQ_TYPE_CYCLIC;
 130 }
 131
 132 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5_core_dev *mdev = priv->mdev;
 135         u8 port_state;
 136
 137         port_state = mlx5_query_vport_state(mdev,
 138                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 139                                             0);
 140
 141         if (port_state == VPORT_STATE_UP) {
 142                 netdev_info(priv->netdev, "Link up\n");
 143                 netif_carrier_on(priv->netdev);
 144         } else {
 145                 netdev_info(priv->netdev, "Link down\n");
 146                 netif_carrier_off(priv->netdev);
 147         }
 148 }
 149
 150 static void mlx5e_update_carrier_work(struct work_struct *work)
 151 {
 152         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 153                                                update_carrier_work);
 154
 155         mutex_lock(&priv->state_lock);
 156         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 157                 if (priv->profile->update_carrier)
 158                         priv->profile->update_carrier(priv);
 159         mutex_unlock(&priv->state_lock);
 160 }
 161
 162 static void mlx5e_update_stats_work(struct work_struct *work)
 163 {
 164         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 165                                                update_stats_work);
 166
 167         mutex_lock(&priv->state_lock);
 168         priv->profile->update_stats(priv);
 169         mutex_unlock(&priv->state_lock);
 170 }
 171
 172 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 173 {
 174         if (!priv->profile->update_stats)
 175                 return;
 176
 177         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 178                 return;
 179
 180         queue_work(priv->wq, &priv->update_stats_work);
 181 }
 182
 183 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 184 {
 185         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 186         struct mlx5_eqe   *eqe = data;
 187
 188         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 189                 return NOTIFY_DONE;
 190
 191         switch (eqe->sub_type) {
 192         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 193         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 194                 queue_work(priv->wq, &priv->update_carrier_work);
 195                 break;
 196         default:
 197                 return NOTIFY_DONE;
 198         }
 199
 200         return NOTIFY_OK;
 201 }
 202
 203 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 204 {
 205         priv->events_nb.notifier_call = async_event;
 206         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 207 }
 208
 209 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 210 {
 211         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 212 }
 213
 214 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 215                                        struct mlx5e_icosq *sq,
 216                                        struct mlx5e_umr_wqe *wqe)
 217 {
 218         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 219         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 220         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 221
 222         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 223                                       ds_cnt);
 224         cseg->umr_mkey  = rq->mkey_be;
 225
 226         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 227         ucseg->xlt_octowords =
 228                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 229         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 230 }
 231
 232 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 233                                      struct mlx5e_channel *c)
 234 {
 235         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 236
 237         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 238                                                   sizeof(*rq->mpwqe.info)),
 239                                        GFP_KERNEL, cpu_to_node(c->cpu));
 240         if (!rq->mpwqe.info)
 241                 return -ENOMEM;
 242
 243         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 244
 245         return 0;
 246 }
 247
 248 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 249                                  u64 npages, u8 page_shift,
 250                                  struct mlx5_core_mkey *umr_mkey,
 251                                  dma_addr_t filler_addr)
 252 {
 253         struct mlx5_mtt *mtt;
 254         int inlen;
 255         void *mkc;
 256         u32 *in;
 257         int err;
 258         int i;
 259
 260         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 261
 262         in = kvzalloc(inlen, GFP_KERNEL);
 263         if (!in)
 264                 return -ENOMEM;
 265
 266         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 267
 268         MLX5_SET(mkc, mkc, free, 1);
 269         MLX5_SET(mkc, mkc, umr_en, 1);
 270         MLX5_SET(mkc, mkc, lw, 1);
 271         MLX5_SET(mkc, mkc, lr, 1);
 272         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 273         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 274         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 275         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 276         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 277         MLX5_SET(mkc, mkc, translations_octword_size,
 278                  MLX5_MTT_OCTW(npages));
 279         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 280         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 281                  MLX5_MTT_OCTW(npages));
 282
 283         /* Initialize the mkey with all MTTs pointing to a default
 284          * page (filler_addr). When the channels are activated, UMR
 285          * WQEs will redirect the RX WQEs to the actual memory from
 286          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 287          * to the default page.
 288          */
 289         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 290         for (i = 0 ; i < npages ; i++)
 291                 mtt[i].ptag = cpu_to_be64(filler_addr);
 292
 293         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 294
 295         kvfree(in);
 296         return err;
 297 }
 298
 299 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 300 {
 301         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 302
 303         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
 304                                      rq->wqe_overflow.addr);
 305 }
 306
 307 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 308 {
 309         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 310 }
 311
 312 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 313 {
 314         struct mlx5e_wqe_frag_info next_frag = {};
 315         struct mlx5e_wqe_frag_info *prev = NULL;
 316         int i;
 317
 318         next_frag.di = &rq->wqe.di[0];
 319
 320         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 321                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 322                 struct mlx5e_wqe_frag_info *frag =
 323                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 324                 int f;
 325
 326                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 327                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 328                                 next_frag.di++;
 329                                 next_frag.offset = 0;
 330                                 if (prev)
 331                                         prev->last_in_page = true;
 332                         }
 333                         *frag = next_frag;
 334
 335                         /* prepare next */
 336                         next_frag.offset += frag_info[f].frag_stride;
 337                         prev = frag;
 338                 }
 339         }
 340
 341         if (prev)
 342                 prev->last_in_page = true;
 343 }
 344
 345 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 346                               int wq_sz, int cpu)
 347 {
 348         int len = wq_sz << rq->wqe.info.log_num_frags;
 349
 350         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 351                                    GFP_KERNEL, cpu_to_node(cpu));
 352         if (!rq->wqe.di)
 353                 return -ENOMEM;
 354
 355         mlx5e_init_frags_partition(rq);
 356
 357         return 0;
 358 }
 359
 360 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 361 {
 362         kvfree(rq->wqe.di);
 363 }
 364
 365 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 366 {
 367         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 368
 369         mlx5e_reporter_rq_cqe_err(rq);
 370 }
 371
 372 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 373 {
 374         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 375         if (!rq->wqe_overflow.page)
 376                 return -ENOMEM;
 377
 378         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 379                                              PAGE_SIZE, rq->buff.map_dir);
 380         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 381                 __free_page(rq->wqe_overflow.page);
 382                 return -ENOMEM;
 383         }
 384         return 0;
 385 }
 386
 387 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 388 {
 389          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 390                         rq->buff.map_dir);
 391          __free_page(rq->wqe_overflow.page);
 392 }
 393
 394 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 395                           struct mlx5e_params *params,
 396                           struct mlx5e_xsk_param *xsk,
 397                           struct xsk_buff_pool *xsk_pool,
 398                           struct mlx5e_rq_param *rqp,
 399                           struct mlx5e_rq *rq)
 400 {
 401         struct page_pool_params pp_params = { 0 };
 402         struct mlx5_core_dev *mdev = c->mdev;
 403         void *rqc = rqp->rqc;
 404         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 405         u32 rq_xdp_ix;
 406         u32 pool_size;
 407         int wq_sz;
 408         int err;
 409         int i;
 410
 411         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 412
 413         rq->wq_type = params->rq_wq_type;
 414         rq->pdev    = c->pdev;
 415         rq->netdev  = c->netdev;
 416         rq->priv    = c->priv;
 417         rq->tstamp  = c->tstamp;
 418         rq->clock   = &mdev->clock;
 419         rq->icosq   = &c->icosq;
 420         rq->ix      = c->ix;
 421         rq->mdev    = mdev;
 422         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 423         rq->xdpsq   = &c->rq_xdpsq;
 424         rq->xsk_pool = xsk_pool;
 425
 426         if (rq->xsk_pool)
 427                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 428         else
 429                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 430         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 431
 432         if (params->xdp_prog)
 433                 bpf_prog_inc(params->xdp_prog);
 434         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 435
 436         rq_xdp_ix = rq->ix;
 437         if (xsk)
 438                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 439         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix, 0);
 440         if (err < 0)
 441                 goto err_rq_xdp_prog;
 442
 443         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 444         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 445         pool_size = 1 << params->log_rq_mtu_frames;
 446
 447         switch (rq->wq_type) {
 448         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 449                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 450                                         &rq->wq_ctrl);
 451                 if (err)
 452                         goto err_rq_xdp;
 453
 454                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 455                 if (err)
 456                         goto err_rq_wq_destroy;
 457
 458                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 459
 460                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 461
 462                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 463                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 464
 465                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 466                 rq->mpwqe.num_strides =
 467                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 468
 469                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 470
 471                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 472                 if (err)
 473                         goto err_rq_drop_page;
 474                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 475
 476                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 477                 if (err)
 478                         goto err_rq_mkey;
 479                 break;
 480         default: /* MLX5_WQ_TYPE_CYCLIC */
 481                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 482                                          &rq->wq_ctrl);
 483                 if (err)
 484                         goto err_rq_xdp;
 485
 486                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 487
 488                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 489
 490                 rq->wqe.info = rqp->frags_info;
 491                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 492
 493                 rq->wqe.frags =
 494                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 495                                         (wq_sz << rq->wqe.info.log_num_frags)),
 496                                       GFP_KERNEL, cpu_to_node(c->cpu));
 497                 if (!rq->wqe.frags) {
 498                         err = -ENOMEM;
 499                         goto err_rq_wq_destroy;
 500                 }
 501
 502                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 503                 if (err)
 504                         goto err_rq_frags;
 505
 506                 rq->mkey_be = c->mkey_be;
 507         }
 508
 509         err = mlx5e_rq_set_handlers(rq, params, xsk);
 510         if (err)
 511                 goto err_free_by_rq_type;
 512
 513         if (xsk) {
 514                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 515                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 516                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 517         } else {
 518                 /* Create a page_pool and register it with rxq */
 519                 pp_params.order     = 0;
 520                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 521                 pp_params.pool_size = pool_size;
 522                 pp_params.nid       = cpu_to_node(c->cpu);
 523                 pp_params.dev       = c->pdev;
 524                 pp_params.dma_dir   = rq->buff.map_dir;
 525
 526                 /* page_pool can be used even when there is no rq->xdp_prog,
 527                  * given page_pool does not handle DMA mapping there is no
 528                  * required state to clear. And page_pool gracefully handle
 529                  * elevated refcnt.
 530                  */
 531                 rq->page_pool = page_pool_create(&pp_params);
 532                 if (IS_ERR(rq->page_pool)) {
 533                         err = PTR_ERR(rq->page_pool);
 534                         rq->page_pool = NULL;
 535                         goto err_free_by_rq_type;
 536                 }
 537                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 538                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 539         }
 540         if (err)
 541                 goto err_free_by_rq_type;
 542
 543         for (i = 0; i < wq_sz; i++) {
 544                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 545                         struct mlx5e_rx_wqe_ll *wqe =
 546                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 547                         u32 byte_count =
 548                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 549                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 550
 551                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 552                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 553                         wqe->data[0].lkey = rq->mkey_be;
 554                 } else {
 555                         struct mlx5e_rx_wqe_cyc *wqe =
 556                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 557                         int f;
 558
 559                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 560                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 561                                         MLX5_HW_START_PADDING;
 562
 563                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 564                                 wqe->data[f].lkey = rq->mkey_be;
 565                         }
 566                         /* check if num_frags is not a pow of two */
 567                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 568                                 wqe->data[f].byte_count = 0;
 569                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 570                                 wqe->data[f].addr = 0;
 571                         }
 572                 }
 573         }
 574
 575         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 576
 577         switch (params->rx_cq_moderation.cq_period_mode) {
 578         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 579                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 580                 break;
 581         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 582         default:
 583                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 584         }
 585
 586         rq->page_cache.head = 0;
 587         rq->page_cache.tail = 0;
 588
 589         return 0;
 590
 591 err_free_by_rq_type:
 592         switch (rq->wq_type) {
 593         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 594                 kvfree(rq->mpwqe.info);
 595 err_rq_mkey:
 596                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 597 err_rq_drop_page:
 598                 mlx5e_free_mpwqe_rq_drop_page(rq);
 599                 break;
 600         default: /* MLX5_WQ_TYPE_CYCLIC */
 601                 mlx5e_free_di_list(rq);
 602 err_rq_frags:
 603                 kvfree(rq->wqe.frags);
 604         }
 605 err_rq_wq_destroy:
 606         mlx5_wq_destroy(&rq->wq_ctrl);
 607 err_rq_xdp:
 608         xdp_rxq_info_unreg(&rq->xdp_rxq);
 609 err_rq_xdp_prog:
 610         if (params->xdp_prog)
 611                 bpf_prog_put(params->xdp_prog);
 612
 613         return err;
 614 }
 615
 616 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 617 {
 618         struct bpf_prog *old_prog;
 619         int i;
 620
 621         old_prog = rcu_dereference_protected(rq->xdp_prog,
 622                                              lockdep_is_held(&rq->priv->state_lock));
 623         if (old_prog)
 624                 bpf_prog_put(old_prog);
 625
 626         switch (rq->wq_type) {
 627         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 628                 kvfree(rq->mpwqe.info);
 629                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 630                 mlx5e_free_mpwqe_rq_drop_page(rq);
 631                 break;
 632         default: /* MLX5_WQ_TYPE_CYCLIC */
 633                 kvfree(rq->wqe.frags);
 634                 mlx5e_free_di_list(rq);
 635         }
 636
 637         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 638              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 639                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 640
 641                 /* With AF_XDP, page_cache is not used, so this loop is not
 642                  * entered, and it's safe to call mlx5e_page_release_dynamic
 643                  * directly.
 644                  */
 645                 mlx5e_page_release_dynamic(rq, dma_info, false);
 646         }
 647
 648         xdp_rxq_info_unreg(&rq->xdp_rxq);
 649         page_pool_destroy(rq->page_pool);
 650         mlx5_wq_destroy(&rq->wq_ctrl);
 651 }
 652
 653 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 654                            struct mlx5e_rq_param *param)
 655 {
 656         struct mlx5_core_dev *mdev = rq->mdev;
 657
 658         void *in;
 659         void *rqc;
 660         void *wq;
 661         int inlen;
 662         int err;
 663
 664         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 665                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 666         in = kvzalloc(inlen, GFP_KERNEL);
 667         if (!in)
 668                 return -ENOMEM;
 669
 670         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 671         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 672
 673         memcpy(rqc, param->rqc, sizeof(param->rqc));
 674
 675         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 676         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 677         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 678                                                 MLX5_ADAPTER_PAGE_SHIFT);
 679         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 680
 681         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 682                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 683
 684         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 685
 686         kvfree(in);
 687
 688         return err;
 689 }
 690
 691 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 692 {
 693         struct mlx5_core_dev *mdev = rq->mdev;
 694
 695         void *in;
 696         void *rqc;
 697         int inlen;
 698         int err;
 699
 700         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 701         in = kvzalloc(inlen, GFP_KERNEL);
 702         if (!in)
 703                 return -ENOMEM;
 704
 705         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 706                 mlx5e_rqwq_reset(rq);
 707
 708         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 709
 710         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 711         MLX5_SET(rqc, rqc, state, next_state);
 712
 713         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 714
 715         kvfree(in);
 716
 717         return err;
 718 }
 719
 720 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 721 {
 722         struct mlx5_core_dev *mdev = rq->mdev;
 723
 724         void *in;
 725         void *rqc;
 726         int inlen;
 727         int err;
 728
 729         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 730         in = kvzalloc(inlen, GFP_KERNEL);
 731         if (!in)
 732                 return -ENOMEM;
 733
 734         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 735
 736         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 737         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 738                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 739         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 740         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 741
 742         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 743
 744         kvfree(in);
 745
 746         return err;
 747 }
 748
 749 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 750 {
 751         struct mlx5_core_dev *mdev = rq->mdev;
 752         void *in;
 753         void *rqc;
 754         int inlen;
 755         int err;
 756
 757         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 758         in = kvzalloc(inlen, GFP_KERNEL);
 759         if (!in)
 760                 return -ENOMEM;
 761
 762         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 763
 764         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 765         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 766                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 767         MLX5_SET(rqc, rqc, vsd, vsd);
 768         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 769
 770         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 771
 772         kvfree(in);
 773
 774         return err;
 775 }
 776
 777 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 778 {
 779         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 780 }
 781
 782 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 783 {
 784         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 785
 786         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 787
 788         do {
 789                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 790                         return 0;
 791
 792                 msleep(20);
 793         } while (time_before(jiffies, exp_time));
 794
 795         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 796                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 797
 798         mlx5e_reporter_rx_timeout(rq);
 799         return -ETIMEDOUT;
 800 }
 801
 802 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 803 {
 804         struct mlx5_wq_ll *wq;
 805         u16 head;
 806         int i;
 807
 808         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 809                 return;
 810
 811         wq = &rq->mpwqe.wq;
 812         head = wq->head;
 813
 814         /* Outstanding UMR WQEs (in progress) start at wq->head */
 815         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 816                 rq->dealloc_wqe(rq, head);
 817                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 818         }
 819
 820         rq->mpwqe.actual_wq_head = wq->head;
 821         rq->mpwqe.umr_in_progress = 0;
 822         rq->mpwqe.umr_completed = 0;
 823 }
 824
 825 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 826 {
 827         __be16 wqe_ix_be;
 828         u16 wqe_ix;
 829
 830         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 831                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 832
 833                 mlx5e_free_rx_in_progress_descs(rq);
 834
 835                 while (!mlx5_wq_ll_is_empty(wq)) {
 836                         struct mlx5e_rx_wqe_ll *wqe;
 837
 838                         wqe_ix_be = *wq->tail_next;
 839                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 840                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 841                         rq->dealloc_wqe(rq, wqe_ix);
 842                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 843                                        &wqe->next.next_wqe_index);
 844                 }
 845         } else {
 846                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 847
 848                 while (!mlx5_wq_cyc_is_empty(wq)) {
 849                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 850                         rq->dealloc_wqe(rq, wqe_ix);
 851                         mlx5_wq_cyc_pop(wq);
 852                 }
 853         }
 854
 855 }
 856
 857 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 858                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 859                   struct xsk_buff_pool *xsk_pool, struct mlx5e_rq *rq)
 860 {
 861         int err;
 862
 863         err = mlx5e_alloc_rq(c, params, xsk, xsk_pool, param, rq);
 864         if (err)
 865                 return err;
 866
 867         err = mlx5e_create_rq(rq, param);
 868         if (err)
 869                 goto err_free_rq;
 870
 871         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 872         if (err)
 873                 goto err_destroy_rq;
 874
 875         if (mlx5e_is_tls_on(c->priv) && !mlx5_accel_is_ktls_device(c->mdev))
 876                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &c->rq.state); /* must be FPGA */
 877
 878         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 879                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 880
 881         if (params->rx_dim_enabled)
 882                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 883
 884         /* We disable csum_complete when XDP is enabled since
 885          * XDP programs might manipulate packets which will render
 886          * skb->checksum incorrect.
 887          */
 888         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 889                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 890
 891         /* For CQE compression on striding RQ, use stride index provided by
 892          * HW if capability is supported.
 893          */
 894         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
 895             MLX5_CAP_GEN(c->mdev, mini_cqe_resp_stride_index))
 896                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &c->rq.state);
 897
 898         return 0;
 899
 900 err_destroy_rq:
 901         mlx5e_destroy_rq(rq);
 902 err_free_rq:
 903         mlx5e_free_rq(rq);
 904
 905         return err;
 906 }
 907
 908 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 909 {
 910         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 911         mlx5e_trigger_irq(rq->icosq);
 912 }
 913
 914 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 915 {
 916         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 917         synchronize_rcu(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
 918 }
 919
 920 void mlx5e_close_rq(struct mlx5e_rq *rq)
 921 {
 922         cancel_work_sync(&rq->dim.work);
 923         cancel_work_sync(&rq->icosq->recover_work);
 924         cancel_work_sync(&rq->recover_work);
 925         mlx5e_destroy_rq(rq);
 926         mlx5e_free_rx_descs(rq);
 927         mlx5e_free_rq(rq);
 928 }
 929
 930 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 931 {
 932         kvfree(sq->db.xdpi_fifo.xi);
 933         kvfree(sq->db.wqe_info);
 934 }
 935
 936 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 937 {
 938         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 939         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 940         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 941
 942         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 943                                       GFP_KERNEL, numa);
 944         if (!xdpi_fifo->xi)
 945                 return -ENOMEM;
 946
 947         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 948         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 949         xdpi_fifo->mask = dsegs_per_wq - 1;
 950
 951         return 0;
 952 }
 953
 954 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 955 {
 956         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 957         int err;
 958
 959         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 960                                         GFP_KERNEL, numa);
 961         if (!sq->db.wqe_info)
 962                 return -ENOMEM;
 963
 964         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 965         if (err) {
 966                 mlx5e_free_xdpsq_db(sq);
 967                 return err;
 968         }
 969
 970         return 0;
 971 }
 972
 973 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 974                              struct mlx5e_params *params,
 975                              struct xsk_buff_pool *xsk_pool,
 976                              struct mlx5e_sq_param *param,
 977                              struct mlx5e_xdpsq *sq,
 978                              bool is_redirect)
 979 {
 980         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 981         struct mlx5_core_dev *mdev = c->mdev;
 982         struct mlx5_wq_cyc *wq = &sq->wq;
 983         int err;
 984
 985         sq->pdev      = c->pdev;
 986         sq->mkey_be   = c->mkey_be;
 987         sq->channel   = c;
 988         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 989         sq->min_inline_mode = params->tx_min_inline_mode;
 990         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 991         sq->xsk_pool  = xsk_pool;
 992
 993         sq->stats = sq->xsk_pool ?
 994                 &c->priv->channel_stats[c->ix].xsksq :
 995                 is_redirect ?
 996                         &c->priv->channel_stats[c->ix].xdpsq :
 997                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 998
 999         param->wq.db_numa_node = cpu_to_node(c->cpu);
1000         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1001         if (err)
1002                 return err;
1003         wq->db = &wq->db[MLX5_SND_DBR];
1004
1005         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1006         if (err)
1007                 goto err_sq_wq_destroy;
1008
1009         return 0;
1010
1011 err_sq_wq_destroy:
1012         mlx5_wq_destroy(&sq->wq_ctrl);
1013
1014         return err;
1015 }
1016
1017 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1018 {
1019         mlx5e_free_xdpsq_db(sq);
1020         mlx5_wq_destroy(&sq->wq_ctrl);
1021 }
1022
1023 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1024 {
1025         kvfree(sq->db.wqe_info);
1026 }
1027
1028 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1029 {
1030         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1031         size_t size;
1032
1033         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1034         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1035         if (!sq->db.wqe_info)
1036                 return -ENOMEM;
1037
1038         return 0;
1039 }
1040
1041 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1042 {
1043         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1044                                               recover_work);
1045
1046         mlx5e_reporter_icosq_cqe_err(sq);
1047 }
1048
1049 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1050                              struct mlx5e_sq_param *param,
1051                              struct mlx5e_icosq *sq)
1052 {
1053         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1054         struct mlx5_core_dev *mdev = c->mdev;
1055         struct mlx5_wq_cyc *wq = &sq->wq;
1056         int err;
1057
1058         sq->channel   = c;
1059         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1060
1061         param->wq.db_numa_node = cpu_to_node(c->cpu);
1062         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1063         if (err)
1064                 return err;
1065         wq->db = &wq->db[MLX5_SND_DBR];
1066
1067         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1068         if (err)
1069                 goto err_sq_wq_destroy;
1070
1071         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1072
1073         return 0;
1074
1075 err_sq_wq_destroy:
1076         mlx5_wq_destroy(&sq->wq_ctrl);
1077
1078         return err;
1079 }
1080
1081 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1082 {
1083         mlx5e_free_icosq_db(sq);
1084         mlx5_wq_destroy(&sq->wq_ctrl);
1085 }
1086
1087 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1088 {
1089         kvfree(sq->db.wqe_info);
1090         kvfree(sq->db.skb_fifo.fifo);
1091         kvfree(sq->db.dma_fifo);
1092 }
1093
1094 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1095 {
1096         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1097         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1098
1099         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1100                                                    sizeof(*sq->db.dma_fifo)),
1101                                         GFP_KERNEL, numa);
1102         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1103                                                         sizeof(*sq->db.skb_fifo.fifo)),
1104                                         GFP_KERNEL, numa);
1105         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1106                                                    sizeof(*sq->db.wqe_info)),
1107                                         GFP_KERNEL, numa);
1108         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1109                 mlx5e_free_txqsq_db(sq);
1110                 return -ENOMEM;
1111         }
1112
1113         sq->dma_fifo_mask = df_sz - 1;
1114
1115         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1116         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1117         sq->db.skb_fifo.mask = df_sz - 1;
1118
1119         return 0;
1120 }
1121
1122 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1123                              int txq_ix,
1124                              struct mlx5e_params *params,
1125                              struct mlx5e_sq_param *param,
1126                              struct mlx5e_txqsq *sq,
1127                              int tc)
1128 {
1129         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1130         struct mlx5_core_dev *mdev = c->mdev;
1131         struct mlx5_wq_cyc *wq = &sq->wq;
1132         int err;
1133
1134         sq->pdev      = c->pdev;
1135         sq->tstamp    = c->tstamp;
1136         sq->clock     = &mdev->clock;
1137         sq->mkey_be   = c->mkey_be;
1138         sq->netdev    = c->netdev;
1139         sq->mdev      = c->mdev;
1140         sq->priv      = c->priv;
1141         sq->ch_ix     = c->ix;
1142         sq->txq_ix    = txq_ix;
1143         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1144         sq->min_inline_mode = params->tx_min_inline_mode;
1145         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1146         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1147         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1148         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1149                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1150         if (MLX5_IPSEC_DEV(c->priv->mdev))
1151                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1152         if (mlx5_accel_is_tls_device(c->priv->mdev))
1153                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1154         if (param->is_mpw)
1155                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1156         sq->stop_room = param->stop_room;
1157
1158         param->wq.db_numa_node = cpu_to_node(c->cpu);
1159         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1160         if (err)
1161                 return err;
1162         wq->db    = &wq->db[MLX5_SND_DBR];
1163
1164         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1165         if (err)
1166                 goto err_sq_wq_destroy;
1167
1168         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1169         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1170
1171         return 0;
1172
1173 err_sq_wq_destroy:
1174         mlx5_wq_destroy(&sq->wq_ctrl);
1175
1176         return err;
1177 }
1178
1179 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1180 {
1181         mlx5e_free_txqsq_db(sq);
1182         mlx5_wq_destroy(&sq->wq_ctrl);
1183 }
1184
1185 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1186                            struct mlx5e_sq_param *param,
1187                            struct mlx5e_create_sq_param *csp,
1188                            u32 *sqn)
1189 {
1190         void *in;
1191         void *sqc;
1192         void *wq;
1193         int inlen;
1194         int err;
1195
1196         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1197                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1198         in = kvzalloc(inlen, GFP_KERNEL);
1199         if (!in)
1200                 return -ENOMEM;
1201
1202         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1203         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1204
1205         memcpy(sqc, param->sqc, sizeof(param->sqc));
1206         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1207         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1208         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1209         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1210
1211         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1212                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1213
1214         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1215         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1216
1217         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1218         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1219         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1220                                           MLX5_ADAPTER_PAGE_SHIFT);
1221         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1222
1223         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1224                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1225
1226         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1227
1228         kvfree(in);
1229
1230         return err;
1231 }
1232
1233 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1234                     struct mlx5e_modify_sq_param *p)
1235 {
1236         void *in;
1237         void *sqc;
1238         int inlen;
1239         int err;
1240
1241         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1242         in = kvzalloc(inlen, GFP_KERNEL);
1243         if (!in)
1244                 return -ENOMEM;
1245
1246         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1247
1248         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1249         MLX5_SET(sqc, sqc, state, p->next_state);
1250         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1251                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1252                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1253         }
1254
1255         err = mlx5_core_modify_sq(mdev, sqn, in);
1256
1257         kvfree(in);
1258
1259         return err;
1260 }
1261
1262 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1263 {
1264         mlx5_core_destroy_sq(mdev, sqn);
1265 }
1266
1267 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1268                         struct mlx5e_sq_param *param,
1269                         struct mlx5e_create_sq_param *csp,
1270                         u32 *sqn)
1271 {
1272         struct mlx5e_modify_sq_param msp = {0};
1273         int err;
1274
1275         err = mlx5e_create_sq(mdev, param, csp, sqn);
1276         if (err)
1277                 return err;
1278
1279         msp.curr_state = MLX5_SQC_STATE_RST;
1280         msp.next_state = MLX5_SQC_STATE_RDY;
1281         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1282         if (err)
1283                 mlx5e_destroy_sq(mdev, *sqn);
1284
1285         return err;
1286 }
1287
1288 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1289                                 struct mlx5e_txqsq *sq, u32 rate);
1290
1291 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1292                             u32 tisn,
1293                             int txq_ix,
1294                             struct mlx5e_params *params,
1295                             struct mlx5e_sq_param *param,
1296                             struct mlx5e_txqsq *sq,
1297                             int tc)
1298 {
1299         struct mlx5e_create_sq_param csp = {};
1300         u32 tx_rate;
1301         int err;
1302
1303         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1304         if (err)
1305                 return err;
1306
1307         csp.tisn            = tisn;
1308         csp.tis_lst_sz      = 1;
1309         csp.cqn             = sq->cq.mcq.cqn;
1310         csp.wq_ctrl         = &sq->wq_ctrl;
1311         csp.min_inline_mode = sq->min_inline_mode;
1312         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1313         if (err)
1314                 goto err_free_txqsq;
1315
1316         tx_rate = c->priv->tx_rates[sq->txq_ix];
1317         if (tx_rate)
1318                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1319
1320         if (params->tx_dim_enabled)
1321                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1322
1323         return 0;
1324
1325 err_free_txqsq:
1326         mlx5e_free_txqsq(sq);
1327
1328         return err;
1329 }
1330
1331 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1332 {
1333         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1334         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1335         netdev_tx_reset_queue(sq->txq);
1336         netif_tx_start_queue(sq->txq);
1337 }
1338
1339 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1340 {
1341         __netif_tx_lock_bh(txq);
1342         netif_tx_stop_queue(txq);
1343         __netif_tx_unlock_bh(txq);
1344 }
1345
1346 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1347 {
1348         struct mlx5_wq_cyc *wq = &sq->wq;
1349
1350         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351         synchronize_rcu(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1352
1353         mlx5e_tx_disable_queue(sq->txq);
1354
1355         /* last doorbell out, godspeed .. */
1356         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1357                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1358                 struct mlx5e_tx_wqe *nop;
1359
1360                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1361                         .num_wqebbs = 1,
1362                 };
1363
1364                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1365                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1366         }
1367 }
1368
1369 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1370 {
1371         struct mlx5_core_dev *mdev = sq->mdev;
1372         struct mlx5_rate_limit rl = {0};
1373
1374         cancel_work_sync(&sq->dim.work);
1375         cancel_work_sync(&sq->recover_work);
1376         mlx5e_destroy_sq(mdev, sq->sqn);
1377         if (sq->rate_limit) {
1378                 rl.rate = sq->rate_limit;
1379                 mlx5_rl_remove_rate(mdev, &rl);
1380         }
1381         mlx5e_free_txqsq_descs(sq);
1382         mlx5e_free_txqsq(sq);
1383 }
1384
1385 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1386 {
1387         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1388                                               recover_work);
1389
1390         mlx5e_reporter_tx_err_cqe(sq);
1391 }
1392
1393 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1394                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1395 {
1396         struct mlx5e_create_sq_param csp = {};
1397         int err;
1398
1399         err = mlx5e_alloc_icosq(c, param, sq);
1400         if (err)
1401                 return err;
1402
1403         csp.cqn             = sq->cq.mcq.cqn;
1404         csp.wq_ctrl         = &sq->wq_ctrl;
1405         csp.min_inline_mode = params->tx_min_inline_mode;
1406         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1407         if (err)
1408                 goto err_free_icosq;
1409
1410         return 0;
1411
1412 err_free_icosq:
1413         mlx5e_free_icosq(sq);
1414
1415         return err;
1416 }
1417
1418 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1419 {
1420         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1421 }
1422
1423 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1424 {
1425         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1426         synchronize_rcu(); /* Sync with NAPI. */
1427 }
1428
1429 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1430 {
1431         struct mlx5e_channel *c = sq->channel;
1432
1433         mlx5e_destroy_sq(c->mdev, sq->sqn);
1434         mlx5e_free_icosq_descs(sq);
1435         mlx5e_free_icosq(sq);
1436 }
1437
1438 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1439                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1440                      struct mlx5e_xdpsq *sq, bool is_redirect)
1441 {
1442         struct mlx5e_create_sq_param csp = {};
1443         int err;
1444
1445         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1446         if (err)
1447                 return err;
1448
1449         csp.tis_lst_sz      = 1;
1450         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1451         csp.cqn             = sq->cq.mcq.cqn;
1452         csp.wq_ctrl         = &sq->wq_ctrl;
1453         csp.min_inline_mode = sq->min_inline_mode;
1454         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1455         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1456         if (err)
1457                 goto err_free_xdpsq;
1458
1459         mlx5e_set_xmit_fp(sq, param->is_mpw);
1460
1461         if (!param->is_mpw) {
1462                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1463                 unsigned int inline_hdr_sz = 0;
1464                 int i;
1465
1466                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1467                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1468                         ds_cnt++;
1469                 }
1470
1471                 /* Pre initialize fixed WQE fields */
1472                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1473                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1474                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1475                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1476                         struct mlx5_wqe_data_seg *dseg;
1477
1478                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1479                                 .num_wqebbs = 1,
1480                                 .num_pkts   = 1,
1481                         };
1482
1483                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1484                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1485
1486                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1487                         dseg->lkey = sq->mkey_be;
1488                 }
1489         }
1490
1491         return 0;
1492
1493 err_free_xdpsq:
1494         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1495         mlx5e_free_xdpsq(sq);
1496
1497         return err;
1498 }
1499
1500 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1501 {
1502         struct mlx5e_channel *c = sq->channel;
1503
1504         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1505         synchronize_rcu(); /* Sync with NAPI. */
1506
1507         mlx5e_destroy_sq(c->mdev, sq->sqn);
1508         mlx5e_free_xdpsq_descs(sq);
1509         mlx5e_free_xdpsq(sq);
1510 }
1511
1512 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1513                                  struct mlx5e_cq_param *param,
1514                                  struct mlx5e_cq *cq)
1515 {
1516         struct mlx5_core_dev *mdev = priv->mdev;
1517         struct mlx5_core_cq *mcq = &cq->mcq;
1518         int eqn_not_used;
1519         unsigned int irqn;
1520         int err;
1521         u32 i;
1522
1523         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1524         if (err)
1525                 return err;
1526
1527         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1528                                &cq->wq_ctrl);
1529         if (err)
1530                 return err;
1531
1532         mcq->cqe_sz     = 64;
1533         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1534         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1535         *mcq->set_ci_db = 0;
1536         *mcq->arm_db    = 0;
1537         mcq->vector     = param->eq_ix;
1538         mcq->comp       = mlx5e_completion_event;
1539         mcq->event      = mlx5e_cq_error_event;
1540         mcq->irqn       = irqn;
1541
1542         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1543                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1544
1545                 cqe->op_own = 0xf1;
1546         }
1547
1548         cq->mdev = mdev;
1549         cq->netdev = priv->netdev;
1550         cq->priv = priv;
1551
1552         return 0;
1553 }
1554
1555 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1556                           struct mlx5e_cq_param *param,
1557                           struct mlx5e_create_cq_param *ccp,
1558                           struct mlx5e_cq *cq)
1559 {
1560         int err;
1561
1562         param->wq.buf_numa_node = ccp->node;
1563         param->wq.db_numa_node  = ccp->node;
1564         param->eq_ix            = ccp->ix;
1565
1566         err = mlx5e_alloc_cq_common(priv, param, cq);
1567
1568         cq->napi     = ccp->napi;
1569         cq->ch_stats = ccp->ch_stats;
1570
1571         return err;
1572 }
1573
1574 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1575 {
1576         mlx5_wq_destroy(&cq->wq_ctrl);
1577 }
1578
1579 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1580 {
1581         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1582         struct mlx5_core_dev *mdev = cq->mdev;
1583         struct mlx5_core_cq *mcq = &cq->mcq;
1584
1585         void *in;
1586         void *cqc;
1587         int inlen;
1588         unsigned int irqn_not_used;
1589         int eqn;
1590         int err;
1591
1592         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1593         if (err)
1594                 return err;
1595
1596         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1597                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1598         in = kvzalloc(inlen, GFP_KERNEL);
1599         if (!in)
1600                 return -ENOMEM;
1601
1602         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1603
1604         memcpy(cqc, param->cqc, sizeof(param->cqc));
1605
1606         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1607                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1608
1609         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1610         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1611         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1612         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1613                                             MLX5_ADAPTER_PAGE_SHIFT);
1614         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1615
1616         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1617
1618         kvfree(in);
1619
1620         if (err)
1621                 return err;
1622
1623         mlx5e_cq_arm(cq);
1624
1625         return 0;
1626 }
1627
1628 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1629 {
1630         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1631 }
1632
1633 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1634                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1635                   struct mlx5e_cq *cq)
1636 {
1637         struct mlx5_core_dev *mdev = priv->mdev;
1638         int err;
1639
1640         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1641         if (err)
1642                 return err;
1643
1644         err = mlx5e_create_cq(cq, param);
1645         if (err)
1646                 goto err_free_cq;
1647
1648         if (MLX5_CAP_GEN(mdev, cq_moderation))
1649                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1650         return 0;
1651
1652 err_free_cq:
1653         mlx5e_free_cq(cq);
1654
1655         return err;
1656 }
1657
1658 void mlx5e_close_cq(struct mlx5e_cq *cq)
1659 {
1660         mlx5e_destroy_cq(cq);
1661         mlx5e_free_cq(cq);
1662 }
1663
1664 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1665                              struct mlx5e_params *params,
1666                              struct mlx5e_create_cq_param *ccp,
1667                              struct mlx5e_channel_param *cparam)
1668 {
1669         int err;
1670         int tc;
1671
1672         for (tc = 0; tc < c->num_tc; tc++) {
1673                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1674                                     ccp, &c->sq[tc].cq);
1675                 if (err)
1676                         goto err_close_tx_cqs;
1677         }
1678
1679         return 0;
1680
1681 err_close_tx_cqs:
1682         for (tc--; tc >= 0; tc--)
1683                 mlx5e_close_cq(&c->sq[tc].cq);
1684
1685         return err;
1686 }
1687
1688 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1689 {
1690         int tc;
1691
1692         for (tc = 0; tc < c->num_tc; tc++)
1693                 mlx5e_close_cq(&c->sq[tc].cq);
1694 }
1695
1696 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1697                           struct mlx5e_params *params,
1698                           struct mlx5e_channel_param *cparam)
1699 {
1700         int err, tc;
1701
1702         for (tc = 0; tc < params->num_tc; tc++) {
1703                 int txq_ix = c->ix + tc * params->num_channels;
1704
1705                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1706                                        params, &cparam->txq_sq, &c->sq[tc], tc);
1707                 if (err)
1708                         goto err_close_sqs;
1709         }
1710
1711         return 0;
1712
1713 err_close_sqs:
1714         for (tc--; tc >= 0; tc--)
1715                 mlx5e_close_txqsq(&c->sq[tc]);
1716
1717         return err;
1718 }
1719
1720 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1721 {
1722         int tc;
1723
1724         for (tc = 0; tc < c->num_tc; tc++)
1725                 mlx5e_close_txqsq(&c->sq[tc]);
1726 }
1727
1728 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1729                                 struct mlx5e_txqsq *sq, u32 rate)
1730 {
1731         struct mlx5e_priv *priv = netdev_priv(dev);
1732         struct mlx5_core_dev *mdev = priv->mdev;
1733         struct mlx5e_modify_sq_param msp = {0};
1734         struct mlx5_rate_limit rl = {0};
1735         u16 rl_index = 0;
1736         int err;
1737
1738         if (rate == sq->rate_limit)
1739                 /* nothing to do */
1740                 return 0;
1741
1742         if (sq->rate_limit) {
1743                 rl.rate = sq->rate_limit;
1744                 /* remove current rl index to free space to next ones */
1745                 mlx5_rl_remove_rate(mdev, &rl);
1746         }
1747
1748         sq->rate_limit = 0;
1749
1750         if (rate) {
1751                 rl.rate = rate;
1752                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1753                 if (err) {
1754                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1755                                    rate, err);
1756                         return err;
1757                 }
1758         }
1759
1760         msp.curr_state = MLX5_SQC_STATE_RDY;
1761         msp.next_state = MLX5_SQC_STATE_RDY;
1762         msp.rl_index   = rl_index;
1763         msp.rl_update  = true;
1764         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1765         if (err) {
1766                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1767                            rate, err);
1768                 /* remove the rate from the table */
1769                 if (rate)
1770                         mlx5_rl_remove_rate(mdev, &rl);
1771                 return err;
1772         }
1773
1774         sq->rate_limit = rate;
1775         return 0;
1776 }
1777
1778 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1779 {
1780         struct mlx5e_priv *priv = netdev_priv(dev);
1781         struct mlx5_core_dev *mdev = priv->mdev;
1782         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1783         int err = 0;
1784
1785         if (!mlx5_rl_is_supported(mdev)) {
1786                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1787                 return -EINVAL;
1788         }
1789
1790         /* rate is given in Mb/sec, HW config is in Kb/sec */
1791         rate = rate << 10;
1792
1793         /* Check whether rate in valid range, 0 is always valid */
1794         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1795                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1796                 return -ERANGE;
1797         }
1798
1799         mutex_lock(&priv->state_lock);
1800         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1801                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1802         if (!err)
1803                 priv->tx_rates[index] = rate;
1804         mutex_unlock(&priv->state_lock);
1805
1806         return err;
1807 }
1808
1809 void mlx5e_build_create_cq_param(struct mlx5e_create_cq_param *ccp, struct mlx5e_channel *c)
1810 {
1811         *ccp = (struct mlx5e_create_cq_param) {
1812                 .napi = &c->napi,
1813                 .ch_stats = c->stats,
1814                 .node = cpu_to_node(c->cpu),
1815                 .ix = c->ix,
1816         };
1817 }
1818
1819 static int mlx5e_open_queues(struct mlx5e_channel *c,
1820                              struct mlx5e_params *params,
1821                              struct mlx5e_channel_param *cparam)
1822 {
1823         struct dim_cq_moder icocq_moder = {0, 0};
1824         struct mlx5e_create_cq_param ccp;
1825         int err;
1826
1827         mlx5e_build_create_cq_param(&ccp, c);
1828
1829         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1830                             &c->async_icosq.cq);
1831         if (err)
1832                 return err;
1833
1834         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1835                             &c->icosq.cq);
1836         if (err)
1837                 goto err_close_async_icosq_cq;
1838
1839         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1840         if (err)
1841                 goto err_close_icosq_cq;
1842
1843         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1844                             &c->xdpsq.cq);
1845         if (err)
1846                 goto err_close_tx_cqs;
1847
1848         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1849                             &c->rq.cq);
1850         if (err)
1851                 goto err_close_xdp_tx_cqs;
1852
1853         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1854                                      &ccp, &c->rq_xdpsq.cq) : 0;
1855         if (err)
1856                 goto err_close_rx_cq;
1857
1858         napi_enable(&c->napi);
1859
1860         spin_lock_init(&c->async_icosq_lock);
1861
1862         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1863         if (err)
1864                 goto err_disable_napi;
1865
1866         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1867         if (err)
1868                 goto err_close_async_icosq;
1869
1870         err = mlx5e_open_sqs(c, params, cparam);
1871         if (err)
1872                 goto err_close_icosq;
1873
1874         if (c->xdp) {
1875                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1876                                        &c->rq_xdpsq, false);
1877                 if (err)
1878                         goto err_close_sqs;
1879         }
1880
1881         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1882         if (err)
1883                 goto err_close_xdp_sq;
1884
1885         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1886         if (err)
1887                 goto err_close_rq;
1888
1889         return 0;
1890
1891 err_close_rq:
1892         mlx5e_close_rq(&c->rq);
1893
1894 err_close_xdp_sq:
1895         if (c->xdp)
1896                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1897
1898 err_close_sqs:
1899         mlx5e_close_sqs(c);
1900
1901 err_close_icosq:
1902         mlx5e_close_icosq(&c->icosq);
1903
1904 err_close_async_icosq:
1905         mlx5e_close_icosq(&c->async_icosq);
1906
1907 err_disable_napi:
1908         napi_disable(&c->napi);
1909
1910         if (c->xdp)
1911                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1912
1913 err_close_rx_cq:
1914         mlx5e_close_cq(&c->rq.cq);
1915
1916 err_close_xdp_tx_cqs:
1917         mlx5e_close_cq(&c->xdpsq.cq);
1918
1919 err_close_tx_cqs:
1920         mlx5e_close_tx_cqs(c);
1921
1922 err_close_icosq_cq:
1923         mlx5e_close_cq(&c->icosq.cq);
1924
1925 err_close_async_icosq_cq:
1926         mlx5e_close_cq(&c->async_icosq.cq);
1927
1928         return err;
1929 }
1930
1931 static void mlx5e_close_queues(struct mlx5e_channel *c)
1932 {
1933         mlx5e_close_xdpsq(&c->xdpsq);
1934         mlx5e_close_rq(&c->rq);
1935         if (c->xdp)
1936                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1937         mlx5e_close_sqs(c);
1938         mlx5e_close_icosq(&c->icosq);
1939         mlx5e_close_icosq(&c->async_icosq);
1940         napi_disable(&c->napi);
1941         if (c->xdp)
1942                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1943         mlx5e_close_cq(&c->rq.cq);
1944         mlx5e_close_cq(&c->xdpsq.cq);
1945         mlx5e_close_tx_cqs(c);
1946         mlx5e_close_cq(&c->icosq.cq);
1947         mlx5e_close_cq(&c->async_icosq.cq);
1948 }
1949
1950 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1951 {
1952         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1953
1954         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1955 }
1956
1957 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1958                               struct mlx5e_params *params,
1959                               struct mlx5e_channel_param *cparam,
1960                               struct xsk_buff_pool *xsk_pool,
1961                               struct mlx5e_channel **cp)
1962 {
1963         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1964         struct net_device *netdev = priv->netdev;
1965         struct mlx5e_xsk_param xsk;
1966         struct mlx5e_channel *c;
1967         unsigned int irq;
1968         int err;
1969         int eqn;
1970
1971         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1972         if (err)
1973                 return err;
1974
1975         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1976         if (!c)
1977                 return -ENOMEM;
1978
1979         c->priv     = priv;
1980         c->mdev     = priv->mdev;
1981         c->tstamp   = &priv->tstamp;
1982         c->ix       = ix;
1983         c->cpu      = cpu;
1984         c->pdev     = mlx5_core_dma_dev(priv->mdev);
1985         c->netdev   = priv->netdev;
1986         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1987         c->num_tc   = params->num_tc;
1988         c->xdp      = !!params->xdp_prog;
1989         c->stats    = &priv->channel_stats[ix].ch;
1990         c->aff_mask = irq_get_effective_affinity_mask(irq);
1991         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1992
1993         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1994
1995         err = mlx5e_open_queues(c, params, cparam);
1996         if (unlikely(err))
1997                 goto err_napi_del;
1998
1999         if (xsk_pool) {
2000                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2001                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2002                 if (unlikely(err))
2003                         goto err_close_queues;
2004         }
2005
2006         *cp = c;
2007
2008         return 0;
2009
2010 err_close_queues:
2011         mlx5e_close_queues(c);
2012
2013 err_napi_del:
2014         netif_napi_del(&c->napi);
2015
2016         kvfree(c);
2017
2018         return err;
2019 }
2020
2021 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2022 {
2023         int tc;
2024
2025         for (tc = 0; tc < c->num_tc; tc++)
2026                 mlx5e_activate_txqsq(&c->sq[tc]);
2027         mlx5e_activate_icosq(&c->icosq);
2028         mlx5e_activate_icosq(&c->async_icosq);
2029         mlx5e_activate_rq(&c->rq);
2030
2031         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2032                 mlx5e_activate_xsk(c);
2033 }
2034
2035 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2036 {
2037         int tc;
2038
2039         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2040                 mlx5e_deactivate_xsk(c);
2041
2042         mlx5e_deactivate_rq(&c->rq);
2043         mlx5e_deactivate_icosq(&c->async_icosq);
2044         mlx5e_deactivate_icosq(&c->icosq);
2045         for (tc = 0; tc < c->num_tc; tc++)
2046                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2047 }
2048
2049 static void mlx5e_close_channel(struct mlx5e_channel *c)
2050 {
2051         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2052                 mlx5e_close_xsk(c);
2053         mlx5e_close_queues(c);
2054         netif_napi_del(&c->napi);
2055
2056         kvfree(c);
2057 }
2058
2059 #define DEFAULT_FRAG_SIZE (2048)
2060
2061 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2062                                       struct mlx5e_params *params,
2063                                       struct mlx5e_xsk_param *xsk,
2064                                       struct mlx5e_rq_frags_info *info)
2065 {
2066         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2067         int frag_size_max = DEFAULT_FRAG_SIZE;
2068         u32 buf_size = 0;
2069         int i;
2070
2071 #ifdef CONFIG_MLX5_EN_IPSEC
2072         if (MLX5_IPSEC_DEV(mdev))
2073                 byte_count += MLX5E_METADATA_ETHER_LEN;
2074 #endif
2075
2076         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2077                 int frag_stride;
2078
2079                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2080                 frag_stride = roundup_pow_of_two(frag_stride);
2081
2082                 info->arr[0].frag_size = byte_count;
2083                 info->arr[0].frag_stride = frag_stride;
2084                 info->num_frags = 1;
2085                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2086                 goto out;
2087         }
2088
2089         if (byte_count > PAGE_SIZE +
2090             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2091                 frag_size_max = PAGE_SIZE;
2092
2093         i = 0;
2094         while (buf_size < byte_count) {
2095                 int frag_size = byte_count - buf_size;
2096
2097                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2098                         frag_size = min(frag_size, frag_size_max);
2099
2100                 info->arr[i].frag_size = frag_size;
2101                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2102
2103                 buf_size += frag_size;
2104                 i++;
2105         }
2106         info->num_frags = i;
2107         /* number of different wqes sharing a page */
2108         info->wqe_bulk = 1 + (info->num_frags % 2);
2109
2110 out:
2111         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2112         info->log_num_frags = order_base_2(info->num_frags);
2113 }
2114
2115 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2116 {
2117         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2118
2119         switch (wq_type) {
2120         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2121                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2122                 break;
2123         default: /* MLX5_WQ_TYPE_CYCLIC */
2124                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2125         }
2126
2127         return order_base_2(sz);
2128 }
2129
2130 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2131 {
2132         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2133
2134         return MLX5_GET(wq, wq, log_wq_sz);
2135 }
2136
2137 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2138                           struct mlx5e_params *params,
2139                           struct mlx5e_xsk_param *xsk,
2140                           struct mlx5e_rq_param *param)
2141 {
2142         struct mlx5_core_dev *mdev = priv->mdev;
2143         void *rqc = param->rqc;
2144         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2145         int ndsegs = 1;
2146
2147         switch (params->rq_wq_type) {
2148         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2149                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2150                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2151                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2152                 MLX5_SET(wq, wq, log_wqe_stride_size,
2153                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2154                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2155                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2156                 break;
2157         default: /* MLX5_WQ_TYPE_CYCLIC */
2158                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2159                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2160                 ndsegs = param->frags_info.num_frags;
2161         }
2162
2163         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2164         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2165         MLX5_SET(wq, wq, log_wq_stride,
2166                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2167         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2168         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2169         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2170         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2171
2172         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2173         mlx5e_build_rx_cq_param(priv, params, xsk, &param->cqp);
2174 }
2175
2176 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2177                                       struct mlx5e_rq_param *param)
2178 {
2179         struct mlx5_core_dev *mdev = priv->mdev;
2180         void *rqc = param->rqc;
2181         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2182
2183         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2184         MLX5_SET(wq, wq, log_wq_stride,
2185                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2186         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2187
2188         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2189 }
2190
2191 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2192                                  struct mlx5e_sq_param *param)
2193 {
2194         void *sqc = param->sqc;
2195         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2196
2197         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2198         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2199
2200         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(priv->mdev));
2201 }
2202
2203 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2204                                  struct mlx5e_params *params,
2205                                  struct mlx5e_sq_param *param)
2206 {
2207         void *sqc = param->sqc;
2208         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2209         bool allow_swp;
2210
2211         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2212                     !!MLX5_IPSEC_DEV(priv->mdev);
2213         mlx5e_build_sq_param_common(priv, param);
2214         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2215         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2216         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE);
2217         param->stop_room = mlx5e_calc_sq_stop_room(priv->mdev, params);
2218         mlx5e_build_tx_cq_param(priv, params, &param->cqp);
2219 }
2220
2221 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2222                                         struct mlx5e_cq_param *param)
2223 {
2224         void *cqc = param->cqc;
2225
2226         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2227         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2228                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2229 }
2230
2231 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2232                              struct mlx5e_params *params,
2233                              struct mlx5e_xsk_param *xsk,
2234                              struct mlx5e_cq_param *param)
2235 {
2236         struct mlx5_core_dev *mdev = priv->mdev;
2237         bool hw_stridx = false;
2238         void *cqc = param->cqc;
2239         u8 log_cq_size;
2240
2241         switch (params->rq_wq_type) {
2242         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2243                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2244                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2245                 hw_stridx = MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index);
2246                 break;
2247         default: /* MLX5_WQ_TYPE_CYCLIC */
2248                 log_cq_size = params->log_rq_mtu_frames;
2249         }
2250
2251         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2252         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2253                 MLX5_SET(cqc, cqc, mini_cqe_res_format, hw_stridx ?
2254                          MLX5_CQE_FORMAT_CSUM_STRIDX : MLX5_CQE_FORMAT_CSUM);
2255                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2256         }
2257
2258         mlx5e_build_common_cq_param(priv, param);
2259         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2260 }
2261
2262 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2263                              struct mlx5e_params *params,
2264                              struct mlx5e_cq_param *param)
2265 {
2266         void *cqc = param->cqc;
2267
2268         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2269
2270         mlx5e_build_common_cq_param(priv, param);
2271         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2272 }
2273
2274 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2275                               u8 log_wq_size,
2276                               struct mlx5e_cq_param *param)
2277 {
2278         void *cqc = param->cqc;
2279
2280         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2281
2282         mlx5e_build_common_cq_param(priv, param);
2283
2284         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2285 }
2286
2287 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2288                              u8 log_wq_size,
2289                              struct mlx5e_sq_param *param)
2290 {
2291         void *sqc = param->sqc;
2292         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2293
2294         mlx5e_build_sq_param_common(priv, param);
2295
2296         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2297         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2298         mlx5e_build_ico_cq_param(priv, log_wq_size, &param->cqp);
2299 }
2300
2301 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2302                              struct mlx5e_params *params,
2303                              struct mlx5e_sq_param *param)
2304 {
2305         void *sqc = param->sqc;
2306         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2307
2308         mlx5e_build_sq_param_common(priv, param);
2309         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2310         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2311         mlx5e_build_tx_cq_param(priv, params, &param->cqp);
2312 }
2313
2314 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2315                                       struct mlx5e_rq_param *rqp)
2316 {
2317         switch (params->rq_wq_type) {
2318         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2319                 return order_base_2(MLX5E_UMR_WQEBBS) +
2320                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2321         default: /* MLX5_WQ_TYPE_CYCLIC */
2322                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2323         }
2324 }
2325
2326 static u8 mlx5e_build_async_icosq_log_wq_sz(struct net_device *netdev)
2327 {
2328         if (netdev->hw_features & NETIF_F_HW_TLS_RX)
2329                 return MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2330
2331         return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2332 }
2333
2334 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2335                                       struct mlx5e_params *params,
2336                                       struct mlx5e_channel_param *cparam)
2337 {
2338         u8 icosq_log_wq_sz, async_icosq_log_wq_sz;
2339
2340         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2341
2342         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2343         async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(priv->netdev);
2344
2345         mlx5e_build_sq_param(priv, params, &cparam->txq_sq);
2346         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2347         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2348         mlx5e_build_icosq_param(priv, async_icosq_log_wq_sz, &cparam->async_icosq);
2349 }
2350
2351 int mlx5e_open_channels(struct mlx5e_priv *priv,
2352                         struct mlx5e_channels *chs)
2353 {
2354         struct mlx5e_channel_param *cparam;
2355         int err = -ENOMEM;
2356         int i;
2357
2358         chs->num = chs->params.num_channels;
2359
2360         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2361         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2362         if (!chs->c || !cparam)
2363                 goto err_free;
2364
2365         mlx5e_build_channel_param(priv, &chs->params, cparam);
2366         for (i = 0; i < chs->num; i++) {
2367                 struct xsk_buff_pool *xsk_pool = NULL;
2368
2369                 if (chs->params.xdp_prog)
2370                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2371
2372                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2373                 if (err)
2374                         goto err_close_channels;
2375         }
2376
2377         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS)) {
2378                 err = mlx5e_port_ptp_open(priv, &chs->params, chs->c[0]->lag_port,
2379                                           &chs->port_ptp);
2380                 if (err)
2381                         goto err_close_channels;
2382         }
2383
2384         mlx5e_health_channels_update(priv);
2385         kvfree(cparam);
2386         return 0;
2387
2388 err_close_channels:
2389         for (i--; i >= 0; i--)
2390                 mlx5e_close_channel(chs->c[i]);
2391
2392 err_free:
2393         kfree(chs->c);
2394         kvfree(cparam);
2395         chs->num = 0;
2396         return err;
2397 }
2398
2399 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2400 {
2401         int i;
2402
2403         for (i = 0; i < chs->num; i++)
2404                 mlx5e_activate_channel(chs->c[i]);
2405
2406         if (chs->port_ptp)
2407                 mlx5e_ptp_activate_channel(chs->port_ptp);
2408 }
2409
2410 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2411
2412 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2413 {
2414         int err = 0;
2415         int i;
2416
2417         for (i = 0; i < chs->num; i++) {
2418                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2419
2420                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2421
2422                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2423                  * doesn't provide any Fill Ring entries at the setup stage.
2424                  */
2425         }
2426
2427         return err ? -ETIMEDOUT : 0;
2428 }
2429
2430 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2431 {
2432         int i;
2433
2434         if (chs->port_ptp)
2435                 mlx5e_ptp_deactivate_channel(chs->port_ptp);
2436
2437         for (i = 0; i < chs->num; i++)
2438                 mlx5e_deactivate_channel(chs->c[i]);
2439 }
2440
2441 void mlx5e_close_channels(struct mlx5e_channels *chs)
2442 {
2443         int i;
2444
2445         if (chs->port_ptp)
2446                 mlx5e_port_ptp_close(chs->port_ptp);
2447
2448         for (i = 0; i < chs->num; i++)
2449                 mlx5e_close_channel(chs->c[i]);
2450
2451         kfree(chs->c);
2452         chs->num = 0;
2453 }
2454
2455 static int
2456 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2457 {
2458         struct mlx5_core_dev *mdev = priv->mdev;
2459         void *rqtc;
2460         int inlen;
2461         int err;
2462         u32 *in;
2463         int i;
2464
2465         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2466         in = kvzalloc(inlen, GFP_KERNEL);
2467         if (!in)
2468                 return -ENOMEM;
2469
2470         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2471
2472         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2473         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2474
2475         for (i = 0; i < sz; i++)
2476                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2477
2478         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2479         if (!err)
2480                 rqt->enabled = true;
2481
2482         kvfree(in);
2483         return err;
2484 }
2485
2486 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2487 {
2488         rqt->enabled = false;
2489         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2490 }
2491
2492 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2493 {
2494         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2495         int err;
2496
2497         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2498         if (err)
2499                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2500         return err;
2501 }
2502
2503 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2504 {
2505         int err;
2506         int ix;
2507
2508         for (ix = 0; ix < priv->max_nch; ix++) {
2509                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2510                 if (unlikely(err))
2511                         goto err_destroy_rqts;
2512         }
2513
2514         return 0;
2515
2516 err_destroy_rqts:
2517         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2518         for (ix--; ix >= 0; ix--)
2519                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2520
2521         return err;
2522 }
2523
2524 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2525 {
2526         int i;
2527
2528         for (i = 0; i < priv->max_nch; i++)
2529                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2530 }
2531
2532 static int mlx5e_rx_hash_fn(int hfunc)
2533 {
2534         return (hfunc == ETH_RSS_HASH_TOP) ?
2535                MLX5_RX_HASH_FN_TOEPLITZ :
2536                MLX5_RX_HASH_FN_INVERTED_XOR8;
2537 }
2538
2539 int mlx5e_bits_invert(unsigned long a, int size)
2540 {
2541         int inv = 0;
2542         int i;
2543
2544         for (i = 0; i < size; i++)
2545                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2546
2547         return inv;
2548 }
2549
2550 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2551                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2552 {
2553         int i;
2554
2555         for (i = 0; i < sz; i++) {
2556                 u32 rqn;
2557
2558                 if (rrp.is_rss) {
2559                         int ix = i;
2560
2561                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2562                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2563
2564                         ix = priv->rss_params.indirection_rqt[ix];
2565                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2566                 } else {
2567                         rqn = rrp.rqn;
2568                 }
2569                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2570         }
2571 }
2572
2573 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2574                        struct mlx5e_redirect_rqt_param rrp)
2575 {
2576         struct mlx5_core_dev *mdev = priv->mdev;
2577         void *rqtc;
2578         int inlen;
2579         u32 *in;
2580         int err;
2581
2582         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2583         in = kvzalloc(inlen, GFP_KERNEL);
2584         if (!in)
2585                 return -ENOMEM;
2586
2587         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2588
2589         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2590         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2591         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2592         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2593
2594         kvfree(in);
2595         return err;
2596 }
2597
2598 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2599                                 struct mlx5e_redirect_rqt_param rrp)
2600 {
2601         if (!rrp.is_rss)
2602                 return rrp.rqn;
2603
2604         if (ix >= rrp.rss.channels->num)
2605                 return priv->drop_rq.rqn;
2606
2607         return rrp.rss.channels->c[ix]->rq.rqn;
2608 }
2609
2610 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2611                                 struct mlx5e_redirect_rqt_param rrp)
2612 {
2613         u32 rqtn;
2614         int ix;
2615
2616         if (priv->indir_rqt.enabled) {
2617                 /* RSS RQ table */
2618                 rqtn = priv->indir_rqt.rqtn;
2619                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2620         }
2621
2622         for (ix = 0; ix < priv->max_nch; ix++) {
2623                 struct mlx5e_redirect_rqt_param direct_rrp = {
2624                         .is_rss = false,
2625                         {
2626                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2627                         },
2628                 };
2629
2630                 /* Direct RQ Tables */
2631                 if (!priv->direct_tir[ix].rqt.enabled)
2632                         continue;
2633
2634                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2635                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2636         }
2637 }
2638
2639 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2640                                             struct mlx5e_channels *chs)
2641 {
2642         struct mlx5e_redirect_rqt_param rrp = {
2643                 .is_rss        = true,
2644                 {
2645                         .rss = {
2646                                 .channels  = chs,
2647                                 .hfunc     = priv->rss_params.hfunc,
2648                         }
2649                 },
2650         };
2651
2652         mlx5e_redirect_rqts(priv, rrp);
2653 }
2654
2655 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2656 {
2657         struct mlx5e_redirect_rqt_param drop_rrp = {
2658                 .is_rss = false,
2659                 {
2660                         .rqn = priv->drop_rq.rqn,
2661                 },
2662         };
2663
2664         mlx5e_redirect_rqts(priv, drop_rrp);
2665 }
2666
2667 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2668         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2669                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2670                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2671         },
2672         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2673                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2674                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2675         },
2676         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2677                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2678                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2679         },
2680         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2681                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2682                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2683         },
2684         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2685                                      .l4_prot_type = 0,
2686                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2687         },
2688         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2689                                      .l4_prot_type = 0,
2690                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2691         },
2692         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2693                                       .l4_prot_type = 0,
2694                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2695         },
2696         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2697                                       .l4_prot_type = 0,
2698                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2699         },
2700         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2701                             .l4_prot_type = 0,
2702                             .rx_hash_fields = MLX5_HASH_IP,
2703         },
2704         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2705                             .l4_prot_type = 0,
2706                             .rx_hash_fields = MLX5_HASH_IP,
2707         },
2708 };
2709
2710 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2711 {
2712         return tirc_default_config[tt];
2713 }
2714
2715 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2716 {
2717         if (!params->lro_en)
2718                 return;
2719
2720 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2721
2722         MLX5_SET(tirc, tirc, lro_enable_mask,
2723                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2724                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2725         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2726                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2727         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2728 }
2729
2730 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2731                                     const struct mlx5e_tirc_config *ttconfig,
2732                                     void *tirc, bool inner)
2733 {
2734         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2735                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2736
2737         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2738         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2739                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2740                                              rx_hash_toeplitz_key);
2741                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2742                                                rx_hash_toeplitz_key);
2743
2744                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2745                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2746         }
2747         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2748                  ttconfig->l3_prot_type);
2749         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2750                  ttconfig->l4_prot_type);
2751         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2752                  ttconfig->rx_hash_fields);
2753 }
2754
2755 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2756                                         enum mlx5e_traffic_types tt,
2757                                         u32 rx_hash_fields)
2758 {
2759         *ttconfig                = tirc_default_config[tt];
2760         ttconfig->rx_hash_fields = rx_hash_fields;
2761 }
2762
2763 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2764 {
2765         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2766         struct mlx5e_rss_params *rss = &priv->rss_params;
2767         struct mlx5_core_dev *mdev = priv->mdev;
2768         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2769         struct mlx5e_tirc_config ttconfig;
2770         int tt;
2771
2772         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2773
2774         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2775                 memset(tirc, 0, ctxlen);
2776                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2777                                             rss->rx_hash_fields[tt]);
2778                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2779                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2780         }
2781
2782         /* Verify inner tirs resources allocated */
2783         if (!priv->inner_indir_tir[0].tirn)
2784                 return;
2785
2786         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2787                 memset(tirc, 0, ctxlen);
2788                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2789                                             rss->rx_hash_fields[tt]);
2790                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2791                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2792         }
2793 }
2794
2795 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2796 {
2797         struct mlx5_core_dev *mdev = priv->mdev;
2798
2799         void *in;
2800         void *tirc;
2801         int inlen;
2802         int err;
2803         int tt;
2804         int ix;
2805
2806         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2807         in = kvzalloc(inlen, GFP_KERNEL);
2808         if (!in)
2809                 return -ENOMEM;
2810
2811         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2812         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2813
2814         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2815
2816         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2817                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2818                 if (err)
2819                         goto free_in;
2820         }
2821
2822         for (ix = 0; ix < priv->max_nch; ix++) {
2823                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2824                 if (err)
2825                         goto free_in;
2826         }
2827
2828 free_in:
2829         kvfree(in);
2830
2831         return err;
2832 }
2833
2834 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2835
2836 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2837                          struct mlx5e_params *params, u16 mtu)
2838 {
2839         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2840         int err;
2841
2842         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2843         if (err)
2844                 return err;
2845
2846         /* Update vport context MTU */
2847         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2848         return 0;
2849 }
2850
2851 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2852                             struct mlx5e_params *params, u16 *mtu)
2853 {
2854         u16 hw_mtu = 0;
2855         int err;
2856
2857         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2858         if (err || !hw_mtu) /* fallback to port oper mtu */
2859                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2860
2861         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2862 }
2863
2864 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2865 {
2866         struct mlx5e_params *params = &priv->channels.params;
2867         struct net_device *netdev = priv->netdev;
2868         struct mlx5_core_dev *mdev = priv->mdev;
2869         u16 mtu;
2870         int err;
2871
2872         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2873         if (err)
2874                 return err;
2875
2876         mlx5e_query_mtu(mdev, params, &mtu);
2877         if (mtu != params->sw_mtu)
2878                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2879                             __func__, mtu, params->sw_mtu);
2880
2881         params->sw_mtu = mtu;
2882         return 0;
2883 }
2884
2885 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2886
2887 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2888 {
2889         struct mlx5e_params *params = &priv->channels.params;
2890         struct net_device *netdev   = priv->netdev;
2891         struct mlx5_core_dev *mdev  = priv->mdev;
2892         u16 max_mtu;
2893
2894         /* MTU range: 68 - hw-specific max */
2895         netdev->min_mtu = ETH_MIN_MTU;
2896
2897         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2898         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2899                                 ETH_MAX_MTU);
2900 }
2901
2902 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2903 {
2904         int tc;
2905
2906         netdev_reset_tc(netdev);
2907
2908         if (ntc == 1)
2909                 return;
2910
2911         netdev_set_num_tc(netdev, ntc);
2912
2913         /* Map netdev TCs to offset 0
2914          * We have our own UP to TXQ mapping for QoS
2915          */
2916         for (tc = 0; tc < ntc; tc++)
2917                 netdev_set_tc_queue(netdev, tc, nch, 0);
2918 }
2919
2920 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2921 {
2922         struct net_device *netdev = priv->netdev;
2923         int num_txqs, num_rxqs, nch, ntc;
2924         int old_num_txqs, old_ntc;
2925         int err;
2926
2927         old_num_txqs = netdev->real_num_tx_queues;
2928         old_ntc = netdev->num_tc;
2929
2930         nch = priv->channels.params.num_channels;
2931         ntc = priv->channels.params.num_tc;
2932         num_txqs = nch * ntc;
2933         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2934                 num_txqs += ntc;
2935         num_rxqs = nch * priv->profile->rq_groups;
2936
2937         mlx5e_netdev_set_tcs(netdev, nch, ntc);
2938
2939         err = netif_set_real_num_tx_queues(netdev, num_txqs);
2940         if (err) {
2941                 netdev_warn(netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2942                 goto err_tcs;
2943         }
2944         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2945         if (err) {
2946                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2947                 goto err_txqs;
2948         }
2949
2950         return 0;
2951
2952 err_txqs:
2953         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2954          * one of nch and ntc is changed in this function. That means, the call
2955          * to netif_set_real_num_tx_queues below should not fail, because it
2956          * decreases the number of TX queues.
2957          */
2958         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2959
2960 err_tcs:
2961         mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2962         return err;
2963 }
2964
2965 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2966                                            struct mlx5e_params *params)
2967 {
2968         struct mlx5_core_dev *mdev = priv->mdev;
2969         int num_comp_vectors, ix, irq;
2970
2971         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2972
2973         for (ix = 0; ix < params->num_channels; ix++) {
2974                 cpumask_clear(priv->scratchpad.cpumask);
2975
2976                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2977                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2978
2979                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2980                 }
2981
2982                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2983         }
2984 }
2985
2986 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2987 {
2988         u16 count = priv->channels.params.num_channels;
2989         int err;
2990
2991         err = mlx5e_update_netdev_queues(priv);
2992         if (err)
2993                 return err;
2994
2995         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2996
2997         if (!netif_is_rxfh_configured(priv->netdev))
2998                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2999                                               MLX5E_INDIR_RQT_SIZE, count);
3000
3001         return 0;
3002 }
3003
3004 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
3005
3006 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
3007 {
3008         int i, ch, tc, num_tc;
3009
3010         ch = priv->channels.num;
3011         num_tc = priv->channels.params.num_tc;
3012
3013         for (i = 0; i < ch; i++) {
3014                 for (tc = 0; tc < num_tc; tc++) {
3015                         struct mlx5e_channel *c = priv->channels.c[i];
3016                         struct mlx5e_txqsq *sq = &c->sq[tc];
3017
3018                         priv->txq2sq[sq->txq_ix] = sq;
3019                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
3020                 }
3021         }
3022
3023         if (!priv->channels.port_ptp)
3024                 return;
3025
3026         for (tc = 0; tc < num_tc; tc++) {
3027                 struct mlx5e_port_ptp *c = priv->channels.port_ptp;
3028                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
3029
3030                 priv->txq2sq[sq->txq_ix] = sq;
3031                 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
3032         }
3033 }
3034
3035 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
3036 {
3037         /* Sync with mlx5e_select_queue. */
3038         WRITE_ONCE(priv->num_tc_x_num_ch,
3039                    priv->channels.params.num_tc * priv->channels.num);
3040 }
3041
3042 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
3043 {
3044         mlx5e_update_num_tc_x_num_ch(priv);
3045         mlx5e_build_txq_maps(priv);
3046         mlx5e_activate_channels(&priv->channels);
3047         mlx5e_xdp_tx_enable(priv);
3048         netif_tx_start_all_queues(priv->netdev);
3049
3050         if (mlx5e_is_vport_rep(priv))
3051                 mlx5e_add_sqs_fwd_rules(priv);
3052
3053         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
3054         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
3055
3056         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
3057 }
3058
3059 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
3060 {
3061         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
3062
3063         mlx5e_redirect_rqts_to_drop(priv);
3064
3065         if (mlx5e_is_vport_rep(priv))
3066                 mlx5e_remove_sqs_fwd_rules(priv);
3067
3068         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
3069          * polling for inactive tx queues.
3070          */
3071         netif_tx_stop_all_queues(priv->netdev);
3072         netif_tx_disable(priv->netdev);
3073         mlx5e_xdp_tx_disable(priv);
3074         mlx5e_deactivate_channels(&priv->channels);
3075 }
3076
3077 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
3078                                       struct mlx5e_channels *new_chs,
3079                                       mlx5e_fp_preactivate preactivate,
3080                                       void *context)
3081 {
3082         struct net_device *netdev = priv->netdev;
3083         struct mlx5e_channels old_chs;
3084         int carrier_ok;
3085         int err = 0;
3086
3087         carrier_ok = netif_carrier_ok(netdev);
3088         netif_carrier_off(netdev);
3089
3090         mlx5e_deactivate_priv_channels(priv);
3091
3092         old_chs = priv->channels;
3093         priv->channels = *new_chs;
3094
3095         /* New channels are ready to roll, call the preactivate hook if needed
3096          * to modify HW settings or update kernel parameters.
3097          */
3098         if (preactivate) {
3099                 err = preactivate(priv, context);
3100                 if (err) {
3101                         priv->channels = old_chs;
3102                         goto out;
3103                 }
3104         }
3105
3106         mlx5e_close_channels(&old_chs);
3107         priv->profile->update_rx(priv);
3108
3109 out:
3110         mlx5e_activate_priv_channels(priv);
3111
3112         /* return carrier back if needed */
3113         if (carrier_ok)
3114                 netif_carrier_on(netdev);
3115
3116         return err;
3117 }
3118
3119 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
3120                                struct mlx5e_channels *new_chs,
3121                                mlx5e_fp_preactivate preactivate,
3122                                void *context)
3123 {
3124         int err;
3125
3126         err = mlx5e_open_channels(priv, new_chs);
3127         if (err)
3128                 return err;
3129
3130         err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context);
3131         if (err)
3132                 goto err_close;
3133
3134         return 0;
3135
3136 err_close:
3137         mlx5e_close_channels(new_chs);
3138
3139         return err;
3140 }
3141
3142 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3143 {
3144         struct mlx5e_channels new_channels = {};
3145
3146         new_channels.params = priv->channels.params;
3147         return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
3148 }
3149
3150 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3151 {
3152         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3153         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3154 }
3155
3156 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
3157                                      enum mlx5_port_status state)
3158 {
3159         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3160         int vport_admin_state;
3161
3162         mlx5_set_port_admin_status(mdev, state);
3163
3164         if (mlx5_eswitch_mode(mdev) != MLX5_ESWITCH_LEGACY)
3165                 return;
3166
3167         if (state == MLX5_PORT_UP)
3168                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
3169         else
3170                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3171
3172         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
3173 }
3174
3175 int mlx5e_open_locked(struct net_device *netdev)
3176 {
3177         struct mlx5e_priv *priv = netdev_priv(netdev);
3178         int err;
3179
3180         set_bit(MLX5E_STATE_OPENED, &priv->state);
3181
3182         err = mlx5e_open_channels(priv, &priv->channels);
3183         if (err)
3184                 goto err_clear_state_opened_flag;
3185
3186         priv->profile->update_rx(priv);
3187         mlx5e_activate_priv_channels(priv);
3188         if (priv->profile->update_carrier)
3189                 priv->profile->update_carrier(priv);
3190
3191         mlx5e_queue_update_stats(priv);
3192         return 0;
3193
3194 err_clear_state_opened_flag:
3195         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3196         return err;
3197 }
3198
3199 int mlx5e_open(struct net_device *netdev)
3200 {
3201         struct mlx5e_priv *priv = netdev_priv(netdev);
3202         int err;
3203
3204         mutex_lock(&priv->state_lock);
3205         err = mlx5e_open_locked(netdev);
3206         if (!err)
3207                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3208         mutex_unlock(&priv->state_lock);
3209
3210         return err;
3211 }
3212
3213 int mlx5e_close_locked(struct net_device *netdev)
3214 {
3215         struct mlx5e_priv *priv = netdev_priv(netdev);
3216
3217         /* May already be CLOSED in case a previous configuration operation
3218          * (e.g RX/TX queue size change) that involves close&open failed.
3219          */
3220         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3221                 return 0;
3222
3223         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3224
3225         netif_carrier_off(priv->netdev);
3226         mlx5e_deactivate_priv_channels(priv);
3227         mlx5e_close_channels(&priv->channels);
3228
3229         return 0;
3230 }
3231
3232 int mlx5e_close(struct net_device *netdev)
3233 {
3234         struct mlx5e_priv *priv = netdev_priv(netdev);
3235         int err;
3236
3237         if (!netif_device_present(netdev))
3238                 return -ENODEV;
3239
3240         mutex_lock(&priv->state_lock);
3241         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3242         err = mlx5e_close_locked(netdev);
3243         mutex_unlock(&priv->state_lock);
3244
3245         return err;
3246 }
3247
3248 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3249 {
3250         mlx5_wq_destroy(&rq->wq_ctrl);
3251 }
3252
3253 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3254                                struct mlx5e_rq *rq,
3255                                struct mlx5e_rq_param *param)
3256 {
3257         void *rqc = param->rqc;
3258         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3259         int err;
3260
3261         param->wq.db_numa_node = param->wq.buf_numa_node;
3262
3263         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3264                                  &rq->wq_ctrl);
3265         if (err)
3266                 return err;
3267
3268         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3269         xdp_rxq_info_unused(&rq->xdp_rxq);
3270
3271         rq->mdev = mdev;
3272
3273         return 0;
3274 }
3275
3276 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3277                                struct mlx5e_cq *cq,
3278                                struct mlx5e_cq_param *param)
3279 {
3280         struct mlx5_core_dev *mdev = priv->mdev;
3281
3282         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3283         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3284
3285         return mlx5e_alloc_cq_common(priv, param, cq);
3286 }
3287
3288 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3289                        struct mlx5e_rq *drop_rq)
3290 {
3291         struct mlx5_core_dev *mdev = priv->mdev;
3292         struct mlx5e_cq_param cq_param = {};
3293         struct mlx5e_rq_param rq_param = {};
3294         struct mlx5e_cq *cq = &drop_rq->cq;
3295         int err;
3296
3297         mlx5e_build_drop_rq_param(priv, &rq_param);
3298
3299         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3300         if (err)
3301                 return err;
3302
3303         err = mlx5e_create_cq(cq, &cq_param);
3304         if (err)
3305                 goto err_free_cq;
3306
3307         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3308         if (err)
3309                 goto err_destroy_cq;
3310
3311         err = mlx5e_create_rq(drop_rq, &rq_param);
3312         if (err)
3313                 goto err_free_rq;
3314
3315         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3316         if (err)
3317                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3318
3319         return 0;
3320
3321 err_free_rq:
3322         mlx5e_free_drop_rq(drop_rq);
3323
3324 err_destroy_cq:
3325         mlx5e_destroy_cq(cq);
3326
3327 err_free_cq:
3328         mlx5e_free_cq(cq);
3329
3330         return err;
3331 }
3332
3333 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3334 {
3335         mlx5e_destroy_rq(drop_rq);
3336         mlx5e_free_drop_rq(drop_rq);
3337         mlx5e_destroy_cq(&drop_rq->cq);
3338         mlx5e_free_cq(&drop_rq->cq);
3339 }
3340
3341 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3342 {
3343         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3344
3345         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3346
3347         if (MLX5_GET(tisc, tisc, tls_en))
3348                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3349
3350         if (mlx5_lag_is_lacp_owner(mdev))
3351                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3352
3353         return mlx5_core_create_tis(mdev, in, tisn);
3354 }
3355
3356 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3357 {
3358         mlx5_core_destroy_tis(mdev, tisn);
3359 }
3360
3361 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3362 {
3363         int tc, i;
3364
3365         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3366                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3367                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3368 }
3369
3370 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3371 {
3372         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3373 }
3374
3375 int mlx5e_create_tises(struct mlx5e_priv *priv)
3376 {
3377         int tc, i;
3378         int err;
3379
3380         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3381                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3382                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3383                         void *tisc;
3384
3385                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3386
3387                         MLX5_SET(tisc, tisc, prio, tc << 1);
3388
3389                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3390                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3391
3392                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3393                         if (err)
3394                                 goto err_close_tises;
3395                 }
3396         }
3397
3398         return 0;
3399
3400 err_close_tises:
3401         for (; i >= 0; i--) {
3402                 for (tc--; tc >= 0; tc--)
3403                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3404                 tc = priv->profile->max_tc;
3405         }
3406
3407         return err;
3408 }
3409
3410 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3411 {
3412         mlx5e_destroy_tises(priv);
3413 }
3414
3415 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3416                                              u32 rqtn, u32 *tirc)
3417 {
3418         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3419         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3420         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3421         MLX5_SET(tirc, tirc, tunneled_offload_en,
3422                  priv->channels.params.tunneled_offload_en);
3423
3424         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3425 }
3426
3427 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3428                                       enum mlx5e_traffic_types tt,
3429                                       u32 *tirc)
3430 {
3431         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3432         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3433                                        &tirc_default_config[tt], tirc, false);
3434 }
3435
3436 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3437 {
3438         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3439         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3440 }
3441
3442 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3443                                             enum mlx5e_traffic_types tt,
3444                                             u32 *tirc)
3445 {
3446         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3447         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3448                                        &tirc_default_config[tt], tirc, true);
3449 }
3450
3451 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3452 {
3453         struct mlx5e_tir *tir;
3454         void *tirc;
3455         int inlen;
3456         int i = 0;
3457         int err;
3458         u32 *in;
3459         int tt;
3460
3461         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3462         in = kvzalloc(inlen, GFP_KERNEL);
3463         if (!in)
3464                 return -ENOMEM;
3465
3466         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3467                 memset(in, 0, inlen);
3468                 tir = &priv->indir_tir[tt];
3469                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3470                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3471                 err = mlx5e_create_tir(priv->mdev, tir, in);
3472                 if (err) {
3473                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3474                         goto err_destroy_inner_tirs;
3475                 }
3476         }
3477
3478         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3479                 goto out;
3480
3481         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3482                 memset(in, 0, inlen);
3483                 tir = &priv->inner_indir_tir[i];
3484                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3485                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3486                 err = mlx5e_create_tir(priv->mdev, tir, in);
3487                 if (err) {
3488                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3489                         goto err_destroy_inner_tirs;
3490                 }
3491         }
3492
3493 out:
3494         kvfree(in);
3495
3496         return 0;
3497
3498 err_destroy_inner_tirs:
3499         for (i--; i >= 0; i--)
3500                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3501
3502         for (tt--; tt >= 0; tt--)
3503                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3504
3505         kvfree(in);
3506
3507         return err;
3508 }
3509
3510 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3511 {
3512         struct mlx5e_tir *tir;
3513         void *tirc;
3514         int inlen;
3515         int err = 0;
3516         u32 *in;
3517         int ix;
3518
3519         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3520         in = kvzalloc(inlen, GFP_KERNEL);
3521         if (!in)
3522                 return -ENOMEM;
3523
3524         for (ix = 0; ix < priv->max_nch; ix++) {
3525                 memset(in, 0, inlen);
3526                 tir = &tirs[ix];
3527                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3528                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3529                 err = mlx5e_create_tir(priv->mdev, tir, in);
3530                 if (unlikely(err))
3531                         goto err_destroy_ch_tirs;
3532         }
3533
3534         goto out;
3535
3536 err_destroy_ch_tirs:
3537         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3538         for (ix--; ix >= 0; ix--)
3539                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3540
3541 out:
3542         kvfree(in);
3543
3544         return err;
3545 }
3546
3547 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3548 {
3549         int i;
3550
3551         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3552                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3553
3554         /* Verify inner tirs resources allocated */
3555         if (!priv->inner_indir_tir[0].tirn)
3556                 return;
3557
3558         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3559                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3560 }
3561
3562 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3563 {
3564         int i;
3565
3566         for (i = 0; i < priv->max_nch; i++)
3567                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3568 }
3569
3570 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3571 {
3572         int err = 0;
3573         int i;
3574
3575         for (i = 0; i < chs->num; i++) {
3576                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3577                 if (err)
3578                         return err;
3579         }
3580
3581         return 0;
3582 }
3583
3584 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3585 {
3586         int err = 0;
3587         int i;
3588
3589         for (i = 0; i < chs->num; i++) {
3590                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3591                 if (err)
3592                         return err;
3593         }
3594
3595         return 0;
3596 }
3597
3598 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3599                                  struct tc_mqprio_qopt *mqprio)
3600 {
3601         struct mlx5e_channels new_channels = {};
3602         u8 tc = mqprio->num_tc;
3603         int err = 0;
3604
3605         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3606
3607         if (tc && tc != MLX5E_MAX_NUM_TC)
3608                 return -EINVAL;
3609
3610         mutex_lock(&priv->state_lock);
3611
3612         new_channels.params = priv->channels.params;
3613         new_channels.params.num_tc = tc ? tc : 1;
3614
3615         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3616                 priv->channels.params = new_channels.params;
3617                 goto out;
3618         }
3619
3620         err = mlx5e_safe_switch_channels(priv, &new_channels,
3621                                          mlx5e_num_channels_changed_ctx, NULL);
3622         if (err)
3623                 goto out;
3624
3625         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3626                                     new_channels.params.num_tc);
3627 out:
3628         mutex_unlock(&priv->state_lock);
3629         return err;
3630 }
3631
3632 static LIST_HEAD(mlx5e_block_cb_list);
3633
3634 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3635                           void *type_data)
3636 {
3637         struct mlx5e_priv *priv = netdev_priv(dev);
3638
3639         switch (type) {
3640         case TC_SETUP_BLOCK: {
3641                 struct flow_block_offload *f = type_data;
3642
3643                 f->unlocked_driver_cb = true;
3644                 return flow_block_cb_setup_simple(type_data,
3645                                                   &mlx5e_block_cb_list,
3646                                                   mlx5e_setup_tc_block_cb,
3647                                                   priv, priv, true);
3648         }
3649         case TC_SETUP_QDISC_MQPRIO:
3650                 return mlx5e_setup_tc_mqprio(priv, type_data);
3651         default:
3652                 return -EOPNOTSUPP;
3653         }
3654 }
3655
3656 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3657 {
3658         int i;
3659
3660         for (i = 0; i < priv->max_nch; i++) {
3661                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3662                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3663                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3664                 int j;
3665
3666                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3667                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3668                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3669
3670                 for (j = 0; j < priv->max_opened_tc; j++) {
3671                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3672
3673                         s->tx_packets    += sq_stats->packets;
3674                         s->tx_bytes      += sq_stats->bytes;
3675                         s->tx_dropped    += sq_stats->dropped;
3676                 }
3677         }
3678 }
3679
3680 void
3681 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3682 {
3683         struct mlx5e_priv *priv = netdev_priv(dev);
3684         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3685
3686         /* In switchdev mode, monitor counters doesn't monitor
3687          * rx/tx stats of 802_3. The update stats mechanism
3688          * should keep the 802_3 layout counters updated
3689          */
3690         if (!mlx5e_monitor_counter_supported(priv) ||
3691             mlx5e_is_uplink_rep(priv)) {
3692                 /* update HW stats in background for next time */
3693                 mlx5e_queue_update_stats(priv);
3694         }
3695
3696         if (mlx5e_is_uplink_rep(priv)) {
3697                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3698                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3699                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3700                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3701         } else {
3702                 mlx5e_fold_sw_stats64(priv, stats);
3703         }
3704
3705         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3706
3707         stats->rx_length_errors =
3708                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3709                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3710                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3711         stats->rx_crc_errors =
3712                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3713         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3714         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3715         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3716                            stats->rx_frame_errors;
3717         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3718 }
3719
3720 static void mlx5e_set_rx_mode(struct net_device *dev)
3721 {
3722         struct mlx5e_priv *priv = netdev_priv(dev);
3723
3724         queue_work(priv->wq, &priv->set_rx_mode_work);
3725 }
3726
3727 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3728 {
3729         struct mlx5e_priv *priv = netdev_priv(netdev);
3730         struct sockaddr *saddr = addr;
3731
3732         if (!is_valid_ether_addr(saddr->sa_data))
3733                 return -EADDRNOTAVAIL;
3734
3735         netif_addr_lock_bh(netdev);
3736         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3737         netif_addr_unlock_bh(netdev);
3738
3739         queue_work(priv->wq, &priv->set_rx_mode_work);
3740
3741         return 0;
3742 }
3743
3744 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3745         do {                                            \
3746                 if (enable)                             \
3747                         *features |= feature;           \
3748                 else                                    \
3749                         *features &= ~feature;          \
3750         } while (0)
3751
3752 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3753
3754 static int set_feature_lro(struct net_device *netdev, bool enable)
3755 {
3756         struct mlx5e_priv *priv = netdev_priv(netdev);
3757         struct mlx5_core_dev *mdev = priv->mdev;
3758         struct mlx5e_channels new_channels = {};
3759         struct mlx5e_params *old_params;
3760         int err = 0;
3761         bool reset;
3762
3763         mutex_lock(&priv->state_lock);
3764
3765         if (enable && priv->xsk.refcnt) {
3766                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3767                             priv->xsk.refcnt);
3768                 err = -EINVAL;
3769                 goto out;
3770         }
3771
3772         old_params = &priv->channels.params;
3773         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3774                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3775                 err = -EINVAL;
3776                 goto out;
3777         }
3778
3779         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3780
3781         new_channels.params = *old_params;
3782         new_channels.params.lro_en = enable;
3783
3784         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3785                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3786                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3787                         reset = false;
3788         }
3789
3790         if (!reset) {
3791                 *old_params = new_channels.params;
3792                 err = mlx5e_modify_tirs_lro(priv);
3793                 goto out;
3794         }
3795
3796         err = mlx5e_safe_switch_channels(priv, &new_channels,
3797                                          mlx5e_modify_tirs_lro_ctx, NULL);
3798 out:
3799         mutex_unlock(&priv->state_lock);
3800         return err;
3801 }
3802
3803 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3804 {
3805         struct mlx5e_priv *priv = netdev_priv(netdev);
3806
3807         if (enable)
3808                 mlx5e_enable_cvlan_filter(priv);
3809         else
3810                 mlx5e_disable_cvlan_filter(priv);
3811
3812         return 0;
3813 }
3814
3815 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3816 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3817 {
3818         struct mlx5e_priv *priv = netdev_priv(netdev);
3819
3820         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3821                 netdev_err(netdev,
3822                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3823                 return -EINVAL;
3824         }
3825
3826         return 0;
3827 }
3828 #endif
3829
3830 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3831 {
3832         struct mlx5e_priv *priv = netdev_priv(netdev);
3833         struct mlx5_core_dev *mdev = priv->mdev;
3834
3835         return mlx5_set_port_fcs(mdev, !enable);
3836 }
3837
3838 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3839 {
3840         struct mlx5e_priv *priv = netdev_priv(netdev);
3841         int err;
3842
3843         mutex_lock(&priv->state_lock);
3844
3845         priv->channels.params.scatter_fcs_en = enable;
3846         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3847         if (err)
3848                 priv->channels.params.scatter_fcs_en = !enable;
3849
3850         mutex_unlock(&priv->state_lock);
3851
3852         return err;
3853 }
3854
3855 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3856 {
3857         struct mlx5e_priv *priv = netdev_priv(netdev);
3858         int err = 0;
3859
3860         mutex_lock(&priv->state_lock);
3861
3862         priv->channels.params.vlan_strip_disable = !enable;
3863         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3864                 goto unlock;
3865
3866         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3867         if (err)
3868                 priv->channels.params.vlan_strip_disable = enable;
3869
3870 unlock:
3871         mutex_unlock(&priv->state_lock);
3872
3873         return err;
3874 }
3875
3876 #ifdef CONFIG_MLX5_EN_ARFS
3877 static int set_feature_arfs(struct net_device *netdev, bool enable)
3878 {
3879         struct mlx5e_priv *priv = netdev_priv(netdev);
3880         int err;
3881
3882         if (enable)
3883                 err = mlx5e_arfs_enable(priv);
3884         else
3885                 err = mlx5e_arfs_disable(priv);
3886
3887         return err;
3888 }
3889 #endif
3890
3891 static int mlx5e_handle_feature(struct net_device *netdev,
3892                                 netdev_features_t *features,
3893                                 netdev_features_t wanted_features,
3894                                 netdev_features_t feature,
3895                                 mlx5e_feature_handler feature_handler)
3896 {
3897         netdev_features_t changes = wanted_features ^ netdev->features;
3898         bool enable = !!(wanted_features & feature);
3899         int err;
3900
3901         if (!(changes & feature))
3902                 return 0;
3903
3904         err = feature_handler(netdev, enable);
3905         if (err) {
3906                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3907                            enable ? "Enable" : "Disable", &feature, err);
3908                 return err;
3909         }
3910
3911         MLX5E_SET_FEATURE(features, feature, enable);
3912         return 0;
3913 }
3914
3915 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3916 {
3917         netdev_features_t oper_features = netdev->features;
3918         int err = 0;
3919
3920 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3921         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3922
3923         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3924         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3925                                     set_feature_cvlan_filter);
3926 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3927         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3928 #endif
3929         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3930         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3931         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3932 #ifdef CONFIG_MLX5_EN_ARFS
3933         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3934 #endif
3935         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3936
3937         if (err) {
3938                 netdev->features = oper_features;
3939                 return -EINVAL;
3940         }
3941
3942         return 0;
3943 }
3944
3945 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3946                                             netdev_features_t features)
3947 {
3948         struct mlx5e_priv *priv = netdev_priv(netdev);
3949         struct mlx5e_params *params;
3950
3951         mutex_lock(&priv->state_lock);
3952         params = &priv->channels.params;
3953         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3954                 /* HW strips the outer C-tag header, this is a problem
3955                  * for S-tag traffic.
3956                  */
3957                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3958                 if (!params->vlan_strip_disable)
3959                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3960         }
3961         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3962                 if (features & NETIF_F_LRO) {
3963                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3964                         features &= ~NETIF_F_LRO;
3965                 }
3966         }
3967
3968         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3969                 features &= ~NETIF_F_RXHASH;
3970                 if (netdev->features & NETIF_F_RXHASH)
3971                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3972         }
3973
3974         mutex_unlock(&priv->state_lock);
3975
3976         return features;
3977 }
3978
3979 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3980                                    struct mlx5e_channels *chs,
3981                                    struct mlx5e_params *new_params,
3982                                    struct mlx5_core_dev *mdev)
3983 {
3984         u16 ix;
3985
3986         for (ix = 0; ix < chs->params.num_channels; ix++) {
3987                 struct xsk_buff_pool *xsk_pool =
3988                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3989                 struct mlx5e_xsk_param xsk;
3990
3991                 if (!xsk_pool)
3992                         continue;
3993
3994                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3995
3996                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3997                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3998                         int max_mtu_frame, max_mtu_page, max_mtu;
3999
4000                         /* Two criteria must be met:
4001                          * 1. HW MTU + all headrooms <= XSK frame size.
4002                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
4003                          */
4004                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
4005                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
4006                         max_mtu = min(max_mtu_frame, max_mtu_page);
4007
4008                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
4009                                    new_params->sw_mtu, ix, max_mtu);
4010                         return false;
4011                 }
4012         }
4013
4014         return true;
4015 }
4016
4017 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
4018                      mlx5e_fp_preactivate preactivate)
4019 {
4020         struct mlx5e_priv *priv = netdev_priv(netdev);
4021         struct mlx5e_channels new_channels = {};
4022         struct mlx5e_params *params;
4023         int err = 0;
4024         bool reset;
4025
4026         mutex_lock(&priv->state_lock);
4027
4028         params = &priv->channels.params;
4029
4030         reset = !params->lro_en;
4031         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
4032
4033         new_channels.params = *params;
4034         new_channels.params.sw_mtu = new_mtu;
4035         err = mlx5e_validate_params(priv, &new_channels.params);
4036         if (err)
4037                 goto out;
4038
4039         if (params->xdp_prog &&
4040             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4041                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
4042                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
4043                 err = -EINVAL;
4044                 goto out;
4045         }
4046
4047         if (priv->xsk.refcnt &&
4048             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4049                                     &new_channels.params, priv->mdev)) {
4050                 err = -EINVAL;
4051                 goto out;
4052         }
4053
4054         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4055                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4056                                                               &new_channels.params,
4057                                                               NULL);
4058                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
4059                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
4060
4061                 /* If XSK is active, XSK RQs are linear. */
4062                 is_linear |= priv->xsk.refcnt;
4063
4064                 /* Always reset in linear mode - hw_mtu is used in data path. */
4065                 reset = reset && (is_linear || (ppw_old != ppw_new));
4066         }
4067
4068         if (!reset) {
4069                 params->sw_mtu = new_mtu;
4070                 if (preactivate)
4071                         preactivate(priv, NULL);
4072                 netdev->mtu = params->sw_mtu;
4073                 goto out;
4074         }
4075
4076         err = mlx5e_safe_switch_channels(priv, &new_channels, preactivate, NULL);
4077         if (err)
4078                 goto out;
4079
4080         netdev->mtu = new_channels.params.sw_mtu;
4081
4082 out:
4083         mutex_unlock(&priv->state_lock);
4084         return err;
4085 }
4086
4087 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4088 {
4089         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4090 }
4091
4092 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4093 {
4094         struct hwtstamp_config config;
4095         int err;
4096
4097         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4098             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4099                 return -EOPNOTSUPP;
4100
4101         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4102                 return -EFAULT;
4103
4104         /* TX HW timestamp */
4105         switch (config.tx_type) {
4106         case HWTSTAMP_TX_OFF:
4107         case HWTSTAMP_TX_ON:
4108                 break;
4109         default:
4110                 return -ERANGE;
4111         }
4112
4113         mutex_lock(&priv->state_lock);
4114         /* RX HW timestamp */
4115         switch (config.rx_filter) {
4116         case HWTSTAMP_FILTER_NONE:
4117                 /* Reset CQE compression to Admin default */
4118                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
4119                 break;
4120         case HWTSTAMP_FILTER_ALL:
4121         case HWTSTAMP_FILTER_SOME:
4122         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4123         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4124         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4125         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4126         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4127         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4128         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4129         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4130         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4131         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4132         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4133         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4134         case HWTSTAMP_FILTER_NTP_ALL:
4135                 /* Disable CQE compression */
4136                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4137                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4138                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4139                 if (err) {
4140                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4141                         mutex_unlock(&priv->state_lock);
4142                         return err;
4143                 }
4144                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4145                 break;
4146         default:
4147                 mutex_unlock(&priv->state_lock);
4148                 return -ERANGE;
4149         }
4150
4151         memcpy(&priv->tstamp, &config, sizeof(config));
4152         mutex_unlock(&priv->state_lock);
4153
4154         /* might need to fix some features */
4155         netdev_update_features(priv->netdev);
4156
4157         return copy_to_user(ifr->ifr_data, &config,
4158                             sizeof(config)) ? -EFAULT : 0;
4159 }
4160
4161 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4162 {
4163         struct hwtstamp_config *cfg = &priv->tstamp;
4164
4165         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4166                 return -EOPNOTSUPP;
4167
4168         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4169 }
4170
4171 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4172 {
4173         struct mlx5e_priv *priv = netdev_priv(dev);
4174
4175         switch (cmd) {
4176         case SIOCSHWTSTAMP:
4177                 return mlx5e_hwstamp_set(priv, ifr);
4178         case SIOCGHWTSTAMP:
4179                 return mlx5e_hwstamp_get(priv, ifr);
4180         default:
4181                 return -EOPNOTSUPP;
4182         }
4183 }
4184
4185 #ifdef CONFIG_MLX5_ESWITCH
4186 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4187 {
4188         struct mlx5e_priv *priv = netdev_priv(dev);
4189         struct mlx5_core_dev *mdev = priv->mdev;
4190
4191         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4192 }
4193
4194 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4195                              __be16 vlan_proto)
4196 {
4197         struct mlx5e_priv *priv = netdev_priv(dev);
4198         struct mlx5_core_dev *mdev = priv->mdev;
4199
4200         if (vlan_proto != htons(ETH_P_8021Q))
4201                 return -EPROTONOSUPPORT;
4202
4203         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4204                                            vlan, qos);
4205 }
4206
4207 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4208 {
4209         struct mlx5e_priv *priv = netdev_priv(dev);
4210         struct mlx5_core_dev *mdev = priv->mdev;
4211
4212         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4213 }
4214
4215 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4216 {
4217         struct mlx5e_priv *priv = netdev_priv(dev);
4218         struct mlx5_core_dev *mdev = priv->mdev;
4219
4220         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4221 }
4222
4223 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4224                       int max_tx_rate)
4225 {
4226         struct mlx5e_priv *priv = netdev_priv(dev);
4227         struct mlx5_core_dev *mdev = priv->mdev;
4228
4229         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4230                                            max_tx_rate, min_tx_rate);
4231 }
4232
4233 static int mlx5_vport_link2ifla(u8 esw_link)
4234 {
4235         switch (esw_link) {
4236         case MLX5_VPORT_ADMIN_STATE_DOWN:
4237                 return IFLA_VF_LINK_STATE_DISABLE;
4238         case MLX5_VPORT_ADMIN_STATE_UP:
4239                 return IFLA_VF_LINK_STATE_ENABLE;
4240         }
4241         return IFLA_VF_LINK_STATE_AUTO;
4242 }
4243
4244 static int mlx5_ifla_link2vport(u8 ifla_link)
4245 {
4246         switch (ifla_link) {
4247         case IFLA_VF_LINK_STATE_DISABLE:
4248                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4249         case IFLA_VF_LINK_STATE_ENABLE:
4250                 return MLX5_VPORT_ADMIN_STATE_UP;
4251         }
4252         return MLX5_VPORT_ADMIN_STATE_AUTO;
4253 }
4254
4255 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4256                                    int link_state)
4257 {
4258         struct mlx5e_priv *priv = netdev_priv(dev);
4259         struct mlx5_core_dev *mdev = priv->mdev;
4260
4261         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4262                                             mlx5_ifla_link2vport(link_state));
4263 }
4264
4265 int mlx5e_get_vf_config(struct net_device *dev,
4266                         int vf, struct ifla_vf_info *ivi)
4267 {
4268         struct mlx5e_priv *priv = netdev_priv(dev);
4269         struct mlx5_core_dev *mdev = priv->mdev;
4270         int err;
4271
4272         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4273         if (err)
4274                 return err;
4275         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4276         return 0;
4277 }
4278
4279 int mlx5e_get_vf_stats(struct net_device *dev,
4280                        int vf, struct ifla_vf_stats *vf_stats)
4281 {
4282         struct mlx5e_priv *priv = netdev_priv(dev);
4283         struct mlx5_core_dev *mdev = priv->mdev;
4284
4285         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4286                                             vf_stats);
4287 }
4288 #endif
4289
4290 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4291 {
4292         switch (proto_type) {
4293         case IPPROTO_GRE:
4294                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4295         case IPPROTO_IPIP:
4296         case IPPROTO_IPV6:
4297                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4298                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4299         default:
4300                 return false;
4301         }
4302 }
4303
4304 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4305                                                            struct sk_buff *skb)
4306 {
4307         switch (skb->inner_protocol) {
4308         case htons(ETH_P_IP):
4309         case htons(ETH_P_IPV6):
4310         case htons(ETH_P_TEB):
4311                 return true;
4312         case htons(ETH_P_MPLS_UC):
4313         case htons(ETH_P_MPLS_MC):
4314                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4315         }
4316         return false;
4317 }
4318
4319 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4320                                                      struct sk_buff *skb,
4321                                                      netdev_features_t features)
4322 {
4323         unsigned int offset = 0;
4324         struct udphdr *udph;
4325         u8 proto;
4326         u16 port;
4327
4328         switch (vlan_get_protocol(skb)) {
4329         case htons(ETH_P_IP):
4330                 proto = ip_hdr(skb)->protocol;
4331                 break;
4332         case htons(ETH_P_IPV6):
4333                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4334                 break;
4335         default:
4336                 goto out;
4337         }
4338
4339         switch (proto) {
4340         case IPPROTO_GRE:
4341                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4342                         return features;
4343                 break;
4344         case IPPROTO_IPIP:
4345         case IPPROTO_IPV6:
4346                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4347                         return features;
4348                 break;
4349         case IPPROTO_UDP:
4350                 udph = udp_hdr(skb);
4351                 port = be16_to_cpu(udph->dest);
4352
4353                 /* Verify if UDP port is being offloaded by HW */
4354                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4355                         return features;
4356
4357 #if IS_ENABLED(CONFIG_GENEVE)
4358                 /* Support Geneve offload for default UDP port */
4359                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4360                         return features;
4361 #endif
4362         }
4363
4364 out:
4365         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4366         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4367 }
4368
4369 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4370                                        struct net_device *netdev,
4371                                        netdev_features_t features)
4372 {
4373         struct mlx5e_priv *priv = netdev_priv(netdev);
4374
4375         features = vlan_features_check(skb, features);
4376         features = vxlan_features_check(skb, features);
4377
4378 #ifdef CONFIG_MLX5_EN_IPSEC
4379         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4380                 return features;
4381 #endif
4382
4383         /* Validate if the tunneled packet is being offloaded by HW */
4384         if (skb->encapsulation &&
4385             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4386                 return mlx5e_tunnel_features_check(priv, skb, features);
4387
4388         return features;
4389 }
4390
4391 static void mlx5e_tx_timeout_work(struct work_struct *work)
4392 {
4393         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4394                                                tx_timeout_work);
4395         struct net_device *netdev = priv->netdev;
4396         int i;
4397
4398         rtnl_lock();
4399         mutex_lock(&priv->state_lock);
4400
4401         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4402                 goto unlock;
4403
4404         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4405                 struct netdev_queue *dev_queue =
4406                         netdev_get_tx_queue(netdev, i);
4407                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4408
4409                 if (!netif_xmit_stopped(dev_queue))
4410                         continue;
4411
4412                 if (mlx5e_reporter_tx_timeout(sq))
4413                 /* break if tried to reopened channels */
4414                         break;
4415         }
4416
4417 unlock:
4418         mutex_unlock(&priv->state_lock);
4419         rtnl_unlock();
4420 }
4421
4422 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4423 {
4424         struct mlx5e_priv *priv = netdev_priv(dev);
4425
4426         netdev_err(dev, "TX timeout detected\n");
4427         queue_work(priv->wq, &priv->tx_timeout_work);
4428 }
4429
4430 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4431 {
4432         struct net_device *netdev = priv->netdev;
4433         struct mlx5e_channels new_channels = {};
4434
4435         if (priv->channels.params.lro_en) {
4436                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4437                 return -EINVAL;
4438         }
4439
4440         if (MLX5_IPSEC_DEV(priv->mdev)) {
4441                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4442                 return -EINVAL;
4443         }
4444
4445         new_channels.params = priv->channels.params;
4446         new_channels.params.xdp_prog = prog;
4447
4448         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4449          * the XDP program.
4450          */
4451         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4452                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4453                             new_channels.params.sw_mtu,
4454                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4455                 return -EINVAL;
4456         }
4457
4458         return 0;
4459 }
4460
4461 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4462 {
4463         struct bpf_prog *old_prog;
4464
4465         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4466                                        lockdep_is_held(&rq->priv->state_lock));
4467         if (old_prog)
4468                 bpf_prog_put(old_prog);
4469 }
4470
4471 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4472 {
4473         struct mlx5e_priv *priv = netdev_priv(netdev);
4474         struct bpf_prog *old_prog;
4475         bool reset, was_opened;
4476         int err = 0;
4477         int i;
4478
4479         mutex_lock(&priv->state_lock);
4480
4481         if (prog) {
4482                 err = mlx5e_xdp_allowed(priv, prog);
4483                 if (err)
4484                         goto unlock;
4485         }
4486
4487         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4488         /* no need for full reset when exchanging programs */
4489         reset = (!priv->channels.params.xdp_prog || !prog);
4490
4491         if (was_opened && !reset)
4492                 /* num_channels is invariant here, so we can take the
4493                  * batched reference right upfront.
4494                  */
4495                 bpf_prog_add(prog, priv->channels.num);
4496
4497         if (was_opened && reset) {
4498                 struct mlx5e_channels new_channels = {};
4499
4500                 new_channels.params = priv->channels.params;
4501                 new_channels.params.xdp_prog = prog;
4502                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4503                 old_prog = priv->channels.params.xdp_prog;
4504
4505                 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
4506                 if (err)
4507                         goto unlock;
4508         } else {
4509                 /* exchange programs, extra prog reference we got from caller
4510                  * as long as we don't fail from this point onwards.
4511                  */
4512                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4513         }
4514
4515         if (old_prog)
4516                 bpf_prog_put(old_prog);
4517
4518         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4519                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4520
4521         if (!was_opened || reset)
4522                 goto unlock;
4523
4524         /* exchanging programs w/o reset, we update ref counts on behalf
4525          * of the channels RQs here.
4526          */
4527         for (i = 0; i < priv->channels.num; i++) {
4528                 struct mlx5e_channel *c = priv->channels.c[i];
4529
4530                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4531                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
4532                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4533         }
4534
4535 unlock:
4536         mutex_unlock(&priv->state_lock);
4537         return err;
4538 }
4539
4540 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4541 {
4542         switch (xdp->command) {
4543         case XDP_SETUP_PROG:
4544                 return mlx5e_xdp_set(dev, xdp->prog);
4545         case XDP_SETUP_XSK_POOL:
4546                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4547                                             xdp->xsk.queue_id);
4548         default:
4549                 return -EINVAL;
4550         }
4551 }
4552
4553 #ifdef CONFIG_MLX5_ESWITCH
4554 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4555                                 struct net_device *dev, u32 filter_mask,
4556                                 int nlflags)
4557 {
4558         struct mlx5e_priv *priv = netdev_priv(dev);
4559         struct mlx5_core_dev *mdev = priv->mdev;
4560         u8 mode, setting;
4561         int err;
4562
4563         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4564         if (err)
4565                 return err;
4566         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4567         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4568                                        mode,
4569                                        0, 0, nlflags, filter_mask, NULL);
4570 }
4571
4572 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4573                                 u16 flags, struct netlink_ext_ack *extack)
4574 {
4575         struct mlx5e_priv *priv = netdev_priv(dev);
4576         struct mlx5_core_dev *mdev = priv->mdev;
4577         struct nlattr *attr, *br_spec;
4578         u16 mode = BRIDGE_MODE_UNDEF;
4579         u8 setting;
4580         int rem;
4581
4582         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4583         if (!br_spec)
4584                 return -EINVAL;
4585
4586         nla_for_each_nested(attr, br_spec, rem) {
4587                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4588                         continue;
4589
4590                 if (nla_len(attr) < sizeof(mode))
4591                         return -EINVAL;
4592
4593                 mode = nla_get_u16(attr);
4594                 if (mode > BRIDGE_MODE_VEPA)
4595                         return -EINVAL;
4596
4597                 break;
4598         }
4599
4600         if (mode == BRIDGE_MODE_UNDEF)
4601                 return -EINVAL;
4602
4603         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4604         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4605 }
4606 #endif
4607
4608 const struct net_device_ops mlx5e_netdev_ops = {
4609         .ndo_open                = mlx5e_open,
4610         .ndo_stop                = mlx5e_close,
4611         .ndo_start_xmit          = mlx5e_xmit,
4612         .ndo_setup_tc            = mlx5e_setup_tc,
4613         .ndo_select_queue        = mlx5e_select_queue,
4614         .ndo_get_stats64         = mlx5e_get_stats,
4615         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4616         .ndo_set_mac_address     = mlx5e_set_mac,
4617         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4618         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4619         .ndo_set_features        = mlx5e_set_features,
4620         .ndo_fix_features        = mlx5e_fix_features,
4621         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4622         .ndo_do_ioctl            = mlx5e_ioctl,
4623         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4624         .ndo_udp_tunnel_add      = udp_tunnel_nic_add_port,
4625         .ndo_udp_tunnel_del      = udp_tunnel_nic_del_port,
4626         .ndo_features_check      = mlx5e_features_check,
4627         .ndo_tx_timeout          = mlx5e_tx_timeout,
4628         .ndo_bpf                 = mlx5e_xdp,
4629         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4630         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4631 #ifdef CONFIG_MLX5_EN_ARFS
4632         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4633 #endif
4634 #ifdef CONFIG_MLX5_ESWITCH
4635         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4636         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4637
4638         /* SRIOV E-Switch NDOs */
4639         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4640         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4641         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4642         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4643         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4644         .ndo_get_vf_config       = mlx5e_get_vf_config,
4645         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4646         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4647 #endif
4648         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4649 };
4650
4651 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4652                                    int num_channels)
4653 {
4654         int i;
4655
4656         for (i = 0; i < len; i++)
4657                 indirection_rqt[i] = i % num_channels;
4658 }
4659
4660 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4661 {
4662         u32 link_speed = 0;
4663         u32 pci_bw = 0;
4664
4665         mlx5e_port_max_linkspeed(mdev, &link_speed);
4666         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4667         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4668                            link_speed, pci_bw);
4669
4670 #define MLX5E_SLOW_PCI_RATIO (2)
4671
4672         return link_speed && pci_bw &&
4673                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4674 }
4675
4676 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4677 {
4678         struct dim_cq_moder moder;
4679
4680         moder.cq_period_mode = cq_period_mode;
4681         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4682         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4683         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4684                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4685
4686         return moder;
4687 }
4688
4689 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4690 {
4691         struct dim_cq_moder moder;
4692
4693         moder.cq_period_mode = cq_period_mode;
4694         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4695         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4696         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4697                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4698
4699         return moder;
4700 }
4701
4702 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4703 {
4704         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4705                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4706                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4707 }
4708
4709 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4710 {
4711         if (params->tx_dim_enabled) {
4712                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4713
4714                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4715         } else {
4716                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4717         }
4718 }
4719
4720 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
4721 {
4722         if (params->rx_dim_enabled) {
4723                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4724
4725                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4726         } else {
4727                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4728         }
4729 }
4730
4731 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4732 {
4733         mlx5e_reset_tx_moderation(params, cq_period_mode);
4734         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4735                         params->tx_cq_moderation.cq_period_mode ==
4736                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4737 }
4738
4739 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4740 {
4741         mlx5e_reset_rx_moderation(params, cq_period_mode);
4742         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4743                         params->rx_cq_moderation.cq_period_mode ==
4744                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4745 }
4746
4747 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4748 {
4749         int i;
4750
4751         /* The supported periods are organized in ascending order */
4752         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4753                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4754                         break;
4755
4756         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4757 }
4758
4759 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4760                            struct mlx5e_params *params)
4761 {
4762         /* Prefer Striding RQ, unless any of the following holds:
4763          * - Striding RQ configuration is not possible/supported.
4764          * - Slow PCI heuristic.
4765          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4766          *
4767          * No XSK params: checking the availability of striding RQ in general.
4768          */
4769         if (!slow_pci_heuristic(mdev) &&
4770             mlx5e_striding_rq_possible(mdev, params) &&
4771             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4772              !mlx5e_rx_is_linear_skb(params, NULL)))
4773                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4774         mlx5e_set_rq_type(mdev, params);
4775         mlx5e_init_rq_type_params(mdev, params);
4776 }
4777
4778 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4779                             u16 num_channels)
4780 {
4781         enum mlx5e_traffic_types tt;
4782
4783         rss_params->hfunc = ETH_RSS_HASH_TOP;
4784         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4785                             sizeof(rss_params->toeplitz_hash_key));
4786         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4787                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4788         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4789                 rss_params->rx_hash_fields[tt] =
4790                         tirc_default_config[tt].rx_hash_fields;
4791 }
4792
4793 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
4794                             struct mlx5e_xsk *xsk,
4795                             struct mlx5e_rss_params *rss_params,
4796                             struct mlx5e_params *params,
4797                             u16 mtu)
4798 {
4799         struct mlx5_core_dev *mdev = priv->mdev;
4800         u8 rx_cq_period_mode;
4801
4802         params->sw_mtu = mtu;
4803         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4804         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4805                                      priv->max_nch);
4806         params->num_tc       = 1;
4807
4808         /* SQ */
4809         params->log_sq_size = is_kdump_kernel() ?
4810                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4811                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4812         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE,
4813                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4814
4815         /* XDP SQ */
4816         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4817                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4818
4819         /* set CQE compression */
4820         params->rx_cqe_compress_def = false;
4821         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4822             MLX5_CAP_GEN(mdev, vport_group_manager))
4823                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4824
4825         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4826         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4827
4828         /* RQ */
4829         mlx5e_build_rq_params(mdev, params);
4830
4831         /* HW LRO */
4832         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4833             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4834                 /* No XSK params: checking the availability of striding RQ in general. */
4835                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4836                         params->lro_en = !slow_pci_heuristic(mdev);
4837         }
4838         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4839
4840         /* CQ moderation params */
4841         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4842                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4843                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4844         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4845         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4846         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4847         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4848
4849         /* TX inline */
4850         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4851
4852         /* RSS */
4853         mlx5e_build_rss_params(rss_params, params->num_channels);
4854         params->tunneled_offload_en =
4855                 mlx5e_tunnel_inner_ft_supported(mdev);
4856
4857         /* AF_XDP */
4858         params->xsk = xsk;
4859 }
4860
4861 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4862 {
4863         struct mlx5e_priv *priv = netdev_priv(netdev);
4864
4865         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4866         if (is_zero_ether_addr(netdev->dev_addr) &&
4867             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4868                 eth_hw_addr_random(netdev);
4869                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4870         }
4871 }
4872
4873 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4874                                 unsigned int entry, struct udp_tunnel_info *ti)
4875 {
4876         struct mlx5e_priv *priv = netdev_priv(netdev);
4877
4878         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4879 }
4880
4881 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4882                                   unsigned int entry, struct udp_tunnel_info *ti)
4883 {
4884         struct mlx5e_priv *priv = netdev_priv(netdev);
4885
4886         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4887 }
4888
4889 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4890 {
4891         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4892                 return;
4893
4894         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4895         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4896         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4897                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4898         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4899         /* Don't count the space hard-coded to the IANA port */
4900         priv->nic_info.tables[0].n_entries =
4901                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4902
4903         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4904 }
4905
4906 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4907 {
4908         int tt;
4909
4910         for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) {
4911                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt)))
4912                         return true;
4913         }
4914         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4915 }
4916
4917 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4918 {
4919         struct mlx5e_priv *priv = netdev_priv(netdev);
4920         struct mlx5_core_dev *mdev = priv->mdev;
4921         bool fcs_supported;
4922         bool fcs_enabled;
4923
4924         SET_NETDEV_DEV(netdev, mdev->device);
4925
4926         netdev->netdev_ops = &mlx5e_netdev_ops;
4927
4928         mlx5e_dcbnl_build_netdev(netdev);
4929
4930         netdev->watchdog_timeo    = 15 * HZ;
4931
4932         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4933
4934         netdev->vlan_features    |= NETIF_F_SG;
4935         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4936         netdev->vlan_features    |= NETIF_F_GRO;
4937         netdev->vlan_features    |= NETIF_F_TSO;
4938         netdev->vlan_features    |= NETIF_F_TSO6;
4939         netdev->vlan_features    |= NETIF_F_RXCSUM;
4940         netdev->vlan_features    |= NETIF_F_RXHASH;
4941
4942         netdev->mpls_features    |= NETIF_F_SG;
4943         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4944         netdev->mpls_features    |= NETIF_F_TSO;
4945         netdev->mpls_features    |= NETIF_F_TSO6;
4946
4947         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4948         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4949
4950         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4951             mlx5e_check_fragmented_striding_rq_cap(mdev))
4952                 netdev->vlan_features    |= NETIF_F_LRO;
4953
4954         netdev->hw_features       = netdev->vlan_features;
4955         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4956         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4957         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4958         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4959
4960         mlx5e_vxlan_set_netdev_info(priv);
4961
4962         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4963                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4964                 netdev->hw_enc_features |= NETIF_F_TSO;
4965                 netdev->hw_enc_features |= NETIF_F_TSO6;
4966                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4967         }
4968
4969         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4970                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4971                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4972                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4973                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4974                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4975                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4976                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4977         }
4978
4979         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4980                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4981                                            NETIF_F_GSO_GRE_CSUM;
4982                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4983                                            NETIF_F_GSO_GRE_CSUM;
4984                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4985                                                 NETIF_F_GSO_GRE_CSUM;
4986         }
4987
4988         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4989                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4990                                        NETIF_F_GSO_IPXIP6;
4991                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4992                                            NETIF_F_GSO_IPXIP6;
4993                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4994                                                 NETIF_F_GSO_IPXIP6;
4995         }
4996
4997         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4998         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4999         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
5000         netdev->features                         |= NETIF_F_GSO_UDP_L4;
5001
5002         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
5003
5004         if (fcs_supported)
5005                 netdev->hw_features |= NETIF_F_RXALL;
5006
5007         if (MLX5_CAP_ETH(mdev, scatter_fcs))
5008                 netdev->hw_features |= NETIF_F_RXFCS;
5009
5010         netdev->features          = netdev->hw_features;
5011         if (!priv->channels.params.lro_en)
5012                 netdev->features  &= ~NETIF_F_LRO;
5013
5014         if (fcs_enabled)
5015                 netdev->features  &= ~NETIF_F_RXALL;
5016
5017         if (!priv->channels.params.scatter_fcs_en)
5018                 netdev->features  &= ~NETIF_F_RXFCS;
5019
5020         /* prefere CQE compression over rxhash */
5021         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
5022                 netdev->features &= ~NETIF_F_RXHASH;
5023
5024 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
5025         if (FT_CAP(flow_modify_en) &&
5026             FT_CAP(modify_root) &&
5027             FT_CAP(identified_miss_table_mode) &&
5028             FT_CAP(flow_table_modify)) {
5029 #ifdef CONFIG_MLX5_ESWITCH
5030                 netdev->hw_features      |= NETIF_F_HW_TC;
5031 #endif
5032 #ifdef CONFIG_MLX5_EN_ARFS
5033                 netdev->hw_features      |= NETIF_F_NTUPLE;
5034 #endif
5035         }
5036
5037         netdev->features         |= NETIF_F_HIGHDMA;
5038         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
5039
5040         netdev->priv_flags       |= IFF_UNICAST_FLT;
5041
5042         mlx5e_set_netdev_dev_addr(netdev);
5043         mlx5e_ipsec_build_netdev(priv);
5044         mlx5e_tls_build_netdev(priv);
5045 }
5046
5047 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5048 {
5049         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
5050         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
5051         struct mlx5_core_dev *mdev = priv->mdev;
5052         int err;
5053
5054         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
5055         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5056         if (!err)
5057                 priv->q_counter =
5058                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5059
5060         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
5061         if (!err)
5062                 priv->drop_rq_q_counter =
5063                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
5064 }
5065
5066 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5067 {
5068         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
5069
5070         MLX5_SET(dealloc_q_counter_in, in, opcode,
5071                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
5072         if (priv->q_counter) {
5073                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5074                          priv->q_counter);
5075                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5076         }
5077
5078         if (priv->drop_rq_q_counter) {
5079                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
5080                          priv->drop_rq_q_counter);
5081                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
5082         }
5083 }
5084
5085 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5086                           struct net_device *netdev,
5087                           const struct mlx5e_profile *profile,
5088                           void *ppriv)
5089 {
5090         struct mlx5e_priv *priv = netdev_priv(netdev);
5091         struct mlx5e_rss_params *rss = &priv->rss_params;
5092         int err;
5093
5094         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5095         if (err)
5096                 return err;
5097
5098         mlx5e_build_nic_params(priv, &priv->xsk, rss, &priv->channels.params,
5099                                netdev->mtu);
5100
5101         mlx5e_timestamp_init(priv);
5102
5103         err = mlx5e_ipsec_init(priv);
5104         if (err)
5105                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5106         err = mlx5e_tls_init(priv);
5107         if (err)
5108                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5109         mlx5e_build_nic_netdev(netdev);
5110         err = mlx5e_devlink_port_register(priv);
5111         if (err)
5112                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5113         mlx5e_health_create_reporters(priv);
5114
5115         return 0;
5116 }
5117
5118 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5119 {
5120         mlx5e_health_destroy_reporters(priv);
5121         mlx5e_devlink_port_unregister(priv);
5122         mlx5e_tls_cleanup(priv);
5123         mlx5e_ipsec_cleanup(priv);
5124         mlx5e_netdev_cleanup(priv->netdev, priv);
5125 }
5126
5127 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5128 {
5129         struct mlx5_core_dev *mdev = priv->mdev;
5130         int err;
5131
5132         mlx5e_create_q_counters(priv);
5133
5134         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5135         if (err) {
5136                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5137                 goto err_destroy_q_counters;
5138         }
5139
5140         err = mlx5e_create_indirect_rqt(priv);
5141         if (err)
5142                 goto err_close_drop_rq;
5143
5144         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5145         if (err)
5146                 goto err_destroy_indirect_rqts;
5147
5148         err = mlx5e_create_indirect_tirs(priv, true);
5149         if (err)
5150                 goto err_destroy_direct_rqts;
5151
5152         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5153         if (err)
5154                 goto err_destroy_indirect_tirs;
5155
5156         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5157         if (unlikely(err))
5158                 goto err_destroy_direct_tirs;
5159
5160         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5161         if (unlikely(err))
5162                 goto err_destroy_xsk_rqts;
5163
5164         err = mlx5e_create_flow_steering(priv);
5165         if (err) {
5166                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5167                 goto err_destroy_xsk_tirs;
5168         }
5169
5170         err = mlx5e_tc_nic_init(priv);
5171         if (err)
5172                 goto err_destroy_flow_steering;
5173
5174         err = mlx5e_accel_init_rx(priv);
5175         if (err)
5176                 goto err_tc_nic_cleanup;
5177
5178 #ifdef CONFIG_MLX5_EN_ARFS
5179         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
5180 #endif
5181
5182         return 0;
5183
5184 err_tc_nic_cleanup:
5185         mlx5e_tc_nic_cleanup(priv);
5186 err_destroy_flow_steering:
5187         mlx5e_destroy_flow_steering(priv);
5188 err_destroy_xsk_tirs:
5189         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5190 err_destroy_xsk_rqts:
5191         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5192 err_destroy_direct_tirs:
5193         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5194 err_destroy_indirect_tirs:
5195         mlx5e_destroy_indirect_tirs(priv);
5196 err_destroy_direct_rqts:
5197         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5198 err_destroy_indirect_rqts:
5199         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5200 err_close_drop_rq:
5201         mlx5e_close_drop_rq(&priv->drop_rq);
5202 err_destroy_q_counters:
5203         mlx5e_destroy_q_counters(priv);
5204         return err;
5205 }
5206
5207 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5208 {
5209         mlx5e_accel_cleanup_rx(priv);
5210         mlx5e_tc_nic_cleanup(priv);
5211         mlx5e_destroy_flow_steering(priv);
5212         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5213         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5214         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5215         mlx5e_destroy_indirect_tirs(priv);
5216         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5217         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5218         mlx5e_close_drop_rq(&priv->drop_rq);
5219         mlx5e_destroy_q_counters(priv);
5220 }
5221
5222 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5223 {
5224         int err;
5225
5226         err = mlx5e_create_tises(priv);
5227         if (err) {
5228                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5229                 return err;
5230         }
5231
5232         mlx5e_dcbnl_initialize(priv);
5233         return 0;
5234 }
5235
5236 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5237 {
5238         struct net_device *netdev = priv->netdev;
5239         struct mlx5_core_dev *mdev = priv->mdev;
5240
5241         mlx5e_init_l2_addr(priv);
5242
5243         /* Marking the link as currently not needed by the Driver */
5244         if (!netif_running(netdev))
5245                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5246
5247         mlx5e_set_netdev_mtu_boundaries(priv);
5248         mlx5e_set_dev_port_mtu(priv);
5249
5250         mlx5_lag_add(mdev, netdev);
5251
5252         mlx5e_enable_async_events(priv);
5253         if (mlx5e_monitor_counter_supported(priv))
5254                 mlx5e_monitor_counter_init(priv);
5255
5256         mlx5e_hv_vhca_stats_create(priv);
5257         if (netdev->reg_state != NETREG_REGISTERED)
5258                 return;
5259         mlx5e_dcbnl_init_app(priv);
5260
5261         queue_work(priv->wq, &priv->set_rx_mode_work);
5262
5263         rtnl_lock();
5264         if (netif_running(netdev))
5265                 mlx5e_open(netdev);
5266         udp_tunnel_nic_reset_ntf(priv->netdev);
5267         netif_device_attach(netdev);
5268         rtnl_unlock();
5269 }
5270
5271 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5272 {
5273         struct mlx5_core_dev *mdev = priv->mdev;
5274
5275         if (priv->netdev->reg_state == NETREG_REGISTERED)
5276                 mlx5e_dcbnl_delete_app(priv);
5277
5278         rtnl_lock();
5279         if (netif_running(priv->netdev))
5280                 mlx5e_close(priv->netdev);
5281         netif_device_detach(priv->netdev);
5282         rtnl_unlock();
5283
5284         queue_work(priv->wq, &priv->set_rx_mode_work);
5285
5286         mlx5e_hv_vhca_stats_destroy(priv);
5287         if (mlx5e_monitor_counter_supported(priv))
5288                 mlx5e_monitor_counter_cleanup(priv);
5289
5290         mlx5e_disable_async_events(priv);
5291         mlx5_lag_remove(mdev);
5292         mlx5_vxlan_reset_to_default(mdev->vxlan);
5293 }
5294
5295 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5296 {
5297         return mlx5e_refresh_tirs(priv, false, false);
5298 }
5299
5300 static const struct mlx5e_profile mlx5e_nic_profile = {
5301         .init              = mlx5e_nic_init,
5302         .cleanup           = mlx5e_nic_cleanup,
5303         .init_rx           = mlx5e_init_nic_rx,
5304         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5305         .init_tx           = mlx5e_init_nic_tx,
5306         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5307         .enable            = mlx5e_nic_enable,
5308         .disable           = mlx5e_nic_disable,
5309         .update_rx         = mlx5e_update_nic_rx,
5310         .update_stats      = mlx5e_stats_update_ndo_stats,
5311         .update_carrier    = mlx5e_update_carrier,
5312         .rx_handlers       = &mlx5e_rx_handlers_nic,
5313         .max_tc            = MLX5E_MAX_NUM_TC,
5314         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5315         .stats_grps        = mlx5e_nic_stats_grps,
5316         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5317 };
5318
5319 /* mlx5e generic netdev management API (move to en_common.c) */
5320
5321 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5322 int mlx5e_netdev_init(struct net_device *netdev,
5323                       struct mlx5e_priv *priv,
5324                       struct mlx5_core_dev *mdev,
5325                       const struct mlx5e_profile *profile,
5326                       void *ppriv)
5327 {
5328         /* priv init */
5329         priv->mdev        = mdev;
5330         priv->netdev      = netdev;
5331         priv->profile     = profile;
5332         priv->ppriv       = ppriv;
5333         priv->msglevel    = MLX5E_MSG_LEVEL;
5334         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5335         priv->max_opened_tc = 1;
5336
5337         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5338                 return -ENOMEM;
5339
5340         mutex_init(&priv->state_lock);
5341         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5342         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5343         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5344         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5345
5346         priv->wq = create_singlethread_workqueue("mlx5e");
5347         if (!priv->wq)
5348                 goto err_free_cpumask;
5349
5350         /* netdev init */
5351         netif_carrier_off(netdev);
5352
5353         return 0;
5354
5355 err_free_cpumask:
5356         free_cpumask_var(priv->scratchpad.cpumask);
5357
5358         return -ENOMEM;
5359 }
5360
5361 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5362 {
5363         destroy_workqueue(priv->wq);
5364         free_cpumask_var(priv->scratchpad.cpumask);
5365 }
5366
5367 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5368                                        const struct mlx5e_profile *profile,
5369                                        int nch,
5370                                        void *ppriv)
5371 {
5372         struct net_device *netdev;
5373         unsigned int ptp_txqs = 0;
5374         int err;
5375
5376         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5377                 ptp_txqs = profile->max_tc;
5378
5379         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5380                                     nch * profile->max_tc + ptp_txqs,
5381                                     nch * profile->rq_groups);
5382         if (!netdev) {
5383                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5384                 return NULL;
5385         }
5386
5387         err = profile->init(mdev, netdev, profile, ppriv);
5388         if (err) {
5389                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5390                 goto err_free_netdev;
5391         }
5392
5393         return netdev;
5394
5395 err_free_netdev:
5396         free_netdev(netdev);
5397
5398         return NULL;
5399 }
5400
5401 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5402 {
5403         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5404         const struct mlx5e_profile *profile;
5405         int max_nch;
5406         int err;
5407
5408         profile = priv->profile;
5409         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5410
5411         /* max number of channels may have changed */
5412         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5413         if (priv->channels.params.num_channels > max_nch) {
5414                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5415                 /* Reducing the number of channels - RXFH has to be reset, and
5416                  * mlx5e_num_channels_changed below will build the RQT.
5417                  */
5418                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5419                 priv->channels.params.num_channels = max_nch;
5420         }
5421         /* 1. Set the real number of queues in the kernel the first time.
5422          * 2. Set our default XPS cpumask.
5423          * 3. Build the RQT.
5424          *
5425          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5426          * netdev has been registered by this point (if this function was called
5427          * in the reload or resume flow).
5428          */
5429         if (take_rtnl)
5430                 rtnl_lock();
5431         err = mlx5e_num_channels_changed(priv);
5432         if (take_rtnl)
5433                 rtnl_unlock();
5434         if (err)
5435                 goto out;
5436
5437         err = profile->init_tx(priv);
5438         if (err)
5439                 goto out;
5440
5441         err = profile->init_rx(priv);
5442         if (err)
5443                 goto err_cleanup_tx;
5444
5445         if (profile->enable)
5446                 profile->enable(priv);
5447
5448         return 0;
5449
5450 err_cleanup_tx:
5451         profile->cleanup_tx(priv);
5452
5453 out:
5454         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5455         cancel_work_sync(&priv->update_stats_work);
5456         return err;
5457 }
5458
5459 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5460 {
5461         const struct mlx5e_profile *profile = priv->profile;
5462
5463         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5464
5465         if (profile->disable)
5466                 profile->disable(priv);
5467         flush_workqueue(priv->wq);
5468
5469         profile->cleanup_rx(priv);
5470         profile->cleanup_tx(priv);
5471         cancel_work_sync(&priv->update_stats_work);
5472 }
5473
5474 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5475 {
5476         const struct mlx5e_profile *profile = priv->profile;
5477         struct net_device *netdev = priv->netdev;
5478
5479         if (profile->cleanup)
5480                 profile->cleanup(priv);
5481         free_netdev(netdev);
5482 }
5483
5484 static int mlx5e_resume(struct auxiliary_device *adev)
5485 {
5486         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5487         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5488         struct net_device *netdev = priv->netdev;
5489         struct mlx5_core_dev *mdev = edev->mdev;
5490         int err;
5491
5492         if (netif_device_present(netdev))
5493                 return 0;
5494
5495         err = mlx5e_create_mdev_resources(mdev);
5496         if (err)
5497                 return err;
5498
5499         err = mlx5e_attach_netdev(priv);
5500         if (err) {
5501                 mlx5e_destroy_mdev_resources(mdev);
5502                 return err;
5503         }
5504
5505         return 0;
5506 }
5507
5508 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5509 {
5510         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5511         struct net_device *netdev = priv->netdev;
5512         struct mlx5_core_dev *mdev = priv->mdev;
5513
5514         if (!netif_device_present(netdev))
5515                 return -ENODEV;
5516
5517         mlx5e_detach_netdev(priv);
5518         mlx5e_destroy_mdev_resources(mdev);
5519         return 0;
5520 }
5521
5522 static int mlx5e_probe(struct auxiliary_device *adev,
5523                        const struct auxiliary_device_id *id)
5524 {
5525         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5526         struct mlx5_core_dev *mdev = edev->mdev;
5527         struct net_device *netdev;
5528         pm_message_t state = {};
5529         void *priv;
5530         int err;
5531         int nch;
5532
5533         nch = mlx5e_get_max_num_channels(mdev);
5534         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5535         if (!netdev) {
5536                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5537                 return -ENOMEM;
5538         }
5539
5540         dev_net_set(netdev, mlx5_core_net(mdev));
5541         priv = netdev_priv(netdev);
5542         dev_set_drvdata(&adev->dev, priv);
5543
5544         err = mlx5e_resume(adev);
5545         if (err) {
5546                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5547                 goto err_destroy_netdev;
5548         }
5549
5550         err = register_netdev(netdev);
5551         if (err) {
5552                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5553                 goto err_resume;
5554         }
5555
5556         mlx5e_devlink_port_type_eth_set(priv);
5557
5558         mlx5e_dcbnl_init_app(priv);
5559         return 0;
5560
5561 err_resume:
5562         mlx5e_suspend(adev, state);
5563 err_destroy_netdev:
5564         mlx5e_destroy_netdev(priv);
5565         return err;
5566 }
5567
5568 static void mlx5e_remove(struct auxiliary_device *adev)
5569 {
5570         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5571         pm_message_t state = {};
5572
5573         mlx5e_dcbnl_delete_app(priv);
5574         unregister_netdev(priv->netdev);
5575         mlx5e_suspend(adev, state);
5576         mlx5e_destroy_netdev(priv);
5577 }
5578
5579 static const struct auxiliary_device_id mlx5e_id_table[] = {
5580         { .name = MLX5_ADEV_NAME ".eth", },
5581         {},
5582 };
5583
5584 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5585
5586 static struct auxiliary_driver mlx5e_driver = {
5587         .name = "eth",
5588         .probe = mlx5e_probe,
5589         .remove = mlx5e_remove,
5590         .suspend = mlx5e_suspend,
5591         .resume = mlx5e_resume,
5592         .id_table = mlx5e_id_table,
5593 };
5594
5595 int mlx5e_init(void)
5596 {
5597         int ret;
5598
5599         mlx5e_ipsec_build_inverse_table();
5600         mlx5e_build_ptys2ethtool_map();
5601         ret = mlx5e_rep_init();
5602         if (ret)
5603                 return ret;
5604
5605         ret = auxiliary_driver_register(&mlx5e_driver);
5606         if (ret)
5607                 mlx5e_rep_cleanup();
5608         return ret;
5609 }
5610
5611 void mlx5e_cleanup(void)
5612 {
5613         auxiliary_driver_unregister(&mlx5e_driver);
5614         mlx5e_rep_cleanup();
5615 }