1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020 HabanaLabs, Ltd.
11 #include <linux/types.h>
12 #include <linux/if_ether.h>
14 #include "hl_boot_if.h"
16 #define NUM_HBM_PSEUDO_CH 2
17 #define NUM_HBM_CH_PER_DEV 8
18 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0
19 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001
20 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1
21 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002
22 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2
23 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004
24 #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3
25 #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008
26 #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4
27 #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010
28 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5
29 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020
30 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6
31 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0
33 #define PLL_MAP_MAX_BITS 128
34 #define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8)
37 * info of the pkt queue pointers in the first async occurrence
39 struct cpucp_pkt_sync_err {
44 struct hl_eq_hbm_ecc_data {
49 /* Supplemental Information according to the mask bits */
51 /* Address in hbm where the ecc happened */
53 /* SERR continuous address counter */
67 struct hl_eq_ecc_data {
70 __u8 memory_wrapper_idx;
74 enum hl_sm_sei_cause {
76 SM_SEI_LBW_4B_UNALIGNED,
77 SM_SEI_AXI_RESPONSE_ERR
80 struct hl_eq_sm_sei_data {
82 /* enum hl_sm_sei_cause */
87 enum hl_fw_alive_severity {
88 FW_ALIVE_SEVERITY_MINOR,
89 FW_ALIVE_SEVERITY_CRITICAL
92 struct hl_eq_fw_alive {
93 __le64 uptime_seconds;
96 /* enum hl_fw_alive_severity */
101 enum hl_pcie_addr_dec_cause {
102 PCIE_ADDR_DEC_HBW_ERR_RESP,
103 PCIE_ADDR_DEC_LBW_ERR_RESP,
104 PCIE_ADDR_DEC_TLP_BLOCKED_BY_RR
107 struct hl_eq_pcie_addr_dec_data {
108 /* enum hl_pcie_addr_dec_cause */
114 struct hl_eq_header hdr;
116 struct hl_eq_ecc_data ecc_data;
117 struct hl_eq_hbm_ecc_data hbm_ecc_data;
118 struct hl_eq_sm_sei_data sm_sei_data;
119 struct cpucp_pkt_sync_err pkt_sync_err;
120 struct hl_eq_fw_alive fw_alive;
121 struct hl_eq_pcie_addr_dec_data pcie_addr_dec_data;
126 #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry)
128 #define EQ_CTL_READY_SHIFT 31
129 #define EQ_CTL_READY_MASK 0x80000000
131 #define EQ_CTL_EVENT_TYPE_SHIFT 16
132 #define EQ_CTL_EVENT_TYPE_MASK 0x0FFF0000
134 #define EQ_CTL_INDEX_SHIFT 0
135 #define EQ_CTL_INDEX_MASK 0x0000FFFF
137 enum pq_init_status {
138 PQ_INIT_STATUS_NA = 0,
139 PQ_INIT_STATUS_READY_FOR_CP,
140 PQ_INIT_STATUS_READY_FOR_HOST,
141 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI,
142 PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR,
143 PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR
147 * CpuCP Primary Queue Packets
149 * During normal operation, the host's kernel driver needs to send various
150 * messages to CpuCP, usually either to SET some value into a H/W periphery or
151 * to GET the current value of some H/W periphery. For example, SET the
152 * frequency of MME/TPC and GET the value of the thermal sensor.
154 * These messages can be initiated either by the User application or by the
155 * host's driver itself, e.g. power management code. In either case, the
156 * communication from the host's driver to CpuCP will *always* be in
157 * synchronous mode, meaning that the host will send a single message and poll
158 * until the message was acknowledged and the results are ready (if results are
161 * This means that only a single message can be sent at a time and the host's
162 * driver must wait for its result before sending the next message. Having said
163 * that, because these are control messages which are sent in a relatively low
164 * frequency, this limitation seems acceptable. It's important to note that
165 * in case of multiple devices, messages to different devices *can* be sent
168 * The message, inputs/outputs (if relevant) and fence object will be located
169 * on the device DDR at an address that will be determined by the host's driver.
170 * During device initialization phase, the host will pass to CpuCP that address.
171 * Most of the message types will contain inputs/outputs inside the message
172 * itself. The common part of each message will contain the opcode of the
173 * message (its type) and a field representing a fence object.
175 * When the host's driver wishes to send a message to CPU CP, it will write the
176 * message contents to the device DDR, clear the fence object and then write to
177 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU.
179 * Upon receiving the interrupt (#121), CpuCP will read the message from the
180 * DDR. In case the message is a SET operation, CpuCP will first perform the
181 * operation and then write to the fence object on the device DDR. In case the
182 * message is a GET operation, CpuCP will first fill the results section on the
183 * device DDR and then write to the fence object. If an error occurred, CpuCP
184 * will fill the rc field with the right error code.
186 * In the meantime, the host's driver will poll on the fence object. Once the
187 * host sees that the fence object is signaled, it will read the results from
188 * the device DDR (if relevant) and resume the code execution in the host's
191 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8
192 * so the value being put by the host's driver matches the value read by CpuCP
194 * Non-QMAN packets should be limited to values 1 through (2^8 - 1)
196 * Detailed description:
198 * CPUCP_PACKET_DISABLE_PCI_ACCESS -
199 * After receiving this packet the embedded CPU must NOT issue PCI
200 * transactions (read/write) towards the Host CPU. This also include
201 * sending MSI-X interrupts.
202 * This packet is usually sent before the device is moved to D3Hot state.
204 * CPUCP_PACKET_ENABLE_PCI_ACCESS -
205 * After receiving this packet the embedded CPU is allowed to issue PCI
206 * transactions towards the Host CPU, including sending MSI-X interrupts.
207 * This packet is usually send after the device is moved to D0 state.
209 * CPUCP_PACKET_TEMPERATURE_GET -
210 * Fetch the current temperature / Max / Max Hyst / Critical /
211 * Critical Hyst of a specified thermal sensor. The packet's
212 * arguments specify the desired sensor and the field to get.
214 * CPUCP_PACKET_VOLTAGE_GET -
215 * Fetch the voltage / Max / Min of a specified sensor. The packet's
216 * arguments specify the sensor and type.
218 * CPUCP_PACKET_CURRENT_GET -
219 * Fetch the current / Max / Min of a specified sensor. The packet's
220 * arguments specify the sensor and type.
222 * CPUCP_PACKET_FAN_SPEED_GET -
223 * Fetch the speed / Max / Min of a specified fan. The packet's
224 * arguments specify the sensor and type.
226 * CPUCP_PACKET_PWM_GET -
227 * Fetch the pwm value / mode of a specified pwm. The packet's
228 * arguments specify the sensor and type.
230 * CPUCP_PACKET_PWM_SET -
231 * Set the pwm value / mode of a specified pwm. The packet's
232 * arguments specify the sensor, type and value.
234 * CPUCP_PACKET_FREQUENCY_SET -
235 * Set the frequency of a specified PLL. The packet's arguments specify
236 * the PLL and the desired frequency. The actual frequency in the device
237 * might differ from the requested frequency.
239 * CPUCP_PACKET_FREQUENCY_GET -
240 * Fetch the frequency of a specified PLL. The packet's arguments specify
243 * CPUCP_PACKET_LED_SET -
244 * Set the state of a specified led. The packet's arguments
245 * specify the led and the desired state.
247 * CPUCP_PACKET_I2C_WR -
248 * Write 32-bit value to I2C device. The packet's arguments specify the
249 * I2C bus, address and value.
251 * CPUCP_PACKET_I2C_RD -
252 * Read 32-bit value from I2C device. The packet's arguments specify the
253 * I2C bus and address.
255 * CPUCP_PACKET_INFO_GET -
256 * Fetch information from the device as specified in the packet's
257 * structure. The host's driver passes the max size it allows the CpuCP to
258 * write to the structure, to prevent data corruption in case of
259 * mismatched driver/FW versions.
261 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed
263 * CPUCP_PACKET_UNMASK_RAZWI_IRQ -
264 * Unmask the given IRQ. The IRQ number is specified in the value field.
265 * The packet is sent after receiving an interrupt and printing its
266 * relevant information.
268 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY -
269 * Unmask the given IRQs. The IRQs numbers are specified in an array right
270 * after the cpucp_packet structure, where its first element is the array
271 * length. The packet is sent after a soft reset was done in order to
272 * handle any interrupts that were sent during the reset process.
274 * CPUCP_PACKET_TEST -
275 * Test packet for CpuCP connectivity. The CPU will put the fence value
276 * in the result field.
278 * CPUCP_PACKET_FREQUENCY_CURR_GET -
279 * Fetch the current frequency of a specified PLL. The packet's arguments
282 * CPUCP_PACKET_MAX_POWER_GET -
283 * Fetch the maximal power of the device.
285 * CPUCP_PACKET_MAX_POWER_SET -
286 * Set the maximal power of the device. The packet's arguments specify
289 * CPUCP_PACKET_EEPROM_DATA_GET -
290 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the
291 * addr field. The CPU will put the returned data size in the result
292 * field. In addition, the host's driver passes the max size it allows the
293 * CpuCP to write to the structure, to prevent data corruption in case of
294 * mismatched driver/FW versions.
296 * CPUCP_PACKET_NIC_INFO_GET -
297 * Fetch information from the device regarding the NIC. the host's driver
298 * passes the max size it allows the CpuCP to write to the structure, to
299 * prevent data corruption in case of mismatched driver/FW versions.
301 * CPUCP_PACKET_TEMPERATURE_SET -
302 * Set the value of the offset property of a specified thermal sensor.
303 * The packet's arguments specify the desired sensor and the field to
306 * CPUCP_PACKET_VOLTAGE_SET -
307 * Trigger the reset_history property of a specified voltage sensor.
308 * The packet's arguments specify the desired sensor and the field to
311 * CPUCP_PACKET_CURRENT_SET -
312 * Trigger the reset_history property of a specified current sensor.
313 * The packet's arguments specify the desired sensor and the field to
316 * CPUCP_PACKET_PCIE_THROUGHPUT_GET -
317 * Get throughput of PCIe.
318 * The packet's arguments specify the transaction direction (TX/RX).
319 * The window measurement is 10[msec], and the return value is in KB/sec.
321 * CPUCP_PACKET_PCIE_REPLAY_CNT_GET
322 * Replay count measures number of "replay" events, which is basicly
323 * number of retries done by PCIe.
325 * CPUCP_PACKET_TOTAL_ENERGY_GET -
326 * Total Energy is measurement of energy from the time FW Linux
327 * is loaded. It is calculated by multiplying the average power
328 * by time (passed from armcp start). The units are in MilliJouls.
330 * CPUCP_PACKET_PLL_INFO_GET -
331 * Fetch frequencies of PLL from the required PLL IP.
332 * The packet's arguments specify the device PLL type
333 * Pll type is the PLL from device pll_index enum.
334 * The result is composed of 4 outputs, each is 16-bit
337 * CPUCP_PACKET_POWER_GET -
338 * Fetch the present power consumption of the device (Current * Voltage).
340 * CPUCP_PACKET_NIC_PFC_SET -
341 * Enable/Disable the NIC PFC feature. The packet's arguments specify the
342 * NIC port, relevant lanes to configure and one bit indication for
345 * CPUCP_PACKET_NIC_FAULT_GET -
346 * Fetch the current indication for local/remote faults from the NIC MAC.
347 * The result is 32-bit value of the relevant register.
349 * CPUCP_PACKET_NIC_LPBK_SET -
350 * Enable/Disable the MAC loopback feature. The packet's arguments specify
351 * the NIC port, relevant lanes to configure and one bit indication for
354 * CPUCP_PACKET_NIC_MAC_INIT -
355 * Configure the NIC MAC channels. The packet's arguments specify the
356 * NIC port and the speed.
358 * CPUCP_PACKET_MSI_INFO_SET -
359 * set the index number for each supported msi type going from
362 * CPUCP_PACKET_NIC_XPCS91_REGS_GET -
363 * Fetch the un/correctable counters values from the NIC MAC.
365 * CPUCP_PACKET_NIC_STAT_REGS_GET -
366 * Fetch various NIC MAC counters from the NIC STAT.
368 * CPUCP_PACKET_NIC_STAT_REGS_CLR -
369 * Clear the various NIC MAC counters in the NIC STAT.
371 * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET -
372 * Fetch all NIC MAC counters from the NIC STAT.
374 * CPUCP_PACKET_IS_IDLE_CHECK -
375 * Check if the device is IDLE in regard to the DMA/compute engines
376 * and QMANs. The f/w will return a bitmask where each bit represents
377 * a different engine or QMAN according to enum cpucp_idle_mask.
378 * The bit will be 1 if the engine is NOT idle.
381 enum cpucp_packet_id {
382 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */
383 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */
384 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */
385 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */
386 CPUCP_PACKET_CURRENT_GET, /* sysfs */
387 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */
388 CPUCP_PACKET_PWM_GET, /* sysfs */
389 CPUCP_PACKET_PWM_SET, /* sysfs */
390 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */
391 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */
392 CPUCP_PACKET_LED_SET, /* debugfs */
393 CPUCP_PACKET_I2C_WR, /* debugfs */
394 CPUCP_PACKET_I2C_RD, /* debugfs */
395 CPUCP_PACKET_INFO_GET, /* IOCTL */
396 CPUCP_PACKET_FLASH_PROGRAM_REMOVED,
397 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */
398 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */
399 CPUCP_PACKET_TEST, /* internal */
400 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */
401 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */
402 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */
403 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */
404 CPUCP_PACKET_NIC_INFO_GET, /* internal */
405 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */
406 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */
407 CPUCP_PACKET_CURRENT_SET, /* sysfs */
408 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */
409 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */
410 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */
411 CPUCP_PACKET_PLL_INFO_GET, /* internal */
412 CPUCP_PACKET_NIC_STATUS, /* internal */
413 CPUCP_PACKET_POWER_GET, /* internal */
414 CPUCP_PACKET_NIC_PFC_SET, /* internal */
415 CPUCP_PACKET_NIC_FAULT_GET, /* internal */
416 CPUCP_PACKET_NIC_LPBK_SET, /* internal */
417 CPUCP_PACKET_NIC_MAC_CFG, /* internal */
418 CPUCP_PACKET_MSI_INFO_SET, /* internal */
419 CPUCP_PACKET_NIC_XPCS91_REGS_GET, /* internal */
420 CPUCP_PACKET_NIC_STAT_REGS_GET, /* internal */
421 CPUCP_PACKET_NIC_STAT_REGS_CLR, /* internal */
422 CPUCP_PACKET_NIC_STAT_REGS_ALL_GET, /* internal */
423 CPUCP_PACKET_IS_IDLE_CHECK, /* internal */
426 #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5
428 #define CPUCP_PKT_CTL_RC_SHIFT 12
429 #define CPUCP_PKT_CTL_RC_MASK 0x0000F000
431 #define CPUCP_PKT_CTL_OPCODE_SHIFT 16
432 #define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000
434 #define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0
435 #define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull
436 #define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16
437 #define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull
438 #define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32
439 #define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull
440 #define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48
441 #define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull
443 #define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0
444 #define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull
445 #define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1
446 #define CPUCP_PKT_VAL_PFC_IN2_MASK 0x000000000000001Eull
448 #define CPUCP_PKT_VAL_LPBK_IN1_SHIFT 0
449 #define CPUCP_PKT_VAL_LPBK_IN1_MASK 0x0000000000000001ull
450 #define CPUCP_PKT_VAL_LPBK_IN2_SHIFT 1
451 #define CPUCP_PKT_VAL_LPBK_IN2_MASK 0x000000000000001Eull
453 #define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT 0
454 #define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK 0x0000000000000001ull
455 #define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT 1
456 #define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK 0x00000000FFFFFFFEull
458 /* heartbeat status bits */
459 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT 0
460 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK 0x00000001
462 struct cpucp_packet {
464 __le64 value; /* For SET packets */
465 __le64 result; /* For GET packets */
466 __le64 addr; /* For PQ */
471 __le32 fence; /* Signal to host that message is completed */
474 struct {/* For temperature/current/voltage/fan/pwm get/set */
479 struct { /* For I2C read/write */
483 __u8 pad; /* unused */
486 struct {/* For PLL info fetch */
488 /* TODO pll_reg is kept temporary before removal */
492 /* For any general request */
495 /* For frequency get/set */
501 /* For get CpuCP info/EEPROM data/NIC info */
502 __le32 data_max_size;
505 * For any general status bitmask. Shall be used whenever the
506 * result cannot be used to hold general purpose data.
511 /* For NIC requests */
515 struct cpucp_unmask_irq_arr_packet {
516 struct cpucp_packet cpucp_pkt;
521 struct cpucp_nic_status_packet {
522 struct cpucp_packet cpucp_pkt;
527 struct cpucp_array_data_packet {
528 struct cpucp_packet cpucp_pkt;
533 enum cpucp_packet_rc {
534 cpucp_packet_success,
535 cpucp_packet_invalid,
540 * cpucp_temp_type should adhere to hwmon_temp_attributes
541 * defined in Linux kernel hwmon.h file
543 enum cpucp_temp_type {
548 cpucp_temp_crit_hyst,
549 cpucp_temp_offset = 19,
550 cpucp_temp_highest = 22,
551 cpucp_temp_reset_history = 23
554 enum cpucp_in_attributes {
558 cpucp_in_highest = 7,
559 cpucp_in_reset_history
562 enum cpucp_curr_attributes {
566 cpucp_curr_highest = 7,
567 cpucp_curr_reset_history
570 enum cpucp_fan_attributes {
576 enum cpucp_pwm_attributes {
581 enum cpucp_pcie_throughput_attributes {
582 cpucp_pcie_throughput_tx,
583 cpucp_pcie_throughput_rx
586 /* TODO temporary kept before removal */
587 enum cpucp_pll_reg_attributes {
591 cpucp_pll_div_factor_reg,
592 cpucp_pll_div_sel_reg
595 /* TODO temporary kept before removal */
596 enum cpucp_pll_type_attributes {
602 * MSI type enumeration table for all ASICs and future SW versions.
603 * For future ASIC-LKD compatibility, we can only add new enumerations.
604 * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES).
605 * Changing the order of entries or removing entries is not allowed.
607 enum cpucp_msi_type {
608 CPUCP_EVENT_QUEUE_MSI_TYPE,
609 CPUCP_NIC_PORT1_MSI_TYPE,
610 CPUCP_NIC_PORT3_MSI_TYPE,
611 CPUCP_NIC_PORT5_MSI_TYPE,
612 CPUCP_NIC_PORT7_MSI_TYPE,
613 CPUCP_NIC_PORT9_MSI_TYPE,
614 CPUCP_NUM_OF_MSI_TYPES
618 * PLL enumeration table used for all ASICs and future SW versions.
619 * For future ASIC-LKD compatibility, we can only add new enumerations.
620 * at the end of the table.
621 * Changing the order of entries or removing entries is not allowed.
658 /* Event Queue Packets */
660 struct eq_generic_event {
668 #define CARD_NAME_MAX_LEN 16
669 #define CPUCP_MAX_SENSORS 128
670 #define CPUCP_MAX_NICS 128
671 #define CPUCP_LANES_PER_NIC 4
672 #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024
673 #define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC)
674 #define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64)
675 #define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64)
677 struct cpucp_sensor {
683 * struct cpucp_card_types - ASIC card type.
684 * @cpucp_card_type_pci: PCI card.
685 * @cpucp_card_type_pmc: PCI Mezzanine Card.
687 enum cpucp_card_types {
692 #define CPUCP_SEC_CONF_ENABLED_SHIFT 0
693 #define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001
695 #define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1
696 #define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002
698 #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2
699 #define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004
702 * struct cpucp_security_info - Security information.
703 * @config: configuration bit field
704 * @keys_num: number of stored keys
705 * @revoked_keys: revoked keys bit field
706 * @min_svn: minimal security version
708 struct cpucp_security_info {
716 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver
717 * @sensors: available sensors description.
718 * @kernel_version: CpuCP linux kernel version.
719 * @reserved: reserved field.
720 * @card_type: card configuration type.
721 * @card_location: in a server, each card has different connections topology
722 * depending on its location (relevant for PMC card type)
723 * @cpld_version: CPLD programmed F/W version.
724 * @infineon_version: Infineon main DC-DC version.
725 * @fuse_version: silicon production FUSE information.
726 * @thermal_version: thermald S/W version.
727 * @cpucp_version: CpuCP S/W version.
728 * @dram_size: available DRAM size.
729 * @card_name: card name that will be displayed in HWMON subsystem on the host
730 * @sec_info: security information
731 * @pll_map: Bit map of supported PLLs for current ASIC version.
732 * @mme_binning_mask: MME binning mask,
733 * (0 = functional, 1 = binned)
736 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS];
737 __u8 kernel_version[VERSION_MAX_LEN];
740 __le32 card_location;
742 __le32 infineon_version;
743 __u8 fuse_version[VERSION_MAX_LEN];
744 __u8 thermal_version[VERSION_MAX_LEN];
745 __u8 cpucp_version[VERSION_MAX_LEN];
748 char card_name[CARD_NAME_MAX_LEN];
753 struct cpucp_security_info sec_info;
755 __u8 pll_map[PLL_MAP_LEN];
756 __le64 mme_binning_mask;
759 struct cpucp_mac_addr {
760 __u8 mac_addr[ETH_ALEN];
763 enum cpucp_serdes_type {
769 MAX_NUM_SERDES_TYPE = UNKNOWN_SERDES_TYPE
772 struct cpucp_nic_info {
773 struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS];
774 __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN];
775 __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
776 __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
777 __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN];
778 __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN];
779 __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN];
780 __le16 serdes_type; /* enum cpucp_serdes_type */
785 * struct cpucp_nic_status - describes the status of a NIC port.
786 * @port: NIC port index.
787 * @bad_format_cnt: e.g. CRC.
788 * @responder_out_of_sequence_psn_cnt: e.g NAK.
789 * @high_ber_reinit_cnt: link reinit due to high BER.
790 * @correctable_err_cnt: e.g. bit-flip.
791 * @uncorrectable_err_cnt: e.g. MAC errors.
792 * @retraining_cnt: re-training counter.
794 * @pcs_link: has PCS link.
795 * @phy_ready: is PHY ready.
796 * @auto_neg: is Autoneg enabled.
797 * @timeout_retransmission_cnt: timeout retransmission events
798 * @high_ber_cnt: high ber events
800 struct cpucp_nic_status {
802 __le32 bad_format_cnt;
803 __le32 responder_out_of_sequence_psn_cnt;
804 __le32 high_ber_reinit;
805 __le32 correctable_err_cnt;
806 __le32 uncorrectable_err_cnt;
807 __le32 retraining_cnt;
812 __le32 timeout_retransmission_cnt;
816 #endif /* CPUCP_IF_H */