1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2020 HabanaLabs, Ltd.
9 #include "../include/hw_ip/mmu/mmu_general.h"
10 #include "../include/hw_ip/mmu/mmu_v1_1.h"
11 #include "../include/gaudi/gaudi_masks.h"
12 #include "../include/gaudi/gaudi_fw_if.h"
13 #include "../include/gaudi/gaudi_reg_map.h"
14 #include "../include/gaudi/gaudi_async_ids_map_extended.h"
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/firmware.h>
19 #include <linux/hwmon.h>
20 #include <linux/iommu.h>
21 #include <linux/seq_file.h>
24 * Gaudi security scheme:
26 * 1. Host is protected by:
30 * 2. DDR is protected by:
31 * - Range registers (protect the first 512MB)
33 * 3. Configuration is protected by:
37 * MMU is always enabled.
39 * QMAN DMA channels 0,1 (PCI DMAN):
40 * - DMA is not secured.
41 * - PQ and CQ are secured.
42 * - CP is secured: The driver needs to parse CB but WREG should be allowed
43 * because of TDMA (tensor DMA). Hence, WREG is always not
46 * When the driver needs to use DMA it will check that Gaudi is idle, set DMA
47 * channel 0 to be secured, execute the DMA and change it back to not secured.
48 * Currently, the driver doesn't use the DMA while there are compute jobs
51 * The current use cases for the driver to use the DMA are:
52 * - Clear SRAM on context switch (happens on context switch when device is
54 * - MMU page tables area clear (happens on init)
56 * QMAN DMA 2-7, TPC, MME, NIC:
57 * PQ is secured and is located on the Host (HBM CON TPC3 bug)
58 * CQ, CP and the engine are not secured
62 #define GAUDI_BOOT_FIT_FILE "habanalabs/gaudi/gaudi-boot-fit.itb"
63 #define GAUDI_LINUX_FW_FILE "habanalabs/gaudi/gaudi-fit.itb"
64 #define GAUDI_TPC_FW_FILE "habanalabs/gaudi/gaudi_tpc.bin"
66 #define GAUDI_DMA_POOL_BLK_SIZE 0x100 /* 256 bytes */
68 #define GAUDI_RESET_TIMEOUT_MSEC 2000 /* 2000ms */
69 #define GAUDI_RESET_WAIT_MSEC 1 /* 1ms */
70 #define GAUDI_CPU_RESET_WAIT_MSEC 200 /* 200ms */
71 #define GAUDI_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */
73 #define GAUDI_PLDM_RESET_WAIT_MSEC 1000 /* 1s */
74 #define GAUDI_PLDM_HRESET_TIMEOUT_MSEC 20000 /* 20s */
75 #define GAUDI_PLDM_TEST_QUEUE_WAIT_USEC 1000000 /* 1s */
76 #define GAUDI_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100)
77 #define GAUDI_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30)
78 #define GAUDI_PLDM_TPC_KERNEL_WAIT_USEC (HL_DEVICE_TIMEOUT_USEC * 30)
79 #define GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC 4000000 /* 4s */
80 #define GAUDI_MSG_TO_CPU_TIMEOUT_USEC 4000000 /* 4s */
81 #define GAUDI_WAIT_FOR_BL_TIMEOUT_USEC 15000000 /* 15s */
83 #define GAUDI_QMAN0_FENCE_VAL 0x72E91AB9
85 #define GAUDI_MAX_STRING_LEN 20
87 #define GAUDI_CB_POOL_CB_CNT 512
88 #define GAUDI_CB_POOL_CB_SIZE 0x20000 /* 128KB */
90 #define GAUDI_ALLOC_CPU_MEM_RETRY_CNT 3
92 #define GAUDI_NUM_OF_TPC_INTR_CAUSE 20
94 #define GAUDI_NUM_OF_QM_ERR_CAUSE 16
96 #define GAUDI_NUM_OF_QM_ARB_ERR_CAUSE 3
98 #define GAUDI_ARB_WDT_TIMEOUT 0x1000000
100 #define GAUDI_CLK_GATE_DEBUGFS_MASK (\
101 BIT(GAUDI_ENGINE_ID_MME_0) |\
102 BIT(GAUDI_ENGINE_ID_MME_2) |\
103 GENMASK_ULL(GAUDI_ENGINE_ID_TPC_7, GAUDI_ENGINE_ID_TPC_0))
105 #define HBM_SCRUBBING_TIMEOUT_US 1000000 /* 1s */
107 #define GAUDI_PLL_MAX 10
109 #define BIN_REG_STRING_SIZE sizeof("0b10101010101010101010101010101010")
111 #define MONITOR_SOB_STRING_SIZE 256
113 static u32 gaudi_stream_master[GAUDI_STREAM_MASTER_ARR_SIZE] = {
114 GAUDI_QUEUE_ID_DMA_0_0,
115 GAUDI_QUEUE_ID_DMA_0_1,
116 GAUDI_QUEUE_ID_DMA_0_2,
117 GAUDI_QUEUE_ID_DMA_0_3,
118 GAUDI_QUEUE_ID_DMA_1_0,
119 GAUDI_QUEUE_ID_DMA_1_1,
120 GAUDI_QUEUE_ID_DMA_1_2,
121 GAUDI_QUEUE_ID_DMA_1_3
124 static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = {
125 "gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3",
126 "gaudi cq 1_0", "gaudi cq 1_1", "gaudi cq 1_2", "gaudi cq 1_3",
127 "gaudi cq 5_0", "gaudi cq 5_1", "gaudi cq 5_2", "gaudi cq 5_3",
131 static const u8 gaudi_dma_assignment[GAUDI_DMA_MAX] = {
132 [GAUDI_PCI_DMA_1] = GAUDI_ENGINE_ID_DMA_0,
133 [GAUDI_PCI_DMA_2] = GAUDI_ENGINE_ID_DMA_1,
134 [GAUDI_HBM_DMA_1] = GAUDI_ENGINE_ID_DMA_2,
135 [GAUDI_HBM_DMA_2] = GAUDI_ENGINE_ID_DMA_3,
136 [GAUDI_HBM_DMA_3] = GAUDI_ENGINE_ID_DMA_4,
137 [GAUDI_HBM_DMA_4] = GAUDI_ENGINE_ID_DMA_5,
138 [GAUDI_HBM_DMA_5] = GAUDI_ENGINE_ID_DMA_6,
139 [GAUDI_HBM_DMA_6] = GAUDI_ENGINE_ID_DMA_7
142 static const u8 gaudi_cq_assignment[NUMBER_OF_CMPLT_QUEUES] = {
143 [0] = GAUDI_QUEUE_ID_DMA_0_0,
144 [1] = GAUDI_QUEUE_ID_DMA_0_1,
145 [2] = GAUDI_QUEUE_ID_DMA_0_2,
146 [3] = GAUDI_QUEUE_ID_DMA_0_3,
147 [4] = GAUDI_QUEUE_ID_DMA_1_0,
148 [5] = GAUDI_QUEUE_ID_DMA_1_1,
149 [6] = GAUDI_QUEUE_ID_DMA_1_2,
150 [7] = GAUDI_QUEUE_ID_DMA_1_3,
153 static const u16 gaudi_packet_sizes[MAX_PACKET_ID] = {
154 [PACKET_WREG_32] = sizeof(struct packet_wreg32),
155 [PACKET_WREG_BULK] = sizeof(struct packet_wreg_bulk),
156 [PACKET_MSG_LONG] = sizeof(struct packet_msg_long),
157 [PACKET_MSG_SHORT] = sizeof(struct packet_msg_short),
158 [PACKET_CP_DMA] = sizeof(struct packet_cp_dma),
159 [PACKET_REPEAT] = sizeof(struct packet_repeat),
160 [PACKET_MSG_PROT] = sizeof(struct packet_msg_prot),
161 [PACKET_FENCE] = sizeof(struct packet_fence),
162 [PACKET_LIN_DMA] = sizeof(struct packet_lin_dma),
163 [PACKET_NOP] = sizeof(struct packet_nop),
164 [PACKET_STOP] = sizeof(struct packet_stop),
165 [PACKET_ARB_POINT] = sizeof(struct packet_arb_point),
166 [PACKET_WAIT] = sizeof(struct packet_wait),
167 [PACKET_LOAD_AND_EXE] = sizeof(struct packet_load_and_exe)
170 static inline bool validate_packet_id(enum packet_id id)
174 case PACKET_WREG_BULK:
175 case PACKET_MSG_LONG:
176 case PACKET_MSG_SHORT:
179 case PACKET_MSG_PROT:
184 case PACKET_ARB_POINT:
186 case PACKET_LOAD_AND_EXE:
193 static const char * const
194 gaudi_tpc_interrupts_cause[GAUDI_NUM_OF_TPC_INTR_CAUSE] = {
195 "tpc_address_exceed_slm",
197 "tpc_spu_mac_overflow",
198 "tpc_spu_addsub_overflow",
199 "tpc_spu_abs_overflow",
200 "tpc_spu_fp_dst_nan_inf",
201 "tpc_spu_fp_dst_denorm",
202 "tpc_vpu_mac_overflow",
203 "tpc_vpu_addsub_overflow",
204 "tpc_vpu_abs_overflow",
205 "tpc_vpu_fp_dst_nan_inf",
206 "tpc_vpu_fp_dst_denorm",
208 "tpc_illegal_instruction",
209 "tpc_pc_wrap_around",
217 static const char * const
218 gaudi_qman_error_cause[GAUDI_NUM_OF_QM_ERR_CAUSE] = {
222 "CP error due to undefined OPCODE",
223 "CP encountered STOP OPCODE",
225 "CP WRREG32 or WRBULK returned error",
227 "FENCE 0 inc over max value and clipped",
228 "FENCE 1 inc over max value and clipped",
229 "FENCE 2 inc over max value and clipped",
230 "FENCE 3 inc over max value and clipped",
231 "FENCE 0 dec under min value and clipped",
232 "FENCE 1 dec under min value and clipped",
233 "FENCE 2 dec under min value and clipped",
234 "FENCE 3 dec under min value and clipped"
237 static const char * const
238 gaudi_qman_arb_error_cause[GAUDI_NUM_OF_QM_ARB_ERR_CAUSE] = {
239 "Choice push while full error",
240 "Choice Q watchdog error",
241 "MSG AXI LBW returned with error"
244 enum gaudi_sm_sei_cause {
245 GAUDI_SM_SEI_SO_OVERFLOW,
246 GAUDI_SM_SEI_LBW_4B_UNALIGNED,
247 GAUDI_SM_SEI_AXI_RESPONSE_ERR
250 static enum hl_queue_type gaudi_queue_type[GAUDI_QUEUE_ID_SIZE] = {
251 QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_0 */
252 QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_1 */
253 QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_2 */
254 QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_3 */
255 QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_0 */
256 QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_1 */
257 QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_2 */
258 QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_3 */
259 QUEUE_TYPE_CPU, /* GAUDI_QUEUE_ID_CPU_PQ */
260 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_0 */
261 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_1 */
262 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_2 */
263 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_3 */
264 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_0 */
265 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_1 */
266 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_2 */
267 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_3 */
268 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_0 */
269 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_1 */
270 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_2 */
271 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_3 */
272 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_0 */
273 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_1 */
274 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_2 */
275 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_5_3 */
276 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_0 */
277 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_1 */
278 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_2 */
279 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_3 */
280 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_0 */
281 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_1 */
282 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_2 */
283 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_3 */
284 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_0 */
285 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_1 */
286 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_2 */
287 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_3 */
288 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_0 */
289 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_1 */
290 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_2 */
291 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_3 */
292 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_0 */
293 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_1 */
294 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_2 */
295 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_3 */
296 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_0 */
297 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_1 */
298 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_2 */
299 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_3 */
300 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_0 */
301 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_1 */
302 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_2 */
303 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_3 */
304 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_0 */
305 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_1 */
306 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_2 */
307 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_3 */
308 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_0 */
309 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_1 */
310 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_2 */
311 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_3 */
312 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_0 */
313 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_1 */
314 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_2 */
315 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_3 */
316 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_0 */
317 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_1 */
318 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_2 */
319 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_3 */
320 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_0 */
321 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_1 */
322 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_2 */
323 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_3 */
324 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_0_0 */
325 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_0_1 */
326 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_0_2 */
327 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_0_3 */
328 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_1_0 */
329 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_1_1 */
330 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_1_2 */
331 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_1_3 */
332 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_2_0 */
333 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_2_1 */
334 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_2_2 */
335 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_2_3 */
336 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_3_0 */
337 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_3_1 */
338 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_3_2 */
339 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_3_3 */
340 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_4_0 */
341 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_4_1 */
342 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_4_2 */
343 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_4_3 */
344 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_5_0 */
345 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_5_1 */
346 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_5_2 */
347 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_5_3 */
348 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_6_0 */
349 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_6_1 */
350 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_6_2 */
351 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_6_3 */
352 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_7_0 */
353 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_7_1 */
354 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_7_2 */
355 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_7_3 */
356 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_8_0 */
357 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_8_1 */
358 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_8_2 */
359 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_8_3 */
360 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_9_0 */
361 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_9_1 */
362 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_9_2 */
363 QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_NIC_9_3 */
366 static struct hl_hw_obj_name_entry gaudi_so_id_to_str[] = {
367 { .id = 0, .name = "SYNC_OBJ_DMA_DOWN_FEEDBACK" },
368 { .id = 1, .name = "SYNC_OBJ_DMA_UP_FEEDBACK" },
369 { .id = 2, .name = "SYNC_OBJ_DMA_STATIC_DRAM_SRAM_FEEDBACK" },
370 { .id = 3, .name = "SYNC_OBJ_DMA_SRAM_DRAM_FEEDBACK" },
371 { .id = 4, .name = "SYNC_OBJ_FIRST_COMPUTE_FINISH" },
372 { .id = 5, .name = "SYNC_OBJ_HOST_DRAM_DONE" },
373 { .id = 6, .name = "SYNC_OBJ_DBG_CTR_DEPRECATED" },
374 { .id = 7, .name = "SYNC_OBJ_DMA_ACTIVATIONS_DRAM_SRAM_FEEDBACK" },
375 { .id = 8, .name = "SYNC_OBJ_ENGINE_SEM_MME_0" },
376 { .id = 9, .name = "SYNC_OBJ_ENGINE_SEM_MME_1" },
377 { .id = 10, .name = "SYNC_OBJ_ENGINE_SEM_TPC_0" },
378 { .id = 11, .name = "SYNC_OBJ_ENGINE_SEM_TPC_1" },
379 { .id = 12, .name = "SYNC_OBJ_ENGINE_SEM_TPC_2" },
380 { .id = 13, .name = "SYNC_OBJ_ENGINE_SEM_TPC_3" },
381 { .id = 14, .name = "SYNC_OBJ_ENGINE_SEM_TPC_4" },
382 { .id = 15, .name = "SYNC_OBJ_ENGINE_SEM_TPC_5" },
383 { .id = 16, .name = "SYNC_OBJ_ENGINE_SEM_TPC_6" },
384 { .id = 17, .name = "SYNC_OBJ_ENGINE_SEM_TPC_7" },
385 { .id = 18, .name = "SYNC_OBJ_ENGINE_SEM_DMA_1" },
386 { .id = 19, .name = "SYNC_OBJ_ENGINE_SEM_DMA_2" },
387 { .id = 20, .name = "SYNC_OBJ_ENGINE_SEM_DMA_3" },
388 { .id = 21, .name = "SYNC_OBJ_ENGINE_SEM_DMA_4" },
389 { .id = 22, .name = "SYNC_OBJ_ENGINE_SEM_DMA_5" },
390 { .id = 23, .name = "SYNC_OBJ_ENGINE_SEM_DMA_6" },
391 { .id = 24, .name = "SYNC_OBJ_ENGINE_SEM_DMA_7" },
392 { .id = 25, .name = "SYNC_OBJ_DBG_CTR_0" },
393 { .id = 26, .name = "SYNC_OBJ_DBG_CTR_1" },
396 static struct hl_hw_obj_name_entry gaudi_monitor_id_to_str[] = {
397 { .id = 200, .name = "MON_OBJ_DMA_DOWN_FEEDBACK_RESET" },
398 { .id = 201, .name = "MON_OBJ_DMA_UP_FEADBACK_RESET" },
399 { .id = 203, .name = "MON_OBJ_DRAM_TO_SRAM_QUEUE_FENCE" },
400 { .id = 204, .name = "MON_OBJ_TPC_0_CLK_GATE" },
401 { .id = 205, .name = "MON_OBJ_TPC_1_CLK_GATE" },
402 { .id = 206, .name = "MON_OBJ_TPC_2_CLK_GATE" },
403 { .id = 207, .name = "MON_OBJ_TPC_3_CLK_GATE" },
404 { .id = 208, .name = "MON_OBJ_TPC_4_CLK_GATE" },
405 { .id = 209, .name = "MON_OBJ_TPC_5_CLK_GATE" },
406 { .id = 210, .name = "MON_OBJ_TPC_6_CLK_GATE" },
407 { .id = 211, .name = "MON_OBJ_TPC_7_CLK_GATE" },
410 static s64 gaudi_state_dump_specs_props[] = {
411 [SP_SYNC_OBJ_BASE_ADDR] = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0,
412 [SP_NEXT_SYNC_OBJ_ADDR] = NEXT_SYNC_OBJ_ADDR_INTERVAL,
413 [SP_SYNC_OBJ_AMOUNT] = NUM_OF_SOB_IN_BLOCK,
414 [SP_MON_OBJ_WR_ADDR_LOW] =
415 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0,
416 [SP_MON_OBJ_WR_ADDR_HIGH] =
417 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0,
418 [SP_MON_OBJ_WR_DATA] = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0,
419 [SP_MON_OBJ_ARM_DATA] = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0,
420 [SP_MON_OBJ_STATUS] = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0,
421 [SP_MONITORS_AMOUNT] = NUM_OF_MONITORS_IN_BLOCK,
422 [SP_TPC0_CMDQ] = mmTPC0_QM_GLBL_CFG0,
423 [SP_TPC0_CFG_SO] = mmTPC0_CFG_QM_SYNC_OBJECT_ADDR,
424 [SP_NEXT_TPC] = mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0,
425 [SP_MME_CMDQ] = mmMME0_QM_GLBL_CFG0,
426 [SP_MME_CFG_SO] = mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL,
427 [SP_NEXT_MME] = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0,
428 [SP_DMA_CMDQ] = mmDMA0_QM_GLBL_CFG0,
429 [SP_DMA_CFG_SO] = mmDMA0_CORE_WR_COMP_ADDR_LO,
430 [SP_DMA_QUEUES_OFFSET] = mmDMA1_QM_GLBL_CFG0 - mmDMA0_QM_GLBL_CFG0,
431 [SP_NUM_OF_MME_ENGINES] = NUM_OF_MME_ENGINES,
432 [SP_SUB_MME_ENG_NUM] = NUM_OF_MME_SUB_ENGINES,
433 [SP_NUM_OF_DMA_ENGINES] = NUM_OF_DMA_ENGINES,
434 [SP_NUM_OF_TPC_ENGINES] = NUM_OF_TPC_ENGINES,
435 [SP_ENGINE_NUM_OF_QUEUES] = NUM_OF_QUEUES,
436 [SP_ENGINE_NUM_OF_STREAMS] = NUM_OF_STREAMS,
437 [SP_ENGINE_NUM_OF_FENCES] = NUM_OF_FENCES,
438 [SP_FENCE0_CNT_OFFSET] =
439 mmDMA0_QM_CP_FENCE0_CNT_0 - mmDMA0_QM_GLBL_CFG0,
440 [SP_FENCE0_RDATA_OFFSET] =
441 mmDMA0_QM_CP_FENCE0_RDATA_0 - mmDMA0_QM_GLBL_CFG0,
442 [SP_CP_STS_OFFSET] = mmDMA0_QM_CP_STS_0 - mmDMA0_QM_GLBL_CFG0,
446 /* The order here is opposite to the order of the indexing in the h/w.
447 * i.e. SYNC_MGR_W_S is actually 0, SYNC_MGR_E_S is 1, etc.
449 static const char * const gaudi_sync_manager_names[] = {
457 struct ecc_info_extract_params {
461 bool disable_clock_gating;
464 static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
466 static int gaudi_send_job_on_qman0(struct hl_device *hdev,
467 struct hl_cs_job *job);
468 static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr,
470 static int gaudi_memset_registers(struct hl_device *hdev, u64 reg_base,
471 u32 num_regs, u32 val);
472 static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel,
474 static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev);
475 static int gaudi_cpucp_info_get(struct hl_device *hdev);
476 static void gaudi_disable_clock_gating(struct hl_device *hdev);
477 static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid);
478 static u32 gaudi_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
480 static u32 gaudi_gen_wait_cb(struct hl_device *hdev,
481 struct hl_gen_wait_properties *prop);
482 static inline enum hl_collective_mode
483 get_collective_mode(struct hl_device *hdev, u32 queue_id)
485 if (gaudi_queue_type[queue_id] == QUEUE_TYPE_EXT)
486 return HL_COLLECTIVE_MASTER;
488 if (queue_id >= GAUDI_QUEUE_ID_DMA_5_0 &&
489 queue_id <= GAUDI_QUEUE_ID_DMA_5_3)
490 return HL_COLLECTIVE_SLAVE;
492 if (queue_id >= GAUDI_QUEUE_ID_TPC_7_0 &&
493 queue_id <= GAUDI_QUEUE_ID_TPC_7_3)
494 return HL_COLLECTIVE_SLAVE;
496 if (queue_id >= GAUDI_QUEUE_ID_NIC_0_0 &&
497 queue_id <= GAUDI_QUEUE_ID_NIC_9_3)
498 return HL_COLLECTIVE_SLAVE;
500 return HL_COLLECTIVE_NOT_SUPPORTED;
503 static inline void set_default_power_values(struct hl_device *hdev)
505 struct asic_fixed_properties *prop = &hdev->asic_prop;
507 if (hdev->card_type == cpucp_card_type_pmc) {
508 prop->max_power_default = MAX_POWER_DEFAULT_PMC;
510 if (prop->fw_security_enabled)
511 prop->dc_power_default = DC_POWER_DEFAULT_PMC_SEC;
513 prop->dc_power_default = DC_POWER_DEFAULT_PMC;
515 prop->max_power_default = MAX_POWER_DEFAULT_PCI;
516 prop->dc_power_default = DC_POWER_DEFAULT_PCI;
520 static int gaudi_set_fixed_properties(struct hl_device *hdev)
522 struct asic_fixed_properties *prop = &hdev->asic_prop;
523 u32 num_sync_stream_queues = 0;
526 prop->max_queues = GAUDI_QUEUE_ID_SIZE;
527 prop->hw_queues_props = kcalloc(prop->max_queues,
528 sizeof(struct hw_queue_properties),
531 if (!prop->hw_queues_props)
534 for (i = 0 ; i < prop->max_queues ; i++) {
535 if (gaudi_queue_type[i] == QUEUE_TYPE_EXT) {
536 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
537 prop->hw_queues_props[i].driver_only = 0;
538 prop->hw_queues_props[i].supports_sync_stream = 1;
539 prop->hw_queues_props[i].cb_alloc_flags =
541 num_sync_stream_queues++;
542 } else if (gaudi_queue_type[i] == QUEUE_TYPE_CPU) {
543 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
544 prop->hw_queues_props[i].driver_only = 1;
545 prop->hw_queues_props[i].supports_sync_stream = 0;
546 prop->hw_queues_props[i].cb_alloc_flags =
548 } else if (gaudi_queue_type[i] == QUEUE_TYPE_INT) {
549 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
550 prop->hw_queues_props[i].driver_only = 0;
551 prop->hw_queues_props[i].supports_sync_stream = 0;
552 prop->hw_queues_props[i].cb_alloc_flags =
556 prop->hw_queues_props[i].collective_mode =
557 get_collective_mode(hdev, i);
560 prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;
561 prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
562 prop->collective_first_sob = 0;
563 prop->collective_first_mon = 0;
565 /* 2 SOBs per internal queue stream are reserved for collective */
566 prop->sync_stream_first_sob =
567 ALIGN(NUMBER_OF_SOBS_IN_GRP, HL_MAX_SOBS_PER_MONITOR)
568 * QMAN_STREAMS * HL_RSVD_SOBS;
570 /* 1 monitor per internal queue stream are reserved for collective
571 * 2 monitors per external queue stream are reserved for collective
573 prop->sync_stream_first_mon =
574 (NUMBER_OF_COLLECTIVE_QUEUES * QMAN_STREAMS) +
575 (NUMBER_OF_EXT_HW_QUEUES * 2);
577 prop->dram_base_address = DRAM_PHYS_BASE;
578 prop->dram_size = GAUDI_HBM_SIZE_32GB;
579 prop->dram_end_address = prop->dram_base_address +
581 prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
583 prop->sram_base_address = SRAM_BASE_ADDR;
584 prop->sram_size = SRAM_SIZE;
585 prop->sram_end_address = prop->sram_base_address +
587 prop->sram_user_base_address = prop->sram_base_address +
588 SRAM_USER_BASE_OFFSET;
590 prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
592 prop->mmu_pgt_size = 0x800000; /* 8MB */
594 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
595 prop->mmu_pte_size = HL_PTE_SIZE;
596 prop->mmu_hop_table_size = HOP_TABLE_SIZE;
597 prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
598 prop->dram_page_size = PAGE_SIZE_2MB;
599 prop->dram_supports_virtual_memory = false;
601 prop->pmmu.hop0_shift = HOP0_SHIFT;
602 prop->pmmu.hop1_shift = HOP1_SHIFT;
603 prop->pmmu.hop2_shift = HOP2_SHIFT;
604 prop->pmmu.hop3_shift = HOP3_SHIFT;
605 prop->pmmu.hop4_shift = HOP4_SHIFT;
606 prop->pmmu.hop0_mask = HOP0_MASK;
607 prop->pmmu.hop1_mask = HOP1_MASK;
608 prop->pmmu.hop2_mask = HOP2_MASK;
609 prop->pmmu.hop3_mask = HOP3_MASK;
610 prop->pmmu.hop4_mask = HOP4_MASK;
611 prop->pmmu.start_addr = VA_HOST_SPACE_START;
612 prop->pmmu.end_addr =
613 (VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2) - 1;
614 prop->pmmu.page_size = PAGE_SIZE_4KB;
615 prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
617 /* PMMU and HPMMU are the same except of page size */
618 memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
619 prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
621 /* shifts and masks are the same in PMMU and DMMU */
622 memcpy(&prop->dmmu, &prop->pmmu, sizeof(prop->pmmu));
623 prop->dmmu.start_addr = (VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2);
624 prop->dmmu.end_addr = VA_HOST_SPACE_END;
625 prop->dmmu.page_size = PAGE_SIZE_2MB;
627 prop->cfg_size = CFG_SIZE;
628 prop->max_asid = MAX_ASID;
629 prop->num_of_events = GAUDI_EVENT_SIZE;
630 prop->tpc_enabled_mask = TPC_ENABLED_MASK;
632 set_default_power_values(hdev);
634 prop->cb_pool_cb_cnt = GAUDI_CB_POOL_CB_CNT;
635 prop->cb_pool_cb_size = GAUDI_CB_POOL_CB_SIZE;
637 prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
638 prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
640 strncpy(prop->cpucp_info.card_name, GAUDI_DEFAULT_CARD_NAME,
643 prop->max_pending_cs = GAUDI_MAX_PENDING_CS;
645 prop->first_available_user_sob[HL_GAUDI_WS_DCORE] =
646 prop->sync_stream_first_sob +
647 (num_sync_stream_queues * HL_RSVD_SOBS);
648 prop->first_available_user_mon[HL_GAUDI_WS_DCORE] =
649 prop->sync_stream_first_mon +
650 (num_sync_stream_queues * HL_RSVD_MONS);
652 prop->first_available_user_msix_interrupt = USHRT_MAX;
654 for (i = 0 ; i < HL_MAX_DCORES ; i++)
655 prop->first_available_cq[i] = USHRT_MAX;
657 prop->fw_cpu_boot_dev_sts0_valid = false;
658 prop->fw_cpu_boot_dev_sts1_valid = false;
659 prop->hard_reset_done_by_fw = false;
660 prop->gic_interrupts_enable = true;
662 prop->server_type = HL_SERVER_TYPE_UNKNOWN;
667 static int gaudi_pci_bars_map(struct hl_device *hdev)
669 static const char * const name[] = {"SRAM", "CFG", "HBM"};
670 bool is_wc[3] = {false, false, true};
673 rc = hl_pci_bars_map(hdev, name, is_wc);
677 hdev->rmmio = hdev->pcie_bar[CFG_BAR_ID] +
678 (CFG_BASE - SPI_FLASH_BASE_ADDR);
683 static u64 gaudi_set_hbm_bar_base(struct hl_device *hdev, u64 addr)
685 struct gaudi_device *gaudi = hdev->asic_specific;
686 struct hl_inbound_pci_region pci_region;
690 if ((gaudi) && (gaudi->hbm_bar_cur_addr == addr))
693 if (hdev->asic_prop.iatu_done_by_fw)
696 /* Inbound Region 2 - Bar 4 - Point to HBM */
697 pci_region.mode = PCI_BAR_MATCH_MODE;
698 pci_region.bar = HBM_BAR_ID;
699 pci_region.addr = addr;
700 rc = hl_pci_set_inbound_region(hdev, 2, &pci_region);
705 old_addr = gaudi->hbm_bar_cur_addr;
706 gaudi->hbm_bar_cur_addr = addr;
712 static int gaudi_init_iatu(struct hl_device *hdev)
714 struct hl_inbound_pci_region inbound_region;
715 struct hl_outbound_pci_region outbound_region;
718 if (hdev->asic_prop.iatu_done_by_fw)
721 /* Inbound Region 0 - Bar 0 - Point to SRAM + CFG */
722 inbound_region.mode = PCI_BAR_MATCH_MODE;
723 inbound_region.bar = SRAM_BAR_ID;
724 inbound_region.addr = SRAM_BASE_ADDR;
725 rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
729 /* Inbound Region 1 - Bar 2 - Point to SPI FLASH */
730 inbound_region.mode = PCI_BAR_MATCH_MODE;
731 inbound_region.bar = CFG_BAR_ID;
732 inbound_region.addr = SPI_FLASH_BASE_ADDR;
733 rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
737 /* Inbound Region 2 - Bar 4 - Point to HBM */
738 inbound_region.mode = PCI_BAR_MATCH_MODE;
739 inbound_region.bar = HBM_BAR_ID;
740 inbound_region.addr = DRAM_PHYS_BASE;
741 rc = hl_pci_set_inbound_region(hdev, 2, &inbound_region);
745 hdev->asic_funcs->set_dma_mask_from_fw(hdev);
747 /* Outbound Region 0 - Point to Host */
748 outbound_region.addr = HOST_PHYS_BASE;
749 outbound_region.size = HOST_PHYS_SIZE;
750 rc = hl_pci_set_outbound_region(hdev, &outbound_region);
756 static enum hl_device_hw_state gaudi_get_hw_state(struct hl_device *hdev)
758 return RREG32(mmHW_STATE);
761 static int gaudi_early_init(struct hl_device *hdev)
763 struct asic_fixed_properties *prop = &hdev->asic_prop;
764 struct pci_dev *pdev = hdev->pdev;
768 rc = gaudi_set_fixed_properties(hdev);
770 dev_err(hdev->dev, "Failed setting fixed properties\n");
774 /* Check BAR sizes */
775 if (pci_resource_len(pdev, SRAM_BAR_ID) != SRAM_BAR_SIZE) {
777 "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
779 (unsigned long long) pci_resource_len(pdev,
783 goto free_queue_props;
786 if (pci_resource_len(pdev, CFG_BAR_ID) != CFG_BAR_SIZE) {
788 "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
790 (unsigned long long) pci_resource_len(pdev,
794 goto free_queue_props;
797 prop->dram_pci_bar_size = pci_resource_len(pdev, HBM_BAR_ID);
799 /* If FW security is enabled at this point it means no access to ELBI */
800 if (hdev->asic_prop.fw_security_enabled) {
801 hdev->asic_prop.iatu_done_by_fw = true;
804 * GIC-security-bit can ONLY be set by CPUCP, so in this stage
805 * decision can only be taken based on PCI ID security.
807 hdev->asic_prop.gic_interrupts_enable = false;
811 rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
814 goto free_queue_props;
816 /* Check whether FW is configuring iATU */
817 if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) &&
818 (fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN))
819 hdev->asic_prop.iatu_done_by_fw = true;
822 rc = hl_pci_init(hdev);
824 goto free_queue_props;
826 /* Before continuing in the initialization, we need to read the preboot
827 * version to determine whether we run with a security-enabled firmware
829 rc = hl_fw_read_preboot_status(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS,
831 mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
833 GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC);
835 if (hdev->reset_on_preboot_fail)
836 hdev->asic_funcs->hw_fini(hdev, true, false);
840 if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
842 "H/W state is dirty, must reset before initializing\n");
843 hdev->asic_funcs->hw_fini(hdev, true, false);
851 kfree(hdev->asic_prop.hw_queues_props);
855 static int gaudi_early_fini(struct hl_device *hdev)
857 kfree(hdev->asic_prop.hw_queues_props);
864 * gaudi_fetch_psoc_frequency - Fetch PSOC frequency values
866 * @hdev: pointer to hl_device structure
869 static int gaudi_fetch_psoc_frequency(struct hl_device *hdev)
871 struct asic_fixed_properties *prop = &hdev->asic_prop;
872 u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
873 u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
876 if (hdev->asic_prop.fw_security_enabled) {
877 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GAUDI_CPU_PLL, pll_freq_arr);
882 freq = pll_freq_arr[2];
884 /* Backward compatibility */
885 div_fctr = RREG32(mmPSOC_CPU_PLL_DIV_FACTOR_2);
886 div_sel = RREG32(mmPSOC_CPU_PLL_DIV_SEL_2);
887 nr = RREG32(mmPSOC_CPU_PLL_NR);
888 nf = RREG32(mmPSOC_CPU_PLL_NF);
889 od = RREG32(mmPSOC_CPU_PLL_OD);
891 if (div_sel == DIV_SEL_REF_CLK ||
892 div_sel == DIV_SEL_DIVIDED_REF) {
893 if (div_sel == DIV_SEL_REF_CLK)
896 freq = PLL_REF_CLK / (div_fctr + 1);
897 } else if (div_sel == DIV_SEL_PLL_CLK ||
898 div_sel == DIV_SEL_DIVIDED_PLL) {
899 pll_clk = PLL_REF_CLK * (nf + 1) /
900 ((nr + 1) * (od + 1));
901 if (div_sel == DIV_SEL_PLL_CLK)
904 freq = pll_clk / (div_fctr + 1);
907 "Received invalid div select value: %d",
913 prop->psoc_timestamp_frequency = freq;
914 prop->psoc_pci_pll_nr = nr;
915 prop->psoc_pci_pll_nf = nf;
916 prop->psoc_pci_pll_od = od;
917 prop->psoc_pci_pll_div_factor = div_fctr;
922 static int _gaudi_init_tpc_mem(struct hl_device *hdev,
923 dma_addr_t tpc_kernel_src_addr, u32 tpc_kernel_size)
925 struct asic_fixed_properties *prop = &hdev->asic_prop;
926 struct packet_lin_dma *init_tpc_mem_pkt;
927 struct hl_cs_job *job;
934 cb = hl_cb_kernel_create(hdev, PAGE_SIZE, false);
938 init_tpc_mem_pkt = cb->kernel_address;
939 cb_size = sizeof(*init_tpc_mem_pkt);
940 memset(init_tpc_mem_pkt, 0, cb_size);
942 init_tpc_mem_pkt->tsize = cpu_to_le32(tpc_kernel_size);
944 ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_LIN_DMA);
945 ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_LIN_MASK, 1);
946 ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
947 ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
949 init_tpc_mem_pkt->ctl = cpu_to_le32(ctl);
951 init_tpc_mem_pkt->src_addr = cpu_to_le64(tpc_kernel_src_addr);
952 dst_addr = (prop->sram_user_base_address &
953 GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >>
954 GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT;
955 init_tpc_mem_pkt->dst_addr |= cpu_to_le64(dst_addr);
957 job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
959 dev_err(hdev->dev, "Failed to allocate a new job\n");
966 atomic_inc(&job->user_cb->cs_cnt);
967 job->user_cb_size = cb_size;
968 job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0;
969 job->patched_cb = job->user_cb;
970 job->job_cb_size = job->user_cb_size + sizeof(struct packet_msg_prot);
972 hl_debugfs_add_job(hdev, job);
974 rc = gaudi_send_job_on_qman0(hdev, job);
979 for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) {
980 rc = gaudi_run_tpc_kernel(hdev, dst_addr, tpc_id);
986 hl_userptr_delete_list(hdev, &job->userptr_list);
987 hl_debugfs_remove_job(hdev, job);
989 atomic_dec(&cb->cs_cnt);
993 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
999 * gaudi_init_tpc_mem() - Initialize TPC memories.
1000 * @hdev: Pointer to hl_device structure.
1002 * Copy TPC kernel fw from firmware file and run it to initialize TPC memories.
1004 * Return: 0 for success, negative value for error.
1006 static int gaudi_init_tpc_mem(struct hl_device *hdev)
1008 const struct firmware *fw;
1011 dma_addr_t dma_handle;
1015 rc = request_firmware(&fw, GAUDI_TPC_FW_FILE, hdev->dev);
1016 if (rc == -EINTR && count-- > 0) {
1022 dev_err(hdev->dev, "Failed to load firmware file %s\n",
1028 cpu_addr = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, fw_size,
1029 &dma_handle, GFP_KERNEL | __GFP_ZERO);
1032 "Failed to allocate %zu of dma memory for TPC kernel\n",
1038 memcpy(cpu_addr, fw->data, fw_size);
1040 rc = _gaudi_init_tpc_mem(hdev, dma_handle, fw_size);
1042 hdev->asic_funcs->asic_dma_free_coherent(hdev, fw->size, cpu_addr,
1046 release_firmware(fw);
1050 static void gaudi_collective_map_sobs(struct hl_device *hdev, u32 stream)
1052 struct gaudi_device *gaudi = hdev->asic_specific;
1053 struct gaudi_collective_properties *prop = &gaudi->collective_props;
1054 struct hl_hw_queue *q;
1055 u32 i, sob_id, sob_group_id, queue_id;
1057 /* Iterate through SOB groups and assign a SOB for each slave queue */
1059 stream * HL_RSVD_SOBS + prop->curr_sob_group_idx[stream];
1060 sob_id = prop->hw_sob_group[sob_group_id].base_sob_id;
1062 queue_id = GAUDI_QUEUE_ID_NIC_0_0 + stream;
1063 for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++) {
1064 q = &hdev->kernel_queues[queue_id + (4 * i)];
1065 q->sync_stream_prop.collective_sob_id = sob_id + i;
1068 /* Both DMA5 and TPC7 use the same resources since only a single
1069 * engine need to participate in the reduction process
1071 queue_id = GAUDI_QUEUE_ID_DMA_5_0 + stream;
1072 q = &hdev->kernel_queues[queue_id];
1073 q->sync_stream_prop.collective_sob_id =
1074 sob_id + NIC_NUMBER_OF_ENGINES;
1076 queue_id = GAUDI_QUEUE_ID_TPC_7_0 + stream;
1077 q = &hdev->kernel_queues[queue_id];
1078 q->sync_stream_prop.collective_sob_id =
1079 sob_id + NIC_NUMBER_OF_ENGINES;
1082 static void gaudi_sob_group_hw_reset(struct kref *ref)
1084 struct gaudi_hw_sob_group *hw_sob_group =
1085 container_of(ref, struct gaudi_hw_sob_group, kref);
1086 struct hl_device *hdev = hw_sob_group->hdev;
1089 for (i = 0 ; i < NUMBER_OF_SOBS_IN_GRP ; i++)
1090 WREG32((mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 +
1091 (hw_sob_group->base_sob_id * 4) + (i * 4)), 0);
1093 kref_init(&hw_sob_group->kref);
1096 static void gaudi_sob_group_reset_error(struct kref *ref)
1098 struct gaudi_hw_sob_group *hw_sob_group =
1099 container_of(ref, struct gaudi_hw_sob_group, kref);
1100 struct hl_device *hdev = hw_sob_group->hdev;
1103 "SOB release shouldn't be called here, base_sob_id: %d\n",
1104 hw_sob_group->base_sob_id);
1107 static void gaudi_collective_mstr_sob_mask_set(struct gaudi_device *gaudi)
1109 struct gaudi_collective_properties *prop;
1112 prop = &gaudi->collective_props;
1114 memset(prop->mstr_sob_mask, 0, sizeof(prop->mstr_sob_mask));
1116 for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++)
1117 if (gaudi->hw_cap_initialized & BIT(HW_CAP_NIC_SHIFT + i))
1118 prop->mstr_sob_mask[i / HL_MAX_SOBS_PER_MONITOR] |=
1119 BIT(i % HL_MAX_SOBS_PER_MONITOR);
1120 /* Set collective engine bit */
1121 prop->mstr_sob_mask[i / HL_MAX_SOBS_PER_MONITOR] |=
1122 BIT(i % HL_MAX_SOBS_PER_MONITOR);
1125 static int gaudi_collective_init(struct hl_device *hdev)
1127 u32 i, sob_id, reserved_sobs_per_group;
1128 struct gaudi_collective_properties *prop;
1129 struct gaudi_device *gaudi;
1131 gaudi = hdev->asic_specific;
1132 prop = &gaudi->collective_props;
1133 sob_id = hdev->asic_prop.collective_first_sob;
1135 /* First sob in group must be aligned to HL_MAX_SOBS_PER_MONITOR */
1136 reserved_sobs_per_group =
1137 ALIGN(NUMBER_OF_SOBS_IN_GRP, HL_MAX_SOBS_PER_MONITOR);
1139 /* Init SOB groups */
1140 for (i = 0 ; i < NUM_SOB_GROUPS; i++) {
1141 prop->hw_sob_group[i].hdev = hdev;
1142 prop->hw_sob_group[i].base_sob_id = sob_id;
1143 sob_id += reserved_sobs_per_group;
1144 gaudi_sob_group_hw_reset(&prop->hw_sob_group[i].kref);
1147 for (i = 0 ; i < QMAN_STREAMS; i++) {
1148 prop->next_sob_group_val[i] = 1;
1149 prop->curr_sob_group_idx[i] = 0;
1150 gaudi_collective_map_sobs(hdev, i);
1153 gaudi_collective_mstr_sob_mask_set(gaudi);
1158 static void gaudi_reset_sob_group(struct hl_device *hdev, u16 sob_group)
1160 struct gaudi_device *gaudi = hdev->asic_specific;
1161 struct gaudi_collective_properties *cprop = &gaudi->collective_props;
1163 kref_put(&cprop->hw_sob_group[sob_group].kref,
1164 gaudi_sob_group_hw_reset);
1167 static void gaudi_collective_master_init_job(struct hl_device *hdev,
1168 struct hl_cs_job *job, u32 stream, u32 sob_group_offset)
1170 u32 master_sob_base, master_monitor, queue_id, cb_size = 0;
1171 struct gaudi_collective_properties *cprop;
1172 struct hl_gen_wait_properties wait_prop;
1173 struct hl_sync_stream_properties *prop;
1174 struct gaudi_device *gaudi;
1176 gaudi = hdev->asic_specific;
1177 cprop = &gaudi->collective_props;
1178 queue_id = job->hw_queue_id;
1179 prop = &hdev->kernel_queues[queue_id].sync_stream_prop;
1182 cprop->hw_sob_group[sob_group_offset].base_sob_id;
1183 master_monitor = prop->collective_mstr_mon_id[0];
1185 cprop->hw_sob_group[sob_group_offset].queue_id = queue_id;
1188 "Generate master wait CBs, sob %d (mask %#x), val:0x%x, mon %u, q %d\n",
1189 master_sob_base, cprop->mstr_sob_mask[0],
1190 cprop->next_sob_group_val[stream],
1191 master_monitor, queue_id);
1193 wait_prop.data = (void *) job->patched_cb;
1194 wait_prop.sob_base = master_sob_base;
1195 wait_prop.sob_mask = cprop->mstr_sob_mask[0];
1196 wait_prop.sob_val = cprop->next_sob_group_val[stream];
1197 wait_prop.mon_id = master_monitor;
1198 wait_prop.q_idx = queue_id;
1199 wait_prop.size = cb_size;
1200 cb_size += gaudi_gen_wait_cb(hdev, &wait_prop);
1202 master_sob_base += HL_MAX_SOBS_PER_MONITOR;
1203 master_monitor = prop->collective_mstr_mon_id[1];
1206 "Generate master wait CBs, sob %d (mask %#x), val:0x%x, mon %u, q %d\n",
1207 master_sob_base, cprop->mstr_sob_mask[1],
1208 cprop->next_sob_group_val[stream],
1209 master_monitor, queue_id);
1211 wait_prop.sob_base = master_sob_base;
1212 wait_prop.sob_mask = cprop->mstr_sob_mask[1];
1213 wait_prop.mon_id = master_monitor;
1214 wait_prop.size = cb_size;
1215 cb_size += gaudi_gen_wait_cb(hdev, &wait_prop);
1218 static void gaudi_collective_slave_init_job(struct hl_device *hdev,
1219 struct hl_cs_job *job, struct hl_cs_compl *cs_cmpl)
1221 struct hl_gen_wait_properties wait_prop;
1222 struct hl_sync_stream_properties *prop;
1223 u32 queue_id, cb_size = 0;
1225 queue_id = job->hw_queue_id;
1226 prop = &hdev->kernel_queues[queue_id].sync_stream_prop;
1228 if (job->cs->encaps_signals) {
1229 /* use the encaps signal handle store earlier in the flow
1230 * and set the SOB information from the encaps
1233 hl_hw_queue_encaps_sig_set_sob_info(hdev, job->cs, job,
1236 dev_dbg(hdev->dev, "collective wait: Sequence %llu found, sob_id: %u, wait for sob_val: %u\n",
1238 cs_cmpl->hw_sob->sob_id,
1242 /* Add to wait CBs using slave monitor */
1243 wait_prop.data = (void *) job->user_cb;
1244 wait_prop.sob_base = cs_cmpl->hw_sob->sob_id;
1245 wait_prop.sob_mask = 0x1;
1246 wait_prop.sob_val = cs_cmpl->sob_val;
1247 wait_prop.mon_id = prop->collective_slave_mon_id;
1248 wait_prop.q_idx = queue_id;
1249 wait_prop.size = cb_size;
1252 "Generate slave wait CB, sob %d, val:%x, mon %d, q %d\n",
1253 cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val,
1254 prop->collective_slave_mon_id, queue_id);
1256 cb_size += gaudi_gen_wait_cb(hdev, &wait_prop);
1259 "generate signal CB, sob_id: %d, sob val: 1, q_idx: %d\n",
1260 prop->collective_sob_id, queue_id);
1262 cb_size += gaudi_gen_signal_cb(hdev, job->user_cb,
1263 prop->collective_sob_id, cb_size, false);
1266 static int gaudi_collective_wait_init_cs(struct hl_cs *cs)
1268 struct hl_cs_compl *signal_cs_cmpl =
1269 container_of(cs->signal_fence, struct hl_cs_compl, base_fence);
1270 struct hl_cs_compl *cs_cmpl =
1271 container_of(cs->fence, struct hl_cs_compl, base_fence);
1272 struct gaudi_collective_properties *cprop;
1273 u32 stream, queue_id, sob_group_offset;
1274 struct gaudi_device *gaudi;
1275 struct hl_device *hdev;
1276 struct hl_cs_job *job;
1281 gaudi = hdev->asic_specific;
1282 cprop = &gaudi->collective_props;
1284 /* In encaps signals case the SOB info will be retrieved from
1285 * the handle in gaudi_collective_slave_init_job.
1287 if (!cs->encaps_signals) {
1288 /* copy the SOB id and value of the signal CS */
1289 cs_cmpl->hw_sob = signal_cs_cmpl->hw_sob;
1290 cs_cmpl->sob_val = signal_cs_cmpl->sob_val;
1293 /* check again if the signal cs already completed.
1294 * if yes then don't send any wait cs since the hw_sob
1295 * could be in reset already. if signal is not completed
1296 * then get refcount to hw_sob to prevent resetting the sob
1297 * while wait cs is not submitted.
1298 * note that this check is protected by two locks,
1299 * hw queue lock and completion object lock,
1300 * and the same completion object lock also protects
1301 * the hw_sob reset handler function.
1302 * The hw_queue lock prevent out of sync of hw_sob
1303 * refcount value, changed by signal/wait flows.
1305 spin_lock(&signal_cs_cmpl->lock);
1307 if (completion_done(&cs->signal_fence->completion)) {
1308 spin_unlock(&signal_cs_cmpl->lock);
1311 /* Increment kref since all slave queues are now waiting on it */
1312 kref_get(&cs_cmpl->hw_sob->kref);
1314 spin_unlock(&signal_cs_cmpl->lock);
1316 /* Calculate the stream from collective master queue (1st job) */
1317 job = list_first_entry(&cs->job_list, struct hl_cs_job, cs_node);
1318 stream = job->hw_queue_id % 4;
1320 stream * HL_RSVD_SOBS + cprop->curr_sob_group_idx[stream];
1322 list_for_each_entry(job, &cs->job_list, cs_node) {
1323 queue_id = job->hw_queue_id;
1325 if (hdev->kernel_queues[queue_id].collective_mode ==
1326 HL_COLLECTIVE_MASTER)
1327 gaudi_collective_master_init_job(hdev, job, stream,
1330 gaudi_collective_slave_init_job(hdev, job, cs_cmpl);
1333 cs_cmpl->sob_group = sob_group_offset;
1335 /* Handle sob group kref and wraparound */
1336 kref_get(&cprop->hw_sob_group[sob_group_offset].kref);
1337 cprop->next_sob_group_val[stream]++;
1339 if (cprop->next_sob_group_val[stream] == HL_MAX_SOB_VAL) {
1341 * Decrement as we reached the max value.
1342 * The release function won't be called here as we've
1343 * just incremented the refcount.
1345 kref_put(&cprop->hw_sob_group[sob_group_offset].kref,
1346 gaudi_sob_group_reset_error);
1347 cprop->next_sob_group_val[stream] = 1;
1348 /* only two SOBs are currently in use */
1349 cprop->curr_sob_group_idx[stream] =
1350 (cprop->curr_sob_group_idx[stream] + 1) &
1353 gaudi_collective_map_sobs(hdev, stream);
1355 dev_dbg(hdev->dev, "switched to SOB group %d, stream: %d\n",
1356 cprop->curr_sob_group_idx[stream], stream);
1360 hl_fence_put(cs->signal_fence);
1361 cs->signal_fence = NULL;
1366 static int gaudi_collective_wait_create_job(struct hl_device *hdev,
1367 struct hl_ctx *ctx, struct hl_cs *cs,
1368 enum hl_collective_mode mode, u32 queue_id, u32 wait_queue_id,
1369 u32 encaps_signal_offset)
1371 struct hw_queue_properties *hw_queue_prop;
1372 struct hl_cs_counters_atomic *cntr;
1373 struct hl_cs_job *job;
1378 cntr = &hdev->aggregated_cs_counters;
1380 if (mode == HL_COLLECTIVE_MASTER) {
1381 /* CB size of collective master queue contains
1382 * 4 msg short packets for monitor 1 configuration
1384 * 4 msg short packets for monitor 2 configuration
1386 * 2 msg prot packets for completion and MSI-X
1388 cb_size = sizeof(struct packet_msg_short) * 8 +
1389 sizeof(struct packet_fence) * 2 +
1390 sizeof(struct packet_msg_prot) * 2;
1393 /* CB size of collective slave queues contains
1394 * 4 msg short packets for monitor configuration
1396 * 1 additional msg short packet for sob signal
1398 cb_size = sizeof(struct packet_msg_short) * 5 +
1399 sizeof(struct packet_fence);
1403 hw_queue_prop = &hdev->asic_prop.hw_queues_props[queue_id];
1404 job = hl_cs_allocate_job(hdev, hw_queue_prop->type, true);
1406 atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
1407 atomic64_inc(&cntr->out_of_mem_drop_cnt);
1408 dev_err(hdev->dev, "Failed to allocate a new job\n");
1412 /* Allocate internal mapped CB for non patched CBs */
1413 cb = hl_cb_kernel_create(hdev, cb_size,
1414 hdev->mmu_enable && !patched_cb);
1416 atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
1417 atomic64_inc(&cntr->out_of_mem_drop_cnt);
1425 atomic_inc(&job->user_cb->cs_cnt);
1426 job->user_cb_size = cb_size;
1427 job->hw_queue_id = queue_id;
1429 /* since its guaranteed to have only one chunk in the collective wait
1430 * cs, we can use this chunk to set the encapsulated signal offset
1433 if (cs->encaps_signals)
1434 job->encaps_sig_wait_offset = encaps_signal_offset;
1437 * No need in parsing, user CB is the patched CB.
1438 * We call hl_cb_destroy() out of two reasons - we don't need
1439 * the CB in the CB idr anymore and to decrement its refcount as
1440 * it was incremented inside hl_cb_kernel_create().
1443 job->patched_cb = job->user_cb;
1445 job->patched_cb = NULL;
1447 job->job_cb_size = job->user_cb_size;
1448 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
1450 /* increment refcount as for external queues we get completion */
1451 if (hw_queue_prop->type == QUEUE_TYPE_EXT)
1454 cs->jobs_in_queue_cnt[job->hw_queue_id]++;
1456 list_add_tail(&job->cs_node, &cs->job_list);
1458 hl_debugfs_add_job(hdev, job);
1463 static int gaudi_collective_wait_create_jobs(struct hl_device *hdev,
1464 struct hl_ctx *ctx, struct hl_cs *cs,
1465 u32 wait_queue_id, u32 collective_engine_id,
1466 u32 encaps_signal_offset)
1468 struct gaudi_device *gaudi = hdev->asic_specific;
1469 struct hw_queue_properties *hw_queue_prop;
1470 u32 queue_id, collective_queue, num_jobs;
1471 u32 stream, nic_queue, nic_idx = 0;
1475 /* Verify wait queue id is configured as master */
1476 hw_queue_prop = &hdev->asic_prop.hw_queues_props[wait_queue_id];
1477 if (!(hw_queue_prop->collective_mode == HL_COLLECTIVE_MASTER)) {
1479 "Queue %d is not configured as collective master\n",
1484 /* Verify engine id is supported */
1485 if (collective_engine_id != GAUDI_ENGINE_ID_DMA_5 &&
1486 collective_engine_id != GAUDI_ENGINE_ID_TPC_7) {
1488 "Collective wait does not support engine %u\n",
1489 collective_engine_id);
1493 stream = wait_queue_id % 4;
1495 if (collective_engine_id == GAUDI_ENGINE_ID_DMA_5)
1496 collective_queue = GAUDI_QUEUE_ID_DMA_5_0 + stream;
1498 collective_queue = GAUDI_QUEUE_ID_TPC_7_0 + stream;
1500 num_jobs = NUMBER_OF_SOBS_IN_GRP + 1;
1501 nic_queue = GAUDI_QUEUE_ID_NIC_0_0 + stream;
1503 /* First job goes to the collective master queue, it will wait for
1504 * the collective slave queues to finish execution.
1505 * The synchronization is done using two monitors:
1506 * First monitor for NICs 0-7, second monitor for NICs 8-9 and the
1507 * reduction engine (DMA5/TPC7).
1509 * Rest of the jobs goes to the collective slave queues which will
1510 * all wait for the user to signal sob 'cs_cmpl->sob_val'.
1512 for (i = 0 ; i < num_jobs ; i++) {
1514 queue_id = wait_queue_id;
1515 rc = gaudi_collective_wait_create_job(hdev, ctx, cs,
1516 HL_COLLECTIVE_MASTER, queue_id,
1517 wait_queue_id, encaps_signal_offset);
1519 if (nic_idx < NIC_NUMBER_OF_ENGINES) {
1520 if (gaudi->hw_cap_initialized &
1521 BIT(HW_CAP_NIC_SHIFT + nic_idx))
1526 queue_id = nic_queue;
1533 queue_id = collective_queue;
1536 rc = gaudi_collective_wait_create_job(hdev, ctx, cs,
1537 HL_COLLECTIVE_SLAVE, queue_id,
1538 wait_queue_id, encaps_signal_offset);
1548 static int gaudi_late_init(struct hl_device *hdev)
1550 struct gaudi_device *gaudi = hdev->asic_specific;
1553 rc = gaudi->cpucp_info_get(hdev);
1555 dev_err(hdev->dev, "Failed to get cpucp info\n");
1559 if ((hdev->card_type == cpucp_card_type_pci) &&
1560 (hdev->nic_ports_mask & 0x3)) {
1562 "PCI card detected, only 8 ports are enabled\n");
1563 hdev->nic_ports_mask &= ~0x3;
1565 /* Stop and disable unused NIC QMANs */
1566 WREG32(mmNIC0_QM0_GLBL_CFG1, NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
1567 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
1568 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
1570 WREG32(mmNIC0_QM1_GLBL_CFG1, NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
1571 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
1572 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
1574 WREG32(mmNIC0_QM0_GLBL_CFG0, 0);
1575 WREG32(mmNIC0_QM1_GLBL_CFG0, 0);
1577 gaudi->hw_cap_initialized &= ~(HW_CAP_NIC0 | HW_CAP_NIC1);
1580 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS);
1582 dev_err(hdev->dev, "Failed to enable PCI access from CPU\n");
1586 /* Scrub both SRAM and DRAM */
1587 rc = hdev->asic_funcs->scrub_device_mem(hdev, 0, 0);
1589 goto disable_pci_access;
1591 rc = gaudi_fetch_psoc_frequency(hdev);
1593 dev_err(hdev->dev, "Failed to fetch psoc frequency\n");
1594 goto disable_pci_access;
1597 rc = gaudi_mmu_clear_pgt_range(hdev);
1599 dev_err(hdev->dev, "Failed to clear MMU page tables range\n");
1600 goto disable_pci_access;
1603 rc = gaudi_init_tpc_mem(hdev);
1605 dev_err(hdev->dev, "Failed to initialize TPC memories\n");
1606 goto disable_pci_access;
1609 rc = gaudi_collective_init(hdev);
1611 dev_err(hdev->dev, "Failed to init collective\n");
1612 goto disable_pci_access;
1615 /* We only support a single ASID for the user, so for the sake of optimization, just
1616 * initialize the ASID one time during device initialization with the fixed value of 1
1618 gaudi_mmu_prepare(hdev, 1);
1623 hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS);
1628 static void gaudi_late_fini(struct hl_device *hdev)
1630 const struct hwmon_channel_info **channel_info_arr;
1633 if (!hdev->hl_chip_info->info)
1636 channel_info_arr = hdev->hl_chip_info->info;
1638 while (channel_info_arr[i]) {
1639 kfree(channel_info_arr[i]->config);
1640 kfree(channel_info_arr[i]);
1644 kfree(channel_info_arr);
1646 hdev->hl_chip_info->info = NULL;
1649 static int gaudi_alloc_cpu_accessible_dma_mem(struct hl_device *hdev)
1651 dma_addr_t dma_addr_arr[GAUDI_ALLOC_CPU_MEM_RETRY_CNT] = {}, end_addr;
1652 void *virt_addr_arr[GAUDI_ALLOC_CPU_MEM_RETRY_CNT] = {};
1656 * The device CPU works with 40-bits addresses, while bit 39 must be set
1657 * to '1' when accessing the host.
1658 * Bits 49:39 of the full host address are saved for a later
1659 * configuration of the HW to perform extension to 50 bits.
1660 * Because there is a single HW register that holds the extension bits,
1661 * these bits must be identical in all allocated range.
1664 for (i = 0 ; i < GAUDI_ALLOC_CPU_MEM_RETRY_CNT ; i++) {
1666 hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
1667 HL_CPU_ACCESSIBLE_MEM_SIZE,
1669 GFP_KERNEL | __GFP_ZERO);
1670 if (!virt_addr_arr[i]) {
1672 goto free_dma_mem_arr;
1675 end_addr = dma_addr_arr[i] + HL_CPU_ACCESSIBLE_MEM_SIZE - 1;
1676 if (GAUDI_CPU_PCI_MSB_ADDR(dma_addr_arr[i]) ==
1677 GAUDI_CPU_PCI_MSB_ADDR(end_addr))
1681 if (i == GAUDI_ALLOC_CPU_MEM_RETRY_CNT) {
1683 "MSB of CPU accessible DMA memory are not identical in all range\n");
1685 goto free_dma_mem_arr;
1688 hdev->cpu_accessible_dma_mem = virt_addr_arr[i];
1689 hdev->cpu_accessible_dma_address = dma_addr_arr[i];
1690 hdev->cpu_pci_msb_addr =
1691 GAUDI_CPU_PCI_MSB_ADDR(hdev->cpu_accessible_dma_address);
1693 if (!hdev->asic_prop.fw_security_enabled)
1694 GAUDI_PCI_TO_CPU_ADDR(hdev->cpu_accessible_dma_address);
1697 for (j = 0 ; j < i ; j++)
1698 hdev->asic_funcs->asic_dma_free_coherent(hdev,
1699 HL_CPU_ACCESSIBLE_MEM_SIZE,
1706 static void gaudi_free_internal_qmans_pq_mem(struct hl_device *hdev)
1708 struct gaudi_device *gaudi = hdev->asic_specific;
1709 struct gaudi_internal_qman_info *q;
1712 for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) {
1713 q = &gaudi->internal_qmans[i];
1714 if (!q->pq_kernel_addr)
1716 hdev->asic_funcs->asic_dma_free_coherent(hdev, q->pq_size,
1722 static int gaudi_alloc_internal_qmans_pq_mem(struct hl_device *hdev)
1724 struct gaudi_device *gaudi = hdev->asic_specific;
1725 struct gaudi_internal_qman_info *q;
1728 for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) {
1729 if (gaudi_queue_type[i] != QUEUE_TYPE_INT)
1732 q = &gaudi->internal_qmans[i];
1735 case GAUDI_QUEUE_ID_DMA_2_0 ... GAUDI_QUEUE_ID_DMA_7_3:
1736 q->pq_size = HBM_DMA_QMAN_SIZE_IN_BYTES;
1738 case GAUDI_QUEUE_ID_MME_0_0 ... GAUDI_QUEUE_ID_MME_1_3:
1739 q->pq_size = MME_QMAN_SIZE_IN_BYTES;
1741 case GAUDI_QUEUE_ID_TPC_0_0 ... GAUDI_QUEUE_ID_TPC_7_3:
1742 q->pq_size = TPC_QMAN_SIZE_IN_BYTES;
1744 case GAUDI_QUEUE_ID_NIC_0_0 ... GAUDI_QUEUE_ID_NIC_9_3:
1745 q->pq_size = NIC_QMAN_SIZE_IN_BYTES;
1748 dev_err(hdev->dev, "Bad internal queue index %d", i);
1750 goto free_internal_qmans_pq_mem;
1753 q->pq_kernel_addr = hdev->asic_funcs->asic_dma_alloc_coherent(
1756 GFP_KERNEL | __GFP_ZERO);
1757 if (!q->pq_kernel_addr) {
1759 goto free_internal_qmans_pq_mem;
1765 free_internal_qmans_pq_mem:
1766 gaudi_free_internal_qmans_pq_mem(hdev);
1770 static void gaudi_set_pci_memory_regions(struct hl_device *hdev)
1772 struct asic_fixed_properties *prop = &hdev->asic_prop;
1773 struct pci_mem_region *region;
1776 region = &hdev->pci_mem_region[PCI_REGION_CFG];
1777 region->region_base = CFG_BASE;
1778 region->region_size = CFG_SIZE;
1779 region->offset_in_bar = CFG_BASE - SPI_FLASH_BASE_ADDR;
1780 region->bar_size = CFG_BAR_SIZE;
1781 region->bar_id = CFG_BAR_ID;
1785 region = &hdev->pci_mem_region[PCI_REGION_SRAM];
1786 region->region_base = SRAM_BASE_ADDR;
1787 region->region_size = SRAM_SIZE;
1788 region->offset_in_bar = 0;
1789 region->bar_size = SRAM_BAR_SIZE;
1790 region->bar_id = SRAM_BAR_ID;
1794 region = &hdev->pci_mem_region[PCI_REGION_DRAM];
1795 region->region_base = DRAM_PHYS_BASE;
1796 region->region_size = hdev->asic_prop.dram_size;
1797 region->offset_in_bar = 0;
1798 region->bar_size = prop->dram_pci_bar_size;
1799 region->bar_id = HBM_BAR_ID;
1803 region = &hdev->pci_mem_region[PCI_REGION_SP_SRAM];
1804 region->region_base = PSOC_SCRATCHPAD_ADDR;
1805 region->region_size = PSOC_SCRATCHPAD_SIZE;
1806 region->offset_in_bar = PSOC_SCRATCHPAD_ADDR - SPI_FLASH_BASE_ADDR;
1807 region->bar_size = CFG_BAR_SIZE;
1808 region->bar_id = CFG_BAR_ID;
1812 static int gaudi_sw_init(struct hl_device *hdev)
1814 struct gaudi_device *gaudi;
1815 u32 i, event_id = 0;
1818 /* Allocate device structure */
1819 gaudi = kzalloc(sizeof(*gaudi), GFP_KERNEL);
1823 for (i = 0 ; i < ARRAY_SIZE(gaudi_irq_map_table) ; i++) {
1824 if (gaudi_irq_map_table[i].valid) {
1825 if (event_id == GAUDI_EVENT_SIZE) {
1827 "Event array exceeds the limit of %u events\n",
1830 goto free_gaudi_device;
1833 gaudi->events[event_id++] =
1834 gaudi_irq_map_table[i].fc_id;
1838 gaudi->cpucp_info_get = gaudi_cpucp_info_get;
1840 gaudi->max_freq_value = GAUDI_MAX_CLK_FREQ;
1842 hdev->asic_specific = gaudi;
1844 /* Create DMA pool for small allocations */
1845 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
1846 &hdev->pdev->dev, GAUDI_DMA_POOL_BLK_SIZE, 8, 0);
1847 if (!hdev->dma_pool) {
1848 dev_err(hdev->dev, "failed to create DMA pool\n");
1850 goto free_gaudi_device;
1853 rc = gaudi_alloc_cpu_accessible_dma_mem(hdev);
1857 hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
1858 if (!hdev->cpu_accessible_dma_pool) {
1860 "Failed to create CPU accessible DMA pool\n");
1862 goto free_cpu_dma_mem;
1865 rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
1866 (uintptr_t) hdev->cpu_accessible_dma_mem,
1867 HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
1870 "Failed to add memory to CPU accessible DMA pool\n");
1872 goto free_cpu_accessible_dma_pool;
1875 rc = gaudi_alloc_internal_qmans_pq_mem(hdev);
1877 goto free_cpu_accessible_dma_pool;
1879 spin_lock_init(&gaudi->hw_queues_lock);
1880 mutex_init(&gaudi->clk_gate_mutex);
1882 hdev->supports_sync_stream = true;
1883 hdev->supports_coresight = true;
1884 hdev->supports_staged_submission = true;
1885 hdev->supports_wait_for_multi_cs = true;
1887 hdev->asic_funcs->set_pci_memory_regions(hdev);
1888 hdev->stream_master_qid_arr =
1889 hdev->asic_funcs->get_stream_master_qid_arr();
1890 hdev->stream_master_qid_arr_size = GAUDI_STREAM_MASTER_ARR_SIZE;
1894 free_cpu_accessible_dma_pool:
1895 gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1897 if (!hdev->asic_prop.fw_security_enabled)
1898 GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address,
1899 hdev->cpu_pci_msb_addr);
1900 hdev->asic_funcs->asic_dma_free_coherent(hdev,
1901 HL_CPU_ACCESSIBLE_MEM_SIZE,
1902 hdev->cpu_accessible_dma_mem,
1903 hdev->cpu_accessible_dma_address);
1905 dma_pool_destroy(hdev->dma_pool);
1911 static int gaudi_sw_fini(struct hl_device *hdev)
1913 struct gaudi_device *gaudi = hdev->asic_specific;
1915 gaudi_free_internal_qmans_pq_mem(hdev);
1917 gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1919 if (!hdev->asic_prop.fw_security_enabled)
1920 GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address,
1921 hdev->cpu_pci_msb_addr);
1923 hdev->asic_funcs->asic_dma_free_coherent(hdev,
1924 HL_CPU_ACCESSIBLE_MEM_SIZE,
1925 hdev->cpu_accessible_dma_mem,
1926 hdev->cpu_accessible_dma_address);
1928 dma_pool_destroy(hdev->dma_pool);
1930 mutex_destroy(&gaudi->clk_gate_mutex);
1937 static irqreturn_t gaudi_irq_handler_single(int irq, void *arg)
1939 struct hl_device *hdev = arg;
1945 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
1946 hl_irq_handler_cq(irq, &hdev->completion_queue[i]);
1948 hl_irq_handler_eq(irq, &hdev->event_queue);
1954 * For backward compatibility, new MSI interrupts should be set after the
1955 * existing CPU and NIC interrupts.
1957 static int gaudi_pci_irq_vector(struct hl_device *hdev, unsigned int nr,
1962 if ((nr != GAUDI_EVENT_QUEUE_MSI_IDX) && (cpu_eq))
1963 dev_crit(hdev->dev, "CPU EQ must use IRQ %d\n",
1964 GAUDI_EVENT_QUEUE_MSI_IDX);
1966 msi_vec = ((nr < GAUDI_EVENT_QUEUE_MSI_IDX) || (cpu_eq)) ? nr :
1967 (nr + NIC_NUMBER_OF_ENGINES + 1);
1969 return pci_irq_vector(hdev->pdev, msi_vec);
1972 static int gaudi_enable_msi_single(struct hl_device *hdev)
1976 dev_dbg(hdev->dev, "Working in single MSI IRQ mode\n");
1978 irq = gaudi_pci_irq_vector(hdev, 0, false);
1979 rc = request_irq(irq, gaudi_irq_handler_single, 0,
1980 "gaudi single msi", hdev);
1983 "Failed to request single MSI IRQ\n");
1988 static int gaudi_enable_msi_multi(struct hl_device *hdev)
1990 int cq_cnt = hdev->asic_prop.completion_queues_count;
1991 int rc, i, irq_cnt_init, irq;
1993 for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
1994 irq = gaudi_pci_irq_vector(hdev, i, false);
1995 rc = request_irq(irq, hl_irq_handler_cq, 0, gaudi_irq_name[i],
1996 &hdev->completion_queue[i]);
1998 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2003 irq = gaudi_pci_irq_vector(hdev, GAUDI_EVENT_QUEUE_MSI_IDX, true);
2004 rc = request_irq(irq, hl_irq_handler_eq, 0, gaudi_irq_name[cq_cnt],
2005 &hdev->event_queue);
2007 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2014 for (i = 0 ; i < irq_cnt_init ; i++)
2015 free_irq(gaudi_pci_irq_vector(hdev, i, false),
2016 &hdev->completion_queue[i]);
2020 static int gaudi_enable_msi(struct hl_device *hdev)
2022 struct gaudi_device *gaudi = hdev->asic_specific;
2025 if (gaudi->hw_cap_initialized & HW_CAP_MSI)
2028 rc = pci_alloc_irq_vectors(hdev->pdev, 1, 1, PCI_IRQ_MSI);
2030 dev_err(hdev->dev, "MSI: Failed to enable support %d\n", rc);
2034 if (rc < NUMBER_OF_INTERRUPTS) {
2035 gaudi->multi_msi_mode = false;
2036 rc = gaudi_enable_msi_single(hdev);
2038 gaudi->multi_msi_mode = true;
2039 rc = gaudi_enable_msi_multi(hdev);
2043 goto free_pci_irq_vectors;
2045 gaudi->hw_cap_initialized |= HW_CAP_MSI;
2049 free_pci_irq_vectors:
2050 pci_free_irq_vectors(hdev->pdev);
2054 static void gaudi_sync_irqs(struct hl_device *hdev)
2056 struct gaudi_device *gaudi = hdev->asic_specific;
2057 int i, cq_cnt = hdev->asic_prop.completion_queues_count;
2059 if (!(gaudi->hw_cap_initialized & HW_CAP_MSI))
2062 /* Wait for all pending IRQs to be finished */
2063 if (gaudi->multi_msi_mode) {
2064 for (i = 0 ; i < cq_cnt ; i++)
2065 synchronize_irq(gaudi_pci_irq_vector(hdev, i, false));
2067 synchronize_irq(gaudi_pci_irq_vector(hdev,
2068 GAUDI_EVENT_QUEUE_MSI_IDX,
2071 synchronize_irq(gaudi_pci_irq_vector(hdev, 0, false));
2075 static void gaudi_disable_msi(struct hl_device *hdev)
2077 struct gaudi_device *gaudi = hdev->asic_specific;
2078 int i, irq, cq_cnt = hdev->asic_prop.completion_queues_count;
2080 if (!(gaudi->hw_cap_initialized & HW_CAP_MSI))
2083 gaudi_sync_irqs(hdev);
2085 if (gaudi->multi_msi_mode) {
2086 irq = gaudi_pci_irq_vector(hdev, GAUDI_EVENT_QUEUE_MSI_IDX,
2088 free_irq(irq, &hdev->event_queue);
2090 for (i = 0 ; i < cq_cnt ; i++) {
2091 irq = gaudi_pci_irq_vector(hdev, i, false);
2092 free_irq(irq, &hdev->completion_queue[i]);
2095 free_irq(gaudi_pci_irq_vector(hdev, 0, false), hdev);
2098 pci_free_irq_vectors(hdev->pdev);
2100 gaudi->hw_cap_initialized &= ~HW_CAP_MSI;
2103 static void gaudi_init_scrambler_sram(struct hl_device *hdev)
2105 struct gaudi_device *gaudi = hdev->asic_specific;
2107 if (hdev->asic_prop.fw_security_enabled)
2110 if (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
2111 CPU_BOOT_DEV_STS0_SRAM_SCR_EN)
2114 if (gaudi->hw_cap_initialized & HW_CAP_SRAM_SCRAMBLER)
2117 if (!hdev->sram_scrambler_enable)
2120 WREG32(mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN,
2121 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2122 WREG32(mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN,
2123 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2124 WREG32(mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN,
2125 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2126 WREG32(mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN,
2127 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2128 WREG32(mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN,
2129 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2130 WREG32(mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN,
2131 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2132 WREG32(mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN,
2133 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2134 WREG32(mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN,
2135 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2137 WREG32(mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN,
2138 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2139 WREG32(mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN,
2140 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2141 WREG32(mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN,
2142 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2143 WREG32(mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN,
2144 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2145 WREG32(mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN,
2146 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2147 WREG32(mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN,
2148 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2149 WREG32(mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN,
2150 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2151 WREG32(mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN,
2152 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT);
2154 WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN,
2155 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
2156 WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN,
2157 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
2158 WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN,
2159 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
2160 WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN,
2161 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
2162 WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN,
2163 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
2164 WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN,
2165 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
2166 WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN,
2167 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
2168 WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN,
2169 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT);
2171 gaudi->hw_cap_initialized |= HW_CAP_SRAM_SCRAMBLER;
2174 static void gaudi_init_scrambler_hbm(struct hl_device *hdev)
2176 struct gaudi_device *gaudi = hdev->asic_specific;
2178 if (hdev->asic_prop.fw_security_enabled)
2181 if (hdev->asic_prop.fw_bootfit_cpu_boot_dev_sts0 &
2182 CPU_BOOT_DEV_STS0_DRAM_SCR_EN)
2185 if (gaudi->hw_cap_initialized & HW_CAP_HBM_SCRAMBLER)
2188 if (!hdev->dram_scrambler_enable)
2191 WREG32(mmNIF_RTR_CTRL_0_SCRAM_HBM_EN,
2192 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2193 WREG32(mmNIF_RTR_CTRL_1_SCRAM_HBM_EN,
2194 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2195 WREG32(mmNIF_RTR_CTRL_2_SCRAM_HBM_EN,
2196 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2197 WREG32(mmNIF_RTR_CTRL_3_SCRAM_HBM_EN,
2198 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2199 WREG32(mmNIF_RTR_CTRL_4_SCRAM_HBM_EN,
2200 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2201 WREG32(mmNIF_RTR_CTRL_5_SCRAM_HBM_EN,
2202 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2203 WREG32(mmNIF_RTR_CTRL_6_SCRAM_HBM_EN,
2204 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2205 WREG32(mmNIF_RTR_CTRL_7_SCRAM_HBM_EN,
2206 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2208 WREG32(mmSIF_RTR_CTRL_0_SCRAM_HBM_EN,
2209 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2210 WREG32(mmSIF_RTR_CTRL_1_SCRAM_HBM_EN,
2211 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2212 WREG32(mmSIF_RTR_CTRL_2_SCRAM_HBM_EN,
2213 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2214 WREG32(mmSIF_RTR_CTRL_3_SCRAM_HBM_EN,
2215 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2216 WREG32(mmSIF_RTR_CTRL_4_SCRAM_HBM_EN,
2217 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2218 WREG32(mmSIF_RTR_CTRL_5_SCRAM_HBM_EN,
2219 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2220 WREG32(mmSIF_RTR_CTRL_6_SCRAM_HBM_EN,
2221 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2222 WREG32(mmSIF_RTR_CTRL_7_SCRAM_HBM_EN,
2223 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT);
2225 WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN,
2226 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
2227 WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN,
2228 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
2229 WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN,
2230 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
2231 WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN,
2232 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
2233 WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN,
2234 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
2235 WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN,
2236 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
2237 WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN,
2238 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
2239 WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN,
2240 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT);
2242 gaudi->hw_cap_initialized |= HW_CAP_HBM_SCRAMBLER;
2245 static void gaudi_init_e2e(struct hl_device *hdev)
2247 if (hdev->asic_prop.fw_security_enabled)
2250 if (hdev->asic_prop.fw_bootfit_cpu_boot_dev_sts0 &
2251 CPU_BOOT_DEV_STS0_E2E_CRED_EN)
2254 WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 247 >> 3);
2255 WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 785 >> 3);
2256 WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 49);
2257 WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 101);
2259 WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3);
2260 WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3);
2261 WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1);
2262 WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39);
2264 WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1);
2265 WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1);
2266 WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1);
2267 WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32);
2269 WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3);
2270 WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3);
2271 WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19);
2272 WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32);
2274 WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3);
2275 WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3);
2276 WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19);
2277 WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32);
2279 WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1);
2280 WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1);
2281 WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1);
2282 WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32);
2284 WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3);
2285 WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3);
2286 WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1);
2287 WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39);
2289 WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 297 >> 3);
2290 WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 908 >> 3);
2291 WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 19);
2292 WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 19);
2294 WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 318 >> 3);
2295 WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 956 >> 3);
2296 WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 79);
2297 WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 163);
2299 WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3);
2300 WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3);
2301 WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1);
2302 WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39);
2304 WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1);
2305 WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1);
2306 WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1);
2307 WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32);
2309 WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3);
2310 WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3);
2311 WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19);
2312 WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32);
2314 WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3);
2315 WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3);
2316 WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19);
2317 WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32);
2319 WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1);
2320 WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1);
2321 WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1);
2322 WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32);
2324 WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3);
2325 WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3);
2326 WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1);
2327 WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39);
2329 WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 318 >> 3);
2330 WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 956 >> 3);
2331 WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 79);
2332 WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 79);
2334 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
2335 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
2336 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
2337 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
2339 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
2340 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
2341 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
2342 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
2344 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
2345 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
2346 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
2347 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
2349 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
2350 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
2351 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
2352 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
2354 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
2355 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
2356 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
2357 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
2359 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
2360 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
2361 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
2362 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
2364 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3);
2365 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3);
2366 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162);
2367 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338);
2369 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3);
2370 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3);
2371 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162);
2372 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338);
2374 if (!hdev->dram_scrambler_enable) {
2375 WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21);
2376 WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22);
2377 WREG32(mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F);
2378 WREG32(mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20);
2380 WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21);
2381 WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22);
2382 WREG32(mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F);
2383 WREG32(mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20);
2385 WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21);
2386 WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22);
2387 WREG32(mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F);
2388 WREG32(mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20);
2390 WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21);
2391 WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22);
2392 WREG32(mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F);
2393 WREG32(mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20);
2395 WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21);
2396 WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22);
2397 WREG32(mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F);
2398 WREG32(mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20);
2400 WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21);
2401 WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22);
2402 WREG32(mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F);
2403 WREG32(mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20);
2405 WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21);
2406 WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22);
2407 WREG32(mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F);
2408 WREG32(mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20);
2410 WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21);
2411 WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22);
2412 WREG32(mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F);
2413 WREG32(mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20);
2415 WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21);
2416 WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22);
2417 WREG32(mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F);
2418 WREG32(mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20);
2420 WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21);
2421 WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22);
2422 WREG32(mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F);
2423 WREG32(mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20);
2425 WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21);
2426 WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22);
2427 WREG32(mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F);
2428 WREG32(mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20);
2430 WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21);
2431 WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22);
2432 WREG32(mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F);
2433 WREG32(mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20);
2435 WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21);
2436 WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22);
2437 WREG32(mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F);
2438 WREG32(mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20);
2440 WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21);
2441 WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22);
2442 WREG32(mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F);
2443 WREG32(mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20);
2445 WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21);
2446 WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22);
2447 WREG32(mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F);
2448 WREG32(mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20);
2450 WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21);
2451 WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22);
2452 WREG32(mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F);
2453 WREG32(mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20);
2455 WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0, 0x21);
2456 WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1, 0x22);
2457 WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F);
2458 WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20);
2460 WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0, 0x21);
2461 WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1, 0x22);
2462 WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F);
2463 WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20);
2465 WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0, 0x21);
2466 WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1, 0x22);
2467 WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F);
2468 WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20);
2470 WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0, 0x21);
2471 WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1, 0x22);
2472 WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F);
2473 WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20);
2475 WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0, 0x21);
2476 WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1, 0x22);
2477 WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F);
2478 WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20);
2480 WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0, 0x21);
2481 WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1, 0x22);
2482 WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F);
2483 WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20);
2485 WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0, 0x21);
2486 WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1, 0x22);
2487 WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F);
2488 WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20);
2490 WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0, 0x21);
2491 WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1, 0x22);
2492 WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F);
2493 WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20);
2496 WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_EN,
2497 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2498 WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_EN,
2499 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2501 WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_EN,
2502 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2503 WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_EN,
2504 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2506 WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_EN,
2507 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2508 WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_EN,
2509 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2511 WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_EN,
2512 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2513 WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_EN,
2514 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2516 WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_EN,
2517 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2518 WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_EN,
2519 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2521 WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_EN,
2522 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2523 WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_EN,
2524 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2526 WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_EN,
2527 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2528 WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_EN,
2529 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2531 WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_EN,
2532 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2533 WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_EN,
2534 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2536 WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_EN,
2537 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2538 WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_EN,
2539 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2541 WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_EN,
2542 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2543 WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_EN,
2544 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2546 WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_EN,
2547 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2548 WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_EN,
2549 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2551 WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_EN,
2552 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2553 WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_EN,
2554 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2556 WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_EN,
2557 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2558 WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_EN,
2559 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2561 WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_EN,
2562 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2563 WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_EN,
2564 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2566 WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_EN,
2567 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2568 WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_EN,
2569 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2571 WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_EN,
2572 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT);
2573 WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_EN,
2574 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT);
2576 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN,
2577 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
2578 WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN,
2579 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
2581 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN,
2582 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
2583 WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN,
2584 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
2586 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN,
2587 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
2588 WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN,
2589 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
2591 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN,
2592 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
2593 WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN,
2594 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
2596 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN,
2597 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
2598 WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN,
2599 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
2601 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN,
2602 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
2603 WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN,
2604 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
2606 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN,
2607 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
2608 WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN,
2609 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
2611 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN,
2612 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT);
2613 WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN,
2614 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT);
2617 static void gaudi_init_hbm_cred(struct hl_device *hdev)
2619 uint32_t hbm0_wr, hbm1_wr, hbm0_rd, hbm1_rd;
2621 if (hdev->asic_prop.fw_security_enabled)
2624 if (hdev->asic_prop.fw_bootfit_cpu_boot_dev_sts0 &
2625 CPU_BOOT_DEV_STS0_HBM_CRED_EN)
2628 hbm0_wr = 0x33333333;
2629 hbm0_rd = 0x77777777;
2630 hbm1_wr = 0x55555555;
2631 hbm1_rd = 0xDDDDDDDD;
2633 WREG32(mmDMA_IF_E_N_HBM0_WR_CRED_CNT, hbm0_wr);
2634 WREG32(mmDMA_IF_E_N_HBM1_WR_CRED_CNT, hbm1_wr);
2635 WREG32(mmDMA_IF_E_N_HBM0_RD_CRED_CNT, hbm0_rd);
2636 WREG32(mmDMA_IF_E_N_HBM1_RD_CRED_CNT, hbm1_rd);
2638 WREG32(mmDMA_IF_E_S_HBM0_WR_CRED_CNT, hbm0_wr);
2639 WREG32(mmDMA_IF_E_S_HBM1_WR_CRED_CNT, hbm1_wr);
2640 WREG32(mmDMA_IF_E_S_HBM0_RD_CRED_CNT, hbm0_rd);
2641 WREG32(mmDMA_IF_E_S_HBM1_RD_CRED_CNT, hbm1_rd);
2643 WREG32(mmDMA_IF_W_N_HBM0_WR_CRED_CNT, hbm0_wr);
2644 WREG32(mmDMA_IF_W_N_HBM1_WR_CRED_CNT, hbm1_wr);
2645 WREG32(mmDMA_IF_W_N_HBM0_RD_CRED_CNT, hbm0_rd);
2646 WREG32(mmDMA_IF_W_N_HBM1_RD_CRED_CNT, hbm1_rd);
2648 WREG32(mmDMA_IF_W_S_HBM0_WR_CRED_CNT, hbm0_wr);
2649 WREG32(mmDMA_IF_W_S_HBM1_WR_CRED_CNT, hbm1_wr);
2650 WREG32(mmDMA_IF_W_S_HBM0_RD_CRED_CNT, hbm0_rd);
2651 WREG32(mmDMA_IF_W_S_HBM1_RD_CRED_CNT, hbm1_rd);
2653 WREG32(mmDMA_IF_E_N_HBM_CRED_EN_0,
2654 (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
2655 (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
2656 WREG32(mmDMA_IF_E_S_HBM_CRED_EN_0,
2657 (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
2658 (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
2659 WREG32(mmDMA_IF_W_N_HBM_CRED_EN_0,
2660 (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
2661 (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
2662 WREG32(mmDMA_IF_W_S_HBM_CRED_EN_0,
2663 (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
2664 (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
2666 WREG32(mmDMA_IF_E_N_HBM_CRED_EN_1,
2667 (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
2668 (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
2669 WREG32(mmDMA_IF_E_S_HBM_CRED_EN_1,
2670 (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
2671 (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
2672 WREG32(mmDMA_IF_W_N_HBM_CRED_EN_1,
2673 (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
2674 (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
2675 WREG32(mmDMA_IF_W_S_HBM_CRED_EN_1,
2676 (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) |
2677 (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT));
2680 static void gaudi_init_golden_registers(struct hl_device *hdev)
2685 gaudi_init_e2e(hdev);
2686 gaudi_init_hbm_cred(hdev);
2688 for (tpc_id = 0, tpc_offset = 0;
2689 tpc_id < TPC_NUMBER_OF_ENGINES;
2690 tpc_id++, tpc_offset += TPC_CFG_OFFSET) {
2691 /* Mask all arithmetic interrupts from TPC */
2692 WREG32(mmTPC0_CFG_TPC_INTR_MASK + tpc_offset, 0x8FFE);
2693 /* Set 16 cache lines */
2694 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset,
2695 ICACHE_FETCH_LINE_NUM, 2);
2698 /* Make sure 1st 128 bytes in SRAM are 0 for Tensor DMA */
2699 for (i = 0 ; i < 128 ; i += 8)
2700 writeq(0, hdev->pcie_bar[SRAM_BAR_ID] + i);
2702 WREG32(mmMME0_CTRL_EUS_ROLLUP_CNT_ADD, 3);
2703 WREG32(mmMME1_CTRL_EUS_ROLLUP_CNT_ADD, 3);
2704 WREG32(mmMME2_CTRL_EUS_ROLLUP_CNT_ADD, 3);
2705 WREG32(mmMME3_CTRL_EUS_ROLLUP_CNT_ADD, 3);
2708 static void gaudi_init_pci_dma_qman(struct hl_device *hdev, int dma_id,
2709 int qman_id, dma_addr_t qman_pq_addr)
2711 struct cpu_dyn_regs *dyn_regs =
2712 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
2713 u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi;
2714 u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi;
2715 u32 q_off, dma_qm_offset;
2716 u32 dma_qm_err_cfg, irq_handler_offset;
2718 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
2720 mtr_base_en_lo = lower_32_bits(CFG_BASE +
2721 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
2722 mtr_base_en_hi = upper_32_bits(CFG_BASE +
2723 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
2724 so_base_en_lo = lower_32_bits(CFG_BASE +
2725 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
2726 so_base_en_hi = upper_32_bits(CFG_BASE +
2727 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
2728 mtr_base_ws_lo = lower_32_bits(CFG_BASE +
2729 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
2730 mtr_base_ws_hi = upper_32_bits(CFG_BASE +
2731 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
2732 so_base_ws_lo = lower_32_bits(CFG_BASE +
2733 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
2734 so_base_ws_hi = upper_32_bits(CFG_BASE +
2735 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
2737 q_off = dma_qm_offset + qman_id * 4;
2739 WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_pq_addr));
2740 WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_pq_addr));
2742 WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HL_QUEUE_LENGTH));
2743 WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
2744 WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
2746 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, QMAN_LDMA_SIZE_OFFSET);
2747 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2748 QMAN_LDMA_SRC_OFFSET);
2749 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2750 QMAN_LDMA_DST_OFFSET);
2752 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
2753 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
2754 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
2755 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
2756 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
2757 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
2758 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
2759 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
2761 WREG32(mmDMA0_QM_CP_BARRIER_CFG_0 + q_off, 0x100);
2763 /* The following configuration is needed only once per QMAN */
2765 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
2766 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
2767 le32_to_cpu(dyn_regs->gic_dma_qm_irq_ctrl);
2769 /* Configure RAZWI IRQ */
2770 dma_qm_err_cfg = PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
2771 if (hdev->stop_on_err)
2773 PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
2775 WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg);
2777 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset,
2778 lower_32_bits(CFG_BASE + irq_handler_offset));
2779 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset,
2780 upper_32_bits(CFG_BASE + irq_handler_offset));
2782 WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset,
2783 gaudi_irq_map_table[GAUDI_EVENT_DMA0_QM].cpu_id +
2786 WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset,
2787 QM_ARB_ERR_MSG_EN_MASK);
2789 /* Increase ARB WDT to support streams architecture */
2790 WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset,
2791 GAUDI_ARB_WDT_TIMEOUT);
2793 WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset,
2794 QMAN_EXTERNAL_MAKE_TRUSTED);
2796 WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
2800 static void gaudi_init_dma_core(struct hl_device *hdev, int dma_id)
2802 struct cpu_dyn_regs *dyn_regs =
2803 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
2804 u32 dma_err_cfg = 1 << DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT;
2805 u32 dma_offset = dma_id * DMA_CORE_OFFSET;
2806 u32 irq_handler_offset;
2808 /* Set to maximum possible according to physical size */
2809 WREG32(mmDMA0_CORE_RD_MAX_OUTSTAND + dma_offset, 0);
2810 WREG32(mmDMA0_CORE_RD_MAX_SIZE + dma_offset, 0);
2812 /* WA for H/W bug H3-2116 */
2813 WREG32(mmDMA0_CORE_LBW_MAX_OUTSTAND + dma_offset, 15);
2815 /* STOP_ON bit implies no completion to operation in case of RAZWI */
2816 if (hdev->stop_on_err)
2817 dma_err_cfg |= 1 << DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT;
2819 WREG32(mmDMA0_CORE_ERR_CFG + dma_offset, dma_err_cfg);
2821 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
2822 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
2823 le32_to_cpu(dyn_regs->gic_dma_core_irq_ctrl);
2825 WREG32(mmDMA0_CORE_ERRMSG_ADDR_LO + dma_offset,
2826 lower_32_bits(CFG_BASE + irq_handler_offset));
2827 WREG32(mmDMA0_CORE_ERRMSG_ADDR_HI + dma_offset,
2828 upper_32_bits(CFG_BASE + irq_handler_offset));
2830 WREG32(mmDMA0_CORE_ERRMSG_WDATA + dma_offset,
2831 gaudi_irq_map_table[GAUDI_EVENT_DMA0_CORE].cpu_id + dma_id);
2832 WREG32(mmDMA0_CORE_PROT + dma_offset,
2833 1 << DMA0_CORE_PROT_ERR_VAL_SHIFT);
2834 /* If the channel is secured, it should be in MMU bypass mode */
2835 WREG32(mmDMA0_CORE_SECURE_PROPS + dma_offset,
2836 1 << DMA0_CORE_SECURE_PROPS_MMBP_SHIFT);
2837 WREG32(mmDMA0_CORE_CFG_0 + dma_offset, 1 << DMA0_CORE_CFG_0_EN_SHIFT);
2840 static void gaudi_enable_qman(struct hl_device *hdev, int dma_id,
2843 u32 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
2845 WREG32(mmDMA0_QM_GLBL_CFG0 + dma_qm_offset, enable_mask);
2848 static void gaudi_init_pci_dma_qmans(struct hl_device *hdev)
2850 struct gaudi_device *gaudi = hdev->asic_specific;
2851 struct hl_hw_queue *q;
2852 int i, j, dma_id, cpu_skip, nic_skip, cq_id = 0, q_idx, msi_vec = 0;
2854 if (gaudi->hw_cap_initialized & HW_CAP_PCI_DMA)
2857 for (i = 0 ; i < PCI_DMA_NUMBER_OF_CHNLS ; i++) {
2858 dma_id = gaudi_dma_assignment[i];
2860 * For queues after the CPU Q need to add 1 to get the correct
2861 * queue. In addition, need to add the CPU EQ and NIC IRQs in
2862 * order to get the correct MSI register.
2866 nic_skip = NIC_NUMBER_OF_ENGINES;
2872 for (j = 0 ; j < QMAN_STREAMS ; j++) {
2873 q_idx = 4 * dma_id + j + cpu_skip;
2874 q = &hdev->kernel_queues[q_idx];
2876 q->msi_vec = nic_skip + cpu_skip + msi_vec++;
2877 gaudi_init_pci_dma_qman(hdev, dma_id, j,
2881 gaudi_init_dma_core(hdev, dma_id);
2883 gaudi_enable_qman(hdev, dma_id, PCI_DMA_QMAN_ENABLE);
2886 gaudi->hw_cap_initialized |= HW_CAP_PCI_DMA;
2889 static void gaudi_init_hbm_dma_qman(struct hl_device *hdev, int dma_id,
2890 int qman_id, u64 qman_base_addr)
2892 struct cpu_dyn_regs *dyn_regs =
2893 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
2894 u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi;
2895 u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi;
2896 u32 dma_qm_err_cfg, irq_handler_offset;
2897 u32 q_off, dma_qm_offset;
2899 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
2901 mtr_base_en_lo = lower_32_bits(CFG_BASE +
2902 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
2903 mtr_base_en_hi = upper_32_bits(CFG_BASE +
2904 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
2905 so_base_en_lo = lower_32_bits(CFG_BASE +
2906 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
2907 so_base_en_hi = upper_32_bits(CFG_BASE +
2908 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
2909 mtr_base_ws_lo = lower_32_bits(CFG_BASE +
2910 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
2911 mtr_base_ws_hi = upper_32_bits(CFG_BASE +
2912 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
2913 so_base_ws_lo = lower_32_bits(CFG_BASE +
2914 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
2915 so_base_ws_hi = upper_32_bits(CFG_BASE +
2916 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
2918 q_off = dma_qm_offset + qman_id * 4;
2921 WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off,
2922 lower_32_bits(qman_base_addr));
2923 WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off,
2924 upper_32_bits(qman_base_addr));
2926 WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HBM_DMA_QMAN_LENGTH));
2927 WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
2928 WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
2930 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2931 QMAN_CPDMA_SIZE_OFFSET);
2932 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2933 QMAN_CPDMA_SRC_OFFSET);
2934 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2935 QMAN_CPDMA_DST_OFFSET);
2937 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
2938 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
2939 le32_to_cpu(dyn_regs->gic_dma_qm_irq_ctrl);
2941 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2942 QMAN_LDMA_SIZE_OFFSET);
2943 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2944 QMAN_LDMA_SRC_OFFSET);
2945 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2946 QMAN_LDMA_DST_OFFSET);
2948 /* Configure RAZWI IRQ */
2949 dma_qm_err_cfg = HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
2950 if (hdev->stop_on_err)
2952 HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
2954 WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg);
2956 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset,
2957 lower_32_bits(CFG_BASE + irq_handler_offset));
2958 WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset,
2959 upper_32_bits(CFG_BASE + irq_handler_offset));
2961 WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset,
2962 gaudi_irq_map_table[GAUDI_EVENT_DMA0_QM].cpu_id +
2965 WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset,
2966 QM_ARB_ERR_MSG_EN_MASK);
2968 /* Increase ARB WDT to support streams architecture */
2969 WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset,
2970 GAUDI_ARB_WDT_TIMEOUT);
2972 WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
2973 WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset,
2974 QMAN_INTERNAL_MAKE_TRUSTED);
2977 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
2978 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
2979 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
2980 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
2982 /* Configure DMA5 CP_MSG_BASE 2/3 for sync stream collective */
2983 if (gaudi_dma_assignment[dma_id] == GAUDI_ENGINE_ID_DMA_5) {
2984 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
2986 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
2988 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
2990 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
2995 static void gaudi_init_hbm_dma_qmans(struct hl_device *hdev)
2997 struct gaudi_device *gaudi = hdev->asic_specific;
2998 struct gaudi_internal_qman_info *q;
3000 int i, j, dma_id, internal_q_index;
3002 if (gaudi->hw_cap_initialized & HW_CAP_HBM_DMA)
3005 for (i = 0 ; i < HBM_DMA_NUMBER_OF_CHNLS ; i++) {
3006 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1 + i];
3008 for (j = 0 ; j < QMAN_STREAMS ; j++) {
3010 * Add the CPU queue in order to get the correct queue
3011 * number as all internal queue are placed after it
3013 internal_q_index = dma_id * QMAN_STREAMS + j + 1;
3015 q = &gaudi->internal_qmans[internal_q_index];
3016 qman_base_addr = (u64) q->pq_dma_addr;
3017 gaudi_init_hbm_dma_qman(hdev, dma_id, j,
3021 /* Initializing lower CP for HBM DMA QMAN */
3022 gaudi_init_hbm_dma_qman(hdev, dma_id, 4, 0);
3024 gaudi_init_dma_core(hdev, dma_id);
3026 gaudi_enable_qman(hdev, dma_id, HBM_DMA_QMAN_ENABLE);
3029 gaudi->hw_cap_initialized |= HW_CAP_HBM_DMA;
3032 static void gaudi_init_mme_qman(struct hl_device *hdev, u32 mme_offset,
3033 int qman_id, u64 qman_base_addr)
3035 struct cpu_dyn_regs *dyn_regs =
3036 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
3037 u32 mtr_base_lo, mtr_base_hi;
3038 u32 so_base_lo, so_base_hi;
3039 u32 irq_handler_offset;
3043 mtr_base_lo = lower_32_bits(CFG_BASE +
3044 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3045 mtr_base_hi = upper_32_bits(CFG_BASE +
3046 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3047 so_base_lo = lower_32_bits(CFG_BASE +
3048 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
3049 so_base_hi = upper_32_bits(CFG_BASE +
3050 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
3052 q_off = mme_offset + qman_id * 4;
3055 WREG32(mmMME0_QM_PQ_BASE_LO_0 + q_off,
3056 lower_32_bits(qman_base_addr));
3057 WREG32(mmMME0_QM_PQ_BASE_HI_0 + q_off,
3058 upper_32_bits(qman_base_addr));
3060 WREG32(mmMME0_QM_PQ_SIZE_0 + q_off, ilog2(MME_QMAN_LENGTH));
3061 WREG32(mmMME0_QM_PQ_PI_0 + q_off, 0);
3062 WREG32(mmMME0_QM_PQ_CI_0 + q_off, 0);
3064 WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3065 QMAN_CPDMA_SIZE_OFFSET);
3066 WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3067 QMAN_CPDMA_SRC_OFFSET);
3068 WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3069 QMAN_CPDMA_DST_OFFSET);
3071 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
3072 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
3073 le32_to_cpu(dyn_regs->gic_mme_qm_irq_ctrl);
3075 WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3076 QMAN_LDMA_SIZE_OFFSET);
3077 WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3078 QMAN_LDMA_SRC_OFFSET);
3079 WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3080 QMAN_LDMA_DST_OFFSET);
3082 /* Configure RAZWI IRQ */
3083 mme_id = mme_offset /
3084 (mmMME1_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0) / 2;
3086 mme_qm_err_cfg = MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
3087 if (hdev->stop_on_err)
3089 MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
3091 WREG32(mmMME0_QM_GLBL_ERR_CFG + mme_offset, mme_qm_err_cfg);
3093 WREG32(mmMME0_QM_GLBL_ERR_ADDR_LO + mme_offset,
3094 lower_32_bits(CFG_BASE + irq_handler_offset));
3095 WREG32(mmMME0_QM_GLBL_ERR_ADDR_HI + mme_offset,
3096 upper_32_bits(CFG_BASE + irq_handler_offset));
3098 WREG32(mmMME0_QM_GLBL_ERR_WDATA + mme_offset,
3099 gaudi_irq_map_table[GAUDI_EVENT_MME0_QM].cpu_id +
3102 WREG32(mmMME0_QM_ARB_ERR_MSG_EN + mme_offset,
3103 QM_ARB_ERR_MSG_EN_MASK);
3105 /* Increase ARB WDT to support streams architecture */
3106 WREG32(mmMME0_QM_ARB_SLV_CHOISE_WDT + mme_offset,
3107 GAUDI_ARB_WDT_TIMEOUT);
3109 WREG32(mmMME0_QM_GLBL_CFG1 + mme_offset, 0);
3110 WREG32(mmMME0_QM_GLBL_PROT + mme_offset,
3111 QMAN_INTERNAL_MAKE_TRUSTED);
3114 WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo);
3115 WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi);
3116 WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo);
3117 WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi);
3120 static void gaudi_init_mme_qmans(struct hl_device *hdev)
3122 struct gaudi_device *gaudi = hdev->asic_specific;
3123 struct gaudi_internal_qman_info *q;
3126 int i, internal_q_index;
3128 if (gaudi->hw_cap_initialized & HW_CAP_MME)
3132 * map GAUDI_QUEUE_ID_MME_0_X to the N_W_MME (mmMME2_QM_BASE)
3133 * and GAUDI_QUEUE_ID_MME_1_X to the S_W_MME (mmMME0_QM_BASE)
3136 mme_offset = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0;
3138 for (i = 0 ; i < MME_NUMBER_OF_QMANS ; i++) {
3139 internal_q_index = GAUDI_QUEUE_ID_MME_0_0 + i;
3140 q = &gaudi->internal_qmans[internal_q_index];
3141 qman_base_addr = (u64) q->pq_dma_addr;
3142 gaudi_init_mme_qman(hdev, mme_offset, (i & 0x3),
3148 /* Initializing lower CP for MME QMANs */
3149 mme_offset = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0;
3150 gaudi_init_mme_qman(hdev, mme_offset, 4, 0);
3151 gaudi_init_mme_qman(hdev, 0, 4, 0);
3153 WREG32(mmMME2_QM_GLBL_CFG0, QMAN_MME_ENABLE);
3154 WREG32(mmMME0_QM_GLBL_CFG0, QMAN_MME_ENABLE);
3156 gaudi->hw_cap_initialized |= HW_CAP_MME;
3159 static void gaudi_init_tpc_qman(struct hl_device *hdev, u32 tpc_offset,
3160 int qman_id, u64 qman_base_addr)
3162 struct cpu_dyn_regs *dyn_regs =
3163 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
3164 u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi;
3165 u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi;
3166 u32 tpc_qm_err_cfg, irq_handler_offset;
3169 mtr_base_en_lo = lower_32_bits(CFG_BASE +
3170 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3171 mtr_base_en_hi = upper_32_bits(CFG_BASE +
3172 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3173 so_base_en_lo = lower_32_bits(CFG_BASE +
3174 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
3175 so_base_en_hi = upper_32_bits(CFG_BASE +
3176 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
3177 mtr_base_ws_lo = lower_32_bits(CFG_BASE +
3178 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3179 mtr_base_ws_hi = upper_32_bits(CFG_BASE +
3180 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3181 so_base_ws_lo = lower_32_bits(CFG_BASE +
3182 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
3183 so_base_ws_hi = upper_32_bits(CFG_BASE +
3184 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
3186 q_off = tpc_offset + qman_id * 4;
3188 tpc_id = tpc_offset /
3189 (mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0);
3192 WREG32(mmTPC0_QM_PQ_BASE_LO_0 + q_off,
3193 lower_32_bits(qman_base_addr));
3194 WREG32(mmTPC0_QM_PQ_BASE_HI_0 + q_off,
3195 upper_32_bits(qman_base_addr));
3197 WREG32(mmTPC0_QM_PQ_SIZE_0 + q_off, ilog2(TPC_QMAN_LENGTH));
3198 WREG32(mmTPC0_QM_PQ_PI_0 + q_off, 0);
3199 WREG32(mmTPC0_QM_PQ_CI_0 + q_off, 0);
3201 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3202 QMAN_CPDMA_SIZE_OFFSET);
3203 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3204 QMAN_CPDMA_SRC_OFFSET);
3205 WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3206 QMAN_CPDMA_DST_OFFSET);
3208 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
3209 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
3210 le32_to_cpu(dyn_regs->gic_tpc_qm_irq_ctrl);
3212 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3213 QMAN_LDMA_SIZE_OFFSET);
3214 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3215 QMAN_LDMA_SRC_OFFSET);
3216 WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3217 QMAN_LDMA_DST_OFFSET);
3219 /* Configure RAZWI IRQ */
3220 tpc_qm_err_cfg = TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
3221 if (hdev->stop_on_err)
3223 TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
3225 WREG32(mmTPC0_QM_GLBL_ERR_CFG + tpc_offset, tpc_qm_err_cfg);
3227 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + tpc_offset,
3228 lower_32_bits(CFG_BASE + irq_handler_offset));
3229 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + tpc_offset,
3230 upper_32_bits(CFG_BASE + irq_handler_offset));
3232 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + tpc_offset,
3233 gaudi_irq_map_table[GAUDI_EVENT_TPC0_QM].cpu_id +
3236 WREG32(mmTPC0_QM_ARB_ERR_MSG_EN + tpc_offset,
3237 QM_ARB_ERR_MSG_EN_MASK);
3239 /* Increase ARB WDT to support streams architecture */
3240 WREG32(mmTPC0_QM_ARB_SLV_CHOISE_WDT + tpc_offset,
3241 GAUDI_ARB_WDT_TIMEOUT);
3243 WREG32(mmTPC0_QM_GLBL_CFG1 + tpc_offset, 0);
3244 WREG32(mmTPC0_QM_GLBL_PROT + tpc_offset,
3245 QMAN_INTERNAL_MAKE_TRUSTED);
3248 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
3249 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
3250 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
3251 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
3253 /* Configure TPC7 CP_MSG_BASE 2/3 for sync stream collective */
3255 WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
3257 WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
3259 WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
3261 WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
3266 static void gaudi_init_tpc_qmans(struct hl_device *hdev)
3268 struct gaudi_device *gaudi = hdev->asic_specific;
3269 struct gaudi_internal_qman_info *q;
3271 u32 so_base_hi, tpc_offset = 0;
3272 u32 tpc_delta = mmTPC1_CFG_SM_BASE_ADDRESS_HIGH -
3273 mmTPC0_CFG_SM_BASE_ADDRESS_HIGH;
3274 int i, tpc_id, internal_q_index;
3276 if (gaudi->hw_cap_initialized & HW_CAP_TPC_MASK)
3279 so_base_hi = upper_32_bits(CFG_BASE +
3280 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
3282 for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) {
3283 for (i = 0 ; i < QMAN_STREAMS ; i++) {
3284 internal_q_index = GAUDI_QUEUE_ID_TPC_0_0 +
3285 tpc_id * QMAN_STREAMS + i;
3286 q = &gaudi->internal_qmans[internal_q_index];
3287 qman_base_addr = (u64) q->pq_dma_addr;
3288 gaudi_init_tpc_qman(hdev, tpc_offset, i,
3292 /* Initializing lower CP for TPC QMAN */
3293 gaudi_init_tpc_qman(hdev, tpc_offset, 4, 0);
3295 /* Enable the QMAN and TPC channel */
3296 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset,
3301 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + tpc_id * tpc_delta,
3304 tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0;
3306 gaudi->hw_cap_initialized |=
3307 FIELD_PREP(HW_CAP_TPC_MASK, 1 << tpc_id);
3311 static void gaudi_init_nic_qman(struct hl_device *hdev, u32 nic_offset,
3312 int qman_id, u64 qman_base_addr, int nic_id)
3314 struct cpu_dyn_regs *dyn_regs =
3315 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
3316 u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi;
3317 u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi;
3318 u32 nic_qm_err_cfg, irq_handler_offset;
3321 mtr_base_en_lo = lower_32_bits(CFG_BASE +
3322 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3323 mtr_base_en_hi = upper_32_bits(CFG_BASE +
3324 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3325 so_base_en_lo = lower_32_bits(CFG_BASE +
3326 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
3327 so_base_en_hi = upper_32_bits(CFG_BASE +
3328 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0);
3329 mtr_base_ws_lo = lower_32_bits(CFG_BASE +
3330 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3331 mtr_base_ws_hi = upper_32_bits(CFG_BASE +
3332 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0);
3333 so_base_ws_lo = lower_32_bits(CFG_BASE +
3334 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
3335 so_base_ws_hi = upper_32_bits(CFG_BASE +
3336 mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0);
3338 q_off = nic_offset + qman_id * 4;
3340 WREG32(mmNIC0_QM0_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_base_addr));
3341 WREG32(mmNIC0_QM0_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_base_addr));
3343 WREG32(mmNIC0_QM0_PQ_SIZE_0 + q_off, ilog2(NIC_QMAN_LENGTH));
3344 WREG32(mmNIC0_QM0_PQ_PI_0 + q_off, 0);
3345 WREG32(mmNIC0_QM0_PQ_CI_0 + q_off, 0);
3347 WREG32(mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3348 QMAN_LDMA_SIZE_OFFSET);
3349 WREG32(mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3350 QMAN_LDMA_SRC_OFFSET);
3351 WREG32(mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3352 QMAN_LDMA_DST_OFFSET);
3354 WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
3355 WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
3356 WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
3357 WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
3359 /* Configure NIC CP_MSG_BASE 2/3 for sync stream collective */
3360 WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
3361 WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
3362 WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
3363 WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
3366 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
3367 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
3368 le32_to_cpu(dyn_regs->gic_nic_qm_irq_ctrl);
3370 /* Configure RAZWI IRQ */
3371 nic_qm_err_cfg = NIC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK;
3372 if (hdev->stop_on_err)
3374 NIC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK;
3376 WREG32(mmNIC0_QM0_GLBL_ERR_CFG + nic_offset, nic_qm_err_cfg);
3378 WREG32(mmNIC0_QM0_GLBL_ERR_ADDR_LO + nic_offset,
3379 lower_32_bits(CFG_BASE + irq_handler_offset));
3380 WREG32(mmNIC0_QM0_GLBL_ERR_ADDR_HI + nic_offset,
3381 upper_32_bits(CFG_BASE + irq_handler_offset));
3383 WREG32(mmNIC0_QM0_GLBL_ERR_WDATA + nic_offset,
3384 gaudi_irq_map_table[GAUDI_EVENT_NIC0_QM0].cpu_id +
3387 WREG32(mmNIC0_QM0_ARB_ERR_MSG_EN + nic_offset,
3388 QM_ARB_ERR_MSG_EN_MASK);
3390 /* Increase ARB WDT to support streams architecture */
3391 WREG32(mmNIC0_QM0_ARB_SLV_CHOISE_WDT + nic_offset,
3392 GAUDI_ARB_WDT_TIMEOUT);
3394 WREG32(mmNIC0_QM0_GLBL_CFG1 + nic_offset, 0);
3395 WREG32(mmNIC0_QM0_GLBL_PROT + nic_offset,
3396 QMAN_INTERNAL_MAKE_TRUSTED);
3400 static void gaudi_init_nic_qmans(struct hl_device *hdev)
3402 struct gaudi_device *gaudi = hdev->asic_specific;
3403 struct gaudi_internal_qman_info *q;
3406 u32 nic_delta_between_qmans =
3407 mmNIC0_QM1_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0;
3408 u32 nic_delta_between_nics =
3409 mmNIC1_QM0_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0;
3410 int i, nic_id, internal_q_index;
3412 if (!hdev->nic_ports_mask)
3415 if (gaudi->hw_cap_initialized & HW_CAP_NIC_MASK)
3418 dev_dbg(hdev->dev, "Initializing NIC QMANs\n");
3420 for (nic_id = 0 ; nic_id < NIC_NUMBER_OF_ENGINES ; nic_id++) {
3421 if (!(hdev->nic_ports_mask & (1 << nic_id))) {
3422 nic_offset += nic_delta_between_qmans;
3424 nic_offset -= (nic_delta_between_qmans * 2);
3425 nic_offset += nic_delta_between_nics;
3430 for (i = 0 ; i < QMAN_STREAMS ; i++) {
3431 internal_q_index = GAUDI_QUEUE_ID_NIC_0_0 +
3432 nic_id * QMAN_STREAMS + i;
3433 q = &gaudi->internal_qmans[internal_q_index];
3434 qman_base_addr = (u64) q->pq_dma_addr;
3435 gaudi_init_nic_qman(hdev, nic_offset, (i & 0x3),
3436 qman_base_addr, nic_id);
3439 /* Enable the QMAN */
3440 WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, NIC_QMAN_ENABLE);
3442 nic_offset += nic_delta_between_qmans;
3444 nic_offset -= (nic_delta_between_qmans * 2);
3445 nic_offset += nic_delta_between_nics;
3448 gaudi->hw_cap_initialized |= 1 << (HW_CAP_NIC_SHIFT + nic_id);
3452 static void gaudi_disable_pci_dma_qmans(struct hl_device *hdev)
3454 struct gaudi_device *gaudi = hdev->asic_specific;
3456 if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA))
3459 WREG32(mmDMA0_QM_GLBL_CFG0, 0);
3460 WREG32(mmDMA1_QM_GLBL_CFG0, 0);
3461 WREG32(mmDMA5_QM_GLBL_CFG0, 0);
3464 static void gaudi_disable_hbm_dma_qmans(struct hl_device *hdev)
3466 struct gaudi_device *gaudi = hdev->asic_specific;
3468 if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA))
3471 WREG32(mmDMA2_QM_GLBL_CFG0, 0);
3472 WREG32(mmDMA3_QM_GLBL_CFG0, 0);
3473 WREG32(mmDMA4_QM_GLBL_CFG0, 0);
3474 WREG32(mmDMA6_QM_GLBL_CFG0, 0);
3475 WREG32(mmDMA7_QM_GLBL_CFG0, 0);
3478 static void gaudi_disable_mme_qmans(struct hl_device *hdev)
3480 struct gaudi_device *gaudi = hdev->asic_specific;
3482 if (!(gaudi->hw_cap_initialized & HW_CAP_MME))
3485 WREG32(mmMME2_QM_GLBL_CFG0, 0);
3486 WREG32(mmMME0_QM_GLBL_CFG0, 0);
3489 static void gaudi_disable_tpc_qmans(struct hl_device *hdev)
3491 struct gaudi_device *gaudi = hdev->asic_specific;
3495 if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK))
3498 for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) {
3499 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, 0);
3500 tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0;
3504 static void gaudi_disable_nic_qmans(struct hl_device *hdev)
3506 struct gaudi_device *gaudi = hdev->asic_specific;
3507 u32 nic_mask, nic_offset = 0;
3508 u32 nic_delta_between_qmans =
3509 mmNIC0_QM1_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0;
3510 u32 nic_delta_between_nics =
3511 mmNIC1_QM0_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0;
3514 for (nic_id = 0 ; nic_id < NIC_NUMBER_OF_ENGINES ; nic_id++) {
3515 nic_mask = 1 << (HW_CAP_NIC_SHIFT + nic_id);
3517 if (gaudi->hw_cap_initialized & nic_mask)
3518 WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, 0);
3520 nic_offset += nic_delta_between_qmans;
3522 nic_offset -= (nic_delta_between_qmans * 2);
3523 nic_offset += nic_delta_between_nics;
3528 static void gaudi_stop_pci_dma_qmans(struct hl_device *hdev)
3530 struct gaudi_device *gaudi = hdev->asic_specific;
3532 if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA))
3535 /* Stop upper CPs of QMANs 0.0 to 1.3 and 5.0 to 5.3 */
3536 WREG32(mmDMA0_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3537 WREG32(mmDMA1_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3538 WREG32(mmDMA5_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3541 static void gaudi_stop_hbm_dma_qmans(struct hl_device *hdev)
3543 struct gaudi_device *gaudi = hdev->asic_specific;
3545 if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA))
3548 /* Stop CPs of HBM DMA QMANs */
3550 WREG32(mmDMA2_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3551 WREG32(mmDMA3_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3552 WREG32(mmDMA4_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3553 WREG32(mmDMA6_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3554 WREG32(mmDMA7_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3557 static void gaudi_stop_mme_qmans(struct hl_device *hdev)
3559 struct gaudi_device *gaudi = hdev->asic_specific;
3561 if (!(gaudi->hw_cap_initialized & HW_CAP_MME))
3564 /* Stop CPs of MME QMANs */
3565 WREG32(mmMME2_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3566 WREG32(mmMME0_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3569 static void gaudi_stop_tpc_qmans(struct hl_device *hdev)
3571 struct gaudi_device *gaudi = hdev->asic_specific;
3573 if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK))
3576 WREG32(mmTPC0_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3577 WREG32(mmTPC1_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3578 WREG32(mmTPC2_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3579 WREG32(mmTPC3_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3580 WREG32(mmTPC4_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3581 WREG32(mmTPC5_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3582 WREG32(mmTPC6_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3583 WREG32(mmTPC7_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
3586 static void gaudi_stop_nic_qmans(struct hl_device *hdev)
3588 struct gaudi_device *gaudi = hdev->asic_specific;
3590 /* Stop upper CPs of QMANs */
3592 if (gaudi->hw_cap_initialized & HW_CAP_NIC0)
3593 WREG32(mmNIC0_QM0_GLBL_CFG1,
3594 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3595 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3596 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3598 if (gaudi->hw_cap_initialized & HW_CAP_NIC1)
3599 WREG32(mmNIC0_QM1_GLBL_CFG1,
3600 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3601 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3602 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3604 if (gaudi->hw_cap_initialized & HW_CAP_NIC2)
3605 WREG32(mmNIC1_QM0_GLBL_CFG1,
3606 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3607 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3608 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3610 if (gaudi->hw_cap_initialized & HW_CAP_NIC3)
3611 WREG32(mmNIC1_QM1_GLBL_CFG1,
3612 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3613 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3614 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3616 if (gaudi->hw_cap_initialized & HW_CAP_NIC4)
3617 WREG32(mmNIC2_QM0_GLBL_CFG1,
3618 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3619 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3620 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3622 if (gaudi->hw_cap_initialized & HW_CAP_NIC5)
3623 WREG32(mmNIC2_QM1_GLBL_CFG1,
3624 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3625 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3626 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3628 if (gaudi->hw_cap_initialized & HW_CAP_NIC6)
3629 WREG32(mmNIC3_QM0_GLBL_CFG1,
3630 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3631 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3632 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3634 if (gaudi->hw_cap_initialized & HW_CAP_NIC7)
3635 WREG32(mmNIC3_QM1_GLBL_CFG1,
3636 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3637 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3638 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3640 if (gaudi->hw_cap_initialized & HW_CAP_NIC8)
3641 WREG32(mmNIC4_QM0_GLBL_CFG1,
3642 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3643 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3644 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3646 if (gaudi->hw_cap_initialized & HW_CAP_NIC9)
3647 WREG32(mmNIC4_QM1_GLBL_CFG1,
3648 NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK |
3649 NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK |
3650 NIC0_QM0_GLBL_CFG1_CP_STOP_MASK);
3653 static void gaudi_pci_dma_stall(struct hl_device *hdev)
3655 struct gaudi_device *gaudi = hdev->asic_specific;
3657 if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA))
3660 WREG32(mmDMA0_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3661 WREG32(mmDMA1_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3662 WREG32(mmDMA5_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3665 static void gaudi_hbm_dma_stall(struct hl_device *hdev)
3667 struct gaudi_device *gaudi = hdev->asic_specific;
3669 if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA))
3672 WREG32(mmDMA2_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3673 WREG32(mmDMA3_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3674 WREG32(mmDMA4_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3675 WREG32(mmDMA6_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3676 WREG32(mmDMA7_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT);
3679 static void gaudi_mme_stall(struct hl_device *hdev)
3681 struct gaudi_device *gaudi = hdev->asic_specific;
3683 if (!(gaudi->hw_cap_initialized & HW_CAP_MME))
3686 /* WA for H3-1800 bug: do ACC and SBAB writes twice */
3687 WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3688 WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3689 WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3690 WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3691 WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3692 WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3693 WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3694 WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3695 WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3696 WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3697 WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3698 WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3699 WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3700 WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT);
3701 WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3702 WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT);
3705 static void gaudi_tpc_stall(struct hl_device *hdev)
3707 struct gaudi_device *gaudi = hdev->asic_specific;
3709 if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK))
3712 WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3713 WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3714 WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3715 WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3716 WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3717 WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3718 WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3719 WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
3722 static void gaudi_set_clock_gating(struct hl_device *hdev)
3724 struct gaudi_device *gaudi = hdev->asic_specific;
3729 /* In case we are during debug session, don't enable the clock gate
3730 * as it may interfere
3735 if (hdev->asic_prop.fw_security_enabled)
3738 for (i = GAUDI_PCI_DMA_1, qman_offset = 0 ; i < GAUDI_HBM_DMA_1 ; i++) {
3739 enable = !!(hdev->clock_gating_mask &
3740 (BIT_ULL(gaudi_dma_assignment[i])));
3742 qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET;
3743 WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset,
3744 enable ? QMAN_CGM1_PWR_GATE_EN : 0);
3745 WREG32(mmDMA0_QM_CGM_CFG + qman_offset,
3746 enable ? QMAN_UPPER_CP_CGM_PWR_GATE_EN : 0);
3749 for (i = GAUDI_HBM_DMA_1 ; i < GAUDI_DMA_MAX ; i++) {
3750 enable = !!(hdev->clock_gating_mask &
3751 (BIT_ULL(gaudi_dma_assignment[i])));
3753 /* GC sends work to DMA engine through Upper CP in DMA5 so
3754 * we need to not enable clock gating in that DMA
3756 if (i == GAUDI_HBM_DMA_4)
3759 qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET;
3760 WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset,
3761 enable ? QMAN_CGM1_PWR_GATE_EN : 0);
3762 WREG32(mmDMA0_QM_CGM_CFG + qman_offset,
3763 enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
3766 enable = !!(hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_0)));
3767 WREG32(mmMME0_QM_CGM_CFG1, enable ? QMAN_CGM1_PWR_GATE_EN : 0);
3768 WREG32(mmMME0_QM_CGM_CFG, enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
3770 enable = !!(hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_2)));
3771 WREG32(mmMME2_QM_CGM_CFG1, enable ? QMAN_CGM1_PWR_GATE_EN : 0);
3772 WREG32(mmMME2_QM_CGM_CFG, enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
3774 for (i = 0, qman_offset = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) {
3775 enable = !!(hdev->clock_gating_mask &
3776 (BIT_ULL(GAUDI_ENGINE_ID_TPC_0 + i)));
3778 WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset,
3779 enable ? QMAN_CGM1_PWR_GATE_EN : 0);
3780 WREG32(mmTPC0_QM_CGM_CFG + qman_offset,
3781 enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);
3783 qman_offset += TPC_QMAN_OFFSET;
3786 gaudi->hw_cap_initialized |= HW_CAP_CLK_GATE;
3789 static void gaudi_disable_clock_gating(struct hl_device *hdev)
3791 struct gaudi_device *gaudi = hdev->asic_specific;
3795 if (hdev->asic_prop.fw_security_enabled)
3798 for (i = 0, qman_offset = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) {
3799 WREG32(mmDMA0_QM_CGM_CFG + qman_offset, 0);
3800 WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, 0);
3802 qman_offset += (mmDMA1_QM_CGM_CFG - mmDMA0_QM_CGM_CFG);
3805 WREG32(mmMME0_QM_CGM_CFG, 0);
3806 WREG32(mmMME0_QM_CGM_CFG1, 0);
3807 WREG32(mmMME2_QM_CGM_CFG, 0);
3808 WREG32(mmMME2_QM_CGM_CFG1, 0);
3810 for (i = 0, qman_offset = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) {
3811 WREG32(mmTPC0_QM_CGM_CFG + qman_offset, 0);
3812 WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset, 0);
3814 qman_offset += (mmTPC1_QM_CGM_CFG - mmTPC0_QM_CGM_CFG);
3817 gaudi->hw_cap_initialized &= ~(HW_CAP_CLK_GATE);
3820 static void gaudi_enable_timestamp(struct hl_device *hdev)
3822 /* Disable the timestamp counter */
3823 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
3825 /* Zero the lower/upper parts of the 64-bit counter */
3826 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
3827 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
3829 /* Enable the counter */
3830 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
3833 static void gaudi_disable_timestamp(struct hl_device *hdev)
3835 /* Disable the timestamp counter */
3836 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
3839 static void gaudi_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
3841 u32 wait_timeout_ms;
3844 "Halting compute engines and disabling interrupts\n");
3847 wait_timeout_ms = GAUDI_PLDM_RESET_WAIT_MSEC;
3849 wait_timeout_ms = GAUDI_RESET_WAIT_MSEC;
3854 gaudi_stop_nic_qmans(hdev);
3855 gaudi_stop_mme_qmans(hdev);
3856 gaudi_stop_tpc_qmans(hdev);
3857 gaudi_stop_hbm_dma_qmans(hdev);
3858 gaudi_stop_pci_dma_qmans(hdev);
3860 hdev->asic_funcs->disable_clock_gating(hdev);
3862 msleep(wait_timeout_ms);
3864 gaudi_pci_dma_stall(hdev);
3865 gaudi_hbm_dma_stall(hdev);
3866 gaudi_tpc_stall(hdev);
3867 gaudi_mme_stall(hdev);
3869 msleep(wait_timeout_ms);
3871 gaudi_disable_nic_qmans(hdev);
3872 gaudi_disable_mme_qmans(hdev);
3873 gaudi_disable_tpc_qmans(hdev);
3874 gaudi_disable_hbm_dma_qmans(hdev);
3875 gaudi_disable_pci_dma_qmans(hdev);
3877 gaudi_disable_timestamp(hdev);
3880 gaudi_disable_msi(hdev);
3883 static int gaudi_mmu_init(struct hl_device *hdev)
3885 struct asic_fixed_properties *prop = &hdev->asic_prop;
3886 struct gaudi_device *gaudi = hdev->asic_specific;
3890 if (!hdev->mmu_enable)
3893 if (gaudi->hw_cap_initialized & HW_CAP_MMU)
3896 for (i = 0 ; i < prop->max_asid ; i++) {
3897 hop0_addr = prop->mmu_pgt_addr +
3898 (i * prop->mmu_hop_table_size);
3900 rc = gaudi_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
3903 "failed to set hop0 addr for asid %d\n", i);
3908 /* init MMU cache manage page */
3909 WREG32(mmSTLB_CACHE_INV_BASE_39_8, MMU_CACHE_MNG_ADDR >> 8);
3910 WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
3912 /* mem cache invalidation */
3913 WREG32(mmSTLB_MEM_CACHE_INVALIDATION, 1);
3915 hdev->asic_funcs->mmu_invalidate_cache(hdev, true, 0);
3917 WREG32(mmMMU_UP_MMU_ENABLE, 1);
3918 WREG32(mmMMU_UP_SPI_MASK, 0xF);
3920 WREG32(mmSTLB_HOP_CONFIGURATION,
3921 hdev->mmu_huge_page_opt ? 0x30440 : 0x40440);
3924 * The H/W expects the first PI after init to be 1. After wraparound
3927 gaudi->mmu_cache_inv_pi = 1;
3929 gaudi->hw_cap_initialized |= HW_CAP_MMU;
3937 static int gaudi_load_firmware_to_device(struct hl_device *hdev)
3941 dst = hdev->pcie_bar[HBM_BAR_ID] + LINUX_FW_OFFSET;
3943 return hl_fw_load_fw_to_device(hdev, GAUDI_LINUX_FW_FILE, dst, 0, 0);
3946 static int gaudi_load_boot_fit_to_device(struct hl_device *hdev)
3950 dst = hdev->pcie_bar[SRAM_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
3952 return hl_fw_load_fw_to_device(hdev, GAUDI_BOOT_FIT_FILE, dst, 0, 0);
3955 static void gaudi_init_dynamic_firmware_loader(struct hl_device *hdev)
3957 struct dynamic_fw_load_mgr *dynamic_loader;
3958 struct cpu_dyn_regs *dyn_regs;
3960 dynamic_loader = &hdev->fw_loader.dynamic_loader;
3963 * here we update initial values for few specific dynamic regs (as
3964 * before reading the first descriptor from FW those value has to be
3965 * hard-coded) in later stages of the protocol those values will be
3966 * updated automatically by reading the FW descriptor so data there
3967 * will always be up-to-date
3969 dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
3970 dyn_regs->kmd_msg_to_cpu =
3971 cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
3972 dyn_regs->cpu_cmd_status_to_host =
3973 cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
3975 dynamic_loader->wait_for_bl_timeout = GAUDI_WAIT_FOR_BL_TIMEOUT_USEC;
3978 static void gaudi_init_static_firmware_loader(struct hl_device *hdev)
3980 struct static_fw_load_mgr *static_loader;
3982 static_loader = &hdev->fw_loader.static_loader;
3984 static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
3985 static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
3986 static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
3987 static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
3988 static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
3989 static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0;
3990 static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1;
3991 static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
3992 static_loader->boot_err1_reg = mmCPU_BOOT_ERR1;
3993 static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
3994 static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
3995 static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR));
3996 static_loader->cpu_reset_wait_msec = hdev->pldm ?
3997 GAUDI_PLDM_RESET_WAIT_MSEC :
3998 GAUDI_CPU_RESET_WAIT_MSEC;
4001 static void gaudi_init_firmware_loader(struct hl_device *hdev)
4003 struct asic_fixed_properties *prop = &hdev->asic_prop;
4004 struct fw_load_mgr *fw_loader = &hdev->fw_loader;
4006 /* fill common fields */
4007 fw_loader->linux_loaded = false;
4008 fw_loader->boot_fit_img.image_name = GAUDI_BOOT_FIT_FILE;
4009 fw_loader->linux_img.image_name = GAUDI_LINUX_FW_FILE;
4010 fw_loader->cpu_timeout = GAUDI_CPU_TIMEOUT_USEC;
4011 fw_loader->boot_fit_timeout = GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC;
4012 fw_loader->skip_bmc = !hdev->bmc_enable;
4013 fw_loader->sram_bar_id = SRAM_BAR_ID;
4014 fw_loader->dram_bar_id = HBM_BAR_ID;
4016 if (prop->dynamic_fw_load)
4017 gaudi_init_dynamic_firmware_loader(hdev);
4019 gaudi_init_static_firmware_loader(hdev);
4022 static int gaudi_init_cpu(struct hl_device *hdev)
4024 struct gaudi_device *gaudi = hdev->asic_specific;
4027 if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
4030 if (gaudi->hw_cap_initialized & HW_CAP_CPU)
4034 * The device CPU works with 40 bits addresses.
4035 * This register sets the extension to 50 bits.
4037 if (!hdev->asic_prop.fw_security_enabled)
4038 WREG32(mmCPU_IF_CPU_MSB_ADDR, hdev->cpu_pci_msb_addr);
4040 rc = hl_fw_init_cpu(hdev);
4045 gaudi->hw_cap_initialized |= HW_CAP_CPU;
4050 static int gaudi_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout)
4052 struct cpu_dyn_regs *dyn_regs =
4053 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
4054 struct asic_fixed_properties *prop = &hdev->asic_prop;
4055 struct gaudi_device *gaudi = hdev->asic_specific;
4056 u32 status, irq_handler_offset;
4058 struct hl_hw_queue *cpu_pq =
4059 &hdev->kernel_queues[GAUDI_QUEUE_ID_CPU_PQ];
4062 if (!hdev->cpu_queues_enable)
4065 if (gaudi->hw_cap_initialized & HW_CAP_CPU_Q)
4068 eq = &hdev->event_queue;
4070 WREG32(mmCPU_IF_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
4071 WREG32(mmCPU_IF_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
4073 WREG32(mmCPU_IF_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
4074 WREG32(mmCPU_IF_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
4076 WREG32(mmCPU_IF_CQ_BASE_ADDR_LOW,
4077 lower_32_bits(hdev->cpu_accessible_dma_address));
4078 WREG32(mmCPU_IF_CQ_BASE_ADDR_HIGH,
4079 upper_32_bits(hdev->cpu_accessible_dma_address));
4081 WREG32(mmCPU_IF_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
4082 WREG32(mmCPU_IF_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
4083 WREG32(mmCPU_IF_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
4085 /* Used for EQ CI */
4086 WREG32(mmCPU_IF_EQ_RD_OFFS, 0);
4088 WREG32(mmCPU_IF_PF_PQ_PI, 0);
4090 if (gaudi->multi_msi_mode)
4091 WREG32(mmCPU_IF_QUEUE_INIT, PQ_INIT_STATUS_READY_FOR_CP);
4093 WREG32(mmCPU_IF_QUEUE_INIT,
4094 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI);
4096 irq_handler_offset = prop->gic_interrupts_enable ?
4097 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
4098 le32_to_cpu(dyn_regs->gic_host_pi_upd_irq);
4100 WREG32(irq_handler_offset,
4101 gaudi_irq_map_table[GAUDI_EVENT_PI_UPDATE].cpu_id);
4103 err = hl_poll_timeout(
4105 mmCPU_IF_QUEUE_INIT,
4107 (status == PQ_INIT_STATUS_READY_FOR_HOST),
4113 "Failed to communicate with Device CPU (CPU-CP timeout)\n");
4117 /* update FW application security bits */
4118 if (prop->fw_cpu_boot_dev_sts0_valid)
4119 prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
4120 if (prop->fw_cpu_boot_dev_sts1_valid)
4121 prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
4123 gaudi->hw_cap_initialized |= HW_CAP_CPU_Q;
4127 static void gaudi_pre_hw_init(struct hl_device *hdev)
4129 /* Perform read from the device to make sure device is up */
4132 if (!hdev->asic_prop.fw_security_enabled) {
4133 /* Set the access through PCI bars (Linux driver only) as
4136 WREG32(mmPCIE_WRAP_LBW_PROT_OVR,
4137 (PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK |
4138 PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK));
4140 /* Perform read to flush the waiting writes to ensure
4141 * configuration was set in the device
4143 RREG32(mmPCIE_WRAP_LBW_PROT_OVR);
4147 * Let's mark in the H/W that we have reached this point. We check
4148 * this value in the reset_before_init function to understand whether
4149 * we need to reset the chip before doing H/W init. This register is
4150 * cleared by the H/W upon H/W reset
4152 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
4155 static int gaudi_hw_init(struct hl_device *hdev)
4157 struct gaudi_device *gaudi = hdev->asic_specific;
4160 gaudi_pre_hw_init(hdev);
4162 /* If iATU is done by FW, the HBM bar ALWAYS points to DRAM_PHYS_BASE.
4163 * So we set it here and if anyone tries to move it later to
4164 * a different address, there will be an error
4166 if (hdev->asic_prop.iatu_done_by_fw)
4167 gaudi->hbm_bar_cur_addr = DRAM_PHYS_BASE;
4170 * Before pushing u-boot/linux to device, need to set the hbm bar to
4171 * base address of dram
4173 if (gaudi_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
4175 "failed to map HBM bar to DRAM base address\n");
4179 rc = gaudi_init_cpu(hdev);
4181 dev_err(hdev->dev, "failed to initialize CPU\n");
4185 /* In case the clock gating was enabled in preboot we need to disable
4186 * it here before touching the MME/TPC registers.
4187 * There is no need to take clk gating mutex because when this function
4188 * runs, no other relevant code can run
4190 hdev->asic_funcs->disable_clock_gating(hdev);
4192 /* SRAM scrambler must be initialized after CPU is running from HBM */
4193 gaudi_init_scrambler_sram(hdev);
4195 /* This is here just in case we are working without CPU */
4196 gaudi_init_scrambler_hbm(hdev);
4198 gaudi_init_golden_registers(hdev);
4200 rc = gaudi_mmu_init(hdev);
4204 gaudi_init_security(hdev);
4206 gaudi_init_pci_dma_qmans(hdev);
4208 gaudi_init_hbm_dma_qmans(hdev);
4210 gaudi_init_mme_qmans(hdev);
4212 gaudi_init_tpc_qmans(hdev);
4214 gaudi_init_nic_qmans(hdev);
4216 hdev->asic_funcs->set_clock_gating(hdev);
4218 gaudi_enable_timestamp(hdev);
4220 /* MSI must be enabled before CPU queues and NIC are initialized */
4221 rc = gaudi_enable_msi(hdev);
4223 goto disable_queues;
4225 /* must be called after MSI was enabled */
4226 rc = gaudi_init_cpu_queues(hdev, GAUDI_CPU_TIMEOUT_USEC);
4228 dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n",
4233 /* Perform read from the device to flush all configuration */
4239 gaudi_disable_msi(hdev);
4241 gaudi_disable_mme_qmans(hdev);
4242 gaudi_disable_pci_dma_qmans(hdev);
4247 static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
4249 struct cpu_dyn_regs *dyn_regs =
4250 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
4251 u32 status, reset_timeout_ms, cpu_timeout_ms, irq_handler_offset;
4252 struct gaudi_device *gaudi = hdev->asic_specific;
4253 bool driver_performs_reset;
4256 dev_err(hdev->dev, "GAUDI doesn't support soft-reset\n");
4261 reset_timeout_ms = GAUDI_PLDM_HRESET_TIMEOUT_MSEC;
4262 cpu_timeout_ms = GAUDI_PLDM_RESET_WAIT_MSEC;
4264 reset_timeout_ms = GAUDI_RESET_TIMEOUT_MSEC;
4265 cpu_timeout_ms = GAUDI_CPU_RESET_WAIT_MSEC;
4270 "Firmware performs HARD reset, going to wait %dms\n",
4276 driver_performs_reset = !!(!hdev->asic_prop.fw_security_enabled &&
4277 !hdev->asic_prop.hard_reset_done_by_fw);
4279 /* Set device to handle FLR by H/W as we will put the device CPU to
4282 if (driver_performs_reset)
4283 WREG32(mmPCIE_AUX_FLR_CTRL, (PCIE_AUX_FLR_CTRL_HW_CTRL_MASK |
4284 PCIE_AUX_FLR_CTRL_INT_MASK_MASK));
4286 /* If linux is loaded in the device CPU we need to communicate with it
4287 * via the GIC. Otherwise, we need to use COMMS or the MSG_TO_CPU
4288 * registers in case of old F/Ws
4290 if (hdev->fw_loader.linux_loaded) {
4291 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
4292 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
4293 le32_to_cpu(dyn_regs->gic_host_halt_irq);
4295 WREG32(irq_handler_offset,
4296 gaudi_irq_map_table[GAUDI_EVENT_HALT_MACHINE].cpu_id);
4298 if (hdev->asic_prop.hard_reset_done_by_fw)
4299 hl_fw_ask_hard_reset_without_linux(hdev);
4301 hl_fw_ask_halt_machine_without_linux(hdev);
4304 if (driver_performs_reset) {
4306 /* Configure the reset registers. Must be done as early as
4307 * possible in case we fail during H/W initialization
4309 WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H,
4310 (CFG_RST_H_DMA_MASK |
4311 CFG_RST_H_MME_MASK |
4313 CFG_RST_H_TPC_7_MASK));
4315 WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L, CFG_RST_L_TPC_MASK);
4317 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H,
4318 (CFG_RST_H_HBM_MASK |
4319 CFG_RST_H_TPC_7_MASK |
4320 CFG_RST_H_NIC_MASK |
4322 CFG_RST_H_DMA_MASK |
4323 CFG_RST_H_MME_MASK |
4324 CFG_RST_H_CPU_MASK |
4325 CFG_RST_H_MMU_MASK));
4327 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L,
4328 (CFG_RST_L_IF_MASK |
4329 CFG_RST_L_PSOC_MASK |
4330 CFG_RST_L_TPC_MASK));
4332 msleep(cpu_timeout_ms);
4334 /* Tell ASIC not to re-initialize PCIe */
4335 WREG32(mmPREBOOT_PCIE_EN, LKD_HARD_RESET_MAGIC);
4337 /* Restart BTL/BLR upon hard-reset */
4338 WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 1);
4340 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST,
4341 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT);
4344 "Issued HARD reset command, going to wait %dms\n",
4348 "Firmware performs HARD reset, going to wait %dms\n",
4354 * After hard reset, we can't poll the BTM_FSM register because the PSOC
4355 * itself is in reset. Need to wait until the reset is deasserted
4357 msleep(reset_timeout_ms);
4359 status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
4360 if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
4362 "Timeout while waiting for device to reset 0x%x\n",
4366 gaudi->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
4367 HW_CAP_HBM | HW_CAP_PCI_DMA |
4368 HW_CAP_MME | HW_CAP_TPC_MASK |
4369 HW_CAP_HBM_DMA | HW_CAP_PLL |
4370 HW_CAP_NIC_MASK | HW_CAP_MMU |
4371 HW_CAP_SRAM_SCRAMBLER |
4372 HW_CAP_HBM_SCRAMBLER |
4375 memset(gaudi->events_stat, 0, sizeof(gaudi->events_stat));
4377 hdev->device_cpu_is_halted = false;
4381 static int gaudi_suspend(struct hl_device *hdev)
4385 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS);
4387 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
4392 static int gaudi_resume(struct hl_device *hdev)
4394 return gaudi_init_iatu(hdev);
4397 static int gaudi_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
4398 void *cpu_addr, dma_addr_t dma_addr, size_t size)
4402 vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
4403 VM_DONTCOPY | VM_NORESERVE;
4405 rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
4406 (dma_addr - HOST_PHYS_BASE), size);
4408 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
4413 static void gaudi_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
4415 struct cpu_dyn_regs *dyn_regs =
4416 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
4417 u32 db_reg_offset, db_value, dma_qm_offset, q_off, irq_handler_offset;
4418 struct gaudi_device *gaudi = hdev->asic_specific;
4419 bool invalid_queue = false;
4422 switch (hw_queue_id) {
4423 case GAUDI_QUEUE_ID_DMA_0_0...GAUDI_QUEUE_ID_DMA_0_3:
4424 dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_1];
4425 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4426 q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4;
4427 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4430 case GAUDI_QUEUE_ID_DMA_1_0...GAUDI_QUEUE_ID_DMA_1_3:
4431 dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_2];
4432 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4433 q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4;
4434 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4437 case GAUDI_QUEUE_ID_DMA_2_0...GAUDI_QUEUE_ID_DMA_2_3:
4438 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1];
4439 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4440 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4441 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4444 case GAUDI_QUEUE_ID_DMA_3_0...GAUDI_QUEUE_ID_DMA_3_3:
4445 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_2];
4446 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4447 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4448 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4451 case GAUDI_QUEUE_ID_DMA_4_0...GAUDI_QUEUE_ID_DMA_4_3:
4452 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_3];
4453 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4454 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4455 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4458 case GAUDI_QUEUE_ID_DMA_5_0...GAUDI_QUEUE_ID_DMA_5_3:
4459 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_4];
4460 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4461 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4462 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4465 case GAUDI_QUEUE_ID_DMA_6_0...GAUDI_QUEUE_ID_DMA_6_3:
4466 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_5];
4467 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4468 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4469 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4472 case GAUDI_QUEUE_ID_DMA_7_0...GAUDI_QUEUE_ID_DMA_7_3:
4473 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_6];
4474 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4475 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4476 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4479 case GAUDI_QUEUE_ID_CPU_PQ:
4480 if (gaudi->hw_cap_initialized & HW_CAP_CPU_Q)
4481 db_reg_offset = mmCPU_IF_PF_PQ_PI;
4483 invalid_queue = true;
4486 case GAUDI_QUEUE_ID_MME_0_0:
4487 db_reg_offset = mmMME2_QM_PQ_PI_0;
4490 case GAUDI_QUEUE_ID_MME_0_1:
4491 db_reg_offset = mmMME2_QM_PQ_PI_1;
4494 case GAUDI_QUEUE_ID_MME_0_2:
4495 db_reg_offset = mmMME2_QM_PQ_PI_2;
4498 case GAUDI_QUEUE_ID_MME_0_3:
4499 db_reg_offset = mmMME2_QM_PQ_PI_3;
4502 case GAUDI_QUEUE_ID_MME_1_0:
4503 db_reg_offset = mmMME0_QM_PQ_PI_0;
4506 case GAUDI_QUEUE_ID_MME_1_1:
4507 db_reg_offset = mmMME0_QM_PQ_PI_1;
4510 case GAUDI_QUEUE_ID_MME_1_2:
4511 db_reg_offset = mmMME0_QM_PQ_PI_2;
4514 case GAUDI_QUEUE_ID_MME_1_3:
4515 db_reg_offset = mmMME0_QM_PQ_PI_3;
4518 case GAUDI_QUEUE_ID_TPC_0_0:
4519 db_reg_offset = mmTPC0_QM_PQ_PI_0;
4522 case GAUDI_QUEUE_ID_TPC_0_1:
4523 db_reg_offset = mmTPC0_QM_PQ_PI_1;
4526 case GAUDI_QUEUE_ID_TPC_0_2:
4527 db_reg_offset = mmTPC0_QM_PQ_PI_2;
4530 case GAUDI_QUEUE_ID_TPC_0_3:
4531 db_reg_offset = mmTPC0_QM_PQ_PI_3;
4534 case GAUDI_QUEUE_ID_TPC_1_0:
4535 db_reg_offset = mmTPC1_QM_PQ_PI_0;
4538 case GAUDI_QUEUE_ID_TPC_1_1:
4539 db_reg_offset = mmTPC1_QM_PQ_PI_1;
4542 case GAUDI_QUEUE_ID_TPC_1_2:
4543 db_reg_offset = mmTPC1_QM_PQ_PI_2;
4546 case GAUDI_QUEUE_ID_TPC_1_3:
4547 db_reg_offset = mmTPC1_QM_PQ_PI_3;
4550 case GAUDI_QUEUE_ID_TPC_2_0:
4551 db_reg_offset = mmTPC2_QM_PQ_PI_0;
4554 case GAUDI_QUEUE_ID_TPC_2_1:
4555 db_reg_offset = mmTPC2_QM_PQ_PI_1;
4558 case GAUDI_QUEUE_ID_TPC_2_2:
4559 db_reg_offset = mmTPC2_QM_PQ_PI_2;
4562 case GAUDI_QUEUE_ID_TPC_2_3:
4563 db_reg_offset = mmTPC2_QM_PQ_PI_3;
4566 case GAUDI_QUEUE_ID_TPC_3_0:
4567 db_reg_offset = mmTPC3_QM_PQ_PI_0;
4570 case GAUDI_QUEUE_ID_TPC_3_1:
4571 db_reg_offset = mmTPC3_QM_PQ_PI_1;
4574 case GAUDI_QUEUE_ID_TPC_3_2:
4575 db_reg_offset = mmTPC3_QM_PQ_PI_2;
4578 case GAUDI_QUEUE_ID_TPC_3_3:
4579 db_reg_offset = mmTPC3_QM_PQ_PI_3;
4582 case GAUDI_QUEUE_ID_TPC_4_0:
4583 db_reg_offset = mmTPC4_QM_PQ_PI_0;
4586 case GAUDI_QUEUE_ID_TPC_4_1:
4587 db_reg_offset = mmTPC4_QM_PQ_PI_1;
4590 case GAUDI_QUEUE_ID_TPC_4_2:
4591 db_reg_offset = mmTPC4_QM_PQ_PI_2;
4594 case GAUDI_QUEUE_ID_TPC_4_3:
4595 db_reg_offset = mmTPC4_QM_PQ_PI_3;
4598 case GAUDI_QUEUE_ID_TPC_5_0:
4599 db_reg_offset = mmTPC5_QM_PQ_PI_0;
4602 case GAUDI_QUEUE_ID_TPC_5_1:
4603 db_reg_offset = mmTPC5_QM_PQ_PI_1;
4606 case GAUDI_QUEUE_ID_TPC_5_2:
4607 db_reg_offset = mmTPC5_QM_PQ_PI_2;
4610 case GAUDI_QUEUE_ID_TPC_5_3:
4611 db_reg_offset = mmTPC5_QM_PQ_PI_3;
4614 case GAUDI_QUEUE_ID_TPC_6_0:
4615 db_reg_offset = mmTPC6_QM_PQ_PI_0;
4618 case GAUDI_QUEUE_ID_TPC_6_1:
4619 db_reg_offset = mmTPC6_QM_PQ_PI_1;
4622 case GAUDI_QUEUE_ID_TPC_6_2:
4623 db_reg_offset = mmTPC6_QM_PQ_PI_2;
4626 case GAUDI_QUEUE_ID_TPC_6_3:
4627 db_reg_offset = mmTPC6_QM_PQ_PI_3;
4630 case GAUDI_QUEUE_ID_TPC_7_0:
4631 db_reg_offset = mmTPC7_QM_PQ_PI_0;
4634 case GAUDI_QUEUE_ID_TPC_7_1:
4635 db_reg_offset = mmTPC7_QM_PQ_PI_1;
4638 case GAUDI_QUEUE_ID_TPC_7_2:
4639 db_reg_offset = mmTPC7_QM_PQ_PI_2;
4642 case GAUDI_QUEUE_ID_TPC_7_3:
4643 db_reg_offset = mmTPC7_QM_PQ_PI_3;
4646 case GAUDI_QUEUE_ID_NIC_0_0...GAUDI_QUEUE_ID_NIC_0_3:
4647 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC0))
4648 invalid_queue = true;
4650 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4651 db_reg_offset = mmNIC0_QM0_PQ_PI_0 + q_off;
4654 case GAUDI_QUEUE_ID_NIC_1_0...GAUDI_QUEUE_ID_NIC_1_3:
4655 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC1))
4656 invalid_queue = true;
4658 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4659 db_reg_offset = mmNIC0_QM1_PQ_PI_0 + q_off;
4662 case GAUDI_QUEUE_ID_NIC_2_0...GAUDI_QUEUE_ID_NIC_2_3:
4663 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC2))
4664 invalid_queue = true;
4666 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4667 db_reg_offset = mmNIC1_QM0_PQ_PI_0 + q_off;
4670 case GAUDI_QUEUE_ID_NIC_3_0...GAUDI_QUEUE_ID_NIC_3_3:
4671 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC3))
4672 invalid_queue = true;
4674 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4675 db_reg_offset = mmNIC1_QM1_PQ_PI_0 + q_off;
4678 case GAUDI_QUEUE_ID_NIC_4_0...GAUDI_QUEUE_ID_NIC_4_3:
4679 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC4))
4680 invalid_queue = true;
4682 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4683 db_reg_offset = mmNIC2_QM0_PQ_PI_0 + q_off;
4686 case GAUDI_QUEUE_ID_NIC_5_0...GAUDI_QUEUE_ID_NIC_5_3:
4687 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC5))
4688 invalid_queue = true;
4690 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4691 db_reg_offset = mmNIC2_QM1_PQ_PI_0 + q_off;
4694 case GAUDI_QUEUE_ID_NIC_6_0...GAUDI_QUEUE_ID_NIC_6_3:
4695 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC6))
4696 invalid_queue = true;
4698 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4699 db_reg_offset = mmNIC3_QM0_PQ_PI_0 + q_off;
4702 case GAUDI_QUEUE_ID_NIC_7_0...GAUDI_QUEUE_ID_NIC_7_3:
4703 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC7))
4704 invalid_queue = true;
4706 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4707 db_reg_offset = mmNIC3_QM1_PQ_PI_0 + q_off;
4710 case GAUDI_QUEUE_ID_NIC_8_0...GAUDI_QUEUE_ID_NIC_8_3:
4711 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC8))
4712 invalid_queue = true;
4714 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4715 db_reg_offset = mmNIC4_QM0_PQ_PI_0 + q_off;
4718 case GAUDI_QUEUE_ID_NIC_9_0...GAUDI_QUEUE_ID_NIC_9_3:
4719 if (!(gaudi->hw_cap_initialized & HW_CAP_NIC9))
4720 invalid_queue = true;
4722 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4723 db_reg_offset = mmNIC4_QM1_PQ_PI_0 + q_off;
4727 invalid_queue = true;
4730 if (invalid_queue) {
4731 /* Should never get here */
4732 dev_err(hdev->dev, "h/w queue %d is invalid. Can't set pi\n",
4739 /* ring the doorbell */
4740 WREG32(db_reg_offset, db_value);
4742 if (hw_queue_id == GAUDI_QUEUE_ID_CPU_PQ) {
4743 /* make sure device CPU will read latest data from host */
4746 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
4747 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
4748 le32_to_cpu(dyn_regs->gic_host_pi_upd_irq);
4750 WREG32(irq_handler_offset,
4751 gaudi_irq_map_table[GAUDI_EVENT_PI_UPDATE].cpu_id);
4755 static void gaudi_pqe_write(struct hl_device *hdev, __le64 *pqe,
4758 __le64 *pbd = (__le64 *) bd;
4760 /* The QMANs are on the host memory so a simple copy suffice */
4765 static void *gaudi_dma_alloc_coherent(struct hl_device *hdev, size_t size,
4766 dma_addr_t *dma_handle, gfp_t flags)
4768 void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
4771 /* Shift to the device's base physical address of host memory */
4773 *dma_handle += HOST_PHYS_BASE;
4778 static void gaudi_dma_free_coherent(struct hl_device *hdev, size_t size,
4779 void *cpu_addr, dma_addr_t dma_handle)
4781 /* Cancel the device's base physical address of host memory */
4782 dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
4784 dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
4787 static int gaudi_hbm_scrubbing(struct hl_device *hdev)
4789 struct asic_fixed_properties *prop = &hdev->asic_prop;
4790 u64 cur_addr = DRAM_BASE_ADDR_USER;
4795 while (cur_addr < prop->dram_end_address) {
4796 for (dma_id = 0 ; dma_id < DMA_NUMBER_OF_CHANNELS ; dma_id++) {
4797 u32 dma_offset = dma_id * DMA_CORE_OFFSET;
4800 min((u64)SZ_2G, prop->dram_end_address - cur_addr);
4803 "Doing HBM scrubbing for 0x%09llx - 0x%09llx\n",
4804 cur_addr, cur_addr + chunk_size);
4806 WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset, 0xdeadbeaf);
4807 WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset, 0xdeadbeaf);
4808 WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset,
4809 lower_32_bits(cur_addr));
4810 WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset,
4811 upper_32_bits(cur_addr));
4812 WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset,
4814 WREG32(mmDMA0_CORE_COMMIT + dma_offset,
4815 ((1 << DMA0_CORE_COMMIT_LIN_SHIFT) |
4816 (1 << DMA0_CORE_COMMIT_MEM_SET_SHIFT)));
4818 cur_addr += chunk_size;
4820 if (cur_addr == prop->dram_end_address)
4824 for (dma_id = 0 ; dma_id < DMA_NUMBER_OF_CHANNELS ; dma_id++) {
4825 u32 dma_offset = dma_id * DMA_CORE_OFFSET;
4827 rc = hl_poll_timeout(
4829 mmDMA0_CORE_STS0 + dma_offset,
4831 ((val & DMA0_CORE_STS0_BUSY_MASK) == 0),
4833 HBM_SCRUBBING_TIMEOUT_US);
4837 "DMA Timeout during HBM scrubbing of DMA #%d\n",
4847 static int gaudi_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size)
4849 struct asic_fixed_properties *prop = &hdev->asic_prop;
4850 struct gaudi_device *gaudi = hdev->asic_specific;
4854 if (!hdev->memory_scrub)
4857 if (!addr && !size) {
4858 /* Wait till device is idle */
4859 rc = hl_poll_timeout(
4861 mmDMA0_CORE_STS0/* dummy */,
4863 (hdev->asic_funcs->is_device_idle(hdev, NULL,
4866 HBM_SCRUBBING_TIMEOUT_US);
4868 dev_err(hdev->dev, "waiting for idle timeout\n");
4873 addr = prop->sram_user_base_address;
4874 size = hdev->pldm ? 0x10000 :
4875 (prop->sram_size - SRAM_USER_BASE_OFFSET);
4876 val = 0x7777777777777777ull;
4878 rc = gaudi_memset_device_memory(hdev, addr, size, val);
4881 "Failed to clear SRAM in mem scrub all\n");
4885 mutex_lock(&gaudi->clk_gate_mutex);
4886 hdev->asic_funcs->disable_clock_gating(hdev);
4888 /* Scrub HBM using all DMA channels in parallel */
4889 rc = gaudi_hbm_scrubbing(hdev);
4892 "Failed to clear HBM in mem scrub all\n");
4894 hdev->asic_funcs->set_clock_gating(hdev);
4895 mutex_unlock(&gaudi->clk_gate_mutex);
4901 static void *gaudi_get_int_queue_base(struct hl_device *hdev,
4902 u32 queue_id, dma_addr_t *dma_handle,
4905 struct gaudi_device *gaudi = hdev->asic_specific;
4906 struct gaudi_internal_qman_info *q;
4908 if (queue_id >= GAUDI_QUEUE_ID_SIZE ||
4909 gaudi_queue_type[queue_id] != QUEUE_TYPE_INT) {
4910 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
4914 q = &gaudi->internal_qmans[queue_id];
4915 *dma_handle = q->pq_dma_addr;
4916 *queue_len = q->pq_size / QMAN_PQ_ENTRY_SIZE;
4918 return q->pq_kernel_addr;
4921 static int gaudi_send_cpu_message(struct hl_device *hdev, u32 *msg,
4922 u16 len, u32 timeout, u64 *result)
4924 struct gaudi_device *gaudi = hdev->asic_specific;
4926 if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) {
4933 timeout = GAUDI_MSG_TO_CPU_TIMEOUT_USEC;
4935 return hl_fw_send_cpu_message(hdev, GAUDI_QUEUE_ID_CPU_PQ, msg, len,
4939 static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id)
4941 struct packet_msg_prot *fence_pkt;
4942 dma_addr_t pkt_dma_addr;
4943 u32 fence_val, tmp, timeout_usec;
4944 dma_addr_t fence_dma_addr;
4949 timeout_usec = GAUDI_PLDM_TEST_QUEUE_WAIT_USEC;
4951 timeout_usec = GAUDI_TEST_QUEUE_WAIT_USEC;
4953 fence_val = GAUDI_QMAN0_FENCE_VAL;
4955 fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
4959 "Failed to allocate memory for H/W queue %d testing\n",
4966 fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev,
4967 sizeof(struct packet_msg_prot),
4968 GFP_KERNEL, &pkt_dma_addr);
4971 "Failed to allocate packet for H/W queue %d testing\n",
4974 goto free_fence_ptr;
4977 tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);
4978 tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);
4979 tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
4981 fence_pkt->ctl = cpu_to_le32(tmp);
4982 fence_pkt->value = cpu_to_le32(fence_val);
4983 fence_pkt->addr = cpu_to_le64(fence_dma_addr);
4985 rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
4986 sizeof(struct packet_msg_prot),
4990 "Failed to send fence packet to H/W queue %d\n",
4995 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
4996 1000, timeout_usec, true);
4998 hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
5000 if (rc == -ETIMEDOUT) {
5002 "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
5003 hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
5008 hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt,
5011 hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
5016 static int gaudi_test_cpu_queue(struct hl_device *hdev)
5018 struct gaudi_device *gaudi = hdev->asic_specific;
5021 * check capability here as send_cpu_message() won't update the result
5022 * value if no capability
5024 if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
5027 return hl_fw_test_cpu_queue(hdev);
5030 static int gaudi_test_queues(struct hl_device *hdev)
5032 int i, rc, ret_val = 0;
5034 for (i = 0 ; i < hdev->asic_prop.max_queues ; i++) {
5035 if (hdev->asic_prop.hw_queues_props[i].type == QUEUE_TYPE_EXT) {
5036 rc = gaudi_test_queue(hdev, i);
5042 rc = gaudi_test_cpu_queue(hdev);
5049 static void *gaudi_dma_pool_zalloc(struct hl_device *hdev, size_t size,
5050 gfp_t mem_flags, dma_addr_t *dma_handle)
5054 if (size > GAUDI_DMA_POOL_BLK_SIZE)
5057 kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
5059 /* Shift to the device's base physical address of host memory */
5061 *dma_handle += HOST_PHYS_BASE;
5066 static void gaudi_dma_pool_free(struct hl_device *hdev, void *vaddr,
5067 dma_addr_t dma_addr)
5069 /* Cancel the device's base physical address of host memory */
5070 dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
5072 dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
5075 static void *gaudi_cpu_accessible_dma_pool_alloc(struct hl_device *hdev,
5076 size_t size, dma_addr_t *dma_handle)
5078 return hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
5081 static void gaudi_cpu_accessible_dma_pool_free(struct hl_device *hdev,
5082 size_t size, void *vaddr)
5084 hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
5087 static int gaudi_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl,
5088 int nents, enum dma_data_direction dir)
5090 struct scatterlist *sg;
5093 if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir))
5096 /* Shift to the device's base physical address of host memory */
5097 for_each_sg(sgl, sg, nents, i)
5098 sg->dma_address += HOST_PHYS_BASE;
5103 static void gaudi_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl,
5104 int nents, enum dma_data_direction dir)
5106 struct scatterlist *sg;
5109 /* Cancel the device's base physical address of host memory */
5110 for_each_sg(sgl, sg, nents, i)
5111 sg->dma_address -= HOST_PHYS_BASE;
5113 dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir);
5116 static u32 gaudi_get_dma_desc_list_size(struct hl_device *hdev,
5117 struct sg_table *sgt)
5119 struct scatterlist *sg, *sg_next_iter;
5120 u32 count, dma_desc_cnt;
5122 dma_addr_t addr, addr_next;
5126 for_each_sg(sgt->sgl, sg, sgt->nents, count) {
5128 len = sg_dma_len(sg);
5129 addr = sg_dma_address(sg);
5134 while ((count + 1) < sgt->nents) {
5135 sg_next_iter = sg_next(sg);
5136 len_next = sg_dma_len(sg_next_iter);
5137 addr_next = sg_dma_address(sg_next_iter);
5142 if ((addr + len == addr_next) &&
5143 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
5155 return dma_desc_cnt * sizeof(struct packet_lin_dma);
5158 static int gaudi_pin_memory_before_cs(struct hl_device *hdev,
5159 struct hl_cs_parser *parser,
5160 struct packet_lin_dma *user_dma_pkt,
5161 u64 addr, enum dma_data_direction dir)
5163 struct hl_userptr *userptr;
5166 if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
5167 parser->job_userptr_list, &userptr))
5168 goto already_pinned;
5170 userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
5174 rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
5179 list_add_tail(&userptr->job_node, parser->job_userptr_list);
5181 rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
5182 userptr->sgt->nents, dir);
5184 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
5188 userptr->dma_mapped = true;
5192 parser->patched_cb_size +=
5193 gaudi_get_dma_desc_list_size(hdev, userptr->sgt);
5198 list_del(&userptr->job_node);
5199 hl_unpin_host_memory(hdev, userptr);
5205 static int gaudi_validate_dma_pkt_host(struct hl_device *hdev,
5206 struct hl_cs_parser *parser,
5207 struct packet_lin_dma *user_dma_pkt,
5210 enum dma_data_direction dir;
5211 bool skip_host_mem_pin = false, user_memset;
5215 user_memset = (le32_to_cpu(user_dma_pkt->ctl) &
5216 GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
5217 GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
5221 skip_host_mem_pin = true;
5223 dev_dbg(hdev->dev, "DMA direction is HOST --> DEVICE\n");
5224 dir = DMA_TO_DEVICE;
5225 addr = le64_to_cpu(user_dma_pkt->src_addr);
5227 dev_dbg(hdev->dev, "DMA direction is DEVICE --> HOST\n");
5228 dir = DMA_FROM_DEVICE;
5229 addr = (le64_to_cpu(user_dma_pkt->dst_addr) &
5230 GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >>
5231 GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT;
5234 if (skip_host_mem_pin)
5235 parser->patched_cb_size += sizeof(*user_dma_pkt);
5237 rc = gaudi_pin_memory_before_cs(hdev, parser, user_dma_pkt,
5243 static int gaudi_validate_dma_pkt_no_mmu(struct hl_device *hdev,
5244 struct hl_cs_parser *parser,
5245 struct packet_lin_dma *user_dma_pkt)
5247 bool src_in_host = false;
5248 u64 dst_addr = (le64_to_cpu(user_dma_pkt->dst_addr) &
5249 GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >>
5250 GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT;
5252 dev_dbg(hdev->dev, "DMA packet details:\n");
5253 dev_dbg(hdev->dev, "source == 0x%llx\n",
5254 le64_to_cpu(user_dma_pkt->src_addr));
5255 dev_dbg(hdev->dev, "destination == 0x%llx\n", dst_addr);
5256 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
5259 * Special handling for DMA with size 0. Bypass all validations
5260 * because no transactions will be done except for WR_COMP, which
5261 * is not a security issue
5263 if (!le32_to_cpu(user_dma_pkt->tsize)) {
5264 parser->patched_cb_size += sizeof(*user_dma_pkt);
5268 if (parser->hw_queue_id <= GAUDI_QUEUE_ID_DMA_0_3)
5271 return gaudi_validate_dma_pkt_host(hdev, parser, user_dma_pkt,
5275 static int gaudi_validate_load_and_exe_pkt(struct hl_device *hdev,
5276 struct hl_cs_parser *parser,
5277 struct packet_load_and_exe *user_pkt)
5281 cfg = le32_to_cpu(user_pkt->cfg);
5283 if (cfg & GAUDI_PKT_LOAD_AND_EXE_CFG_DST_MASK) {
5285 "User not allowed to use Load and Execute\n");
5289 parser->patched_cb_size += sizeof(struct packet_load_and_exe);
5294 static int gaudi_validate_cb(struct hl_device *hdev,
5295 struct hl_cs_parser *parser, bool is_mmu)
5297 u32 cb_parsed_length = 0;
5300 parser->patched_cb_size = 0;
5302 /* cb_user_size is more than 0 so loop will always be executed */
5303 while (cb_parsed_length < parser->user_cb_size) {
5304 enum packet_id pkt_id;
5306 struct gaudi_packet *user_pkt;
5308 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
5310 pkt_id = (enum packet_id) (
5311 (le64_to_cpu(user_pkt->header) &
5312 PACKET_HEADER_PACKET_ID_MASK) >>
5313 PACKET_HEADER_PACKET_ID_SHIFT);
5315 if (!validate_packet_id(pkt_id)) {
5316 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
5321 pkt_size = gaudi_packet_sizes[pkt_id];
5322 cb_parsed_length += pkt_size;
5323 if (cb_parsed_length > parser->user_cb_size) {
5325 "packet 0x%x is out of CB boundary\n", pkt_id);
5331 case PACKET_MSG_PROT:
5333 "User not allowed to use MSG_PROT\n");
5338 dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
5343 dev_err(hdev->dev, "User not allowed to use STOP\n");
5347 case PACKET_WREG_BULK:
5349 "User not allowed to use WREG_BULK\n");
5353 case PACKET_LOAD_AND_EXE:
5354 rc = gaudi_validate_load_and_exe_pkt(hdev, parser,
5355 (struct packet_load_and_exe *) user_pkt);
5358 case PACKET_LIN_DMA:
5359 parser->contains_dma_pkt = true;
5361 parser->patched_cb_size += pkt_size;
5363 rc = gaudi_validate_dma_pkt_no_mmu(hdev, parser,
5364 (struct packet_lin_dma *) user_pkt);
5367 case PACKET_WREG_32:
5368 case PACKET_MSG_LONG:
5369 case PACKET_MSG_SHORT:
5373 case PACKET_ARB_POINT:
5374 parser->patched_cb_size += pkt_size;
5378 dev_err(hdev->dev, "Invalid packet header 0x%x\n",
5389 * The new CB should have space at the end for two MSG_PROT packets:
5390 * 1. A packet that will act as a completion packet
5391 * 2. A packet that will generate MSI-X interrupt
5393 if (parser->completion)
5394 parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
5399 static int gaudi_patch_dma_packet(struct hl_device *hdev,
5400 struct hl_cs_parser *parser,
5401 struct packet_lin_dma *user_dma_pkt,
5402 struct packet_lin_dma *new_dma_pkt,
5403 u32 *new_dma_pkt_size)
5405 struct hl_userptr *userptr;
5406 struct scatterlist *sg, *sg_next_iter;
5407 u32 count, dma_desc_cnt, user_wrcomp_en_mask, ctl;
5409 dma_addr_t dma_addr, dma_addr_next;
5410 u64 device_memory_addr, addr;
5411 enum dma_data_direction dir;
5412 struct sg_table *sgt;
5413 bool src_in_host = false;
5414 bool skip_host_mem_pin = false;
5417 ctl = le32_to_cpu(user_dma_pkt->ctl);
5419 if (parser->hw_queue_id <= GAUDI_QUEUE_ID_DMA_0_3)
5422 user_memset = (ctl & GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
5423 GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
5426 addr = le64_to_cpu(user_dma_pkt->src_addr);
5427 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
5428 dir = DMA_TO_DEVICE;
5430 skip_host_mem_pin = true;
5432 addr = le64_to_cpu(user_dma_pkt->dst_addr);
5433 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
5434 dir = DMA_FROM_DEVICE;
5437 if ((!skip_host_mem_pin) &&
5438 (!hl_userptr_is_pinned(hdev, addr,
5439 le32_to_cpu(user_dma_pkt->tsize),
5440 parser->job_userptr_list, &userptr))) {
5441 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
5442 addr, user_dma_pkt->tsize);
5446 if ((user_memset) && (dir == DMA_TO_DEVICE)) {
5447 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
5448 *new_dma_pkt_size = sizeof(*user_dma_pkt);
5452 user_wrcomp_en_mask = ctl & GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK;
5457 for_each_sg(sgt->sgl, sg, sgt->nents, count) {
5458 len = sg_dma_len(sg);
5459 dma_addr = sg_dma_address(sg);
5464 while ((count + 1) < sgt->nents) {
5465 sg_next_iter = sg_next(sg);
5466 len_next = sg_dma_len(sg_next_iter);
5467 dma_addr_next = sg_dma_address(sg_next_iter);
5472 if ((dma_addr + len == dma_addr_next) &&
5473 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
5482 ctl = le32_to_cpu(user_dma_pkt->ctl);
5483 if (likely(dma_desc_cnt))
5484 ctl &= ~GAUDI_PKT_CTL_EB_MASK;
5485 ctl &= ~GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK;
5486 new_dma_pkt->ctl = cpu_to_le32(ctl);
5487 new_dma_pkt->tsize = cpu_to_le32(len);
5489 if (dir == DMA_TO_DEVICE) {
5490 new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
5491 new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
5493 new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
5494 new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
5498 device_memory_addr += len;
5503 if (!dma_desc_cnt) {
5505 "Error of 0 SG entries when patching DMA packet\n");
5509 /* Fix the last dma packet - wrcomp must be as user set it */
5511 new_dma_pkt->ctl |= cpu_to_le32(user_wrcomp_en_mask);
5513 *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
5518 static int gaudi_patch_cb(struct hl_device *hdev,
5519 struct hl_cs_parser *parser)
5521 u32 cb_parsed_length = 0;
5522 u32 cb_patched_cur_length = 0;
5525 /* cb_user_size is more than 0 so loop will always be executed */
5526 while (cb_parsed_length < parser->user_cb_size) {
5527 enum packet_id pkt_id;
5529 u32 new_pkt_size = 0;
5530 struct gaudi_packet *user_pkt, *kernel_pkt;
5532 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
5533 kernel_pkt = parser->patched_cb->kernel_address +
5534 cb_patched_cur_length;
5536 pkt_id = (enum packet_id) (
5537 (le64_to_cpu(user_pkt->header) &
5538 PACKET_HEADER_PACKET_ID_MASK) >>
5539 PACKET_HEADER_PACKET_ID_SHIFT);
5541 if (!validate_packet_id(pkt_id)) {
5542 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
5547 pkt_size = gaudi_packet_sizes[pkt_id];
5548 cb_parsed_length += pkt_size;
5549 if (cb_parsed_length > parser->user_cb_size) {
5551 "packet 0x%x is out of CB boundary\n", pkt_id);
5557 case PACKET_LIN_DMA:
5558 rc = gaudi_patch_dma_packet(hdev, parser,
5559 (struct packet_lin_dma *) user_pkt,
5560 (struct packet_lin_dma *) kernel_pkt,
5562 cb_patched_cur_length += new_pkt_size;
5565 case PACKET_MSG_PROT:
5567 "User not allowed to use MSG_PROT\n");
5572 dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
5577 dev_err(hdev->dev, "User not allowed to use STOP\n");
5581 case PACKET_WREG_32:
5582 case PACKET_WREG_BULK:
5583 case PACKET_MSG_LONG:
5584 case PACKET_MSG_SHORT:
5588 case PACKET_ARB_POINT:
5589 case PACKET_LOAD_AND_EXE:
5590 memcpy(kernel_pkt, user_pkt, pkt_size);
5591 cb_patched_cur_length += pkt_size;
5595 dev_err(hdev->dev, "Invalid packet header 0x%x\n",
5608 static int gaudi_parse_cb_mmu(struct hl_device *hdev,
5609 struct hl_cs_parser *parser)
5611 u64 patched_cb_handle;
5612 u32 patched_cb_size;
5613 struct hl_cb *user_cb;
5617 * The new CB should have space at the end for two MSG_PROT pkt:
5618 * 1. A packet that will act as a completion packet
5619 * 2. A packet that will generate MSI interrupt
5621 if (parser->completion)
5622 parser->patched_cb_size = parser->user_cb_size +
5623 sizeof(struct packet_msg_prot) * 2;
5625 parser->patched_cb_size = parser->user_cb_size;
5627 rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
5628 parser->patched_cb_size, false, false,
5629 &patched_cb_handle);
5633 "Failed to allocate patched CB for DMA CS %d\n",
5638 patched_cb_handle >>= PAGE_SHIFT;
5639 parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
5640 (u32) patched_cb_handle);
5641 /* hl_cb_get should never fail */
5642 if (!parser->patched_cb) {
5643 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
5644 (u32) patched_cb_handle);
5650 * The check that parser->user_cb_size <= parser->user_cb->size was done
5651 * in validate_queue_index().
5653 memcpy(parser->patched_cb->kernel_address,
5654 parser->user_cb->kernel_address,
5655 parser->user_cb_size);
5657 patched_cb_size = parser->patched_cb_size;
5659 /* Validate patched CB instead of user CB */
5660 user_cb = parser->user_cb;
5661 parser->user_cb = parser->patched_cb;
5662 rc = gaudi_validate_cb(hdev, parser, true);
5663 parser->user_cb = user_cb;
5666 hl_cb_put(parser->patched_cb);
5670 if (patched_cb_size != parser->patched_cb_size) {
5671 dev_err(hdev->dev, "user CB size mismatch\n");
5672 hl_cb_put(parser->patched_cb);
5679 * Always call cb destroy here because we still have 1 reference
5680 * to it by calling cb_get earlier. After the job will be completed,
5681 * cb_put will release it, but here we want to remove it from the
5684 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
5685 patched_cb_handle << PAGE_SHIFT);
5690 static int gaudi_parse_cb_no_mmu(struct hl_device *hdev,
5691 struct hl_cs_parser *parser)
5693 u64 patched_cb_handle;
5696 rc = gaudi_validate_cb(hdev, parser, false);
5701 rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
5702 parser->patched_cb_size, false, false,
5703 &patched_cb_handle);
5706 "Failed to allocate patched CB for DMA CS %d\n", rc);
5710 patched_cb_handle >>= PAGE_SHIFT;
5711 parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
5712 (u32) patched_cb_handle);
5713 /* hl_cb_get should never fail here */
5714 if (!parser->patched_cb) {
5715 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
5716 (u32) patched_cb_handle);
5721 rc = gaudi_patch_cb(hdev, parser);
5724 hl_cb_put(parser->patched_cb);
5728 * Always call cb destroy here because we still have 1 reference
5729 * to it by calling cb_get earlier. After the job will be completed,
5730 * cb_put will release it, but here we want to remove it from the
5733 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
5734 patched_cb_handle << PAGE_SHIFT);
5738 hl_userptr_delete_list(hdev, parser->job_userptr_list);
5742 static int gaudi_parse_cb_no_ext_queue(struct hl_device *hdev,
5743 struct hl_cs_parser *parser)
5745 struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
5746 struct gaudi_device *gaudi = hdev->asic_specific;
5747 u32 nic_mask_q_id = 1 << (HW_CAP_NIC_SHIFT +
5748 ((parser->hw_queue_id - GAUDI_QUEUE_ID_NIC_0_0) >> 2));
5750 if ((parser->hw_queue_id >= GAUDI_QUEUE_ID_NIC_0_0) &&
5751 (parser->hw_queue_id <= GAUDI_QUEUE_ID_NIC_9_3) &&
5752 (!(gaudi->hw_cap_initialized & nic_mask_q_id))) {
5753 dev_err(hdev->dev, "h/w queue %d is disabled\n",
5754 parser->hw_queue_id);
5758 /* For internal queue jobs just check if CB address is valid */
5759 if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
5760 parser->user_cb_size,
5761 asic_prop->sram_user_base_address,
5762 asic_prop->sram_end_address))
5765 if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
5766 parser->user_cb_size,
5767 asic_prop->dram_user_base_address,
5768 asic_prop->dram_end_address))
5771 /* PMMU and HPMMU addresses are equal, check only one of them */
5772 if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb,
5773 parser->user_cb_size,
5774 asic_prop->pmmu.start_addr,
5775 asic_prop->pmmu.end_addr))
5779 "CB address 0x%px + 0x%x for internal QMAN is not valid\n",
5780 parser->user_cb, parser->user_cb_size);
5785 static int gaudi_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
5787 struct gaudi_device *gaudi = hdev->asic_specific;
5789 if (parser->queue_type == QUEUE_TYPE_INT)
5790 return gaudi_parse_cb_no_ext_queue(hdev, parser);
5792 if (gaudi->hw_cap_initialized & HW_CAP_MMU)
5793 return gaudi_parse_cb_mmu(hdev, parser);
5795 return gaudi_parse_cb_no_mmu(hdev, parser);
5798 static void gaudi_add_end_of_cb_packets(struct hl_device *hdev,
5799 void *kernel_address, u32 len,
5800 u64 cq_addr, u32 cq_val, u32 msi_vec,
5803 struct gaudi_device *gaudi = hdev->asic_specific;
5804 struct packet_msg_prot *cq_pkt;
5807 cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
5809 tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);
5810 tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
5813 tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);
5815 cq_pkt->ctl = cpu_to_le32(tmp);
5816 cq_pkt->value = cpu_to_le32(cq_val);
5817 cq_pkt->addr = cpu_to_le64(cq_addr);
5821 tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);
5822 tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
5823 cq_pkt->ctl = cpu_to_le32(tmp);
5824 cq_pkt->value = cpu_to_le32(1);
5826 if (!gaudi->multi_msi_mode)
5829 cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_MSI_INTR_0 + msi_vec * 4);
5832 static void gaudi_update_eq_ci(struct hl_device *hdev, u32 val)
5834 WREG32(mmCPU_IF_EQ_RD_OFFS, val);
5837 static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr,
5840 struct packet_lin_dma *lin_dma_pkt;
5841 struct hl_cs_job *job;
5842 u32 cb_size, ctl, err_cause;
5847 cb = hl_cb_kernel_create(hdev, PAGE_SIZE, false);
5851 lin_dma_pkt = cb->kernel_address;
5852 memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
5853 cb_size = sizeof(*lin_dma_pkt);
5855 ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_LIN_DMA);
5856 ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK, 1);
5857 ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_LIN_MASK, 1);
5858 ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
5859 ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
5861 lin_dma_pkt->ctl = cpu_to_le32(ctl);
5862 lin_dma_pkt->src_addr = cpu_to_le64(val);
5863 lin_dma_pkt->dst_addr |= cpu_to_le64(addr);
5864 lin_dma_pkt->tsize = cpu_to_le32(size);
5866 job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
5868 dev_err(hdev->dev, "Failed to allocate a new job\n");
5873 /* Verify DMA is OK */
5874 err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE);
5875 if (err_cause && !hdev->init_done) {
5877 "Clearing DMA0 engine from errors (cause 0x%x)\n",
5879 WREG32(mmDMA0_CORE_ERR_CAUSE, err_cause);
5884 atomic_inc(&job->user_cb->cs_cnt);
5885 job->user_cb_size = cb_size;
5886 job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0;
5887 job->patched_cb = job->user_cb;
5888 job->job_cb_size = job->user_cb_size + sizeof(struct packet_msg_prot);
5890 hl_debugfs_add_job(hdev, job);
5892 rc = gaudi_send_job_on_qman0(hdev, job);
5893 hl_debugfs_remove_job(hdev, job);
5895 atomic_dec(&cb->cs_cnt);
5897 /* Verify DMA is OK */
5898 err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE);
5900 dev_err(hdev->dev, "DMA Failed, cause 0x%x\n", err_cause);
5902 if (!hdev->init_done) {
5904 "Clearing DMA0 engine from errors (cause 0x%x)\n",
5906 WREG32(mmDMA0_CORE_ERR_CAUSE, err_cause);
5913 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, id << PAGE_SHIFT);
5918 static int gaudi_memset_registers(struct hl_device *hdev, u64 reg_base,
5919 u32 num_regs, u32 val)
5921 struct packet_msg_long *pkt;
5922 struct hl_cs_job *job;
5927 cb_size = (sizeof(*pkt) * num_regs) + sizeof(struct packet_msg_prot);
5929 if (cb_size > SZ_2M) {
5930 dev_err(hdev->dev, "CB size must be smaller than %uMB", SZ_2M);
5934 cb = hl_cb_kernel_create(hdev, cb_size, false);
5938 pkt = cb->kernel_address;
5940 ctl = FIELD_PREP(GAUDI_PKT_LONG_CTL_OP_MASK, 0); /* write the value */
5941 ctl |= FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_LONG);
5942 ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);
5943 ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
5944 ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
5946 for (i = 0; i < num_regs ; i++, pkt++) {
5947 pkt->ctl = cpu_to_le32(ctl);
5948 pkt->value = cpu_to_le32(val);
5949 pkt->addr = cpu_to_le64(reg_base + (i * 4));
5952 job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
5954 dev_err(hdev->dev, "Failed to allocate a new job\n");
5961 atomic_inc(&job->user_cb->cs_cnt);
5962 job->user_cb_size = cb_size;
5963 job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0;
5964 job->patched_cb = job->user_cb;
5965 job->job_cb_size = cb_size;
5967 hl_debugfs_add_job(hdev, job);
5969 rc = gaudi_send_job_on_qman0(hdev, job);
5970 hl_debugfs_remove_job(hdev, job);
5972 atomic_dec(&cb->cs_cnt);
5976 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
5981 static int gaudi_restore_sm_registers(struct hl_device *hdev)
5987 base_addr = CFG_BASE + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0;
5988 num_regs = NUM_OF_SOB_IN_BLOCK;
5989 rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
5991 dev_err(hdev->dev, "failed resetting SM registers");
5995 base_addr = CFG_BASE + mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0;
5996 num_regs = NUM_OF_SOB_IN_BLOCK;
5997 rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
5999 dev_err(hdev->dev, "failed resetting SM registers");
6003 base_addr = CFG_BASE + mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0;
6004 num_regs = NUM_OF_SOB_IN_BLOCK;
6005 rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
6007 dev_err(hdev->dev, "failed resetting SM registers");
6011 base_addr = CFG_BASE + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0;
6012 num_regs = NUM_OF_MONITORS_IN_BLOCK;
6013 rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
6015 dev_err(hdev->dev, "failed resetting SM registers");
6019 base_addr = CFG_BASE + mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0;
6020 num_regs = NUM_OF_MONITORS_IN_BLOCK;
6021 rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
6023 dev_err(hdev->dev, "failed resetting SM registers");
6027 base_addr = CFG_BASE + mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0;
6028 num_regs = NUM_OF_MONITORS_IN_BLOCK;
6029 rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
6031 dev_err(hdev->dev, "failed resetting SM registers");
6035 base_addr = CFG_BASE + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 +
6036 (GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT * 4);
6037 num_regs = NUM_OF_SOB_IN_BLOCK - GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT;
6038 rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
6040 dev_err(hdev->dev, "failed resetting SM registers");
6044 base_addr = CFG_BASE + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 +
6045 (GAUDI_FIRST_AVAILABLE_W_S_MONITOR * 4);
6046 num_regs = NUM_OF_MONITORS_IN_BLOCK - GAUDI_FIRST_AVAILABLE_W_S_MONITOR;
6047 rc = gaudi_memset_registers(hdev, base_addr, num_regs, 0);
6049 dev_err(hdev->dev, "failed resetting SM registers");
6056 static void gaudi_restore_dma_registers(struct hl_device *hdev)
6058 u32 sob_delta = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 -
6059 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0;
6062 for (i = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) {
6063 u64 sob_addr = CFG_BASE +
6064 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 +
6066 u32 dma_offset = i * DMA_CORE_OFFSET;
6068 WREG32(mmDMA0_CORE_WR_COMP_ADDR_LO + dma_offset,
6069 lower_32_bits(sob_addr));
6070 WREG32(mmDMA0_CORE_WR_COMP_ADDR_HI + dma_offset,
6071 upper_32_bits(sob_addr));
6072 WREG32(mmDMA0_CORE_WR_COMP_WDATA + dma_offset, 0x80000001);
6074 /* For DMAs 2-7, need to restore WR_AWUSER_31_11 as it can be
6075 * modified by the user for SRAM reduction
6078 WREG32(mmDMA0_CORE_WR_AWUSER_31_11 + dma_offset,
6083 static void gaudi_restore_qm_registers(struct hl_device *hdev)
6088 for (i = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) {
6089 qman_offset = i * DMA_QMAN_OFFSET;
6090 WREG32(mmDMA0_QM_ARB_CFG_0 + qman_offset, 0);
6093 for (i = 0 ; i < MME_NUMBER_OF_MASTER_ENGINES ; i++) {
6094 qman_offset = i * (mmMME2_QM_BASE - mmMME0_QM_BASE);
6095 WREG32(mmMME0_QM_ARB_CFG_0 + qman_offset, 0);
6098 for (i = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) {
6099 qman_offset = i * TPC_QMAN_OFFSET;
6100 WREG32(mmTPC0_QM_ARB_CFG_0 + qman_offset, 0);
6103 for (i = 0 ; i < NIC_NUMBER_OF_ENGINES ; i++) {
6104 qman_offset = (i >> 1) * NIC_MACRO_QMAN_OFFSET +
6105 (i & 0x1) * NIC_ENGINE_QMAN_OFFSET;
6106 WREG32(mmNIC0_QM0_ARB_CFG_0 + qman_offset, 0);
6110 static int gaudi_restore_user_registers(struct hl_device *hdev)
6114 rc = gaudi_restore_sm_registers(hdev);
6118 gaudi_restore_dma_registers(hdev);
6119 gaudi_restore_qm_registers(hdev);
6124 static int gaudi_context_switch(struct hl_device *hdev, u32 asid)
6129 static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev)
6131 struct asic_fixed_properties *prop = &hdev->asic_prop;
6132 struct gaudi_device *gaudi = hdev->asic_specific;
6133 u64 addr = prop->mmu_pgt_addr;
6134 u32 size = prop->mmu_pgt_size + MMU_CACHE_MNG_SIZE;
6136 if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
6139 return gaudi_memset_device_memory(hdev, addr, size, 0);
6142 static void gaudi_restore_phase_topology(struct hl_device *hdev)
6147 static int gaudi_debugfs_read32(struct hl_device *hdev, u64 addr,
6148 bool user_address, u32 *val)
6150 struct asic_fixed_properties *prop = &hdev->asic_prop;
6151 struct gaudi_device *gaudi = hdev->asic_specific;
6152 u64 hbm_bar_addr, host_phys_end;
6155 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
6157 if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
6159 if ((gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) &&
6160 (hdev->clock_gating_mask &
6161 GAUDI_CLK_GATE_DEBUGFS_MASK)) {
6163 dev_err_ratelimited(hdev->dev,
6164 "Can't read register - clock gating is enabled!\n");
6167 *val = RREG32(addr - CFG_BASE);
6170 } else if ((addr >= SRAM_BASE_ADDR) &&
6171 (addr < SRAM_BASE_ADDR + SRAM_BAR_SIZE)) {
6172 *val = readl(hdev->pcie_bar[SRAM_BAR_ID] +
6173 (addr - SRAM_BASE_ADDR));
6174 } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
6175 u64 bar_base_addr = DRAM_PHYS_BASE +
6176 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
6178 hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);
6179 if (hbm_bar_addr != U64_MAX) {
6180 *val = readl(hdev->pcie_bar[HBM_BAR_ID] +
6181 (addr - bar_base_addr));
6183 hbm_bar_addr = gaudi_set_hbm_bar_base(hdev,
6186 if (hbm_bar_addr == U64_MAX)
6188 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
6189 user_address && !iommu_present(&pci_bus_type)) {
6190 *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
6198 static int gaudi_debugfs_write32(struct hl_device *hdev, u64 addr,
6199 bool user_address, u32 val)
6201 struct asic_fixed_properties *prop = &hdev->asic_prop;
6202 struct gaudi_device *gaudi = hdev->asic_specific;
6203 u64 hbm_bar_addr, host_phys_end;
6206 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
6208 if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
6210 if ((gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) &&
6211 (hdev->clock_gating_mask &
6212 GAUDI_CLK_GATE_DEBUGFS_MASK)) {
6214 dev_err_ratelimited(hdev->dev,
6215 "Can't write register - clock gating is enabled!\n");
6218 WREG32(addr - CFG_BASE, val);
6221 } else if ((addr >= SRAM_BASE_ADDR) &&
6222 (addr < SRAM_BASE_ADDR + SRAM_BAR_SIZE)) {
6223 writel(val, hdev->pcie_bar[SRAM_BAR_ID] +
6224 (addr - SRAM_BASE_ADDR));
6225 } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
6226 u64 bar_base_addr = DRAM_PHYS_BASE +
6227 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
6229 hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);
6230 if (hbm_bar_addr != U64_MAX) {
6231 writel(val, hdev->pcie_bar[HBM_BAR_ID] +
6232 (addr - bar_base_addr));
6234 hbm_bar_addr = gaudi_set_hbm_bar_base(hdev,
6237 if (hbm_bar_addr == U64_MAX)
6239 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
6240 user_address && !iommu_present(&pci_bus_type)) {
6241 *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
6249 static int gaudi_debugfs_read64(struct hl_device *hdev, u64 addr,
6250 bool user_address, u64 *val)
6252 struct asic_fixed_properties *prop = &hdev->asic_prop;
6253 struct gaudi_device *gaudi = hdev->asic_specific;
6254 u64 hbm_bar_addr, host_phys_end;
6257 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
6259 if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
6261 if ((gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) &&
6262 (hdev->clock_gating_mask &
6263 GAUDI_CLK_GATE_DEBUGFS_MASK)) {
6265 dev_err_ratelimited(hdev->dev,
6266 "Can't read register - clock gating is enabled!\n");
6269 u32 val_l = RREG32(addr - CFG_BASE);
6270 u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
6272 *val = (((u64) val_h) << 32) | val_l;
6275 } else if ((addr >= SRAM_BASE_ADDR) &&
6276 (addr <= SRAM_BASE_ADDR + SRAM_BAR_SIZE - sizeof(u64))) {
6277 *val = readq(hdev->pcie_bar[SRAM_BAR_ID] +
6278 (addr - SRAM_BASE_ADDR));
6280 DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
6281 u64 bar_base_addr = DRAM_PHYS_BASE +
6282 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
6284 hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);
6285 if (hbm_bar_addr != U64_MAX) {
6286 *val = readq(hdev->pcie_bar[HBM_BAR_ID] +
6287 (addr - bar_base_addr));
6289 hbm_bar_addr = gaudi_set_hbm_bar_base(hdev,
6292 if (hbm_bar_addr == U64_MAX)
6294 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
6295 user_address && !iommu_present(&pci_bus_type)) {
6296 *val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
6304 static int gaudi_debugfs_write64(struct hl_device *hdev, u64 addr,
6305 bool user_address, u64 val)
6307 struct asic_fixed_properties *prop = &hdev->asic_prop;
6308 struct gaudi_device *gaudi = hdev->asic_specific;
6309 u64 hbm_bar_addr, host_phys_end;
6312 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
6314 if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
6316 if ((gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) &&
6317 (hdev->clock_gating_mask &
6318 GAUDI_CLK_GATE_DEBUGFS_MASK)) {
6320 dev_err_ratelimited(hdev->dev,
6321 "Can't write register - clock gating is enabled!\n");
6324 WREG32(addr - CFG_BASE, lower_32_bits(val));
6325 WREG32(addr + sizeof(u32) - CFG_BASE,
6326 upper_32_bits(val));
6329 } else if ((addr >= SRAM_BASE_ADDR) &&
6330 (addr <= SRAM_BASE_ADDR + SRAM_BAR_SIZE - sizeof(u64))) {
6331 writeq(val, hdev->pcie_bar[SRAM_BAR_ID] +
6332 (addr - SRAM_BASE_ADDR));
6334 DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
6335 u64 bar_base_addr = DRAM_PHYS_BASE +
6336 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
6338 hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr);
6339 if (hbm_bar_addr != U64_MAX) {
6340 writeq(val, hdev->pcie_bar[HBM_BAR_ID] +
6341 (addr - bar_base_addr));
6343 hbm_bar_addr = gaudi_set_hbm_bar_base(hdev,
6346 if (hbm_bar_addr == U64_MAX)
6348 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
6349 user_address && !iommu_present(&pci_bus_type)) {
6350 *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
6358 static int gaudi_dma_core_transfer(struct hl_device *hdev, int dma_id, u64 addr,
6359 u32 size_to_dma, dma_addr_t dma_addr)
6365 dma_offset = dma_id * DMA_CORE_OFFSET;
6367 WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset, lower_32_bits(addr));
6368 WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset, upper_32_bits(addr));
6369 WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset, lower_32_bits(dma_addr));
6370 WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset, upper_32_bits(dma_addr));
6371 WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset, size_to_dma);
6372 WREG32(mmDMA0_CORE_COMMIT + dma_offset,
6373 (1 << DMA0_CORE_COMMIT_LIN_SHIFT));
6375 rc = hl_poll_timeout(
6377 mmDMA0_CORE_STS0 + dma_offset,
6379 ((val & DMA0_CORE_STS0_BUSY_MASK) == 0),
6385 "DMA %d timed-out during reading of 0x%llx\n",
6390 /* Verify DMA is OK */
6391 err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
6393 dev_err(hdev->dev, "DMA Failed, cause 0x%x\n", err_cause);
6395 "Clearing DMA0 engine from errors (cause 0x%x)\n",
6397 WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
6405 static int gaudi_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
6408 u32 dma_core_sts0, err_cause, cfg1, size_left, pos, size_to_dma;
6409 struct gaudi_device *gaudi = hdev->asic_specific;
6410 u64 dma_offset, qm_offset;
6411 dma_addr_t dma_addr;
6416 kernel_addr = hdev->asic_funcs->asic_dma_alloc_coherent(
6419 GFP_KERNEL | __GFP_ZERO);
6424 mutex_lock(&gaudi->clk_gate_mutex);
6426 hdev->asic_funcs->disable_clock_gating(hdev);
6428 hdev->asic_funcs->hw_queues_lock(hdev);
6430 dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_1];
6431 dma_offset = dma_id * DMA_CORE_OFFSET;
6432 qm_offset = dma_id * DMA_QMAN_OFFSET;
6433 dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);
6434 is_eng_idle = IS_DMA_IDLE(dma_core_sts0);
6437 dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_2];
6438 dma_offset = dma_id * DMA_CORE_OFFSET;
6439 qm_offset = dma_id * DMA_QMAN_OFFSET;
6440 dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);
6441 is_eng_idle = IS_DMA_IDLE(dma_core_sts0);
6444 dev_err_ratelimited(hdev->dev,
6445 "Can't read via DMA because it is BUSY\n");
6451 cfg1 = RREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset);
6452 WREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset,
6453 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
6455 /* TODO: remove this by mapping the DMA temporary buffer to the MMU
6456 * using the compute ctx ASID, if exists. If not, use the kernel ctx
6459 WREG32_OR(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_VAL_SHIFT));
6461 /* Verify DMA is OK */
6462 err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
6465 "Clearing DMA0 engine from errors (cause 0x%x)\n",
6467 WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
6472 size_to_dma = SZ_2M;
6474 while (size_left > 0) {
6476 if (size_left < SZ_2M)
6477 size_to_dma = size_left;
6479 rc = gaudi_dma_core_transfer(hdev, dma_id, addr, size_to_dma,
6484 memcpy(blob_addr + pos, kernel_addr, size_to_dma);
6486 if (size_left <= SZ_2M)
6494 /* TODO: remove this by mapping the DMA temporary buffer to the MMU
6495 * using the compute ctx ASID, if exists. If not, use the kernel ctx
6498 WREG32_AND(mmDMA0_CORE_PROT + dma_offset,
6499 ~BIT(DMA0_CORE_PROT_VAL_SHIFT));
6501 WREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset, cfg1);
6504 hdev->asic_funcs->hw_queues_unlock(hdev);
6506 hdev->asic_funcs->set_clock_gating(hdev);
6508 mutex_unlock(&gaudi->clk_gate_mutex);
6510 hdev->asic_funcs->asic_dma_free_coherent(hdev, SZ_2M, kernel_addr,
6516 static u64 gaudi_read_pte(struct hl_device *hdev, u64 addr)
6518 struct gaudi_device *gaudi = hdev->asic_specific;
6520 if (hdev->hard_reset_pending)
6523 return readq(hdev->pcie_bar[HBM_BAR_ID] +
6524 (addr - gaudi->hbm_bar_cur_addr));
6527 static void gaudi_write_pte(struct hl_device *hdev, u64 addr, u64 val)
6529 struct gaudi_device *gaudi = hdev->asic_specific;
6531 if (hdev->hard_reset_pending)
6534 writeq(val, hdev->pcie_bar[HBM_BAR_ID] +
6535 (addr - gaudi->hbm_bar_cur_addr));
6538 void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
6540 /* mask to zero the MMBP and ASID bits */
6541 WREG32_AND(reg, ~0x7FF);
6542 WREG32_OR(reg, asid);
6545 static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid)
6547 struct gaudi_device *gaudi = hdev->asic_specific;
6549 if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
6552 if (asid & ~DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK) {
6553 dev_crit(hdev->dev, "asid %u is too big\n", asid);
6557 mutex_lock(&gaudi->clk_gate_mutex);
6559 hdev->asic_funcs->disable_clock_gating(hdev);
6561 gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_0, asid);
6562 gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_1, asid);
6563 gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_2, asid);
6564 gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_3, asid);
6565 gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_4, asid);
6567 gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_0, asid);
6568 gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_1, asid);
6569 gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_2, asid);
6570 gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_3, asid);
6571 gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_4, asid);
6573 gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_0, asid);
6574 gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_1, asid);
6575 gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_2, asid);
6576 gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_3, asid);
6577 gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_4, asid);
6579 gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_0, asid);
6580 gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_1, asid);
6581 gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_2, asid);
6582 gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_3, asid);
6583 gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_4, asid);
6585 gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_0, asid);
6586 gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_1, asid);
6587 gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_2, asid);
6588 gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_3, asid);
6589 gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_4, asid);
6591 gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_0, asid);
6592 gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_1, asid);
6593 gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_2, asid);
6594 gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_3, asid);
6595 gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_4, asid);
6597 gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_0, asid);
6598 gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_1, asid);
6599 gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_2, asid);
6600 gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_3, asid);
6601 gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_4, asid);
6603 gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_0, asid);
6604 gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_1, asid);
6605 gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_2, asid);
6606 gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_3, asid);
6607 gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_4, asid);
6609 gaudi_mmu_prepare_reg(hdev, mmDMA0_CORE_NON_SECURE_PROPS, asid);
6610 gaudi_mmu_prepare_reg(hdev, mmDMA1_CORE_NON_SECURE_PROPS, asid);
6611 gaudi_mmu_prepare_reg(hdev, mmDMA2_CORE_NON_SECURE_PROPS, asid);
6612 gaudi_mmu_prepare_reg(hdev, mmDMA3_CORE_NON_SECURE_PROPS, asid);
6613 gaudi_mmu_prepare_reg(hdev, mmDMA4_CORE_NON_SECURE_PROPS, asid);
6614 gaudi_mmu_prepare_reg(hdev, mmDMA5_CORE_NON_SECURE_PROPS, asid);
6615 gaudi_mmu_prepare_reg(hdev, mmDMA6_CORE_NON_SECURE_PROPS, asid);
6616 gaudi_mmu_prepare_reg(hdev, mmDMA7_CORE_NON_SECURE_PROPS, asid);
6618 gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_0, asid);
6619 gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_1, asid);
6620 gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_2, asid);
6621 gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_3, asid);
6622 gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_4, asid);
6623 gaudi_mmu_prepare_reg(hdev, mmTPC0_CFG_ARUSER_LO, asid);
6624 gaudi_mmu_prepare_reg(hdev, mmTPC0_CFG_AWUSER_LO, asid);
6626 gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_0, asid);
6627 gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_1, asid);
6628 gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_2, asid);
6629 gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_3, asid);
6630 gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_4, asid);
6631 gaudi_mmu_prepare_reg(hdev, mmTPC1_CFG_ARUSER_LO, asid);
6632 gaudi_mmu_prepare_reg(hdev, mmTPC1_CFG_AWUSER_LO, asid);
6634 gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_0, asid);
6635 gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_1, asid);
6636 gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_2, asid);
6637 gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_3, asid);
6638 gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_4, asid);
6639 gaudi_mmu_prepare_reg(hdev, mmTPC2_CFG_ARUSER_LO, asid);
6640 gaudi_mmu_prepare_reg(hdev, mmTPC2_CFG_AWUSER_LO, asid);
6642 gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_0, asid);
6643 gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_1, asid);
6644 gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_2, asid);
6645 gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_3, asid);
6646 gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_4, asid);
6647 gaudi_mmu_prepare_reg(hdev, mmTPC3_CFG_ARUSER_LO, asid);
6648 gaudi_mmu_prepare_reg(hdev, mmTPC3_CFG_AWUSER_LO, asid);
6650 gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_0, asid);
6651 gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_1, asid);
6652 gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_2, asid);
6653 gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_3, asid);
6654 gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_4, asid);
6655 gaudi_mmu_prepare_reg(hdev, mmTPC4_CFG_ARUSER_LO, asid);
6656 gaudi_mmu_prepare_reg(hdev, mmTPC4_CFG_AWUSER_LO, asid);
6658 gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_0, asid);
6659 gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_1, asid);
6660 gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_2, asid);
6661 gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_3, asid);
6662 gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_4, asid);
6663 gaudi_mmu_prepare_reg(hdev, mmTPC5_CFG_ARUSER_LO, asid);
6664 gaudi_mmu_prepare_reg(hdev, mmTPC5_CFG_AWUSER_LO, asid);
6666 gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_0, asid);
6667 gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_1, asid);
6668 gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_2, asid);
6669 gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_3, asid);
6670 gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_4, asid);
6671 gaudi_mmu_prepare_reg(hdev, mmTPC6_CFG_ARUSER_LO, asid);
6672 gaudi_mmu_prepare_reg(hdev, mmTPC6_CFG_AWUSER_LO, asid);
6674 gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_0, asid);
6675 gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_1, asid);
6676 gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_2, asid);
6677 gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_3, asid);
6678 gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_4, asid);
6679 gaudi_mmu_prepare_reg(hdev, mmTPC7_CFG_ARUSER_LO, asid);
6680 gaudi_mmu_prepare_reg(hdev, mmTPC7_CFG_AWUSER_LO, asid);
6682 gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_0, asid);
6683 gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_1, asid);
6684 gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_2, asid);
6685 gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_3, asid);
6686 gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_4, asid);
6687 gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_0, asid);
6688 gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_1, asid);
6689 gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_2, asid);
6690 gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_3, asid);
6691 gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_4, asid);
6693 gaudi_mmu_prepare_reg(hdev, mmMME0_SBAB_ARUSER0, asid);
6694 gaudi_mmu_prepare_reg(hdev, mmMME0_SBAB_ARUSER1, asid);
6695 gaudi_mmu_prepare_reg(hdev, mmMME1_SBAB_ARUSER0, asid);
6696 gaudi_mmu_prepare_reg(hdev, mmMME1_SBAB_ARUSER1, asid);
6697 gaudi_mmu_prepare_reg(hdev, mmMME2_SBAB_ARUSER0, asid);
6698 gaudi_mmu_prepare_reg(hdev, mmMME2_SBAB_ARUSER1, asid);
6699 gaudi_mmu_prepare_reg(hdev, mmMME3_SBAB_ARUSER0, asid);
6700 gaudi_mmu_prepare_reg(hdev, mmMME3_SBAB_ARUSER1, asid);
6701 gaudi_mmu_prepare_reg(hdev, mmMME0_ACC_WBC, asid);
6702 gaudi_mmu_prepare_reg(hdev, mmMME1_ACC_WBC, asid);
6703 gaudi_mmu_prepare_reg(hdev, mmMME2_ACC_WBC, asid);
6704 gaudi_mmu_prepare_reg(hdev, mmMME3_ACC_WBC, asid);
6706 if (gaudi->hw_cap_initialized & HW_CAP_NIC0) {
6707 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0,
6709 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1,
6711 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2,
6713 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3,
6715 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4,
6719 if (gaudi->hw_cap_initialized & HW_CAP_NIC1) {
6720 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_0,
6722 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_1,
6724 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_2,
6726 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_3,
6728 gaudi_mmu_prepare_reg(hdev, mmNIC0_QM1_GLBL_NON_SECURE_PROPS_4,
6732 if (gaudi->hw_cap_initialized & HW_CAP_NIC2) {
6733 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_0,
6735 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_1,
6737 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_2,
6739 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_3,
6741 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM0_GLBL_NON_SECURE_PROPS_4,
6745 if (gaudi->hw_cap_initialized & HW_CAP_NIC3) {
6746 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_0,
6748 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_1,
6750 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_2,
6752 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_3,
6754 gaudi_mmu_prepare_reg(hdev, mmNIC1_QM1_GLBL_NON_SECURE_PROPS_4,
6758 if (gaudi->hw_cap_initialized & HW_CAP_NIC4) {
6759 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_0,
6761 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_1,
6763 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_2,
6765 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_3,
6767 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM0_GLBL_NON_SECURE_PROPS_4,
6771 if (gaudi->hw_cap_initialized & HW_CAP_NIC5) {
6772 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0,
6774 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1,
6776 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2,
6778 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3,
6780 gaudi_mmu_prepare_reg(hdev, mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4,
6784 if (gaudi->hw_cap_initialized & HW_CAP_NIC6) {
6785 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_0,
6787 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_1,
6789 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_2,
6791 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_3,
6793 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM0_GLBL_NON_SECURE_PROPS_4,
6797 if (gaudi->hw_cap_initialized & HW_CAP_NIC7) {
6798 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_0,
6800 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_1,
6802 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_2,
6804 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_3,
6806 gaudi_mmu_prepare_reg(hdev, mmNIC3_QM1_GLBL_NON_SECURE_PROPS_4,
6810 if (gaudi->hw_cap_initialized & HW_CAP_NIC8) {
6811 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_0,
6813 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_1,
6815 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_2,
6817 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_3,
6819 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM0_GLBL_NON_SECURE_PROPS_4,
6823 if (gaudi->hw_cap_initialized & HW_CAP_NIC9) {
6824 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_0,
6826 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_1,
6828 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_2,
6830 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_3,
6832 gaudi_mmu_prepare_reg(hdev, mmNIC4_QM1_GLBL_NON_SECURE_PROPS_4,
6836 gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_ARUSER, asid);
6837 gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_AWUSER, asid);
6839 hdev->asic_funcs->set_clock_gating(hdev);
6841 mutex_unlock(&gaudi->clk_gate_mutex);
6844 static int gaudi_send_job_on_qman0(struct hl_device *hdev,
6845 struct hl_cs_job *job)
6847 struct packet_msg_prot *fence_pkt;
6849 dma_addr_t fence_dma_addr;
6851 u32 tmp, timeout, dma_offset;
6855 timeout = GAUDI_PLDM_QMAN0_TIMEOUT_USEC;
6857 timeout = HL_DEVICE_TIMEOUT_USEC;
6859 if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
6860 dev_err_ratelimited(hdev->dev,
6861 "Can't send driver job on QMAN0 because the device is not idle\n");
6865 fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
6869 "Failed to allocate fence memory for QMAN0\n");
6873 cb = job->patched_cb;
6875 fence_pkt = cb->kernel_address +
6876 job->job_cb_size - sizeof(struct packet_msg_prot);
6878 tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);
6879 tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);
6880 tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
6882 fence_pkt->ctl = cpu_to_le32(tmp);
6883 fence_pkt->value = cpu_to_le32(GAUDI_QMAN0_FENCE_VAL);
6884 fence_pkt->addr = cpu_to_le64(fence_dma_addr);
6886 dma_offset = gaudi_dma_assignment[GAUDI_PCI_DMA_1] * DMA_CORE_OFFSET;
6888 WREG32(mmDMA0_CORE_PROT + dma_offset,
6889 BIT(DMA0_CORE_PROT_ERR_VAL_SHIFT) | BIT(DMA0_CORE_PROT_VAL_SHIFT));
6891 rc = hl_hw_queue_send_cb_no_cmpl(hdev, GAUDI_QUEUE_ID_DMA_0_0,
6892 job->job_cb_size, cb->bus_address);
6894 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
6895 goto free_fence_ptr;
6898 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
6899 (tmp == GAUDI_QMAN0_FENCE_VAL), 1000,
6902 hl_hw_queue_inc_ci_kernel(hdev, GAUDI_QUEUE_ID_DMA_0_0);
6904 if (rc == -ETIMEDOUT) {
6905 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
6906 goto free_fence_ptr;
6910 WREG32(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_ERR_VAL_SHIFT));
6912 hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
6917 static void gaudi_get_event_desc(u16 event_type, char *desc, size_t size)
6919 if (event_type >= GAUDI_EVENT_SIZE)
6920 goto event_not_supported;
6922 if (!gaudi_irq_map_table[event_type].valid)
6923 goto event_not_supported;
6925 snprintf(desc, size, gaudi_irq_map_table[event_type].name);
6929 event_not_supported:
6930 snprintf(desc, size, "N/A");
6933 static const char *gaudi_get_razwi_initiator_dma_name(struct hl_device *hdev,
6934 u32 x_y, bool is_write)
6936 u32 dma_id[2], dma_offset, err_cause[2], mask, i;
6938 mask = is_write ? DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK :
6939 DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK;
6942 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0:
6943 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1:
6947 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0:
6948 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1:
6952 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0:
6953 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1:
6957 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0:
6958 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1:
6963 goto unknown_initiator;
6966 for (i = 0 ; i < 2 ; i++) {
6967 dma_offset = dma_id[i] * DMA_CORE_OFFSET;
6968 err_cause[i] = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
6972 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0:
6973 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1:
6974 if ((err_cause[0] & mask) && !(err_cause[1] & mask))
6976 else if (!(err_cause[0] & mask) && (err_cause[1] & mask))
6979 return "DMA0 or DMA2";
6980 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0:
6981 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1:
6982 if ((err_cause[0] & mask) && !(err_cause[1] & mask))
6984 else if (!(err_cause[0] & mask) && (err_cause[1] & mask))
6987 return "DMA1 or DMA3";
6988 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0:
6989 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1:
6990 if ((err_cause[0] & mask) && !(err_cause[1] & mask))
6992 else if (!(err_cause[0] & mask) && (err_cause[1] & mask))
6995 return "DMA4 or DMA6";
6996 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0:
6997 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1:
6998 if ((err_cause[0] & mask) && !(err_cause[1] & mask))
7000 else if (!(err_cause[0] & mask) && (err_cause[1] & mask))
7003 return "DMA5 or DMA7";
7007 return "unknown initiator";
7010 static const char *gaudi_get_razwi_initiator_name(struct hl_device *hdev,
7013 u32 val, x_y, axi_id;
7015 val = is_write ? RREG32(mmMMU_UP_RAZWI_WRITE_ID) :
7016 RREG32(mmMMU_UP_RAZWI_READ_ID);
7017 x_y = val & ((RAZWI_INITIATOR_Y_MASK << RAZWI_INITIATOR_Y_SHIFT) |
7018 (RAZWI_INITIATOR_X_MASK << RAZWI_INITIATOR_X_SHIFT));
7019 axi_id = val & (RAZWI_INITIATOR_AXI_ID_MASK <<
7020 RAZWI_INITIATOR_AXI_ID_SHIFT);
7023 case RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0:
7024 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC))
7026 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC))
7029 case RAZWI_INITIATOR_ID_X_Y_TPC1:
7031 case RAZWI_INITIATOR_ID_X_Y_MME0_0:
7032 case RAZWI_INITIATOR_ID_X_Y_MME0_1:
7034 case RAZWI_INITIATOR_ID_X_Y_MME1_0:
7035 case RAZWI_INITIATOR_ID_X_Y_MME1_1:
7037 case RAZWI_INITIATOR_ID_X_Y_TPC2:
7039 case RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC:
7040 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC))
7042 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_PCI))
7044 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_CPU))
7046 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_PSOC))
7049 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0:
7050 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1:
7051 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0:
7052 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1:
7053 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0:
7054 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1:
7055 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0:
7056 case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1:
7057 return gaudi_get_razwi_initiator_dma_name(hdev, x_y, is_write);
7058 case RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2:
7059 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC))
7061 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC))
7063 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC_FT))
7066 case RAZWI_INITIATOR_ID_X_Y_TPC5:
7068 case RAZWI_INITIATOR_ID_X_Y_MME2_0:
7069 case RAZWI_INITIATOR_ID_X_Y_MME2_1:
7071 case RAZWI_INITIATOR_ID_X_Y_MME3_0:
7072 case RAZWI_INITIATOR_ID_X_Y_MME3_1:
7074 case RAZWI_INITIATOR_ID_X_Y_TPC6:
7076 case RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5:
7077 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC))
7079 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC))
7081 if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC_FT))
7089 "Unknown RAZWI initiator ID 0x%x [Y=%d, X=%d, AXI_ID=%d]\n",
7091 (val >> RAZWI_INITIATOR_Y_SHIFT) & RAZWI_INITIATOR_Y_MASK,
7092 (val >> RAZWI_INITIATOR_X_SHIFT) & RAZWI_INITIATOR_X_MASK,
7093 (val >> RAZWI_INITIATOR_AXI_ID_SHIFT) &
7094 RAZWI_INITIATOR_AXI_ID_MASK);
7096 return "unknown initiator";
7099 static void gaudi_print_razwi_info(struct hl_device *hdev)
7101 if (RREG32(mmMMU_UP_RAZWI_WRITE_VLD)) {
7102 dev_err_ratelimited(hdev->dev,
7103 "RAZWI event caused by illegal write of %s\n",
7104 gaudi_get_razwi_initiator_name(hdev, true));
7105 WREG32(mmMMU_UP_RAZWI_WRITE_VLD, 0);
7108 if (RREG32(mmMMU_UP_RAZWI_READ_VLD)) {
7109 dev_err_ratelimited(hdev->dev,
7110 "RAZWI event caused by illegal read of %s\n",
7111 gaudi_get_razwi_initiator_name(hdev, false));
7112 WREG32(mmMMU_UP_RAZWI_READ_VLD, 0);
7116 static void gaudi_print_mmu_error_info(struct hl_device *hdev)
7118 struct gaudi_device *gaudi = hdev->asic_specific;
7122 if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
7125 val = RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE);
7126 if (val & MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
7127 addr = val & MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
7129 addr |= RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE_VA);
7131 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n",
7134 WREG32(mmMMU_UP_PAGE_ERROR_CAPTURE, 0);
7137 val = RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE);
7138 if (val & MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK) {
7139 addr = val & MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK;
7141 addr |= RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE_VA);
7143 dev_err_ratelimited(hdev->dev,
7144 "MMU access error on va 0x%llx\n", addr);
7146 WREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE, 0);
7151 * +-------------------+------------------------------------------------------+
7152 * | Configuration Reg | Description |
7154 * +-------------------+------------------------------------------------------+
7155 * | 0xF30 - 0xF3F |ECC single error indication (1 bit per memory wrapper)|
7156 * | |0xF30 memory wrappers 31:0 (MSB to LSB) |
7157 * | |0xF34 memory wrappers 63:32 |
7158 * | |0xF38 memory wrappers 95:64 |
7159 * | |0xF3C memory wrappers 127:96 |
7160 * +-------------------+------------------------------------------------------+
7161 * | 0xF40 - 0xF4F |ECC double error indication (1 bit per memory wrapper)|
7162 * | |0xF40 memory wrappers 31:0 (MSB to LSB) |
7163 * | |0xF44 memory wrappers 63:32 |
7164 * | |0xF48 memory wrappers 95:64 |
7165 * | |0xF4C memory wrappers 127:96 |
7166 * +-------------------+------------------------------------------------------+
7168 static int gaudi_extract_ecc_info(struct hl_device *hdev,
7169 struct ecc_info_extract_params *params, u64 *ecc_address,
7170 u64 *ecc_syndrom, u8 *memory_wrapper_idx)
7172 struct gaudi_device *gaudi = hdev->asic_specific;
7173 u32 i, num_mem_regs, reg, err_bit;
7174 u64 err_addr, err_word = 0;
7177 num_mem_regs = params->num_memories / 32 +
7178 ((params->num_memories % 32) ? 1 : 0);
7180 if (params->block_address >= CFG_BASE)
7181 params->block_address -= CFG_BASE;
7184 err_addr = params->block_address + GAUDI_ECC_DERR0_OFFSET;
7186 err_addr = params->block_address + GAUDI_ECC_SERR0_OFFSET;
7188 if (params->disable_clock_gating) {
7189 mutex_lock(&gaudi->clk_gate_mutex);
7190 hdev->asic_funcs->disable_clock_gating(hdev);
7193 /* Set invalid wrapper index */
7194 *memory_wrapper_idx = 0xFF;
7196 /* Iterate through memory wrappers, a single bit must be set */
7197 for (i = 0 ; i < num_mem_regs ; i++) {
7199 err_word = RREG32(err_addr);
7201 err_bit = __ffs(err_word);
7202 *memory_wrapper_idx = err_bit + (32 * i);
7207 if (*memory_wrapper_idx == 0xFF) {
7208 dev_err(hdev->dev, "ECC error information cannot be found\n");
7210 goto enable_clk_gate;
7213 WREG32(params->block_address + GAUDI_ECC_MEM_SEL_OFFSET,
7214 *memory_wrapper_idx);
7217 RREG32(params->block_address + GAUDI_ECC_ADDRESS_OFFSET);
7219 RREG32(params->block_address + GAUDI_ECC_SYNDROME_OFFSET);
7221 /* Clear error indication */
7222 reg = RREG32(params->block_address + GAUDI_ECC_MEM_INFO_CLR_OFFSET);
7224 reg |= FIELD_PREP(GAUDI_ECC_MEM_INFO_CLR_DERR_MASK, 1);
7226 reg |= FIELD_PREP(GAUDI_ECC_MEM_INFO_CLR_SERR_MASK, 1);
7228 WREG32(params->block_address + GAUDI_ECC_MEM_INFO_CLR_OFFSET, reg);
7231 if (params->disable_clock_gating) {
7232 hdev->asic_funcs->set_clock_gating(hdev);
7234 mutex_unlock(&gaudi->clk_gate_mutex);
7241 * gaudi_queue_idx_dec - decrement queue index (pi/ci) and handle wrap
7243 * @idx: the current pi/ci value
7244 * @q_len: the queue length (power of 2)
7246 * @return the cyclically decremented index
7248 static inline u32 gaudi_queue_idx_dec(u32 idx, u32 q_len)
7250 u32 mask = q_len - 1;
7253 * modular decrement is equivalent to adding (queue_size -1)
7254 * later we take LSBs to make sure the value is in the
7255 * range [0, queue_len - 1]
7257 return (idx + q_len - 1) & mask;
7261 * gaudi_print_sw_config_stream_data - print SW config stream data
7263 * @hdev: pointer to the habanalabs device structure
7264 * @stream: the QMAN's stream
7265 * @qman_base: base address of QMAN registers block
7267 static void gaudi_print_sw_config_stream_data(struct hl_device *hdev, u32 stream,
7270 u64 cq_ptr_lo, cq_ptr_hi, cq_tsize, cq_ptr;
7271 u32 cq_ptr_lo_off, size;
7273 cq_ptr_lo_off = mmTPC0_QM_CQ_PTR_LO_1 - mmTPC0_QM_CQ_PTR_LO_0;
7275 cq_ptr_lo = qman_base + (mmTPC0_QM_CQ_PTR_LO_0 - mmTPC0_QM_BASE) +
7276 stream * cq_ptr_lo_off;
7277 cq_ptr_hi = cq_ptr_lo +
7278 (mmTPC0_QM_CQ_PTR_HI_0 - mmTPC0_QM_CQ_PTR_LO_0);
7279 cq_tsize = cq_ptr_lo +
7280 (mmTPC0_QM_CQ_TSIZE_0 - mmTPC0_QM_CQ_PTR_LO_0);
7282 cq_ptr = (((u64) RREG32(cq_ptr_hi)) << 32) | RREG32(cq_ptr_lo);
7283 size = RREG32(cq_tsize);
7284 dev_info(hdev->dev, "stop on err: stream: %u, addr: %#llx, size: %u\n",
7285 stream, cq_ptr, size);
7289 * gaudi_print_last_pqes_on_err - print last PQEs on error
7291 * @hdev: pointer to the habanalabs device structure
7292 * @qid_base: first QID of the QMAN (out of 4 streams)
7293 * @stream: the QMAN's stream
7294 * @qman_base: base address of QMAN registers block
7295 * @pr_sw_conf: if true print the SW config stream data (CQ PTR and SIZE)
7297 static void gaudi_print_last_pqes_on_err(struct hl_device *hdev, u32 qid_base,
7298 u32 stream, u64 qman_base,
7301 u32 ci, qm_ci_stream_off, queue_len;
7302 struct hl_hw_queue *q;
7306 q = &hdev->kernel_queues[qid_base + stream];
7308 qm_ci_stream_off = mmTPC0_QM_PQ_CI_1 - mmTPC0_QM_PQ_CI_0;
7309 pq_ci = qman_base + (mmTPC0_QM_PQ_CI_0 - mmTPC0_QM_BASE) +
7310 stream * qm_ci_stream_off;
7312 queue_len = (q->queue_type == QUEUE_TYPE_INT) ?
7313 q->int_queue_len : HL_QUEUE_LENGTH;
7315 hdev->asic_funcs->hw_queues_lock(hdev);
7318 gaudi_print_sw_config_stream_data(hdev, stream, qman_base);
7322 /* we should start printing form ci -1 */
7323 ci = gaudi_queue_idx_dec(ci, queue_len);
7325 for (i = 0; i < PQ_FETCHER_CACHE_SIZE; i++) {
7330 bd = q->kernel_address;
7333 len = le32_to_cpu(bd->len);
7334 /* len 0 means uninitialized entry- break */
7338 addr = le64_to_cpu(bd->ptr);
7340 dev_info(hdev->dev, "stop on err PQE(stream %u): ci: %u, addr: %#llx, size: %u\n",
7341 stream, ci, addr, len);
7343 /* get previous ci, wrap if needed */
7344 ci = gaudi_queue_idx_dec(ci, queue_len);
7347 hdev->asic_funcs->hw_queues_unlock(hdev);
7351 * print_qman_data_on_err - extract QMAN data on error
7353 * @hdev: pointer to the habanalabs device structure
7354 * @qid_base: first QID of the QMAN (out of 4 streams)
7355 * @stream: the QMAN's stream
7356 * @qman_base: base address of QMAN registers block
7358 * This function attempt to exatract as much data as possible on QMAN error.
7359 * On upper CP print the SW config stream data and last 8 PQEs.
7360 * On lower CP print SW config data and last PQEs of ALL 4 upper CPs
7362 static void print_qman_data_on_err(struct hl_device *hdev, u32 qid_base,
7363 u32 stream, u64 qman_base)
7367 if (stream != QMAN_STREAMS) {
7368 gaudi_print_last_pqes_on_err(hdev, qid_base, stream, qman_base,
7373 gaudi_print_sw_config_stream_data(hdev, stream, qman_base);
7375 for (i = 0; i < QMAN_STREAMS; i++)
7376 gaudi_print_last_pqes_on_err(hdev, qid_base, i, qman_base,
7380 static void gaudi_handle_qman_err_generic(struct hl_device *hdev,
7381 const char *qm_name,
7385 u32 i, j, glbl_sts_val, arb_err_val, glbl_sts_clr_val;
7386 u64 glbl_sts_addr, arb_err_addr;
7389 glbl_sts_addr = qman_base + (mmTPC0_QM_GLBL_STS1_0 - mmTPC0_QM_BASE);
7390 arb_err_addr = qman_base + (mmTPC0_QM_ARB_ERR_CAUSE - mmTPC0_QM_BASE);
7392 /* Iterate through all stream GLBL_STS1 registers + Lower CP */
7393 for (i = 0 ; i < QMAN_STREAMS + 1 ; i++) {
7394 glbl_sts_clr_val = 0;
7395 glbl_sts_val = RREG32(glbl_sts_addr + 4 * i);
7400 if (i == QMAN_STREAMS)
7401 snprintf(reg_desc, ARRAY_SIZE(reg_desc), "LowerCP");
7403 snprintf(reg_desc, ARRAY_SIZE(reg_desc), "stream%u", i);
7405 for (j = 0 ; j < GAUDI_NUM_OF_QM_ERR_CAUSE ; j++) {
7406 if (glbl_sts_val & BIT(j)) {
7407 dev_err_ratelimited(hdev->dev,
7408 "%s %s. err cause: %s\n",
7410 gaudi_qman_error_cause[j]);
7411 glbl_sts_clr_val |= BIT(j);
7415 /* Write 1 clear errors */
7416 if (!hdev->stop_on_err)
7417 WREG32(glbl_sts_addr + 4 * i, glbl_sts_clr_val);
7419 print_qman_data_on_err(hdev, qid_base, i, qman_base);
7422 arb_err_val = RREG32(arb_err_addr);
7427 for (j = 0 ; j < GAUDI_NUM_OF_QM_ARB_ERR_CAUSE ; j++) {
7428 if (arb_err_val & BIT(j)) {
7429 dev_err_ratelimited(hdev->dev,
7430 "%s ARB_ERR. err cause: %s\n",
7432 gaudi_qman_arb_error_cause[j]);
7437 static void gaudi_print_sm_sei_info(struct hl_device *hdev, u16 event_type,
7438 struct hl_eq_sm_sei_data *sei_data)
7440 u32 index = event_type - GAUDI_EVENT_DMA_IF_SEI_0;
7442 /* Flip the bits as the enum is ordered in the opposite way */
7443 index = (index ^ 0x3) & 0x3;
7445 switch (sei_data->sei_cause) {
7446 case SM_SEI_SO_OVERFLOW:
7447 dev_err_ratelimited(hdev->dev,
7448 "%s SEI Error: SOB Group %u overflow/underflow",
7449 gaudi_sync_manager_names[index],
7450 le32_to_cpu(sei_data->sei_log));
7452 case SM_SEI_LBW_4B_UNALIGNED:
7453 dev_err_ratelimited(hdev->dev,
7454 "%s SEI Error: Unaligned 4B LBW access, monitor agent address low - %#x",
7455 gaudi_sync_manager_names[index],
7456 le32_to_cpu(sei_data->sei_log));
7458 case SM_SEI_AXI_RESPONSE_ERR:
7459 dev_err_ratelimited(hdev->dev,
7460 "%s SEI Error: AXI ID %u response error",
7461 gaudi_sync_manager_names[index],
7462 le32_to_cpu(sei_data->sei_log));
7465 dev_err_ratelimited(hdev->dev, "Unknown SM SEI cause %u",
7466 le32_to_cpu(sei_data->sei_log));
7471 static void gaudi_handle_ecc_event(struct hl_device *hdev, u16 event_type,
7472 struct hl_eq_ecc_data *ecc_data)
7474 struct ecc_info_extract_params params;
7475 u64 ecc_address = 0, ecc_syndrom = 0;
7476 u8 index, memory_wrapper_idx = 0;
7477 bool extract_info_from_fw;
7480 if (hdev->asic_prop.fw_security_enabled) {
7481 extract_info_from_fw = true;
7482 goto extract_ecc_info;
7485 switch (event_type) {
7486 case GAUDI_EVENT_PCIE_CORE_SERR ... GAUDI_EVENT_PCIE_PHY_DERR:
7487 case GAUDI_EVENT_DMA0_SERR_ECC ... GAUDI_EVENT_MMU_DERR:
7488 extract_info_from_fw = true;
7490 case GAUDI_EVENT_TPC0_SERR ... GAUDI_EVENT_TPC7_SERR:
7491 index = event_type - GAUDI_EVENT_TPC0_SERR;
7492 params.block_address = mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET;
7493 params.num_memories = 90;
7494 params.derr = false;
7495 params.disable_clock_gating = true;
7496 extract_info_from_fw = false;
7498 case GAUDI_EVENT_TPC0_DERR ... GAUDI_EVENT_TPC7_DERR:
7499 index = event_type - GAUDI_EVENT_TPC0_DERR;
7500 params.block_address =
7501 mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET;
7502 params.num_memories = 90;
7504 params.disable_clock_gating = true;
7505 extract_info_from_fw = false;
7507 case GAUDI_EVENT_MME0_ACC_SERR:
7508 case GAUDI_EVENT_MME1_ACC_SERR:
7509 case GAUDI_EVENT_MME2_ACC_SERR:
7510 case GAUDI_EVENT_MME3_ACC_SERR:
7511 index = (event_type - GAUDI_EVENT_MME0_ACC_SERR) / 4;
7512 params.block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET;
7513 params.num_memories = 128;
7514 params.derr = false;
7515 params.disable_clock_gating = true;
7516 extract_info_from_fw = false;
7518 case GAUDI_EVENT_MME0_ACC_DERR:
7519 case GAUDI_EVENT_MME1_ACC_DERR:
7520 case GAUDI_EVENT_MME2_ACC_DERR:
7521 case GAUDI_EVENT_MME3_ACC_DERR:
7522 index = (event_type - GAUDI_EVENT_MME0_ACC_DERR) / 4;
7523 params.block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET;
7524 params.num_memories = 128;
7526 params.disable_clock_gating = true;
7527 extract_info_from_fw = false;
7529 case GAUDI_EVENT_MME0_SBAB_SERR:
7530 case GAUDI_EVENT_MME1_SBAB_SERR:
7531 case GAUDI_EVENT_MME2_SBAB_SERR:
7532 case GAUDI_EVENT_MME3_SBAB_SERR:
7533 index = (event_type - GAUDI_EVENT_MME0_SBAB_SERR) / 4;
7534 params.block_address =
7535 mmMME0_SBAB_BASE + index * MME_ACC_OFFSET;
7536 params.num_memories = 33;
7537 params.derr = false;
7538 params.disable_clock_gating = true;
7539 extract_info_from_fw = false;
7541 case GAUDI_EVENT_MME0_SBAB_DERR:
7542 case GAUDI_EVENT_MME1_SBAB_DERR:
7543 case GAUDI_EVENT_MME2_SBAB_DERR:
7544 case GAUDI_EVENT_MME3_SBAB_DERR:
7545 index = (event_type - GAUDI_EVENT_MME0_SBAB_DERR) / 4;
7546 params.block_address =
7547 mmMME0_SBAB_BASE + index * MME_ACC_OFFSET;
7548 params.num_memories = 33;
7550 params.disable_clock_gating = true;
7551 extract_info_from_fw = false;
7558 if (extract_info_from_fw) {
7559 ecc_address = le64_to_cpu(ecc_data->ecc_address);
7560 ecc_syndrom = le64_to_cpu(ecc_data->ecc_syndrom);
7561 memory_wrapper_idx = ecc_data->memory_wrapper_idx;
7563 rc = gaudi_extract_ecc_info(hdev, ¶ms, &ecc_address,
7564 &ecc_syndrom, &memory_wrapper_idx);
7570 "ECC error detected. address: %#llx. Syndrom: %#llx. block id %u\n",
7571 ecc_address, ecc_syndrom, memory_wrapper_idx);
7574 static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type)
7581 switch (event_type) {
7582 case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM:
7583 index = event_type - GAUDI_EVENT_TPC0_QM;
7584 qid_base = GAUDI_QUEUE_ID_TPC_0_0 + index * QMAN_STREAMS;
7585 qman_base = mmTPC0_QM_BASE + index * TPC_QMAN_OFFSET;
7586 snprintf(desc, ARRAY_SIZE(desc), "%s%d", "TPC_QM", index);
7588 case GAUDI_EVENT_MME0_QM ... GAUDI_EVENT_MME2_QM:
7589 index = event_type - GAUDI_EVENT_MME0_QM;
7590 qid_base = GAUDI_QUEUE_ID_MME_0_0 + index * QMAN_STREAMS;
7591 qman_base = mmMME0_QM_BASE + index * MME_QMAN_OFFSET;
7592 snprintf(desc, ARRAY_SIZE(desc), "%s%d", "MME_QM", index);
7594 case GAUDI_EVENT_DMA0_QM ... GAUDI_EVENT_DMA7_QM:
7595 index = event_type - GAUDI_EVENT_DMA0_QM;
7596 qid_base = GAUDI_QUEUE_ID_DMA_0_0 + index * QMAN_STREAMS;
7597 /* skip GAUDI_QUEUE_ID_CPU_PQ if necessary */
7600 qman_base = mmDMA0_QM_BASE + index * DMA_QMAN_OFFSET;
7601 snprintf(desc, ARRAY_SIZE(desc), "%s%d", "DMA_QM", index);
7603 case GAUDI_EVENT_NIC0_QM0:
7604 qid_base = GAUDI_QUEUE_ID_NIC_0_0;
7605 qman_base = mmNIC0_QM0_BASE;
7606 snprintf(desc, ARRAY_SIZE(desc), "NIC0_QM0");
7608 case GAUDI_EVENT_NIC0_QM1:
7609 qid_base = GAUDI_QUEUE_ID_NIC_1_0;
7610 qman_base = mmNIC0_QM1_BASE;
7611 snprintf(desc, ARRAY_SIZE(desc), "NIC0_QM1");
7613 case GAUDI_EVENT_NIC1_QM0:
7614 qid_base = GAUDI_QUEUE_ID_NIC_2_0;
7615 qman_base = mmNIC1_QM0_BASE;
7616 snprintf(desc, ARRAY_SIZE(desc), "NIC1_QM0");
7618 case GAUDI_EVENT_NIC1_QM1:
7619 qid_base = GAUDI_QUEUE_ID_NIC_3_0;
7620 qman_base = mmNIC1_QM1_BASE;
7621 snprintf(desc, ARRAY_SIZE(desc), "NIC1_QM1");
7623 case GAUDI_EVENT_NIC2_QM0:
7624 qid_base = GAUDI_QUEUE_ID_NIC_4_0;
7625 qman_base = mmNIC2_QM0_BASE;
7626 snprintf(desc, ARRAY_SIZE(desc), "NIC2_QM0");
7628 case GAUDI_EVENT_NIC2_QM1:
7629 qid_base = GAUDI_QUEUE_ID_NIC_5_0;
7630 qman_base = mmNIC2_QM1_BASE;
7631 snprintf(desc, ARRAY_SIZE(desc), "NIC2_QM1");
7633 case GAUDI_EVENT_NIC3_QM0:
7634 qid_base = GAUDI_QUEUE_ID_NIC_6_0;
7635 qman_base = mmNIC3_QM0_BASE;
7636 snprintf(desc, ARRAY_SIZE(desc), "NIC3_QM0");
7638 case GAUDI_EVENT_NIC3_QM1:
7639 qid_base = GAUDI_QUEUE_ID_NIC_7_0;
7640 qman_base = mmNIC3_QM1_BASE;
7641 snprintf(desc, ARRAY_SIZE(desc), "NIC3_QM1");
7643 case GAUDI_EVENT_NIC4_QM0:
7644 qid_base = GAUDI_QUEUE_ID_NIC_8_0;
7645 qman_base = mmNIC4_QM0_BASE;
7646 snprintf(desc, ARRAY_SIZE(desc), "NIC4_QM0");
7648 case GAUDI_EVENT_NIC4_QM1:
7649 qid_base = GAUDI_QUEUE_ID_NIC_9_0;
7650 qman_base = mmNIC4_QM1_BASE;
7651 snprintf(desc, ARRAY_SIZE(desc), "NIC4_QM1");
7657 gaudi_handle_qman_err_generic(hdev, desc, qman_base, qid_base);
7660 static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type,
7665 gaudi_get_event_desc(event_type, desc, sizeof(desc));
7666 dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
7670 gaudi_print_razwi_info(hdev);
7671 gaudi_print_mmu_error_info(hdev);
7675 static void gaudi_print_out_of_sync_info(struct hl_device *hdev,
7676 struct cpucp_pkt_sync_err *sync_err)
7678 struct hl_hw_queue *q = &hdev->kernel_queues[GAUDI_QUEUE_ID_CPU_PQ];
7680 dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%u\n",
7681 sync_err->pi, sync_err->ci, q->pi, atomic_read(&q->ci));
7684 static void gaudi_print_fw_alive_info(struct hl_device *hdev,
7685 struct hl_eq_fw_alive *fw_alive)
7688 "FW alive report: severity=%s, process_id=%u, thread_id=%u, uptime=%llu seconds\n",
7689 (fw_alive->severity == FW_ALIVE_SEVERITY_MINOR) ?
7690 "Minor" : "Critical", fw_alive->process_id,
7691 fw_alive->thread_id, fw_alive->uptime_seconds);
7694 static int gaudi_soft_reset_late_init(struct hl_device *hdev)
7696 struct gaudi_device *gaudi = hdev->asic_specific;
7698 /* Unmask all IRQs since some could have been received
7699 * during the soft reset
7701 return hl_fw_unmask_irq_arr(hdev, gaudi->events, sizeof(gaudi->events));
7704 static int gaudi_hbm_read_interrupts(struct hl_device *hdev, int device,
7705 struct hl_eq_hbm_ecc_data *hbm_ecc_data)
7707 u32 base, val, val2, wr_par, rd_par, ca_par, derr, serr, type, ch;
7710 if (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
7711 CPU_BOOT_DEV_STS0_HBM_ECC_EN) {
7712 if (!hbm_ecc_data) {
7713 dev_err(hdev->dev, "No FW ECC data");
7717 wr_par = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK,
7718 le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
7719 rd_par = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK,
7720 le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
7721 ca_par = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK,
7722 le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
7723 derr = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_DERR_MASK,
7724 le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
7725 serr = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_SERR_MASK,
7726 le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
7727 type = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK,
7728 le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
7729 ch = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK,
7730 le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
7733 "HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n",
7734 device, ch, wr_par, rd_par, ca_par, serr, derr);
7736 "HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%u, SEC_CNT=%d, DEC_CNT=%d\n",
7737 device, ch, hbm_ecc_data->first_addr, type,
7738 hbm_ecc_data->sec_cont_cnt, hbm_ecc_data->sec_cnt,
7739 hbm_ecc_data->dec_cnt);
7743 if (hdev->asic_prop.fw_security_enabled) {
7744 dev_info(hdev->dev, "Cannot access MC regs for ECC data while security is enabled\n");
7748 base = GAUDI_HBM_CFG_BASE + device * GAUDI_HBM_CFG_OFFSET;
7749 for (ch = 0 ; ch < GAUDI_HBM_CHANNELS ; ch++) {
7750 val = RREG32_MASK(base + ch * 0x1000 + 0x06C, 0x0000FFFF);
7751 val = (val & 0xFF) | ((val >> 8) & 0xFF);
7755 "HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n",
7756 device, ch * 2, val & 0x1, (val >> 1) & 0x1,
7757 (val >> 2) & 0x1, (val >> 3) & 0x1,
7760 val2 = RREG32(base + ch * 0x1000 + 0x060);
7762 "HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DEC_CNT=%d\n",
7764 RREG32(base + ch * 0x1000 + 0x064),
7765 (val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10,
7766 (val2 & 0xFF0000) >> 16,
7767 (val2 & 0xFF000000) >> 24);
7770 val = RREG32_MASK(base + ch * 0x1000 + 0x07C, 0x0000FFFF);
7771 val = (val & 0xFF) | ((val >> 8) & 0xFF);
7775 "HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n",
7776 device, ch * 2 + 1, val & 0x1, (val >> 1) & 0x1,
7777 (val >> 2) & 0x1, (val >> 3) & 0x1,
7780 val2 = RREG32(base + ch * 0x1000 + 0x070);
7782 "HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DEC_CNT=%d\n",
7784 RREG32(base + ch * 0x1000 + 0x074),
7785 (val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10,
7786 (val2 & 0xFF0000) >> 16,
7787 (val2 & 0xFF000000) >> 24);
7790 /* Clear interrupts */
7791 RMWREG32(base + (ch * 0x1000) + 0x060, 0x1C8, 0x1FF);
7792 RMWREG32(base + (ch * 0x1000) + 0x070, 0x1C8, 0x1FF);
7793 WREG32(base + (ch * 0x1000) + 0x06C, 0x1F1F);
7794 WREG32(base + (ch * 0x1000) + 0x07C, 0x1F1F);
7795 RMWREG32(base + (ch * 0x1000) + 0x060, 0x0, 0xF);
7796 RMWREG32(base + (ch * 0x1000) + 0x070, 0x0, 0xF);
7799 val = RREG32(base + 0x8F30);
7800 val2 = RREG32(base + 0x8F34);
7804 "HBM %d MC SRAM SERR info: Reg 0x8F30=0x%x, Reg 0x8F34=0x%x\n",
7807 val = RREG32(base + 0x8F40);
7808 val2 = RREG32(base + 0x8F44);
7812 "HBM %d MC SRAM DERR info: Reg 0x8F40=0x%x, Reg 0x8F44=0x%x\n",
7819 static int gaudi_hbm_event_to_dev(u16 hbm_event_type)
7821 switch (hbm_event_type) {
7822 case GAUDI_EVENT_HBM0_SPI_0:
7823 case GAUDI_EVENT_HBM0_SPI_1:
7825 case GAUDI_EVENT_HBM1_SPI_0:
7826 case GAUDI_EVENT_HBM1_SPI_1:
7828 case GAUDI_EVENT_HBM2_SPI_0:
7829 case GAUDI_EVENT_HBM2_SPI_1:
7831 case GAUDI_EVENT_HBM3_SPI_0:
7832 case GAUDI_EVENT_HBM3_SPI_1:
7838 /* Should never happen */
7842 static bool gaudi_tpc_read_interrupts(struct hl_device *hdev, u8 tpc_id,
7843 char *interrupt_name)
7845 struct gaudi_device *gaudi = hdev->asic_specific;
7846 u32 tpc_offset = tpc_id * TPC_CFG_OFFSET, tpc_interrupts_cause, i;
7847 bool soft_reset_required = false;
7849 /* Accessing the TPC_INTR_CAUSE registers requires disabling the clock
7850 * gating, and thus cannot be done in CPU-CP and should be done instead
7854 mutex_lock(&gaudi->clk_gate_mutex);
7856 hdev->asic_funcs->disable_clock_gating(hdev);
7858 tpc_interrupts_cause = RREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset) &
7859 TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK;
7861 for (i = 0 ; i < GAUDI_NUM_OF_TPC_INTR_CAUSE ; i++)
7862 if (tpc_interrupts_cause & BIT(i)) {
7863 dev_err_ratelimited(hdev->dev,
7864 "TPC%d_%s interrupt cause: %s\n",
7865 tpc_id, interrupt_name,
7866 gaudi_tpc_interrupts_cause[i]);
7867 /* If this is QM error, we need to soft-reset */
7869 soft_reset_required = true;
7872 /* Clear interrupts */
7873 WREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset, 0);
7875 hdev->asic_funcs->set_clock_gating(hdev);
7877 mutex_unlock(&gaudi->clk_gate_mutex);
7879 return soft_reset_required;
7882 static int tpc_dec_event_to_tpc_id(u16 tpc_dec_event_type)
7884 return (tpc_dec_event_type - GAUDI_EVENT_TPC0_DEC) >> 1;
7887 static int tpc_krn_event_to_tpc_id(u16 tpc_dec_event_type)
7889 return (tpc_dec_event_type - GAUDI_EVENT_TPC0_KRN_ERR) / 6;
7892 static void gaudi_print_clk_change_info(struct hl_device *hdev,
7895 switch (event_type) {
7896 case GAUDI_EVENT_FIX_POWER_ENV_S:
7897 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_POWER;
7898 dev_info_ratelimited(hdev->dev,
7899 "Clock throttling due to power consumption\n");
7902 case GAUDI_EVENT_FIX_POWER_ENV_E:
7903 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_POWER;
7904 dev_info_ratelimited(hdev->dev,
7905 "Power envelop is safe, back to optimal clock\n");
7908 case GAUDI_EVENT_FIX_THERMAL_ENV_S:
7909 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_THERMAL;
7910 dev_info_ratelimited(hdev->dev,
7911 "Clock throttling due to overheating\n");
7914 case GAUDI_EVENT_FIX_THERMAL_ENV_E:
7915 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_THERMAL;
7916 dev_info_ratelimited(hdev->dev,
7917 "Thermal envelop is safe, back to optimal clock\n");
7921 dev_err(hdev->dev, "Received invalid clock change event %d\n",
7927 static void gaudi_handle_eqe(struct hl_device *hdev,
7928 struct hl_eq_entry *eq_entry)
7930 struct gaudi_device *gaudi = hdev->asic_specific;
7931 u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
7932 u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
7933 >> EQ_CTL_EVENT_TYPE_SHIFT);
7934 bool reset_required;
7938 if (event_type >= GAUDI_EVENT_SIZE) {
7939 dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
7940 event_type, GAUDI_EVENT_SIZE - 1);
7944 gaudi->events_stat[event_type]++;
7945 gaudi->events_stat_aggregate[event_type]++;
7947 switch (event_type) {
7948 case GAUDI_EVENT_PCIE_CORE_DERR:
7949 case GAUDI_EVENT_PCIE_IF_DERR:
7950 case GAUDI_EVENT_PCIE_PHY_DERR:
7951 case GAUDI_EVENT_TPC0_DERR ... GAUDI_EVENT_TPC7_DERR:
7952 case GAUDI_EVENT_MME0_ACC_DERR:
7953 case GAUDI_EVENT_MME0_SBAB_DERR:
7954 case GAUDI_EVENT_MME1_ACC_DERR:
7955 case GAUDI_EVENT_MME1_SBAB_DERR:
7956 case GAUDI_EVENT_MME2_ACC_DERR:
7957 case GAUDI_EVENT_MME2_SBAB_DERR:
7958 case GAUDI_EVENT_MME3_ACC_DERR:
7959 case GAUDI_EVENT_MME3_SBAB_DERR:
7960 case GAUDI_EVENT_DMA0_DERR_ECC ... GAUDI_EVENT_DMA7_DERR_ECC:
7962 case GAUDI_EVENT_CPU_IF_ECC_DERR:
7963 case GAUDI_EVENT_PSOC_MEM_DERR:
7964 case GAUDI_EVENT_PSOC_CORESIGHT_DERR:
7965 case GAUDI_EVENT_SRAM0_DERR ... GAUDI_EVENT_SRAM28_DERR:
7966 case GAUDI_EVENT_DMA_IF0_DERR ... GAUDI_EVENT_DMA_IF3_DERR:
7967 case GAUDI_EVENT_HBM_0_DERR ... GAUDI_EVENT_HBM_3_DERR:
7968 case GAUDI_EVENT_MMU_DERR:
7969 case GAUDI_EVENT_NIC0_CS_DBG_DERR ... GAUDI_EVENT_NIC4_CS_DBG_DERR:
7970 gaudi_print_irq_info(hdev, event_type, true);
7971 gaudi_handle_ecc_event(hdev, event_type, &eq_entry->ecc_data);
7974 case GAUDI_EVENT_GIC500:
7975 case GAUDI_EVENT_AXI_ECC:
7976 case GAUDI_EVENT_L2_RAM_ECC:
7977 case GAUDI_EVENT_PLL0 ... GAUDI_EVENT_PLL17:
7978 gaudi_print_irq_info(hdev, event_type, false);
7981 case GAUDI_EVENT_HBM0_SPI_0:
7982 case GAUDI_EVENT_HBM1_SPI_0:
7983 case GAUDI_EVENT_HBM2_SPI_0:
7984 case GAUDI_EVENT_HBM3_SPI_0:
7985 gaudi_print_irq_info(hdev, event_type, false);
7986 gaudi_hbm_read_interrupts(hdev,
7987 gaudi_hbm_event_to_dev(event_type),
7988 &eq_entry->hbm_ecc_data);
7991 case GAUDI_EVENT_HBM0_SPI_1:
7992 case GAUDI_EVENT_HBM1_SPI_1:
7993 case GAUDI_EVENT_HBM2_SPI_1:
7994 case GAUDI_EVENT_HBM3_SPI_1:
7995 gaudi_print_irq_info(hdev, event_type, false);
7996 gaudi_hbm_read_interrupts(hdev,
7997 gaudi_hbm_event_to_dev(event_type),
7998 &eq_entry->hbm_ecc_data);
7999 hl_fw_unmask_irq(hdev, event_type);
8002 case GAUDI_EVENT_TPC0_DEC:
8003 case GAUDI_EVENT_TPC1_DEC:
8004 case GAUDI_EVENT_TPC2_DEC:
8005 case GAUDI_EVENT_TPC3_DEC:
8006 case GAUDI_EVENT_TPC4_DEC:
8007 case GAUDI_EVENT_TPC5_DEC:
8008 case GAUDI_EVENT_TPC6_DEC:
8009 case GAUDI_EVENT_TPC7_DEC:
8010 gaudi_print_irq_info(hdev, event_type, true);
8011 reset_required = gaudi_tpc_read_interrupts(hdev,
8012 tpc_dec_event_to_tpc_id(event_type),
8013 "AXI_SLV_DEC_Error");
8014 if (reset_required) {
8015 dev_err(hdev->dev, "reset required due to %s\n",
8016 gaudi_irq_map_table[event_type].name);
8018 hl_device_reset(hdev, 0);
8020 hl_fw_unmask_irq(hdev, event_type);
8024 case GAUDI_EVENT_TPC0_KRN_ERR:
8025 case GAUDI_EVENT_TPC1_KRN_ERR:
8026 case GAUDI_EVENT_TPC2_KRN_ERR:
8027 case GAUDI_EVENT_TPC3_KRN_ERR:
8028 case GAUDI_EVENT_TPC4_KRN_ERR:
8029 case GAUDI_EVENT_TPC5_KRN_ERR:
8030 case GAUDI_EVENT_TPC6_KRN_ERR:
8031 case GAUDI_EVENT_TPC7_KRN_ERR:
8032 gaudi_print_irq_info(hdev, event_type, true);
8033 reset_required = gaudi_tpc_read_interrupts(hdev,
8034 tpc_krn_event_to_tpc_id(event_type),
8036 if (reset_required) {
8037 dev_err(hdev->dev, "reset required due to %s\n",
8038 gaudi_irq_map_table[event_type].name);
8040 hl_device_reset(hdev, 0);
8042 hl_fw_unmask_irq(hdev, event_type);
8046 case GAUDI_EVENT_PCIE_CORE_SERR:
8047 case GAUDI_EVENT_PCIE_IF_SERR:
8048 case GAUDI_EVENT_PCIE_PHY_SERR:
8049 case GAUDI_EVENT_TPC0_SERR ... GAUDI_EVENT_TPC7_SERR:
8050 case GAUDI_EVENT_MME0_ACC_SERR:
8051 case GAUDI_EVENT_MME0_SBAB_SERR:
8052 case GAUDI_EVENT_MME1_ACC_SERR:
8053 case GAUDI_EVENT_MME1_SBAB_SERR:
8054 case GAUDI_EVENT_MME2_ACC_SERR:
8055 case GAUDI_EVENT_MME2_SBAB_SERR:
8056 case GAUDI_EVENT_MME3_ACC_SERR:
8057 case GAUDI_EVENT_MME3_SBAB_SERR:
8058 case GAUDI_EVENT_DMA0_SERR_ECC ... GAUDI_EVENT_DMA7_SERR_ECC:
8059 case GAUDI_EVENT_CPU_IF_ECC_SERR:
8060 case GAUDI_EVENT_PSOC_MEM_SERR:
8061 case GAUDI_EVENT_PSOC_CORESIGHT_SERR:
8062 case GAUDI_EVENT_SRAM0_SERR ... GAUDI_EVENT_SRAM28_SERR:
8063 case GAUDI_EVENT_DMA_IF0_SERR ... GAUDI_EVENT_DMA_IF3_SERR:
8064 case GAUDI_EVENT_HBM_0_SERR ... GAUDI_EVENT_HBM_3_SERR:
8066 case GAUDI_EVENT_MMU_SERR:
8067 gaudi_print_irq_info(hdev, event_type, true);
8068 gaudi_handle_ecc_event(hdev, event_type, &eq_entry->ecc_data);
8069 hl_fw_unmask_irq(hdev, event_type);
8072 case GAUDI_EVENT_PCIE_DEC:
8073 case GAUDI_EVENT_MME0_WBC_RSP:
8074 case GAUDI_EVENT_MME0_SBAB0_RSP:
8075 case GAUDI_EVENT_MME1_WBC_RSP:
8076 case GAUDI_EVENT_MME1_SBAB0_RSP:
8077 case GAUDI_EVENT_MME2_WBC_RSP:
8078 case GAUDI_EVENT_MME2_SBAB0_RSP:
8079 case GAUDI_EVENT_MME3_WBC_RSP:
8080 case GAUDI_EVENT_MME3_SBAB0_RSP:
8081 case GAUDI_EVENT_CPU_AXI_SPLITTER:
8082 case GAUDI_EVENT_PSOC_AXI_DEC:
8083 case GAUDI_EVENT_PSOC_PRSTN_FALL:
8084 case GAUDI_EVENT_MMU_PAGE_FAULT:
8085 case GAUDI_EVENT_MMU_WR_PERM:
8086 case GAUDI_EVENT_RAZWI_OR_ADC:
8087 case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM:
8088 case GAUDI_EVENT_MME0_QM ... GAUDI_EVENT_MME2_QM:
8089 case GAUDI_EVENT_DMA0_QM ... GAUDI_EVENT_DMA7_QM:
8091 case GAUDI_EVENT_NIC0_QM0:
8092 case GAUDI_EVENT_NIC0_QM1:
8093 case GAUDI_EVENT_NIC1_QM0:
8094 case GAUDI_EVENT_NIC1_QM1:
8095 case GAUDI_EVENT_NIC2_QM0:
8096 case GAUDI_EVENT_NIC2_QM1:
8097 case GAUDI_EVENT_NIC3_QM0:
8098 case GAUDI_EVENT_NIC3_QM1:
8099 case GAUDI_EVENT_NIC4_QM0:
8100 case GAUDI_EVENT_NIC4_QM1:
8101 case GAUDI_EVENT_DMA0_CORE ... GAUDI_EVENT_DMA7_CORE:
8102 gaudi_print_irq_info(hdev, event_type, true);
8103 gaudi_handle_qman_err(hdev, event_type);
8104 hl_fw_unmask_irq(hdev, event_type);
8107 case GAUDI_EVENT_RAZWI_OR_ADC_SW:
8108 gaudi_print_irq_info(hdev, event_type, true);
8111 case GAUDI_EVENT_TPC0_BMON_SPMU:
8112 case GAUDI_EVENT_TPC1_BMON_SPMU:
8113 case GAUDI_EVENT_TPC2_BMON_SPMU:
8114 case GAUDI_EVENT_TPC3_BMON_SPMU:
8115 case GAUDI_EVENT_TPC4_BMON_SPMU:
8116 case GAUDI_EVENT_TPC5_BMON_SPMU:
8117 case GAUDI_EVENT_TPC6_BMON_SPMU:
8118 case GAUDI_EVENT_TPC7_BMON_SPMU:
8119 case GAUDI_EVENT_DMA_BM_CH0 ... GAUDI_EVENT_DMA_BM_CH7:
8120 gaudi_print_irq_info(hdev, event_type, false);
8121 hl_fw_unmask_irq(hdev, event_type);
8124 case GAUDI_EVENT_DMA_IF_SEI_0 ... GAUDI_EVENT_DMA_IF_SEI_3:
8125 gaudi_print_irq_info(hdev, event_type, false);
8126 gaudi_print_sm_sei_info(hdev, event_type,
8127 &eq_entry->sm_sei_data);
8128 rc = hl_state_dump(hdev);
8131 "Error during system state dump %d\n", rc);
8132 hl_fw_unmask_irq(hdev, event_type);
8135 case GAUDI_EVENT_FIX_POWER_ENV_S ... GAUDI_EVENT_FIX_THERMAL_ENV_E:
8136 gaudi_print_clk_change_info(hdev, event_type);
8137 hl_fw_unmask_irq(hdev, event_type);
8140 case GAUDI_EVENT_PSOC_GPIO_U16_0:
8141 cause = le64_to_cpu(eq_entry->data[0]) & 0xFF;
8143 "Received high temp H/W interrupt %d (cause %d)\n",
8147 case GAUDI_EVENT_DEV_RESET_REQ:
8148 gaudi_print_irq_info(hdev, event_type, false);
8151 case GAUDI_EVENT_PKT_QUEUE_OUT_SYNC:
8152 gaudi_print_irq_info(hdev, event_type, false);
8153 gaudi_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
8156 case GAUDI_EVENT_FW_ALIVE_S:
8157 gaudi_print_irq_info(hdev, event_type, false);
8158 gaudi_print_fw_alive_info(hdev, &eq_entry->fw_alive);
8162 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
8170 if (hdev->asic_prop.fw_security_enabled)
8171 hl_device_reset(hdev, HL_RESET_HARD | HL_RESET_FW);
8172 else if (hdev->hard_reset_on_fw_events)
8173 hl_device_reset(hdev, HL_RESET_HARD);
8175 hl_fw_unmask_irq(hdev, event_type);
8178 static void *gaudi_get_events_stat(struct hl_device *hdev, bool aggregate,
8181 struct gaudi_device *gaudi = hdev->asic_specific;
8184 *size = (u32) sizeof(gaudi->events_stat_aggregate);
8185 return gaudi->events_stat_aggregate;
8188 *size = (u32) sizeof(gaudi->events_stat);
8189 return gaudi->events_stat;
8192 static int gaudi_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
8195 struct gaudi_device *gaudi = hdev->asic_specific;
8196 u32 status, timeout_usec;
8199 if (!(gaudi->hw_cap_initialized & HW_CAP_MMU) ||
8200 hdev->hard_reset_pending)
8204 timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC;
8206 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
8208 /* L0 & L1 invalidation */
8209 WREG32(mmSTLB_INV_PS, 3);
8210 WREG32(mmSTLB_CACHE_INV, gaudi->mmu_cache_inv_pi++);
8211 WREG32(mmSTLB_INV_PS, 2);
8213 rc = hl_poll_timeout(
8221 WREG32(mmSTLB_INV_SET, 0);
8224 dev_err_ratelimited(hdev->dev,
8225 "MMU cache invalidation timeout\n");
8226 hl_device_reset(hdev, HL_RESET_HARD);
8232 static int gaudi_mmu_invalidate_cache_range(struct hl_device *hdev,
8233 bool is_hard, u32 flags,
8234 u32 asid, u64 va, u64 size)
8236 /* Treat as invalidate all because there is no range invalidation
8239 return hdev->asic_funcs->mmu_invalidate_cache(hdev, is_hard, flags);
8242 static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev,
8243 u32 asid, u64 phys_addr)
8245 u32 status, timeout_usec;
8249 timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC;
8251 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
8253 WREG32(MMU_ASID, asid);
8254 WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
8255 WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
8256 WREG32(MMU_BUSY, 0x80000000);
8258 rc = hl_poll_timeout(
8262 !(status & 0x80000000),
8268 "Timeout during MMU hop0 config of asid %d\n", asid);
8275 static int gaudi_send_heartbeat(struct hl_device *hdev)
8277 struct gaudi_device *gaudi = hdev->asic_specific;
8279 if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
8282 return hl_fw_send_heartbeat(hdev);
8285 static int gaudi_cpucp_info_get(struct hl_device *hdev)
8287 struct gaudi_device *gaudi = hdev->asic_specific;
8288 struct asic_fixed_properties *prop = &hdev->asic_prop;
8291 if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
8294 rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
8295 mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
8300 if (!strlen(prop->cpucp_info.card_name))
8301 strncpy(prop->cpucp_info.card_name, GAUDI_DEFAULT_CARD_NAME,
8304 hdev->card_type = le32_to_cpu(hdev->asic_prop.cpucp_info.card_type);
8306 set_default_power_values(hdev);
8308 hdev->max_power = prop->max_power_default;
8313 static bool gaudi_is_device_idle(struct hl_device *hdev, u64 *mask_arr,
8314 u8 mask_len, struct seq_file *s)
8316 struct gaudi_device *gaudi = hdev->asic_specific;
8317 const char *fmt = "%-5d%-9s%#-14x%#-12x%#x\n";
8318 const char *mme_slave_fmt = "%-5d%-9s%-14s%-12s%#x\n";
8319 const char *nic_fmt = "%-5d%-9s%#-14x%#x\n";
8320 unsigned long *mask = (unsigned long *)mask_arr;
8321 u32 qm_glbl_sts0, qm_cgm_sts, dma_core_sts0, tpc_cfg_sts, mme_arch_sts;
8322 bool is_idle = true, is_eng_idle, is_slave;
8324 int i, dma_id, port;
8326 mutex_lock(&gaudi->clk_gate_mutex);
8328 hdev->asic_funcs->disable_clock_gating(hdev);
8332 "\nDMA is_idle QM_GLBL_STS0 QM_CGM_STS DMA_CORE_STS0\n"
8333 "--- ------- ------------ ---------- -------------\n");
8335 for (i = 0 ; i < DMA_NUMBER_OF_CHNLS ; i++) {
8336 dma_id = gaudi_dma_assignment[i];
8337 offset = dma_id * DMA_QMAN_OFFSET;
8339 qm_glbl_sts0 = RREG32(mmDMA0_QM_GLBL_STS0 + offset);
8340 qm_cgm_sts = RREG32(mmDMA0_QM_CGM_STS + offset);
8341 dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + offset);
8342 is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) &&
8343 IS_DMA_IDLE(dma_core_sts0);
8344 is_idle &= is_eng_idle;
8346 if (mask && !is_eng_idle)
8347 set_bit(GAUDI_ENGINE_ID_DMA_0 + dma_id, mask);
8349 seq_printf(s, fmt, dma_id,
8350 is_eng_idle ? "Y" : "N", qm_glbl_sts0,
8351 qm_cgm_sts, dma_core_sts0);
8356 "\nTPC is_idle QM_GLBL_STS0 QM_CGM_STS CFG_STATUS\n"
8357 "--- ------- ------------ ---------- ----------\n");
8359 for (i = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) {
8360 offset = i * TPC_QMAN_OFFSET;
8361 qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + offset);
8362 qm_cgm_sts = RREG32(mmTPC0_QM_CGM_STS + offset);
8363 tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + offset);
8364 is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) &&
8365 IS_TPC_IDLE(tpc_cfg_sts);
8366 is_idle &= is_eng_idle;
8368 if (mask && !is_eng_idle)
8369 set_bit(GAUDI_ENGINE_ID_TPC_0 + i, mask);
8371 seq_printf(s, fmt, i,
8372 is_eng_idle ? "Y" : "N",
8373 qm_glbl_sts0, qm_cgm_sts, tpc_cfg_sts);
8378 "\nMME is_idle QM_GLBL_STS0 QM_CGM_STS ARCH_STATUS\n"
8379 "--- ------- ------------ ---------- -----------\n");
8381 for (i = 0 ; i < MME_NUMBER_OF_ENGINES ; i++) {
8382 offset = i * MME_QMAN_OFFSET;
8383 mme_arch_sts = RREG32(mmMME0_CTRL_ARCH_STATUS + offset);
8384 is_eng_idle = IS_MME_IDLE(mme_arch_sts);
8386 /* MME 1 & 3 are slaves, no need to check their QMANs */
8389 qm_glbl_sts0 = RREG32(mmMME0_QM_GLBL_STS0 + offset);
8390 qm_cgm_sts = RREG32(mmMME0_QM_CGM_STS + offset);
8391 is_eng_idle &= IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts);
8394 is_idle &= is_eng_idle;
8396 if (mask && !is_eng_idle)
8397 set_bit(GAUDI_ENGINE_ID_MME_0 + i, mask);
8400 seq_printf(s, fmt, i,
8401 is_eng_idle ? "Y" : "N",
8402 qm_glbl_sts0, qm_cgm_sts, mme_arch_sts);
8404 seq_printf(s, mme_slave_fmt, i,
8405 is_eng_idle ? "Y" : "N", "-",
8411 seq_puts(s, "\nNIC is_idle QM_GLBL_STS0 QM_CGM_STS\n"
8412 "--- ------- ------------ ----------\n");
8414 for (i = 0 ; i < (NIC_NUMBER_OF_ENGINES / 2) ; i++) {
8415 offset = i * NIC_MACRO_QMAN_OFFSET;
8417 if (gaudi->hw_cap_initialized & BIT(HW_CAP_NIC_SHIFT + port)) {
8418 qm_glbl_sts0 = RREG32(mmNIC0_QM0_GLBL_STS0 + offset);
8419 qm_cgm_sts = RREG32(mmNIC0_QM0_CGM_STS + offset);
8420 is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts);
8421 is_idle &= is_eng_idle;
8423 if (mask && !is_eng_idle)
8424 set_bit(GAUDI_ENGINE_ID_NIC_0 + port, mask);
8426 seq_printf(s, nic_fmt, port,
8427 is_eng_idle ? "Y" : "N",
8428 qm_glbl_sts0, qm_cgm_sts);
8432 if (gaudi->hw_cap_initialized & BIT(HW_CAP_NIC_SHIFT + port)) {
8433 qm_glbl_sts0 = RREG32(mmNIC0_QM1_GLBL_STS0 + offset);
8434 qm_cgm_sts = RREG32(mmNIC0_QM1_CGM_STS + offset);
8435 is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts);
8436 is_idle &= is_eng_idle;
8438 if (mask && !is_eng_idle)
8439 set_bit(GAUDI_ENGINE_ID_NIC_0 + port, mask);
8441 seq_printf(s, nic_fmt, port,
8442 is_eng_idle ? "Y" : "N",
8443 qm_glbl_sts0, qm_cgm_sts);
8450 hdev->asic_funcs->set_clock_gating(hdev);
8452 mutex_unlock(&gaudi->clk_gate_mutex);
8457 static void gaudi_hw_queues_lock(struct hl_device *hdev)
8458 __acquires(&gaudi->hw_queues_lock)
8460 struct gaudi_device *gaudi = hdev->asic_specific;
8462 spin_lock(&gaudi->hw_queues_lock);
8465 static void gaudi_hw_queues_unlock(struct hl_device *hdev)
8466 __releases(&gaudi->hw_queues_lock)
8468 struct gaudi_device *gaudi = hdev->asic_specific;
8470 spin_unlock(&gaudi->hw_queues_lock);
8473 static u32 gaudi_get_pci_id(struct hl_device *hdev)
8475 return hdev->pdev->device;
8478 static int gaudi_get_eeprom_data(struct hl_device *hdev, void *data,
8481 struct gaudi_device *gaudi = hdev->asic_specific;
8483 if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))
8486 return hl_fw_get_eeprom_data(hdev, data, max_size);
8490 * this function should be used only during initialization and/or after reset,
8491 * when there are no active users.
8493 static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel,
8496 struct gaudi_device *gaudi = hdev->asic_specific;
8501 offset = tpc_id * (mmTPC1_CFG_STATUS - mmTPC0_CFG_STATUS);
8504 kernel_timeout = GAUDI_PLDM_TPC_KERNEL_WAIT_USEC;
8506 kernel_timeout = HL_DEVICE_TIMEOUT_USEC;
8508 mutex_lock(&gaudi->clk_gate_mutex);
8510 hdev->asic_funcs->disable_clock_gating(hdev);
8512 WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW + offset,
8513 lower_32_bits(tpc_kernel));
8514 WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH + offset,
8515 upper_32_bits(tpc_kernel));
8517 WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW + offset,
8518 lower_32_bits(tpc_kernel));
8519 WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH + offset,
8520 upper_32_bits(tpc_kernel));
8521 /* set a valid LUT pointer, content is of no significance */
8522 WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO + offset,
8523 lower_32_bits(tpc_kernel));
8524 WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI + offset,
8525 upper_32_bits(tpc_kernel));
8527 WREG32(mmTPC0_CFG_QM_SYNC_OBJECT_ADDR + offset,
8528 lower_32_bits(CFG_BASE +
8529 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0));
8531 WREG32(mmTPC0_CFG_TPC_CMD + offset,
8532 (1 << TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT |
8533 1 << TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT));
8534 /* wait a bit for the engine to start executing */
8535 usleep_range(1000, 1500);
8537 /* wait until engine has finished executing */
8538 rc = hl_poll_timeout(
8540 mmTPC0_CFG_STATUS + offset,
8542 (status & TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK) ==
8543 TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK,
8549 "Timeout while waiting for TPC%d icache prefetch\n",
8551 hdev->asic_funcs->set_clock_gating(hdev);
8552 mutex_unlock(&gaudi->clk_gate_mutex);
8556 WREG32(mmTPC0_CFG_TPC_EXECUTE + offset,
8557 1 << TPC0_CFG_TPC_EXECUTE_V_SHIFT);
8559 /* wait a bit for the engine to start executing */
8560 usleep_range(1000, 1500);
8562 /* wait until engine has finished executing */
8563 rc = hl_poll_timeout(
8565 mmTPC0_CFG_STATUS + offset,
8567 (status & TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK) ==
8568 TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK,
8574 "Timeout while waiting for TPC%d vector pipe\n",
8576 hdev->asic_funcs->set_clock_gating(hdev);
8577 mutex_unlock(&gaudi->clk_gate_mutex);
8581 rc = hl_poll_timeout(
8583 mmTPC0_CFG_WQ_INFLIGHT_CNTR + offset,
8589 hdev->asic_funcs->set_clock_gating(hdev);
8590 mutex_unlock(&gaudi->clk_gate_mutex);
8594 "Timeout while waiting for TPC%d kernel to execute\n",
8602 static int gaudi_internal_cb_pool_init(struct hl_device *hdev,
8605 struct gaudi_device *gaudi = hdev->asic_specific;
8606 int min_alloc_order, rc, collective_cb_size;
8608 if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
8611 hdev->internal_cb_pool_virt_addr =
8612 hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
8613 HOST_SPACE_INTERNAL_CB_SZ,
8614 &hdev->internal_cb_pool_dma_addr,
8615 GFP_KERNEL | __GFP_ZERO);
8617 if (!hdev->internal_cb_pool_virt_addr)
8620 collective_cb_size = sizeof(struct packet_msg_short) * 5 +
8621 sizeof(struct packet_fence);
8622 min_alloc_order = ilog2(collective_cb_size);
8624 hdev->internal_cb_pool = gen_pool_create(min_alloc_order, -1);
8625 if (!hdev->internal_cb_pool) {
8627 "Failed to create internal CB pool\n");
8629 goto free_internal_cb_pool;
8632 rc = gen_pool_add(hdev->internal_cb_pool,
8633 (uintptr_t) hdev->internal_cb_pool_virt_addr,
8634 HOST_SPACE_INTERNAL_CB_SZ, -1);
8637 "Failed to add memory to internal CB pool\n");
8639 goto destroy_internal_cb_pool;
8642 hdev->internal_cb_va_base = hl_reserve_va_block(hdev, ctx,
8643 HL_VA_RANGE_TYPE_HOST, HOST_SPACE_INTERNAL_CB_SZ,
8644 HL_MMU_VA_ALIGNMENT_NOT_NEEDED);
8646 if (!hdev->internal_cb_va_base) {
8648 goto destroy_internal_cb_pool;
8651 mutex_lock(&ctx->mmu_lock);
8652 rc = hl_mmu_map_contiguous(ctx, hdev->internal_cb_va_base,
8653 hdev->internal_cb_pool_dma_addr,
8654 HOST_SPACE_INTERNAL_CB_SZ);
8656 hdev->asic_funcs->mmu_invalidate_cache(hdev, false, VM_TYPE_USERPTR);
8657 mutex_unlock(&ctx->mmu_lock);
8660 goto unreserve_internal_cb_pool;
8664 unreserve_internal_cb_pool:
8665 hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base,
8666 HOST_SPACE_INTERNAL_CB_SZ);
8667 destroy_internal_cb_pool:
8668 gen_pool_destroy(hdev->internal_cb_pool);
8669 free_internal_cb_pool:
8670 hdev->asic_funcs->asic_dma_free_coherent(hdev,
8671 HOST_SPACE_INTERNAL_CB_SZ,
8672 hdev->internal_cb_pool_virt_addr,
8673 hdev->internal_cb_pool_dma_addr);
8678 static void gaudi_internal_cb_pool_fini(struct hl_device *hdev,
8681 struct gaudi_device *gaudi = hdev->asic_specific;
8683 if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
8686 mutex_lock(&ctx->mmu_lock);
8687 hl_mmu_unmap_contiguous(ctx, hdev->internal_cb_va_base,
8688 HOST_SPACE_INTERNAL_CB_SZ);
8689 hl_unreserve_va_block(hdev, ctx, hdev->internal_cb_va_base,
8690 HOST_SPACE_INTERNAL_CB_SZ);
8691 hdev->asic_funcs->mmu_invalidate_cache(hdev, true, VM_TYPE_USERPTR);
8692 mutex_unlock(&ctx->mmu_lock);
8694 gen_pool_destroy(hdev->internal_cb_pool);
8696 hdev->asic_funcs->asic_dma_free_coherent(hdev,
8697 HOST_SPACE_INTERNAL_CB_SZ,
8698 hdev->internal_cb_pool_virt_addr,
8699 hdev->internal_cb_pool_dma_addr);
8702 static int gaudi_ctx_init(struct hl_ctx *ctx)
8706 if (ctx->asid == HL_KERNEL_ASID_ID)
8709 rc = gaudi_internal_cb_pool_init(ctx->hdev, ctx);
8713 rc = gaudi_restore_user_registers(ctx->hdev);
8715 gaudi_internal_cb_pool_fini(ctx->hdev, ctx);
8720 static void gaudi_ctx_fini(struct hl_ctx *ctx)
8722 if (ctx->asid == HL_KERNEL_ASID_ID)
8725 gaudi_internal_cb_pool_fini(ctx->hdev, ctx);
8728 static u32 gaudi_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
8730 return gaudi_cq_assignment[cq_idx];
8733 static u32 gaudi_get_signal_cb_size(struct hl_device *hdev)
8735 return sizeof(struct packet_msg_short) +
8736 sizeof(struct packet_msg_prot) * 2;
8739 static u32 gaudi_get_wait_cb_size(struct hl_device *hdev)
8741 return sizeof(struct packet_msg_short) * 4 +
8742 sizeof(struct packet_fence) +
8743 sizeof(struct packet_msg_prot) * 2;
8746 static u32 gaudi_get_sob_addr(struct hl_device *hdev, u32 sob_id)
8748 return mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + (sob_id * 4);
8751 static u32 gaudi_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
8754 struct hl_cb *cb = (struct hl_cb *) data;
8755 struct packet_msg_short *pkt;
8756 u32 value, ctl, pkt_size = sizeof(*pkt);
8758 pkt = cb->kernel_address + size;
8759 memset(pkt, 0, pkt_size);
8761 /* Inc by 1, Mode ADD */
8762 value = FIELD_PREP(GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK, 1);
8763 value |= FIELD_PREP(GAUDI_PKT_SHORT_VAL_SOB_MOD_MASK, 1);
8765 ctl = FIELD_PREP(GAUDI_PKT_SHORT_CTL_ADDR_MASK, sob_id * 4);
8766 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OP_MASK, 0); /* write the value */
8767 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 3); /* W_S SOB base */
8768 ctl |= FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
8769 ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, eb);
8770 ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
8771 ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
8773 pkt->value = cpu_to_le32(value);
8774 pkt->ctl = cpu_to_le32(ctl);
8776 return size + pkt_size;
8779 static u32 gaudi_add_mon_msg_short(struct packet_msg_short *pkt, u32 value,
8782 u32 ctl, pkt_size = sizeof(*pkt);
8784 memset(pkt, 0, pkt_size);
8786 ctl = FIELD_PREP(GAUDI_PKT_SHORT_CTL_ADDR_MASK, addr);
8787 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 2); /* W_S MON base */
8788 ctl |= FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
8789 ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 0);
8790 ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
8791 ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 0); /* last pkt MB */
8793 pkt->value = cpu_to_le32(value);
8794 pkt->ctl = cpu_to_le32(ctl);
8799 static u32 gaudi_add_arm_monitor_pkt(struct hl_device *hdev,
8800 struct packet_msg_short *pkt, u16 sob_base, u8 sob_mask,
8801 u16 sob_val, u16 mon_id)
8804 u32 ctl, value, pkt_size = sizeof(*pkt);
8805 u16 msg_addr_offset;
8808 if (hl_gen_sob_mask(sob_base, sob_mask, &mask)) {
8810 "sob_base %u (mask %#x) is not valid\n",
8811 sob_base, sob_mask);
8816 * monitor_base should be the content of the base0 address registers,
8817 * so it will be added to the msg short offsets
8819 monitor_base = mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0;
8822 (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 + mon_id * 4) -
8825 memset(pkt, 0, pkt_size);
8827 /* Monitor config packet: bind the monitor to a sync object */
8828 value = FIELD_PREP(GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_MASK, sob_base / 8);
8829 value |= FIELD_PREP(GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_MASK, sob_val);
8830 value |= FIELD_PREP(GAUDI_PKT_SHORT_VAL_MON_MODE_MASK,
8831 0); /* GREATER OR EQUAL*/
8832 value |= FIELD_PREP(GAUDI_PKT_SHORT_VAL_MON_MASK_MASK, mask);
8834 ctl = FIELD_PREP(GAUDI_PKT_SHORT_CTL_ADDR_MASK, msg_addr_offset);
8835 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OP_MASK, 0); /* write the value */
8836 ctl |= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 2); /* W_S MON base */
8837 ctl |= FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
8838 ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 0);
8839 ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
8840 ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
8842 pkt->value = cpu_to_le32(value);
8843 pkt->ctl = cpu_to_le32(ctl);
8848 static u32 gaudi_add_fence_pkt(struct packet_fence *pkt)
8850 u32 ctl, cfg, pkt_size = sizeof(*pkt);
8852 memset(pkt, 0, pkt_size);
8854 cfg = FIELD_PREP(GAUDI_PKT_FENCE_CFG_DEC_VAL_MASK, 1);
8855 cfg |= FIELD_PREP(GAUDI_PKT_FENCE_CFG_TARGET_VAL_MASK, 1);
8856 cfg |= FIELD_PREP(GAUDI_PKT_FENCE_CFG_ID_MASK, 2);
8858 ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_FENCE);
8859 ctl |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 0);
8860 ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);
8861 ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);
8863 pkt->cfg = cpu_to_le32(cfg);
8864 pkt->ctl = cpu_to_le32(ctl);
8869 static int gaudi_get_fence_addr(struct hl_device *hdev, u32 queue_id, u64 *addr)
8871 u32 offset, nic_index;
8874 case GAUDI_QUEUE_ID_DMA_0_0:
8875 offset = mmDMA0_QM_CP_FENCE2_RDATA_0;
8877 case GAUDI_QUEUE_ID_DMA_0_1:
8878 offset = mmDMA0_QM_CP_FENCE2_RDATA_1;
8880 case GAUDI_QUEUE_ID_DMA_0_2:
8881 offset = mmDMA0_QM_CP_FENCE2_RDATA_2;
8883 case GAUDI_QUEUE_ID_DMA_0_3:
8884 offset = mmDMA0_QM_CP_FENCE2_RDATA_3;
8886 case GAUDI_QUEUE_ID_DMA_1_0:
8887 offset = mmDMA1_QM_CP_FENCE2_RDATA_0;
8889 case GAUDI_QUEUE_ID_DMA_1_1:
8890 offset = mmDMA1_QM_CP_FENCE2_RDATA_1;
8892 case GAUDI_QUEUE_ID_DMA_1_2:
8893 offset = mmDMA1_QM_CP_FENCE2_RDATA_2;
8895 case GAUDI_QUEUE_ID_DMA_1_3:
8896 offset = mmDMA1_QM_CP_FENCE2_RDATA_3;
8898 case GAUDI_QUEUE_ID_DMA_5_0:
8899 offset = mmDMA5_QM_CP_FENCE2_RDATA_0;
8901 case GAUDI_QUEUE_ID_DMA_5_1:
8902 offset = mmDMA5_QM_CP_FENCE2_RDATA_1;
8904 case GAUDI_QUEUE_ID_DMA_5_2:
8905 offset = mmDMA5_QM_CP_FENCE2_RDATA_2;
8907 case GAUDI_QUEUE_ID_DMA_5_3:
8908 offset = mmDMA5_QM_CP_FENCE2_RDATA_3;
8910 case GAUDI_QUEUE_ID_TPC_7_0:
8911 offset = mmTPC7_QM_CP_FENCE2_RDATA_0;
8913 case GAUDI_QUEUE_ID_TPC_7_1:
8914 offset = mmTPC7_QM_CP_FENCE2_RDATA_1;
8916 case GAUDI_QUEUE_ID_TPC_7_2:
8917 offset = mmTPC7_QM_CP_FENCE2_RDATA_2;
8919 case GAUDI_QUEUE_ID_TPC_7_3:
8920 offset = mmTPC7_QM_CP_FENCE2_RDATA_3;
8922 case GAUDI_QUEUE_ID_NIC_0_0:
8923 case GAUDI_QUEUE_ID_NIC_1_0:
8924 case GAUDI_QUEUE_ID_NIC_2_0:
8925 case GAUDI_QUEUE_ID_NIC_3_0:
8926 case GAUDI_QUEUE_ID_NIC_4_0:
8927 case GAUDI_QUEUE_ID_NIC_5_0:
8928 case GAUDI_QUEUE_ID_NIC_6_0:
8929 case GAUDI_QUEUE_ID_NIC_7_0:
8930 case GAUDI_QUEUE_ID_NIC_8_0:
8931 case GAUDI_QUEUE_ID_NIC_9_0:
8932 nic_index = (queue_id - GAUDI_QUEUE_ID_NIC_0_0) >> 2;
8933 offset = mmNIC0_QM0_CP_FENCE2_RDATA_0 +
8934 (nic_index >> 1) * NIC_MACRO_QMAN_OFFSET +
8935 (nic_index & 0x1) * NIC_ENGINE_QMAN_OFFSET;
8937 case GAUDI_QUEUE_ID_NIC_0_1:
8938 case GAUDI_QUEUE_ID_NIC_1_1:
8939 case GAUDI_QUEUE_ID_NIC_2_1:
8940 case GAUDI_QUEUE_ID_NIC_3_1:
8941 case GAUDI_QUEUE_ID_NIC_4_1:
8942 case GAUDI_QUEUE_ID_NIC_5_1:
8943 case GAUDI_QUEUE_ID_NIC_6_1:
8944 case GAUDI_QUEUE_ID_NIC_7_1:
8945 case GAUDI_QUEUE_ID_NIC_8_1:
8946 case GAUDI_QUEUE_ID_NIC_9_1:
8947 nic_index = (queue_id - GAUDI_QUEUE_ID_NIC_0_1) >> 2;
8948 offset = mmNIC0_QM0_CP_FENCE2_RDATA_1 +
8949 (nic_index >> 1) * NIC_MACRO_QMAN_OFFSET +
8950 (nic_index & 0x1) * NIC_ENGINE_QMAN_OFFSET;
8952 case GAUDI_QUEUE_ID_NIC_0_2:
8953 case GAUDI_QUEUE_ID_NIC_1_2:
8954 case GAUDI_QUEUE_ID_NIC_2_2:
8955 case GAUDI_QUEUE_ID_NIC_3_2:
8956 case GAUDI_QUEUE_ID_NIC_4_2:
8957 case GAUDI_QUEUE_ID_NIC_5_2:
8958 case GAUDI_QUEUE_ID_NIC_6_2:
8959 case GAUDI_QUEUE_ID_NIC_7_2:
8960 case GAUDI_QUEUE_ID_NIC_8_2:
8961 case GAUDI_QUEUE_ID_NIC_9_2:
8962 nic_index = (queue_id - GAUDI_QUEUE_ID_NIC_0_2) >> 2;
8963 offset = mmNIC0_QM0_CP_FENCE2_RDATA_2 +
8964 (nic_index >> 1) * NIC_MACRO_QMAN_OFFSET +
8965 (nic_index & 0x1) * NIC_ENGINE_QMAN_OFFSET;
8967 case GAUDI_QUEUE_ID_NIC_0_3:
8968 case GAUDI_QUEUE_ID_NIC_1_3:
8969 case GAUDI_QUEUE_ID_NIC_2_3:
8970 case GAUDI_QUEUE_ID_NIC_3_3:
8971 case GAUDI_QUEUE_ID_NIC_4_3:
8972 case GAUDI_QUEUE_ID_NIC_5_3:
8973 case GAUDI_QUEUE_ID_NIC_6_3:
8974 case GAUDI_QUEUE_ID_NIC_7_3:
8975 case GAUDI_QUEUE_ID_NIC_8_3:
8976 case GAUDI_QUEUE_ID_NIC_9_3:
8977 nic_index = (queue_id - GAUDI_QUEUE_ID_NIC_0_3) >> 2;
8978 offset = mmNIC0_QM0_CP_FENCE2_RDATA_3 +
8979 (nic_index >> 1) * NIC_MACRO_QMAN_OFFSET +
8980 (nic_index & 0x1) * NIC_ENGINE_QMAN_OFFSET;
8986 *addr = CFG_BASE + offset;
8991 static u32 gaudi_add_mon_pkts(void *buf, u16 mon_id, u64 fence_addr)
8995 u16 msg_addr_offset;
8998 * monitor_base should be the content of the base0 address registers,
8999 * so it will be added to the msg short offsets
9001 monitor_base = mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0;
9003 /* First monitor config packet: low address of the sync */
9005 (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_id * 4) -
9008 size += gaudi_add_mon_msg_short(buf + size, (u32) fence_addr,
9011 /* Second monitor config packet: high address of the sync */
9013 (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_id * 4) -
9016 size += gaudi_add_mon_msg_short(buf + size, (u32) (fence_addr >> 32),
9020 * Third monitor config packet: the payload, i.e. what to write when the
9024 (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_id * 4) -
9027 size += gaudi_add_mon_msg_short(buf + size, 1, msg_addr_offset);
9032 static u32 gaudi_gen_wait_cb(struct hl_device *hdev,
9033 struct hl_gen_wait_properties *prop)
9035 struct hl_cb *cb = (struct hl_cb *) prop->data;
9036 void *buf = cb->kernel_address;
9038 u32 size = prop->size;
9040 if (gaudi_get_fence_addr(hdev, prop->q_idx, &fence_addr)) {
9041 dev_crit(hdev->dev, "wrong queue id %d for wait packet\n",
9046 size += gaudi_add_mon_pkts(buf + size, prop->mon_id, fence_addr);
9047 size += gaudi_add_arm_monitor_pkt(hdev, buf + size, prop->sob_base,
9048 prop->sob_mask, prop->sob_val, prop->mon_id);
9049 size += gaudi_add_fence_pkt(buf + size);
9054 static void gaudi_reset_sob(struct hl_device *hdev, void *data)
9056 struct hl_hw_sob *hw_sob = (struct hl_hw_sob *) data;
9058 dev_dbg(hdev->dev, "reset SOB, q_idx: %d, sob_id: %d\n", hw_sob->q_idx,
9061 WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 +
9062 hw_sob->sob_id * 4, 0);
9064 kref_init(&hw_sob->kref);
9067 static void gaudi_set_dma_mask_from_fw(struct hl_device *hdev)
9069 if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) ==
9070 HL_POWER9_HOST_MAGIC) {
9071 hdev->power9_64bit_dma_enable = 1;
9072 hdev->dma_mask = 64;
9074 hdev->power9_64bit_dma_enable = 0;
9075 hdev->dma_mask = 48;
9079 static u64 gaudi_get_device_time(struct hl_device *hdev)
9081 u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
9083 return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
9086 static int gaudi_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
9087 u32 *block_size, u32 *block_id)
9092 static int gaudi_block_mmap(struct hl_device *hdev,
9093 struct vm_area_struct *vma,
9094 u32 block_id, u32 block_size)
9099 static void gaudi_enable_events_from_fw(struct hl_device *hdev)
9101 struct cpu_dyn_regs *dyn_regs =
9102 &hdev->fw_loader.dynamic_loader.comm_desc.cpu_dyn_regs;
9103 u32 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
9104 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
9105 le32_to_cpu(dyn_regs->gic_host_ints_irq);
9107 WREG32(irq_handler_offset,
9108 gaudi_irq_map_table[GAUDI_EVENT_INTS_REGISTER].cpu_id);
9111 static int gaudi_map_pll_idx_to_fw_idx(u32 pll_idx)
9114 case HL_GAUDI_CPU_PLL: return CPU_PLL;
9115 case HL_GAUDI_PCI_PLL: return PCI_PLL;
9116 case HL_GAUDI_NIC_PLL: return NIC_PLL;
9117 case HL_GAUDI_DMA_PLL: return DMA_PLL;
9118 case HL_GAUDI_MESH_PLL: return MESH_PLL;
9119 case HL_GAUDI_MME_PLL: return MME_PLL;
9120 case HL_GAUDI_TPC_PLL: return TPC_PLL;
9121 case HL_GAUDI_IF_PLL: return IF_PLL;
9122 case HL_GAUDI_SRAM_PLL: return SRAM_PLL;
9123 case HL_GAUDI_HBM_PLL: return HBM_PLL;
9124 default: return -EINVAL;
9128 static int gaudi_add_sync_to_engine_map_entry(
9129 struct hl_sync_to_engine_map *map, u32 reg_value,
9130 enum hl_sync_engine_type engine_type, u32 engine_id)
9132 struct hl_sync_to_engine_map_entry *entry;
9134 /* Reg value represents a partial address of sync object,
9135 * it is used as unique identifier. For this we need to
9136 * clear the cutoff cfg base bits from the value.
9138 if (reg_value == 0 || reg_value == 0xffffffff)
9140 reg_value -= (u32)CFG_BASE;
9142 /* create a new hash entry */
9143 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
9146 entry->engine_type = engine_type;
9147 entry->engine_id = engine_id;
9148 entry->sync_id = reg_value;
9149 hash_add(map->tb, &entry->node, reg_value);
9154 static int gaudi_gen_sync_to_engine_map(struct hl_device *hdev,
9155 struct hl_sync_to_engine_map *map)
9157 struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
9158 struct gaudi_device *gaudi = hdev->asic_specific;
9162 /* Iterate over TPC engines */
9163 for (i = 0; i < sds->props[SP_NUM_OF_TPC_ENGINES]; ++i) {
9164 /* TPC registered must be accessed with clock gating disabled */
9165 mutex_lock(&gaudi->clk_gate_mutex);
9166 hdev->asic_funcs->disable_clock_gating(hdev);
9168 reg_value = RREG32(sds->props[SP_TPC0_CFG_SO] +
9169 sds->props[SP_NEXT_TPC] * i);
9171 /* We can reenable clock_gating */
9172 hdev->asic_funcs->set_clock_gating(hdev);
9173 mutex_unlock(&gaudi->clk_gate_mutex);
9175 rc = gaudi_add_sync_to_engine_map_entry(map, reg_value,
9178 goto free_sync_to_engine_map;
9181 /* Iterate over MME engines */
9182 for (i = 0; i < sds->props[SP_NUM_OF_MME_ENGINES]; ++i) {
9183 for (j = 0; j < sds->props[SP_SUB_MME_ENG_NUM]; ++j) {
9184 /* MME registered must be accessed with clock gating
9187 mutex_lock(&gaudi->clk_gate_mutex);
9188 hdev->asic_funcs->disable_clock_gating(hdev);
9190 reg_value = RREG32(sds->props[SP_MME_CFG_SO] +
9191 sds->props[SP_NEXT_MME] * i +
9194 /* We can reenable clock_gating */
9195 hdev->asic_funcs->set_clock_gating(hdev);
9196 mutex_unlock(&gaudi->clk_gate_mutex);
9198 rc = gaudi_add_sync_to_engine_map_entry(
9199 map, reg_value, ENGINE_MME,
9200 i * sds->props[SP_SUB_MME_ENG_NUM] + j);
9202 goto free_sync_to_engine_map;
9206 /* Iterate over DMA engines */
9207 for (i = 0; i < sds->props[SP_NUM_OF_DMA_ENGINES]; ++i) {
9208 reg_value = RREG32(sds->props[SP_DMA_CFG_SO] +
9209 sds->props[SP_DMA_QUEUES_OFFSET] * i);
9210 rc = gaudi_add_sync_to_engine_map_entry(map, reg_value,
9213 goto free_sync_to_engine_map;
9218 free_sync_to_engine_map:
9219 hl_state_dump_free_sync_to_engine_map(map);
9224 static int gaudi_monitor_valid(struct hl_mon_state_dump *mon)
9227 SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_MASK,
9231 static void gaudi_fill_sobs_from_mon(char *sobs, struct hl_mon_state_dump *mon)
9233 const size_t max_write = 10;
9237 /* Sync object ID is calculated as follows:
9238 * (8 * group_id + cleared bits in mask)
9240 gid = FIELD_GET(SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK,
9242 mask = FIELD_GET(SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK,
9245 for (i = 0, offset = 0; mask && offset < MONITOR_SOB_STRING_SIZE -
9246 max_write; mask >>= 1, i++) {
9248 sob = gid * MONITOR_MAX_SOBS + i;
9251 offset += snprintf(sobs + offset, max_write,
9254 offset += snprintf(sobs + offset, max_write, "%u", sob);
9259 static int gaudi_print_single_monitor(char **buf, size_t *size, size_t *offset,
9260 struct hl_device *hdev,
9261 struct hl_mon_state_dump *mon)
9264 char scratch_buf1[BIN_REG_STRING_SIZE],
9265 scratch_buf2[BIN_REG_STRING_SIZE];
9266 char monitored_sobs[MONITOR_SOB_STRING_SIZE] = {0};
9268 name = hl_state_dump_get_monitor_name(hdev, mon);
9272 gaudi_fill_sobs_from_mon(monitored_sobs, mon);
9274 return hl_snprintf_resize(
9276 "Mon id: %u%s, wait for group id: %u mask %s to reach val: %u and write %u to address 0x%llx. Pending: %s. Means sync objects [%s] are being monitored.",
9278 FIELD_GET(SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK,
9280 hl_format_as_binary(
9281 scratch_buf1, sizeof(scratch_buf1),
9283 SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK,
9285 FIELD_GET(SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_MASK,
9288 (((u64)mon->wr_addr_high) << 32) | mon->wr_addr_low,
9289 hl_format_as_binary(
9290 scratch_buf2, sizeof(scratch_buf2),
9292 SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_MASK,
9298 static int gaudi_print_fences_single_engine(
9299 struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
9300 enum hl_sync_engine_type engine_type, u32 engine_id, char **buf,
9301 size_t *size, size_t *offset)
9303 struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
9304 int rc = -ENOMEM, i;
9305 u32 *statuses, *fences;
9307 statuses = kcalloc(sds->props[SP_ENGINE_NUM_OF_QUEUES],
9308 sizeof(*statuses), GFP_KERNEL);
9312 fences = kcalloc(sds->props[SP_ENGINE_NUM_OF_FENCES] *
9313 sds->props[SP_ENGINE_NUM_OF_QUEUES],
9314 sizeof(*fences), GFP_KERNEL);
9318 for (i = 0; i < sds->props[SP_ENGINE_NUM_OF_FENCES]; ++i)
9319 statuses[i] = RREG32(status_base_offset + i * sizeof(u32));
9321 for (i = 0; i < sds->props[SP_ENGINE_NUM_OF_FENCES] *
9322 sds->props[SP_ENGINE_NUM_OF_QUEUES]; ++i)
9323 fences[i] = RREG32(base_offset + i * sizeof(u32));
9325 /* The actual print */
9326 for (i = 0; i < sds->props[SP_ENGINE_NUM_OF_QUEUES]; ++i) {
9328 u64 fence_cnt, fence_rdata;
9329 const char *engine_name;
9331 if (!FIELD_GET(TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_MASK,
9336 FIELD_GET(TPC0_QM_CP_STS_0_FENCE_ID_MASK, statuses[i]);
9337 fence_cnt = base_offset + CFG_BASE +
9339 (i + fence_id * sds->props[SP_ENGINE_NUM_OF_QUEUES]);
9340 fence_rdata = fence_cnt - sds->props[SP_FENCE0_CNT_OFFSET] +
9341 sds->props[SP_FENCE0_RDATA_OFFSET];
9342 engine_name = hl_sync_engine_to_string(engine_type);
9344 rc = hl_snprintf_resize(
9346 "%s%u, stream %u: fence id %u cnt = 0x%llx (%s%u_QM.CP_FENCE%u_CNT_%u) rdata = 0x%llx (%s%u_QM.CP_FENCE%u_RDATA_%u) value = %u, cp_status = %u\n",
9347 engine_name, engine_id,
9349 fence_cnt, engine_name, engine_id, fence_id, i,
9350 fence_rdata, engine_name, engine_id, fence_id, i,
9368 static struct hl_state_dump_specs_funcs gaudi_state_dump_funcs = {
9369 .monitor_valid = gaudi_monitor_valid,
9370 .print_single_monitor = gaudi_print_single_monitor,
9371 .gen_sync_to_engine_map = gaudi_gen_sync_to_engine_map,
9372 .print_fences_single_engine = gaudi_print_fences_single_engine,
9375 static void gaudi_state_dump_init(struct hl_device *hdev)
9377 struct hl_state_dump_specs *sds = &hdev->state_dump_specs;
9380 for (i = 0; i < ARRAY_SIZE(gaudi_so_id_to_str); ++i)
9381 hash_add(sds->so_id_to_str_tb,
9382 &gaudi_so_id_to_str[i].node,
9383 gaudi_so_id_to_str[i].id);
9385 for (i = 0; i < ARRAY_SIZE(gaudi_monitor_id_to_str); ++i)
9386 hash_add(sds->monitor_id_to_str_tb,
9387 &gaudi_monitor_id_to_str[i].node,
9388 gaudi_monitor_id_to_str[i].id);
9390 sds->props = gaudi_state_dump_specs_props;
9392 sds->sync_namager_names = gaudi_sync_manager_names;
9394 sds->funcs = gaudi_state_dump_funcs;
9397 static u32 *gaudi_get_stream_master_qid_arr(void)
9399 return gaudi_stream_master;
9402 static const struct hl_asic_funcs gaudi_funcs = {
9403 .early_init = gaudi_early_init,
9404 .early_fini = gaudi_early_fini,
9405 .late_init = gaudi_late_init,
9406 .late_fini = gaudi_late_fini,
9407 .sw_init = gaudi_sw_init,
9408 .sw_fini = gaudi_sw_fini,
9409 .hw_init = gaudi_hw_init,
9410 .hw_fini = gaudi_hw_fini,
9411 .halt_engines = gaudi_halt_engines,
9412 .suspend = gaudi_suspend,
9413 .resume = gaudi_resume,
9415 .ring_doorbell = gaudi_ring_doorbell,
9416 .pqe_write = gaudi_pqe_write,
9417 .asic_dma_alloc_coherent = gaudi_dma_alloc_coherent,
9418 .asic_dma_free_coherent = gaudi_dma_free_coherent,
9419 .scrub_device_mem = gaudi_scrub_device_mem,
9420 .get_int_queue_base = gaudi_get_int_queue_base,
9421 .test_queues = gaudi_test_queues,
9422 .asic_dma_pool_zalloc = gaudi_dma_pool_zalloc,
9423 .asic_dma_pool_free = gaudi_dma_pool_free,
9424 .cpu_accessible_dma_pool_alloc = gaudi_cpu_accessible_dma_pool_alloc,
9425 .cpu_accessible_dma_pool_free = gaudi_cpu_accessible_dma_pool_free,
9426 .hl_dma_unmap_sg = gaudi_dma_unmap_sg,
9427 .cs_parser = gaudi_cs_parser,
9428 .asic_dma_map_sg = gaudi_dma_map_sg,
9429 .get_dma_desc_list_size = gaudi_get_dma_desc_list_size,
9430 .add_end_of_cb_packets = gaudi_add_end_of_cb_packets,
9431 .update_eq_ci = gaudi_update_eq_ci,
9432 .context_switch = gaudi_context_switch,
9433 .restore_phase_topology = gaudi_restore_phase_topology,
9434 .debugfs_read32 = gaudi_debugfs_read32,
9435 .debugfs_write32 = gaudi_debugfs_write32,
9436 .debugfs_read64 = gaudi_debugfs_read64,
9437 .debugfs_write64 = gaudi_debugfs_write64,
9438 .debugfs_read_dma = gaudi_debugfs_read_dma,
9439 .add_device_attr = gaudi_add_device_attr,
9440 .handle_eqe = gaudi_handle_eqe,
9441 .set_pll_profile = gaudi_set_pll_profile,
9442 .get_events_stat = gaudi_get_events_stat,
9443 .read_pte = gaudi_read_pte,
9444 .write_pte = gaudi_write_pte,
9445 .mmu_invalidate_cache = gaudi_mmu_invalidate_cache,
9446 .mmu_invalidate_cache_range = gaudi_mmu_invalidate_cache_range,
9447 .send_heartbeat = gaudi_send_heartbeat,
9448 .set_clock_gating = gaudi_set_clock_gating,
9449 .disable_clock_gating = gaudi_disable_clock_gating,
9450 .debug_coresight = gaudi_debug_coresight,
9451 .is_device_idle = gaudi_is_device_idle,
9452 .soft_reset_late_init = gaudi_soft_reset_late_init,
9453 .hw_queues_lock = gaudi_hw_queues_lock,
9454 .hw_queues_unlock = gaudi_hw_queues_unlock,
9455 .get_pci_id = gaudi_get_pci_id,
9456 .get_eeprom_data = gaudi_get_eeprom_data,
9457 .send_cpu_message = gaudi_send_cpu_message,
9458 .pci_bars_map = gaudi_pci_bars_map,
9459 .init_iatu = gaudi_init_iatu,
9462 .halt_coresight = gaudi_halt_coresight,
9463 .ctx_init = gaudi_ctx_init,
9464 .ctx_fini = gaudi_ctx_fini,
9465 .get_clk_rate = gaudi_get_clk_rate,
9466 .get_queue_id_for_cq = gaudi_get_queue_id_for_cq,
9467 .load_firmware_to_device = gaudi_load_firmware_to_device,
9468 .load_boot_fit_to_device = gaudi_load_boot_fit_to_device,
9469 .get_signal_cb_size = gaudi_get_signal_cb_size,
9470 .get_wait_cb_size = gaudi_get_wait_cb_size,
9471 .gen_signal_cb = gaudi_gen_signal_cb,
9472 .gen_wait_cb = gaudi_gen_wait_cb,
9473 .reset_sob = gaudi_reset_sob,
9474 .reset_sob_group = gaudi_reset_sob_group,
9475 .set_dma_mask_from_fw = gaudi_set_dma_mask_from_fw,
9476 .get_device_time = gaudi_get_device_time,
9477 .collective_wait_init_cs = gaudi_collective_wait_init_cs,
9478 .collective_wait_create_jobs = gaudi_collective_wait_create_jobs,
9479 .scramble_addr = hl_mmu_scramble_addr,
9480 .descramble_addr = hl_mmu_descramble_addr,
9481 .ack_protection_bits_errors = gaudi_ack_protection_bits_errors,
9482 .get_hw_block_id = gaudi_get_hw_block_id,
9483 .hw_block_mmap = gaudi_block_mmap,
9484 .enable_events_from_fw = gaudi_enable_events_from_fw,
9485 .map_pll_idx_to_fw_idx = gaudi_map_pll_idx_to_fw_idx,
9486 .init_firmware_loader = gaudi_init_firmware_loader,
9487 .init_cpu_scrambler_dram = gaudi_init_scrambler_hbm,
9488 .state_dump_init = gaudi_state_dump_init,
9489 .get_sob_addr = gaudi_get_sob_addr,
9490 .set_pci_memory_regions = gaudi_set_pci_memory_regions,
9491 .get_stream_master_qid_arr = gaudi_get_stream_master_qid_arr
9495 * gaudi_set_asic_funcs - set GAUDI function pointers
9497 * @hdev: pointer to hl_device structure
9500 void gaudi_set_asic_funcs(struct hl_device *hdev)
9502 hdev->asic_funcs = &gaudi_funcs;