drivers/memory/tegra/tegra186.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2017-2021 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/io.h>
   7 #include <linux/iommu.h>
   8 #include <linux/module.h>
   9 #include <linux/mod_devicetable.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12
  13 #include <soc/tegra/mc.h>
  14
  15 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
  16 #include <dt-bindings/memory/tegra186-mc.h>
  17 #endif
  18
  19 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
  20 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
  21 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
  22
  23 static void tegra186_mc_program_sid(struct tegra_mc *mc)
  24 {
  25         unsigned int i;
  26
  27         for (i = 0; i < mc->soc->num_clients; i++) {
  28                 const struct tegra_mc_client *client = &mc->soc->clients[i];
  29                 u32 override, security;
  30
  31                 override = readl(mc->regs + client->regs.sid.override);
  32                 security = readl(mc->regs + client->regs.sid.security);
  33
  34                 dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
  35                         client->name, override, security);
  36
  37                 dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid,
  38                         client->name);
  39                 writel(client->sid, mc->regs + client->regs.sid.override);
  40
  41                 override = readl(mc->regs + client->regs.sid.override);
  42                 security = readl(mc->regs + client->regs.sid.security);
  43
  44                 dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
  45                         client->name, override, security);
  46         }
  47 }
  48
  49 static int tegra186_mc_probe(struct tegra_mc *mc)
  50 {
  51         int err;
  52
  53         err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
  54         if (err < 0)
  55                 return err;
  56
  57         tegra186_mc_program_sid(mc);
  58
  59         return 0;
  60 }
  61
  62 static void tegra186_mc_remove(struct tegra_mc *mc)
  63 {
  64         of_platform_depopulate(mc->dev);
  65 }
  66
  67 static int tegra186_mc_resume(struct tegra_mc *mc)
  68 {
  69         tegra186_mc_program_sid(mc);
  70
  71         return 0;
  72 }
  73
  74 #if IS_ENABLED(CONFIG_IOMMU_API)
  75 static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
  76                                             const struct tegra_mc_client *client,
  77                                             unsigned int sid)
  78 {
  79         u32 value, old;
  80
  81         value = readl(mc->regs + client->regs.sid.security);
  82         if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
  83                 /*
  84                  * If the secure firmware has locked this down the override
  85                  * for this memory client, there's nothing we can do here.
  86                  */
  87                 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
  88                         return;
  89
  90                 /*
  91                  * Otherwise, try to set the override itself. Typically the
  92                  * secure firmware will never have set this configuration.
  93                  * Instead, it will either have disabled write access to
  94                  * this field, or it will already have set an explicit
  95                  * override itself.
  96                  */
  97                 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
  98
  99                 value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
 100                 writel(value, mc->regs + client->regs.sid.security);
 101         }
 102
 103         value = readl(mc->regs + client->regs.sid.override);
 104         old = value & MC_SID_STREAMID_OVERRIDE_MASK;
 105
 106         if (old != sid) {
 107                 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
 108                         client->name, sid);
 109                 writel(sid, mc->regs + client->regs.sid.override);
 110         }
 111 }
 112 #endif
 113
 114 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
 115 {
 116 #if IS_ENABLED(CONFIG_IOMMU_API)
 117         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 118         struct of_phandle_args args;
 119         unsigned int i, index = 0;
 120
 121         while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
 122                                            index, &args)) {
 123                 if (args.np == mc->dev->of_node && args.args_count != 0) {
 124                         for (i = 0; i < mc->soc->num_clients; i++) {
 125                                 const struct tegra_mc_client *client = &mc->soc->clients[i];
 126
 127                                 if (client->id == args.args[0]) {
 128                                         u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
 129
 130                                         tegra186_mc_client_sid_override(mc, client, sid);
 131                                 }
 132                         }
 133                 }
 134
 135                 index++;
 136         }
 137 #endif
 138
 139         return 0;
 140 }
 141
 142 const struct tegra_mc_ops tegra186_mc_ops = {
 143         .probe = tegra186_mc_probe,
 144         .remove = tegra186_mc_remove,
 145         .resume = tegra186_mc_resume,
 146         .probe_device = tegra186_mc_probe_device,
 147 };
 148
 149 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
 150 static const struct tegra_mc_client tegra186_mc_clients[] = {
 151         {
 152                 .id = TEGRA186_MEMORY_CLIENT_PTCR,
 153                 .name = "ptcr",
 154                 .sid = TEGRA186_SID_PASSTHROUGH,
 155                 .regs = {
 156                         .sid = {
 157                                 .override = 0x000,
 158                                 .security = 0x004,
 159                         },
 160                 },
 161         }, {
 162                 .id = TEGRA186_MEMORY_CLIENT_AFIR,
 163                 .name = "afir",
 164                 .sid = TEGRA186_SID_AFI,
 165                 .regs = {
 166                         .sid = {
 167                                 .override = 0x070,
 168                                 .security = 0x074,
 169                         },
 170                 },
 171         }, {
 172                 .id = TEGRA186_MEMORY_CLIENT_HDAR,
 173                 .name = "hdar",
 174                 .sid = TEGRA186_SID_HDA,
 175                 .regs = {
 176                         .sid = {
 177                                 .override = 0x0a8,
 178                                 .security = 0x0ac,
 179                         },
 180                 },
 181         }, {
 182                 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
 183                 .name = "host1xdmar",
 184                 .sid = TEGRA186_SID_HOST1X,
 185                 .regs = {
 186                         .sid = {
 187                                 .override = 0x0b0,
 188                                 .security = 0x0b4,
 189                         },
 190                 },
 191         }, {
 192                 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
 193                 .name = "nvencsrd",
 194                 .sid = TEGRA186_SID_NVENC,
 195                 .regs = {
 196                         .sid = {
 197                                 .override = 0x0e0,
 198                                 .security = 0x0e4,
 199                         },
 200                 },
 201         }, {
 202                 .id = TEGRA186_MEMORY_CLIENT_SATAR,
 203                 .name = "satar",
 204                 .sid = TEGRA186_SID_SATA,
 205                 .regs = {
 206                         .sid = {
 207                                 .override = 0x0f8,
 208                                 .security = 0x0fc,
 209                         },
 210                 },
 211         }, {
 212                 .id = TEGRA186_MEMORY_CLIENT_MPCORER,
 213                 .name = "mpcorer",
 214                 .sid = TEGRA186_SID_PASSTHROUGH,
 215                 .regs = {
 216                         .sid = {
 217                                 .override = 0x138,
 218                                 .security = 0x13c,
 219                         },
 220                 },
 221         }, {
 222                 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
 223                 .name = "nvencswr",
 224                 .sid = TEGRA186_SID_NVENC,
 225                 .regs = {
 226                         .sid = {
 227                                 .override = 0x158,
 228                                 .security = 0x15c,
 229                         },
 230                 },
 231         }, {
 232                 .id = TEGRA186_MEMORY_CLIENT_AFIW,
 233                 .name = "afiw",
 234                 .sid = TEGRA186_SID_AFI,
 235                 .regs = {
 236                         .sid = {
 237                                 .override = 0x188,
 238                                 .security = 0x18c,
 239                         },
 240                 },
 241         }, {
 242                 .id = TEGRA186_MEMORY_CLIENT_HDAW,
 243                 .name = "hdaw",
 244                 .sid = TEGRA186_SID_HDA,
 245                 .regs = {
 246                         .sid = {
 247                                 .override = 0x1a8,
 248                                 .security = 0x1ac,
 249                         },
 250                 },
 251         }, {
 252                 .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
 253                 .name = "mpcorew",
 254                 .sid = TEGRA186_SID_PASSTHROUGH,
 255                 .regs = {
 256                         .sid = {
 257                                 .override = 0x1c8,
 258                                 .security = 0x1cc,
 259                         },
 260                 },
 261         }, {
 262                 .id = TEGRA186_MEMORY_CLIENT_SATAW,
 263                 .name = "sataw",
 264                 .sid = TEGRA186_SID_SATA,
 265                 .regs = {
 266                         .sid = {
 267                                 .override = 0x1e8,
 268                                 .security = 0x1ec,
 269                         },
 270                 },
 271         }, {
 272                 .id = TEGRA186_MEMORY_CLIENT_ISPRA,
 273                 .name = "ispra",
 274                 .sid = TEGRA186_SID_ISP,
 275                 .regs = {
 276                         .sid = {
 277                                 .override = 0x220,
 278                                 .security = 0x224,
 279                         },
 280                 },
 281         }, {
 282                 .id = TEGRA186_MEMORY_CLIENT_ISPWA,
 283                 .name = "ispwa",
 284                 .sid = TEGRA186_SID_ISP,
 285                 .regs = {
 286                         .sid = {
 287                                 .override = 0x230,
 288                                 .security = 0x234,
 289                         },
 290                 },
 291         }, {
 292                 .id = TEGRA186_MEMORY_CLIENT_ISPWB,
 293                 .name = "ispwb",
 294                 .sid = TEGRA186_SID_ISP,
 295                 .regs = {
 296                         .sid = {
 297                                 .override = 0x238,
 298                                 .security = 0x23c,
 299                         },
 300                 },
 301         }, {
 302                 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
 303                 .name = "xusb_hostr",
 304                 .sid = TEGRA186_SID_XUSB_HOST,
 305                 .regs = {
 306                         .sid = {
 307                                 .override = 0x250,
 308                                 .security = 0x254,
 309                         },
 310                 },
 311         }, {
 312                 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
 313                 .name = "xusb_hostw",
 314                 .sid = TEGRA186_SID_XUSB_HOST,
 315                 .regs = {
 316                         .sid = {
 317                                 .override = 0x258,
 318                                 .security = 0x25c,
 319                         },
 320                 },
 321         }, {
 322                 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
 323                 .name = "xusb_devr",
 324                 .sid = TEGRA186_SID_XUSB_DEV,
 325                 .regs = {
 326                         .sid = {
 327                                 .override = 0x260,
 328                                 .security = 0x264,
 329                         },
 330                 },
 331         }, {
 332                 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
 333                 .name = "xusb_devw",
 334                 .sid = TEGRA186_SID_XUSB_DEV,
 335                 .regs = {
 336                         .sid = {
 337                                 .override = 0x268,
 338                                 .security = 0x26c,
 339                         },
 340                 },
 341         }, {
 342                 .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
 343                 .name = "tsecsrd",
 344                 .sid = TEGRA186_SID_TSEC,
 345                 .regs = {
 346                         .sid = {
 347                                 .override = 0x2a0,
 348                                 .security = 0x2a4,
 349                         },
 350                 },
 351         }, {
 352                 .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
 353                 .name = "tsecswr",
 354                 .sid = TEGRA186_SID_TSEC,
 355                 .regs = {
 356                         .sid = {
 357                                 .override = 0x2a8,
 358                                 .security = 0x2ac,
 359                         },
 360                 },
 361         }, {
 362                 .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
 363                 .name = "gpusrd",
 364                 .sid = TEGRA186_SID_GPU,
 365                 .regs = {
 366                         .sid = {
 367                                 .override = 0x2c0,
 368                                 .security = 0x2c4,
 369                         },
 370                 },
 371         }, {
 372                 .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
 373                 .name = "gpuswr",
 374                 .sid = TEGRA186_SID_GPU,
 375                 .regs = {
 376                         .sid = {
 377                                 .override = 0x2c8,
 378                                 .security = 0x2cc,
 379                         },
 380                 },
 381         }, {
 382                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
 383                 .name = "sdmmcra",
 384                 .sid = TEGRA186_SID_SDMMC1,
 385                 .regs = {
 386                         .sid = {
 387                                 .override = 0x300,
 388                                 .security = 0x304,
 389                         },
 390                 },
 391         }, {
 392                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
 393                 .name = "sdmmcraa",
 394                 .sid = TEGRA186_SID_SDMMC2,
 395                 .regs = {
 396                         .sid = {
 397                                 .override = 0x308,
 398                                 .security = 0x30c,
 399                         },
 400                 },
 401         }, {
 402                 .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
 403                 .name = "sdmmcr",
 404                 .sid = TEGRA186_SID_SDMMC3,
 405                 .regs = {
 406                         .sid = {
 407                                 .override = 0x310,
 408                                 .security = 0x314,
 409                         },
 410                 },
 411         }, {
 412                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
 413                 .name = "sdmmcrab",
 414                 .sid = TEGRA186_SID_SDMMC4,
 415                 .regs = {
 416                         .sid = {
 417                                 .override = 0x318,
 418                                 .security = 0x31c,
 419                         },
 420                 },
 421         }, {
 422                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
 423                 .name = "sdmmcwa",
 424                 .sid = TEGRA186_SID_SDMMC1,
 425                 .regs = {
 426                         .sid = {
 427                                 .override = 0x320,
 428                                 .security = 0x324,
 429                         },
 430                 },
 431         }, {
 432                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
 433                 .name = "sdmmcwaa",
 434                 .sid = TEGRA186_SID_SDMMC2,
 435                 .regs = {
 436                         .sid = {
 437                                 .override = 0x328,
 438                                 .security = 0x32c,
 439                         },
 440                 },
 441         }, {
 442                 .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
 443                 .name = "sdmmcw",
 444                 .sid = TEGRA186_SID_SDMMC3,
 445                 .regs = {
 446                         .sid = {
 447                                 .override = 0x330,
 448                                 .security = 0x334,
 449                         },
 450                 },
 451         }, {
 452                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
 453                 .name = "sdmmcwab",
 454                 .sid = TEGRA186_SID_SDMMC4,
 455                 .regs = {
 456                         .sid = {
 457                                 .override = 0x338,
 458                                 .security = 0x33c,
 459                         },
 460                 },
 461         }, {
 462                 .id = TEGRA186_MEMORY_CLIENT_VICSRD,
 463                 .name = "vicsrd",
 464                 .sid = TEGRA186_SID_VIC,
 465                 .regs = {
 466                         .sid = {
 467                                 .override = 0x360,
 468                                 .security = 0x364,
 469                         },
 470                 },
 471         }, {
 472                 .id = TEGRA186_MEMORY_CLIENT_VICSWR,
 473                 .name = "vicswr",
 474                 .sid = TEGRA186_SID_VIC,
 475                 .regs = {
 476                         .sid = {
 477                                 .override = 0x368,
 478                                 .security = 0x36c,
 479                         },
 480                 },
 481         }, {
 482                 .id = TEGRA186_MEMORY_CLIENT_VIW,
 483                 .name = "viw",
 484                 .sid = TEGRA186_SID_VI,
 485                 .regs = {
 486                         .sid = {
 487                                 .override = 0x390,
 488                                 .security = 0x394,
 489                         },
 490                 },
 491         }, {
 492                 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
 493                 .name = "nvdecsrd",
 494                 .sid = TEGRA186_SID_NVDEC,
 495                 .regs = {
 496                         .sid = {
 497                                 .override = 0x3c0,
 498                                 .security = 0x3c4,
 499                         },
 500                 },
 501         }, {
 502                 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
 503                 .name = "nvdecswr",
 504                 .sid = TEGRA186_SID_NVDEC,
 505                 .regs = {
 506                         .sid = {
 507                                 .override = 0x3c8,
 508                                 .security = 0x3cc,
 509                         },
 510                 },
 511         }, {
 512                 .id = TEGRA186_MEMORY_CLIENT_APER,
 513                 .name = "aper",
 514                 .sid = TEGRA186_SID_APE,
 515                 .regs = {
 516                         .sid = {
 517                                 .override = 0x3d0,
 518                                 .security = 0x3d4,
 519                         },
 520                 },
 521         }, {
 522                 .id = TEGRA186_MEMORY_CLIENT_APEW,
 523                 .name = "apew",
 524                 .sid = TEGRA186_SID_APE,
 525                 .regs = {
 526                         .sid = {
 527                                 .override = 0x3d8,
 528                                 .security = 0x3dc,
 529                         },
 530                 },
 531         }, {
 532                 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
 533                 .name = "nvjpgsrd",
 534                 .sid = TEGRA186_SID_NVJPG,
 535                 .regs = {
 536                         .sid = {
 537                                 .override = 0x3f0,
 538                                 .security = 0x3f4,
 539                         },
 540                 },
 541         }, {
 542                 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
 543                 .name = "nvjpgswr",
 544                 .sid = TEGRA186_SID_NVJPG,
 545                 .regs = {
 546                         .sid = {
 547                                 .override = 0x3f8,
 548                                 .security = 0x3fc,
 549                         },
 550                 },
 551         }, {
 552                 .id = TEGRA186_MEMORY_CLIENT_SESRD,
 553                 .name = "sesrd",
 554                 .sid = TEGRA186_SID_SE,
 555                 .regs = {
 556                         .sid = {
 557                                 .override = 0x400,
 558                                 .security = 0x404,
 559                         },
 560                 },
 561         }, {
 562                 .id = TEGRA186_MEMORY_CLIENT_SESWR,
 563                 .name = "seswr",
 564                 .sid = TEGRA186_SID_SE,
 565                 .regs = {
 566                         .sid = {
 567                                 .override = 0x408,
 568                                 .security = 0x40c,
 569                         },
 570                 },
 571         }, {
 572                 .id = TEGRA186_MEMORY_CLIENT_ETRR,
 573                 .name = "etrr",
 574                 .sid = TEGRA186_SID_ETR,
 575                 .regs = {
 576                         .sid = {
 577                                 .override = 0x420,
 578                                 .security = 0x424,
 579                         },
 580                 },
 581         }, {
 582                 .id = TEGRA186_MEMORY_CLIENT_ETRW,
 583                 .name = "etrw",
 584                 .sid = TEGRA186_SID_ETR,
 585                 .regs = {
 586                         .sid = {
 587                                 .override = 0x428,
 588                                 .security = 0x42c,
 589                         },
 590                 },
 591         }, {
 592                 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
 593                 .name = "tsecsrdb",
 594                 .sid = TEGRA186_SID_TSECB,
 595                 .regs = {
 596                         .sid = {
 597                                 .override = 0x430,
 598                                 .security = 0x434,
 599                         },
 600                 },
 601         }, {
 602                 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
 603                 .name = "tsecswrb",
 604                 .sid = TEGRA186_SID_TSECB,
 605                 .regs = {
 606                         .sid = {
 607                                 .override = 0x438,
 608                                 .security = 0x43c,
 609                         },
 610                 },
 611         }, {
 612                 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
 613                 .name = "gpusrd2",
 614                 .sid = TEGRA186_SID_GPU,
 615                 .regs = {
 616                         .sid = {
 617                                 .override = 0x440,
 618                                 .security = 0x444,
 619                         },
 620                 },
 621         }, {
 622                 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
 623                 .name = "gpuswr2",
 624                 .sid = TEGRA186_SID_GPU,
 625                 .regs = {
 626                         .sid = {
 627                                 .override = 0x448,
 628                                 .security = 0x44c,
 629                         },
 630                 },
 631         }, {
 632                 .id = TEGRA186_MEMORY_CLIENT_AXISR,
 633                 .name = "axisr",
 634                 .sid = TEGRA186_SID_GPCDMA_0,
 635                 .regs = {
 636                         .sid = {
 637                                 .override = 0x460,
 638                                 .security = 0x464,
 639                         },
 640                 },
 641         }, {
 642                 .id = TEGRA186_MEMORY_CLIENT_AXISW,
 643                 .name = "axisw",
 644                 .sid = TEGRA186_SID_GPCDMA_0,
 645                 .regs = {
 646                         .sid = {
 647                                 .override = 0x468,
 648                                 .security = 0x46c,
 649                         },
 650                 },
 651         }, {
 652                 .id = TEGRA186_MEMORY_CLIENT_EQOSR,
 653                 .name = "eqosr",
 654                 .sid = TEGRA186_SID_EQOS,
 655                 .regs = {
 656                         .sid = {
 657                                 .override = 0x470,
 658                                 .security = 0x474,
 659                         },
 660                 },
 661         }, {
 662                 .id = TEGRA186_MEMORY_CLIENT_EQOSW,
 663                 .name = "eqosw",
 664                 .sid = TEGRA186_SID_EQOS,
 665                 .regs = {
 666                         .sid = {
 667                                 .override = 0x478,
 668                                 .security = 0x47c,
 669                         },
 670                 },
 671         }, {
 672                 .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
 673                 .name = "ufshcr",
 674                 .sid = TEGRA186_SID_UFSHC,
 675                 .regs = {
 676                         .sid = {
 677                                 .override = 0x480,
 678                                 .security = 0x484,
 679                         },
 680                 },
 681         }, {
 682                 .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
 683                 .name = "ufshcw",
 684                 .sid = TEGRA186_SID_UFSHC,
 685                 .regs = {
 686                         .sid = {
 687                                 .override = 0x488,
 688                                 .security = 0x48c,
 689                         },
 690                 },
 691         }, {
 692                 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
 693                 .name = "nvdisplayr",
 694                 .sid = TEGRA186_SID_NVDISPLAY,
 695                 .regs = {
 696                         .sid = {
 697                                 .override = 0x490,
 698                                 .security = 0x494,
 699                         },
 700                 },
 701         }, {
 702                 .id = TEGRA186_MEMORY_CLIENT_BPMPR,
 703                 .name = "bpmpr",
 704                 .sid = TEGRA186_SID_BPMP,
 705                 .regs = {
 706                         .sid = {
 707                                 .override = 0x498,
 708                                 .security = 0x49c,
 709                         },
 710                 },
 711         }, {
 712                 .id = TEGRA186_MEMORY_CLIENT_BPMPW,
 713                 .name = "bpmpw",
 714                 .sid = TEGRA186_SID_BPMP,
 715                 .regs = {
 716                         .sid = {
 717                                 .override = 0x4a0,
 718                                 .security = 0x4a4,
 719                         },
 720                 },
 721         }, {
 722                 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
 723                 .name = "bpmpdmar",
 724                 .sid = TEGRA186_SID_BPMP,
 725                 .regs = {
 726                         .sid = {
 727                                 .override = 0x4a8,
 728                                 .security = 0x4ac,
 729                         },
 730                 },
 731         }, {
 732                 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
 733                 .name = "bpmpdmaw",
 734                 .sid = TEGRA186_SID_BPMP,
 735                 .regs = {
 736                         .sid = {
 737                                 .override = 0x4b0,
 738                                 .security = 0x4b4,
 739                         },
 740                 },
 741         }, {
 742                 .id = TEGRA186_MEMORY_CLIENT_AONR,
 743                 .name = "aonr",
 744                 .sid = TEGRA186_SID_AON,
 745                 .regs = {
 746                         .sid = {
 747                                 .override = 0x4b8,
 748                                 .security = 0x4bc,
 749                         },
 750                 },
 751         }, {
 752                 .id = TEGRA186_MEMORY_CLIENT_AONW,
 753                 .name = "aonw",
 754                 .sid = TEGRA186_SID_AON,
 755                 .regs = {
 756                         .sid = {
 757                                 .override = 0x4c0,
 758                                 .security = 0x4c4,
 759                         },
 760                 },
 761         }, {
 762                 .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
 763                 .name = "aondmar",
 764                 .sid = TEGRA186_SID_AON,
 765                 .regs = {
 766                         .sid = {
 767                                 .override = 0x4c8,
 768                                 .security = 0x4cc,
 769                         },
 770                 },
 771         }, {
 772                 .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
 773                 .name = "aondmaw",
 774                 .sid = TEGRA186_SID_AON,
 775                 .regs = {
 776                         .sid = {
 777                                 .override = 0x4d0,
 778                                 .security = 0x4d4,
 779                         },
 780                 },
 781         }, {
 782                 .id = TEGRA186_MEMORY_CLIENT_SCER,
 783                 .name = "scer",
 784                 .sid = TEGRA186_SID_SCE,
 785                 .regs = {
 786                         .sid = {
 787                                 .override = 0x4d8,
 788                                 .security = 0x4dc,
 789                         },
 790                 },
 791         }, {
 792                 .id = TEGRA186_MEMORY_CLIENT_SCEW,
 793                 .name = "scew",
 794                 .sid = TEGRA186_SID_SCE,
 795                 .regs = {
 796                         .sid = {
 797                                 .override = 0x4e0,
 798                                 .security = 0x4e4,
 799                         },
 800                 },
 801         }, {
 802                 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
 803                 .name = "scedmar",
 804                 .sid = TEGRA186_SID_SCE,
 805                 .regs = {
 806                         .sid = {
 807                                 .override = 0x4e8,
 808                                 .security = 0x4ec,
 809                         },
 810                 },
 811         }, {
 812                 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
 813                 .name = "scedmaw",
 814                 .sid = TEGRA186_SID_SCE,
 815                 .regs = {
 816                         .sid = {
 817                                 .override = 0x4f0,
 818                                 .security = 0x4f4,
 819                         },
 820                 },
 821         }, {
 822                 .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
 823                 .name = "apedmar",
 824                 .sid = TEGRA186_SID_APE,
 825                 .regs = {
 826                         .sid = {
 827                                 .override = 0x4f8,
 828                                 .security = 0x4fc,
 829                         },
 830                 },
 831         }, {
 832                 .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
 833                 .name = "apedmaw",
 834                 .sid = TEGRA186_SID_APE,
 835                 .regs = {
 836                         .sid = {
 837                                 .override = 0x500,
 838                                 .security = 0x504,
 839                         },
 840                 },
 841         }, {
 842                 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
 843                 .name = "nvdisplayr1",
 844                 .sid = TEGRA186_SID_NVDISPLAY,
 845                 .regs = {
 846                         .sid = {
 847                                 .override = 0x508,
 848                                 .security = 0x50c,
 849                         },
 850                 },
 851         }, {
 852                 .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
 853                 .name = "vicsrd1",
 854                 .sid = TEGRA186_SID_VIC,
 855                 .regs = {
 856                         .sid = {
 857                                 .override = 0x510,
 858                                 .security = 0x514,
 859                         },
 860                 },
 861         }, {
 862                 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
 863                 .name = "nvdecsrd1",
 864                 .sid = TEGRA186_SID_NVDEC,
 865                 .regs = {
 866                         .sid = {
 867                                 .override = 0x518,
 868                                 .security = 0x51c,
 869                         },
 870                 },
 871         },
 872 };
 873
 874 const struct tegra_mc_soc tegra186_mc_soc = {
 875         .num_clients = ARRAY_SIZE(tegra186_mc_clients),
 876         .clients = tegra186_mc_clients,
 877         .num_address_bits = 40,
 878         .ops = &tegra186_mc_ops,
 879 };
 880 #endif