drivers/memory/omap-gpmc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * GPMC support functions
   4  *
   5  * Copyright (C) 2005-2006 Nokia Corporation
   6  *
   7  * Author: Juha Yrjola
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  */
  12 #include <linux/irq.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/ioport.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/io.h>
  20 #include <linux/gpio/driver.h>
  21 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
  22 #include <linux/gpio/machine.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irqdomain.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_device.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/omap-gpmc.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/sizes.h>
  33
  34 #include <linux/platform_data/mtd-nand-omap2.h>
  35
  36 #define DEVICE_NAME             "omap-gpmc"
  37
  38 /* GPMC register offsets */
  39 #define GPMC_REVISION           0x00
  40 #define GPMC_SYSCONFIG          0x10
  41 #define GPMC_SYSSTATUS          0x14
  42 #define GPMC_IRQSTATUS          0x18
  43 #define GPMC_IRQENABLE          0x1c
  44 #define GPMC_TIMEOUT_CONTROL    0x40
  45 #define GPMC_ERR_ADDRESS        0x44
  46 #define GPMC_ERR_TYPE           0x48
  47 #define GPMC_CONFIG             0x50
  48 #define GPMC_STATUS             0x54
  49 #define GPMC_PREFETCH_CONFIG1   0x1e0
  50 #define GPMC_PREFETCH_CONFIG2   0x1e4
  51 #define GPMC_PREFETCH_CONTROL   0x1ec
  52 #define GPMC_PREFETCH_STATUS    0x1f0
  53 #define GPMC_ECC_CONFIG         0x1f4
  54 #define GPMC_ECC_CONTROL        0x1f8
  55 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  56 #define GPMC_ECC1_RESULT        0x200
  57 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  58 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  59 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  60 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  61 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  64
  65 /* GPMC ECC control settings */
  66 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  67 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  68 #define GPMC_ECC_CTRL_ECCREG1           0x001
  69 #define GPMC_ECC_CTRL_ECCREG2           0x002
  70 #define GPMC_ECC_CTRL_ECCREG3           0x003
  71 #define GPMC_ECC_CTRL_ECCREG4           0x004
  72 #define GPMC_ECC_CTRL_ECCREG5           0x005
  73 #define GPMC_ECC_CTRL_ECCREG6           0x006
  74 #define GPMC_ECC_CTRL_ECCREG7           0x007
  75 #define GPMC_ECC_CTRL_ECCREG8           0x008
  76 #define GPMC_ECC_CTRL_ECCREG9           0x009
  77
  78 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  79
  80 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  81
  82 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  83 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  84 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  86 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  87 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  88
  89 #define GPMC_CS0_OFFSET         0x60
  90 #define GPMC_CS_SIZE            0x30
  91 #define GPMC_BCH_SIZE           0x10
  92
  93 /*
  94  * The first 1MB of GPMC address space is typically mapped to
  95  * the internal ROM. Never allocate the first page, to
  96  * facilitate bug detection; even if we didn't boot from ROM.
  97  * As GPMC minimum partition size is 16MB we can only start from
  98  * there.
  99  */
 100 #define GPMC_MEM_START          0x1000000
 101 #define GPMC_MEM_END            0x3FFFFFFF
 102
 103 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 104 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 105
 106 #define CS_NUM_SHIFT            24
 107 #define ENABLE_PREFETCH         (0x1 << 7)
 108 #define DMA_MPU_MODE            2
 109
 110 #define GPMC_REVISION_MAJOR(l)          (((l) >> 4) & 0xf)
 111 #define GPMC_REVISION_MINOR(l)          ((l) & 0xf)
 112
 113 #define GPMC_HAS_WR_ACCESS              0x1
 114 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 115 #define GPMC_HAS_MUX_AAD                0x4
 116
 117 #define GPMC_NR_WAITPINS                4
 118
 119 #define GPMC_CS_CONFIG1         0x00
 120 #define GPMC_CS_CONFIG2         0x04
 121 #define GPMC_CS_CONFIG3         0x08
 122 #define GPMC_CS_CONFIG4         0x0c
 123 #define GPMC_CS_CONFIG5         0x10
 124 #define GPMC_CS_CONFIG6         0x14
 125 #define GPMC_CS_CONFIG7         0x18
 126 #define GPMC_CS_NAND_COMMAND    0x1c
 127 #define GPMC_CS_NAND_ADDRESS    0x20
 128 #define GPMC_CS_NAND_DATA       0x24
 129
 130 /* Control Commands */
 131 #define GPMC_CONFIG_RDY_BSY     0x00000001
 132 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 133 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 134
 135 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 136 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 137 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 138 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 139 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 140 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 141 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 142 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
 143 /** CLKACTIVATIONTIME Max Ticks */
 144 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 145 #define GPMC_CONFIG1_PAGE_LEN(val)      (((val) & 3) << 23)
 146 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 147 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 148 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 149 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 150 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
 151 /** WAITMONITORINGTIME Max Ticks */
 152 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 153 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  (((val) & 3) << 16)
 154 #define GPMC_CONFIG1_DEVICESIZE(val)    (((val) & 3) << 12)
 155 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 156 /** DEVICESIZE Max Value */
 157 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 158 #define GPMC_CONFIG1_DEVICETYPE(val)    (((val) & 3) << 10)
 159 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 160 #define GPMC_CONFIG1_MUXTYPE(val)       (((val) & 3) << 8)
 161 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 162 #define GPMC_CONFIG1_FCLK_DIV(val)      ((val) & 3)
 163 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 164 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 165 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 166 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 167
 168 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 169 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 170 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 171 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 172 /* All CONFIG7 bits except reserved bits */
 173 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 174                                          GPMC_CONFIG7_CSVALID_MASK |     \
 175                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 176
 177 #define GPMC_DEVICETYPE_NOR             0
 178 #define GPMC_DEVICETYPE_NAND            2
 179 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 180 #define WR_RD_PIN_MONITORING            0x00600000
 181
 182 /* ECC commands */
 183 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 184 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 185 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 186
 187 #define GPMC_NR_NAND_IRQS       2 /* number of NAND specific IRQs */
 188
 189 enum gpmc_clk_domain {
 190         GPMC_CD_FCLK,
 191         GPMC_CD_CLK
 192 };
 193
 194 struct gpmc_cs_data {
 195         const char *name;
 196
 197 #define GPMC_CS_RESERVED        (1 << 0)
 198         u32 flags;
 199
 200         struct resource mem;
 201 };
 202
 203 /* Structure to save gpmc cs context */
 204 struct gpmc_cs_config {
 205         u32 config1;
 206         u32 config2;
 207         u32 config3;
 208         u32 config4;
 209         u32 config5;
 210         u32 config6;
 211         u32 config7;
 212         int is_valid;
 213 };
 214
 215 /*
 216  * Structure to save/restore gpmc context
 217  * to support core off on OMAP3
 218  */
 219 struct omap3_gpmc_regs {
 220         u32 sysconfig;
 221         u32 irqenable;
 222         u32 timeout_ctrl;
 223         u32 config;
 224         u32 prefetch_config1;
 225         u32 prefetch_config2;
 226         u32 prefetch_control;
 227         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 228 };
 229
 230 struct gpmc_device {
 231         struct device *dev;
 232         int irq;
 233         struct irq_chip irq_chip;
 234         struct gpio_chip gpio_chip;
 235         int nirqs;
 236 };
 237
 238 static struct irq_domain *gpmc_irq_domain;
 239
 240 static struct resource  gpmc_mem_root;
 241 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 242 static DEFINE_SPINLOCK(gpmc_mem_lock);
 243 /* Define chip-selects as reserved by default until probe completes */
 244 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 245 static unsigned int gpmc_nr_waitpins;
 246 static unsigned int gpmc_capability;
 247 static void __iomem *gpmc_base;
 248
 249 static struct clk *gpmc_l3_clk;
 250
 251 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 252
 253 static void gpmc_write_reg(int idx, u32 val)
 254 {
 255         writel_relaxed(val, gpmc_base + idx);
 256 }
 257
 258 static u32 gpmc_read_reg(int idx)
 259 {
 260         return readl_relaxed(gpmc_base + idx);
 261 }
 262
 263 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 264 {
 265         void __iomem *reg_addr;
 266
 267         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 268         writel_relaxed(val, reg_addr);
 269 }
 270
 271 static u32 gpmc_cs_read_reg(int cs, int idx)
 272 {
 273         void __iomem *reg_addr;
 274
 275         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 276         return readl_relaxed(reg_addr);
 277 }
 278
 279 /* TODO: Add support for gpmc_fck to clock framework and use it */
 280 static unsigned long gpmc_get_fclk_period(void)
 281 {
 282         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 283
 284         rate /= 1000;
 285         rate = 1000000000 / rate;       /* In picoseconds */
 286
 287         return rate;
 288 }
 289
 290 /**
 291  * gpmc_get_clk_period - get period of selected clock domain in ps
 292  * @cs: Chip Select Region.
 293  * @cd: Clock Domain.
 294  *
 295  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 296  * prior to calling this function with GPMC_CD_CLK.
 297  */
 298 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 299 {
 300         unsigned long tick_ps = gpmc_get_fclk_period();
 301         u32 l;
 302         int div;
 303
 304         switch (cd) {
 305         case GPMC_CD_CLK:
 306                 /* get current clk divider */
 307                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 308                 div = (l & 0x03) + 1;
 309                 /* get GPMC_CLK period */
 310                 tick_ps *= div;
 311                 break;
 312         case GPMC_CD_FCLK:
 313         default:
 314                 break;
 315         }
 316
 317         return tick_ps;
 318 }
 319
 320 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 321                                          enum gpmc_clk_domain cd)
 322 {
 323         unsigned long tick_ps;
 324
 325         /* Calculate in picosecs to yield more exact results */
 326         tick_ps = gpmc_get_clk_period(cs, cd);
 327
 328         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 329 }
 330
 331 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 332 {
 333         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 334 }
 335
 336 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 337 {
 338         unsigned long tick_ps;
 339
 340         /* Calculate in picosecs to yield more exact results */
 341         tick_ps = gpmc_get_fclk_period();
 342
 343         return (time_ps + tick_ps - 1) / tick_ps;
 344 }
 345
 346 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
 347                                          enum gpmc_clk_domain cd)
 348 {
 349         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 350 }
 351
 352 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 353 {
 354         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 355 }
 356
 357 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 358 {
 359         return ticks * gpmc_get_fclk_period();
 360 }
 361
 362 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 363 {
 364         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 365
 366         return ticks * gpmc_get_fclk_period();
 367 }
 368
 369 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 370 {
 371         u32 l;
 372
 373         l = gpmc_cs_read_reg(cs, reg);
 374         if (value)
 375                 l |= mask;
 376         else
 377                 l &= ~mask;
 378         gpmc_cs_write_reg(cs, reg, l);
 379 }
 380
 381 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 382 {
 383         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 384                            GPMC_CONFIG1_TIME_PARA_GRAN,
 385                            p->time_para_granularity);
 386         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 387                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 388         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 389                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 390         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 391                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 392         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 393                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 394         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 395                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 396                            p->cycle2cyclesamecsen);
 397         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 398                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 399                            p->cycle2cyclediffcsen);
 400 }
 401
 402 #ifdef CONFIG_OMAP_GPMC_DEBUG
 403 /**
 404  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 405  * @cs:      Chip Select Region
 406  * @reg:     GPMC_CS_CONFIGn register offset.
 407  * @st_bit:  Start Bit
 408  * @end_bit: End Bit. Must be >= @st_bit.
 409  * @max:     Maximum parameter value (before optional @shift).
 410  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 411  * @name:    DTS node name, w/o "gpmc,"
 412  * @cd:      Clock Domain of timing parameter.
 413  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 414  * @raw:     Raw Format Option.
 415  *           raw format:  gpmc,name = <value>
 416  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 417  *           Where x ns -- y ns result in the same tick value.
 418  *           When @max is exceeded, "invalid" is printed inside comment.
 419  * @noval:   Parameter values equal to 0 are not printed.
 420  * @return:  Specified timing parameter (after optional @shift).
 421  *
 422  */
 423 static int get_gpmc_timing_reg(
 424         /* timing specifiers */
 425         int cs, int reg, int st_bit, int end_bit, int max,
 426         const char *name, const enum gpmc_clk_domain cd,
 427         /* value transform */
 428         int shift,
 429         /* format specifiers */
 430         bool raw, bool noval)
 431 {
 432         u32 l;
 433         int nr_bits;
 434         int mask;
 435         bool invalid;
 436
 437         l = gpmc_cs_read_reg(cs, reg);
 438         nr_bits = end_bit - st_bit + 1;
 439         mask = (1 << nr_bits) - 1;
 440         l = (l >> st_bit) & mask;
 441         if (!max)
 442                 max = mask;
 443         invalid = l > max;
 444         if (shift)
 445                 l = (shift << l);
 446         if (noval && (l == 0))
 447                 return 0;
 448         if (!raw) {
 449                 /* DTS tick format for timings in ns */
 450                 unsigned int time_ns;
 451                 unsigned int time_ns_min = 0;
 452
 453                 if (l)
 454                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 455                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 456                 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
 457                         name, time_ns, time_ns_min, time_ns, l,
 458                         invalid ? "; invalid " : " ");
 459         } else {
 460                 /* raw format */
 461                 pr_info("gpmc,%s = <%u>;%s\n", name, l,
 462                         invalid ? " /* invalid */" : "");
 463         }
 464
 465         return l;
 466 }
 467
 468 #define GPMC_PRINT_CONFIG(cs, config) \
 469         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 470                 gpmc_cs_read_reg(cs, config))
 471 #define GPMC_GET_RAW(reg, st, end, field) \
 472         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 473 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 474         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 475 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 476         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 477 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 478         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 479 #define GPMC_GET_TICKS(reg, st, end, field) \
 480         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 481 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 482         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 483 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 484         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 485
 486 static void gpmc_show_regs(int cs, const char *desc)
 487 {
 488         pr_info("gpmc cs%i %s:\n", cs, desc);
 489         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 490         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 491         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 492         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 493         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 494         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 495 }
 496
 497 /*
 498  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 499  * see commit c9fb809.
 500  */
 501 static void gpmc_cs_show_timings(int cs, const char *desc)
 502 {
 503         gpmc_show_regs(cs, desc);
 504
 505         pr_info("gpmc cs%i access configuration:\n", cs);
 506         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 507         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 508         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
 509                                GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 510         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 511         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 512         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 513         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 514                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 515                                "burst-length");
 516         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 517         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 518         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 519         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 520         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 521
 522         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 523
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 525
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 527         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 528
 529         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 531
 532         pr_info("gpmc cs%i timings configuration:\n", cs);
 533         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 534         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 535         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 536
 537         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 538         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 539         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 540         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 541                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 542                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 543                                 "adv-aad-mux-rd-off-ns");
 544                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 545                                 "adv-aad-mux-wr-off-ns");
 546         }
 547
 548         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 549         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 550         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 551                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 552                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 553         }
 554         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 555         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 556
 557         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 558         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 559         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 560
 561         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 562
 563         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 564         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 565
 566         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 567                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 568                               "wait-monitoring-ns", GPMC_CD_CLK);
 569         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 570                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 571                               "clk-activation-ns", GPMC_CD_FCLK);
 572
 573         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 574         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 575 }
 576 #else
 577 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 578 {
 579 }
 580 #endif
 581
 582 /**
 583  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 584  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 585  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 586  *
 587  * @cs:      Chip Select Region.
 588  * @reg:     GPMC_CS_CONFIGn register offset.
 589  * @st_bit:  Start Bit
 590  * @end_bit: End Bit. Must be >= @st_bit.
 591  * @max:     Maximum parameter value.
 592  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 593  * @time:    Timing parameter in ns.
 594  * @cd:      Timing parameter clock domain.
 595  * @name:    Timing parameter name.
 596  * @return:  0 on success, -1 on error.
 597  */
 598 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 599                                int time, enum gpmc_clk_domain cd, const char *name)
 600 {
 601         u32 l;
 602         int ticks, mask, nr_bits;
 603
 604         if (time == 0)
 605                 ticks = 0;
 606         else
 607                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 608         nr_bits = end_bit - st_bit + 1;
 609         mask = (1 << nr_bits) - 1;
 610
 611         if (!max)
 612                 max = mask;
 613
 614         if (ticks > max) {
 615                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 616                        __func__, cs, name, time, ticks, max);
 617
 618                 return -1;
 619         }
 620
 621         l = gpmc_cs_read_reg(cs, reg);
 622 #ifdef CONFIG_OMAP_GPMC_DEBUG
 623         pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 624                 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 625                         (l >> st_bit) & mask, time);
 626 #endif
 627         l &= ~(mask << st_bit);
 628         l |= ticks << st_bit;
 629         gpmc_cs_write_reg(cs, reg, l);
 630
 631         return 0;
 632 }
 633
 634 /**
 635  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 636  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 637  * read  --> don't sample bus too early
 638  * write --> data is longer on bus
 639  *
 640  * Formula:
 641  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 642  *                    / waitmonitoring_ticks)
 643  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 644  * div <= 0 check.
 645  *
 646  * @wait_monitoring: WAITMONITORINGTIME in ns.
 647  * @return:          -1 on failure to scale, else proper divider > 0.
 648  */
 649 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 650 {
 651         int div = gpmc_ns_to_ticks(wait_monitoring);
 652
 653         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 654         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 655
 656         if (div > 4)
 657                 return -1;
 658         if (div <= 0)
 659                 div = 1;
 660
 661         return div;
 662 }
 663
 664 /**
 665  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 666  * @sync_clk: GPMC_CLK period in ps.
 667  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 668  *            Else, returns -1.
 669  */
 670 int gpmc_calc_divider(unsigned int sync_clk)
 671 {
 672         int div = gpmc_ps_to_ticks(sync_clk);
 673
 674         if (div > 4)
 675                 return -1;
 676         if (div <= 0)
 677                 div = 1;
 678
 679         return div;
 680 }
 681
 682 /**
 683  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 684  * @cs:     Chip Select Region.
 685  * @t:      GPMC timing parameters.
 686  * @s:      GPMC timing settings.
 687  * @return: 0 on success, -1 on error.
 688  */
 689 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 690                         const struct gpmc_settings *s)
 691 {
 692         int div, ret;
 693         u32 l;
 694
 695         div = gpmc_calc_divider(t->sync_clk);
 696         if (div < 0)
 697                 return -EINVAL;
 698
 699         /*
 700          * See if we need to change the divider for waitmonitoringtime.
 701          *
 702          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 703          * pure asynchronous accesses, i.e. both read and write asynchronous.
 704          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 705          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 706          *
 707          * This statement must not change div to scale async WAITMONITORINGTIME
 708          * to protect mixed synchronous and asynchronous accesses.
 709          *
 710          * We raise an error later if WAITMONITORINGTIME does not fit.
 711          */
 712         if (!s->sync_read && !s->sync_write &&
 713             (s->wait_on_read || s->wait_on_write)
 714            ) {
 715                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 716                 if (div < 0) {
 717                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 718                                __func__,
 719                                t->wait_monitoring
 720                                );
 721                         return -ENXIO;
 722                 }
 723         }
 724
 725         ret = 0;
 726         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
 727                                    GPMC_CD_FCLK, "cs_on");
 728         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
 729                                    GPMC_CD_FCLK, "cs_rd_off");
 730         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
 731                                    GPMC_CD_FCLK, "cs_wr_off");
 732         if (ret)
 733                 return -ENXIO;
 734
 735         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
 736                                    GPMC_CD_FCLK, "adv_on");
 737         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
 738                                    GPMC_CD_FCLK, "adv_rd_off");
 739         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
 740                                    GPMC_CD_FCLK, "adv_wr_off");
 741         if (ret)
 742                 return -ENXIO;
 743
 744         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 745                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
 746                                            t->adv_aad_mux_on, GPMC_CD_FCLK,
 747                                            "adv_aad_mux_on");
 748                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
 749                                            t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
 750                                            "adv_aad_mux_rd_off");
 751                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
 752                                            t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
 753                                            "adv_aad_mux_wr_off");
 754                 if (ret)
 755                         return -ENXIO;
 756         }
 757
 758         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
 759                                    GPMC_CD_FCLK, "oe_on");
 760         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
 761                                    GPMC_CD_FCLK, "oe_off");
 762         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 763                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
 764                                            t->oe_aad_mux_on, GPMC_CD_FCLK,
 765                                            "oe_aad_mux_on");
 766                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
 767                                            t->oe_aad_mux_off, GPMC_CD_FCLK,
 768                                            "oe_aad_mux_off");
 769         }
 770         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
 771                                    GPMC_CD_FCLK, "we_on");
 772         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
 773                                    GPMC_CD_FCLK, "we_off");
 774         if (ret)
 775                 return -ENXIO;
 776
 777         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
 778                                    GPMC_CD_FCLK, "rd_cycle");
 779         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
 780                                    GPMC_CD_FCLK, "wr_cycle");
 781         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
 782                                    GPMC_CD_FCLK, "access");
 783         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
 784                                    t->page_burst_access, GPMC_CD_FCLK,
 785                                    "page_burst_access");
 786         if (ret)
 787                 return -ENXIO;
 788
 789         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
 790                                    t->bus_turnaround, GPMC_CD_FCLK,
 791                                    "bus_turnaround");
 792         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
 793                                    t->cycle2cycle_delay, GPMC_CD_FCLK,
 794                                    "cycle2cycle_delay");
 795         if (ret)
 796                 return -ENXIO;
 797
 798         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
 799                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
 800                                            t->wr_data_mux_bus, GPMC_CD_FCLK,
 801                                            "wr_data_mux_bus");
 802                 if (ret)
 803                         return -ENXIO;
 804         }
 805         if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
 806                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
 807                                            t->wr_access, GPMC_CD_FCLK,
 808                                            "wr_access");
 809                 if (ret)
 810                         return -ENXIO;
 811         }
 812
 813         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 814         l &= ~0x03;
 815         l |= (div - 1);
 816         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 817
 818         ret = 0;
 819         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
 820                                    GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 821                                    t->wait_monitoring, GPMC_CD_CLK,
 822                                    "wait_monitoring");
 823         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
 824                                    GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 825                                    t->clk_activation, GPMC_CD_FCLK,
 826                                    "clk_activation");
 827         if (ret)
 828                 return -ENXIO;
 829
 830 #ifdef CONFIG_OMAP_GPMC_DEBUG
 831         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 832                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 833 #endif
 834
 835         gpmc_cs_bool_timings(cs, &t->bool_timings);
 836         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 837
 838         return 0;
 839 }
 840
 841 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 842 {
 843         u32 l;
 844         u32 mask;
 845
 846         /*
 847          * Ensure that base address is aligned on a
 848          * boundary equal to or greater than size.
 849          */
 850         if (base & (size - 1))
 851                 return -EINVAL;
 852
 853         base >>= GPMC_CHUNK_SHIFT;
 854         mask = (1 << GPMC_SECTION_SHIFT) - size;
 855         mask >>= GPMC_CHUNK_SHIFT;
 856         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 857
 858         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 859         l &= ~GPMC_CONFIG7_MASK;
 860         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 861         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 862         l |= GPMC_CONFIG7_CSVALID;
 863         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 864
 865         return 0;
 866 }
 867
 868 static void gpmc_cs_enable_mem(int cs)
 869 {
 870         u32 l;
 871
 872         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 873         l |= GPMC_CONFIG7_CSVALID;
 874         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 875 }
 876
 877 static void gpmc_cs_disable_mem(int cs)
 878 {
 879         u32 l;
 880
 881         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 882         l &= ~GPMC_CONFIG7_CSVALID;
 883         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 884 }
 885
 886 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 887 {
 888         u32 l;
 889         u32 mask;
 890
 891         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 892         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 893         mask = (l >> 8) & 0x0f;
 894         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 895 }
 896
 897 static int gpmc_cs_mem_enabled(int cs)
 898 {
 899         u32 l;
 900
 901         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 902         return l & GPMC_CONFIG7_CSVALID;
 903 }
 904
 905 static void gpmc_cs_set_reserved(int cs, int reserved)
 906 {
 907         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 908
 909         gpmc->flags |= GPMC_CS_RESERVED;
 910 }
 911
 912 static bool gpmc_cs_reserved(int cs)
 913 {
 914         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 915
 916         return gpmc->flags & GPMC_CS_RESERVED;
 917 }
 918
 919 static unsigned long gpmc_mem_align(unsigned long size)
 920 {
 921         int order;
 922
 923         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 924         order = GPMC_CHUNK_SHIFT - 1;
 925         do {
 926                 size >>= 1;
 927                 order++;
 928         } while (size);
 929         size = 1 << order;
 930         return size;
 931 }
 932
 933 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 934 {
 935         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 936         struct resource *res = &gpmc->mem;
 937         int r;
 938
 939         size = gpmc_mem_align(size);
 940         spin_lock(&gpmc_mem_lock);
 941         res->start = base;
 942         res->end = base + size - 1;
 943         r = request_resource(&gpmc_mem_root, res);
 944         spin_unlock(&gpmc_mem_lock);
 945
 946         return r;
 947 }
 948
 949 static int gpmc_cs_delete_mem(int cs)
 950 {
 951         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 952         struct resource *res = &gpmc->mem;
 953         int r;
 954
 955         spin_lock(&gpmc_mem_lock);
 956         r = release_resource(res);
 957         res->start = 0;
 958         res->end = 0;
 959         spin_unlock(&gpmc_mem_lock);
 960
 961         return r;
 962 }
 963
 964 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 965 {
 966         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 967         struct resource *res = &gpmc->mem;
 968         int r = -1;
 969
 970         if (cs >= gpmc_cs_num) {
 971                 pr_err("%s: requested chip-select is disabled\n", __func__);
 972                 return -ENODEV;
 973         }
 974         size = gpmc_mem_align(size);
 975         if (size > (1 << GPMC_SECTION_SHIFT))
 976                 return -ENOMEM;
 977
 978         spin_lock(&gpmc_mem_lock);
 979         if (gpmc_cs_reserved(cs)) {
 980                 r = -EBUSY;
 981                 goto out;
 982         }
 983         if (gpmc_cs_mem_enabled(cs))
 984                 r = adjust_resource(res, res->start & ~(size - 1), size);
 985         if (r < 0)
 986                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 987                                       size, NULL, NULL);
 988         if (r < 0)
 989                 goto out;
 990
 991         /* Disable CS while changing base address and size mask */
 992         gpmc_cs_disable_mem(cs);
 993
 994         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
 995         if (r < 0) {
 996                 release_resource(res);
 997                 goto out;
 998         }
 999
1000         /* Enable CS */
1001         gpmc_cs_enable_mem(cs);
1002         *base = res->start;
1003         gpmc_cs_set_reserved(cs, 1);
1004 out:
1005         spin_unlock(&gpmc_mem_lock);
1006         return r;
1007 }
1008 EXPORT_SYMBOL(gpmc_cs_request);
1009
1010 void gpmc_cs_free(int cs)
1011 {
1012         struct gpmc_cs_data *gpmc;
1013         struct resource *res;
1014
1015         spin_lock(&gpmc_mem_lock);
1016         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1017                 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
1018                 spin_unlock(&gpmc_mem_lock);
1019                 return;
1020         }
1021         gpmc = &gpmc_cs[cs];
1022         res = &gpmc->mem;
1023
1024         gpmc_cs_disable_mem(cs);
1025         if (res->flags)
1026                 release_resource(res);
1027         gpmc_cs_set_reserved(cs, 0);
1028         spin_unlock(&gpmc_mem_lock);
1029 }
1030 EXPORT_SYMBOL(gpmc_cs_free);
1031
1032 /**
1033  * gpmc_configure - write request to configure gpmc
1034  * @cmd: command type
1035  * @wval: value to write
1036  * @return status of the operation
1037  */
1038 int gpmc_configure(int cmd, int wval)
1039 {
1040         u32 regval;
1041
1042         switch (cmd) {
1043         case GPMC_CONFIG_WP:
1044                 regval = gpmc_read_reg(GPMC_CONFIG);
1045                 if (wval)
1046                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1047                 else
1048                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1049                 gpmc_write_reg(GPMC_CONFIG, regval);
1050                 break;
1051
1052         default:
1053                 pr_err("%s: command not supported\n", __func__);
1054                 return -EINVAL;
1055         }
1056
1057         return 0;
1058 }
1059 EXPORT_SYMBOL(gpmc_configure);
1060
1061 static bool gpmc_nand_writebuffer_empty(void)
1062 {
1063         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1064                 return true;
1065
1066         return false;
1067 }
1068
1069 static struct gpmc_nand_ops nand_ops = {
1070         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1071 };
1072
1073 /**
1074  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1075  * @reg: the GPMC NAND register map exclusive for NAND use.
1076  * @cs: GPMC chip select number on which the NAND sits. The
1077  *      register map returned will be specific to this chip select.
1078  *
1079  * Returns NULL on error e.g. invalid cs.
1080  */
1081 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1082 {
1083         int i;
1084
1085         if (cs >= gpmc_cs_num)
1086                 return NULL;
1087
1088         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1089                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1090         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1091                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1092         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1093                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1094         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1095         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1096         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1097         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1098         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1099         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1100         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1101         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1102
1103         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1104                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1105                                            GPMC_BCH_SIZE * i;
1106                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1107                                            GPMC_BCH_SIZE * i;
1108                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1109                                            GPMC_BCH_SIZE * i;
1110                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1111                                            GPMC_BCH_SIZE * i;
1112                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1113                                            i * GPMC_BCH_SIZE;
1114                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1115                                            i * GPMC_BCH_SIZE;
1116                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1117                                            i * GPMC_BCH_SIZE;
1118         }
1119
1120         return &nand_ops;
1121 }
1122 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1123
1124 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1125                                                 struct gpmc_settings *s,
1126                                                 int freq, int latency)
1127 {
1128         struct gpmc_device_timings dev_t;
1129         const int t_cer  = 15;
1130         const int t_avdp = 12;
1131         const int t_cez  = 20; /* max of t_cez, t_oez */
1132         const int t_wpl  = 40;
1133         const int t_wph  = 30;
1134         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1135
1136         switch (freq) {
1137         case 104:
1138                 min_gpmc_clk_period = 9600; /* 104 MHz */
1139                 t_ces   = 3;
1140                 t_avds  = 4;
1141                 t_avdh  = 2;
1142                 t_ach   = 3;
1143                 t_aavdh = 6;
1144                 t_rdyo  = 6;
1145                 break;
1146         case 83:
1147                 min_gpmc_clk_period = 12000; /* 83 MHz */
1148                 t_ces   = 5;
1149                 t_avds  = 4;
1150                 t_avdh  = 2;
1151                 t_ach   = 6;
1152                 t_aavdh = 6;
1153                 t_rdyo  = 9;
1154                 break;
1155         case 66:
1156                 min_gpmc_clk_period = 15000; /* 66 MHz */
1157                 t_ces   = 6;
1158                 t_avds  = 5;
1159                 t_avdh  = 2;
1160                 t_ach   = 6;
1161                 t_aavdh = 6;
1162                 t_rdyo  = 11;
1163                 break;
1164         default:
1165                 min_gpmc_clk_period = 18500; /* 54 MHz */
1166                 t_ces   = 7;
1167                 t_avds  = 7;
1168                 t_avdh  = 7;
1169                 t_ach   = 9;
1170                 t_aavdh = 7;
1171                 t_rdyo  = 15;
1172                 break;
1173         }
1174
1175         /* Set synchronous read timings */
1176         memset(&dev_t, 0, sizeof(dev_t));
1177
1178         if (!s->sync_write) {
1179                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1180                 dev_t.t_wpl = t_wpl * 1000;
1181                 dev_t.t_wph = t_wph * 1000;
1182                 dev_t.t_aavdh = t_aavdh * 1000;
1183         }
1184         dev_t.ce_xdelay = true;
1185         dev_t.avd_xdelay = true;
1186         dev_t.oe_xdelay = true;
1187         dev_t.we_xdelay = true;
1188         dev_t.clk = min_gpmc_clk_period;
1189         dev_t.t_bacc = dev_t.clk;
1190         dev_t.t_ces = t_ces * 1000;
1191         dev_t.t_avds = t_avds * 1000;
1192         dev_t.t_avdh = t_avdh * 1000;
1193         dev_t.t_ach = t_ach * 1000;
1194         dev_t.cyc_iaa = (latency + 1);
1195         dev_t.t_cez_r = t_cez * 1000;
1196         dev_t.t_cez_w = dev_t.t_cez_r;
1197         dev_t.cyc_aavdh_oe = 1;
1198         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1199
1200         gpmc_calc_timings(t, s, &dev_t);
1201 }
1202
1203 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1204                                   int latency,
1205                                   struct gpmc_onenand_info *info)
1206 {
1207         int ret;
1208         struct gpmc_timings gpmc_t;
1209         struct gpmc_settings gpmc_s;
1210
1211         gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1212
1213         info->sync_read = gpmc_s.sync_read;
1214         info->sync_write = gpmc_s.sync_write;
1215         info->burst_len = gpmc_s.burst_len;
1216
1217         if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1218                 return 0;
1219
1220         gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1221
1222         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1223         if (ret < 0)
1224                 return ret;
1225
1226         return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1227 }
1228 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1229
1230 int gpmc_get_client_irq(unsigned int irq_config)
1231 {
1232         if (!gpmc_irq_domain) {
1233                 pr_warn("%s called before GPMC IRQ domain available\n",
1234                         __func__);
1235                 return 0;
1236         }
1237
1238         /* we restrict this to NAND IRQs only */
1239         if (irq_config >= GPMC_NR_NAND_IRQS)
1240                 return 0;
1241
1242         return irq_create_mapping(gpmc_irq_domain, irq_config);
1243 }
1244
1245 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1246 {
1247         u32 regval;
1248
1249         /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1250         if (hwirq >= GPMC_NR_NAND_IRQS)
1251                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1252
1253         regval = gpmc_read_reg(GPMC_IRQENABLE);
1254         if (endis)
1255                 regval |= BIT(hwirq);
1256         else
1257                 regval &= ~BIT(hwirq);
1258         gpmc_write_reg(GPMC_IRQENABLE, regval);
1259
1260         return 0;
1261 }
1262
1263 static void gpmc_irq_disable(struct irq_data *p)
1264 {
1265         gpmc_irq_endis(p->hwirq, false);
1266 }
1267
1268 static void gpmc_irq_enable(struct irq_data *p)
1269 {
1270         gpmc_irq_endis(p->hwirq, true);
1271 }
1272
1273 static void gpmc_irq_mask(struct irq_data *d)
1274 {
1275         gpmc_irq_endis(d->hwirq, false);
1276 }
1277
1278 static void gpmc_irq_unmask(struct irq_data *d)
1279 {
1280         gpmc_irq_endis(d->hwirq, true);
1281 }
1282
1283 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1284 {
1285         u32 regval;
1286
1287         /* NAND IRQs polarity is not configurable */
1288         if (hwirq < GPMC_NR_NAND_IRQS)
1289                 return;
1290
1291         /* WAITPIN starts at BIT 8 */
1292         hwirq += 8 - GPMC_NR_NAND_IRQS;
1293
1294         regval = gpmc_read_reg(GPMC_CONFIG);
1295         if (rising_edge)
1296                 regval &= ~BIT(hwirq);
1297         else
1298                 regval |= BIT(hwirq);
1299
1300         gpmc_write_reg(GPMC_CONFIG, regval);
1301 }
1302
1303 static void gpmc_irq_ack(struct irq_data *d)
1304 {
1305         unsigned int hwirq = d->hwirq;
1306
1307         /* skip reserved bits */
1308         if (hwirq >= GPMC_NR_NAND_IRQS)
1309                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1310
1311         /* Setting bit to 1 clears (or Acks) the interrupt */
1312         gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1313 }
1314
1315 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1316 {
1317         /* can't set type for NAND IRQs */
1318         if (d->hwirq < GPMC_NR_NAND_IRQS)
1319                 return -EINVAL;
1320
1321         /* We can support either rising or falling edge at a time */
1322         if (trigger == IRQ_TYPE_EDGE_FALLING)
1323                 gpmc_irq_edge_config(d->hwirq, false);
1324         else if (trigger == IRQ_TYPE_EDGE_RISING)
1325                 gpmc_irq_edge_config(d->hwirq, true);
1326         else
1327                 return -EINVAL;
1328
1329         return 0;
1330 }
1331
1332 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1333                         irq_hw_number_t hw)
1334 {
1335         struct gpmc_device *gpmc = d->host_data;
1336
1337         irq_set_chip_data(virq, gpmc);
1338         if (hw < GPMC_NR_NAND_IRQS) {
1339                 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1340                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1341                                          handle_simple_irq);
1342         } else {
1343                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1344                                          handle_edge_irq);
1345         }
1346
1347         return 0;
1348 }
1349
1350 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1351         .map    = gpmc_irq_map,
1352         .xlate  = irq_domain_xlate_twocell,
1353 };
1354
1355 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1356 {
1357         int hwirq, virq;
1358         u32 regval, regvalx;
1359         struct gpmc_device *gpmc = data;
1360
1361         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1362         regvalx = regval;
1363
1364         if (!regval)
1365                 return IRQ_NONE;
1366
1367         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1368                 /* skip reserved status bits */
1369                 if (hwirq == GPMC_NR_NAND_IRQS)
1370                         regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1371
1372                 if (regvalx & BIT(hwirq)) {
1373                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1374                         if (!virq) {
1375                                 dev_warn(gpmc->dev,
1376                                          "spurious irq detected hwirq %d, virq %d\n",
1377                                          hwirq, virq);
1378                         }
1379
1380                         generic_handle_irq(virq);
1381                 }
1382         }
1383
1384         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1385
1386         return IRQ_HANDLED;
1387 }
1388
1389 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1390 {
1391         u32 regval;
1392         int rc;
1393
1394         /* Disable interrupts */
1395         gpmc_write_reg(GPMC_IRQENABLE, 0);
1396
1397         /* clear interrupts */
1398         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1399         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1400
1401         gpmc->irq_chip.name = "gpmc";
1402         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1403         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1404         gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1405         gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1406         gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1407         gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1408
1409         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1410                                                 gpmc->nirqs,
1411                                                 &gpmc_irq_domain_ops,
1412                                                 gpmc);
1413         if (!gpmc_irq_domain) {
1414                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1415                 return -ENODEV;
1416         }
1417
1418         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1419         if (rc) {
1420                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1421                         gpmc->irq, rc);
1422                 irq_domain_remove(gpmc_irq_domain);
1423                 gpmc_irq_domain = NULL;
1424         }
1425
1426         return rc;
1427 }
1428
1429 static int gpmc_free_irq(struct gpmc_device *gpmc)
1430 {
1431         int hwirq;
1432
1433         free_irq(gpmc->irq, gpmc);
1434
1435         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1436                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1437
1438         irq_domain_remove(gpmc_irq_domain);
1439         gpmc_irq_domain = NULL;
1440
1441         return 0;
1442 }
1443
1444 static void gpmc_mem_exit(void)
1445 {
1446         int cs;
1447
1448         for (cs = 0; cs < gpmc_cs_num; cs++) {
1449                 if (!gpmc_cs_mem_enabled(cs))
1450                         continue;
1451                 gpmc_cs_delete_mem(cs);
1452         }
1453 }
1454
1455 static void gpmc_mem_init(void)
1456 {
1457         int cs;
1458
1459         gpmc_mem_root.start = GPMC_MEM_START;
1460         gpmc_mem_root.end = GPMC_MEM_END;
1461
1462         /* Reserve all regions that has been set up by bootloader */
1463         for (cs = 0; cs < gpmc_cs_num; cs++) {
1464                 u32 base, size;
1465
1466                 if (!gpmc_cs_mem_enabled(cs))
1467                         continue;
1468                 gpmc_cs_get_memconf(cs, &base, &size);
1469                 if (gpmc_cs_insert_mem(cs, base, size)) {
1470                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1471                                 __func__, cs, base, base + size);
1472                         gpmc_cs_disable_mem(cs);
1473                 }
1474         }
1475 }
1476
1477 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1478 {
1479         u32 temp;
1480         int div;
1481
1482         div = gpmc_calc_divider(sync_clk);
1483         temp = gpmc_ps_to_ticks(time_ps);
1484         temp = (temp + div - 1) / div;
1485         return gpmc_ticks_to_ps(temp * div);
1486 }
1487
1488 /* XXX: can the cycles be avoided ? */
1489 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1490                                        struct gpmc_device_timings *dev_t,
1491                                        bool mux)
1492 {
1493         u32 temp;
1494
1495         /* adv_rd_off */
1496         temp = dev_t->t_avdp_r;
1497         /* XXX: mux check required ? */
1498         if (mux) {
1499                 /* XXX: t_avdp not to be required for sync, only added for tusb
1500                  * this indirectly necessitates requirement of t_avdp_r and
1501                  * t_avdp_w instead of having a single t_avdp
1502                  */
1503                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1504                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1505         }
1506         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1507
1508         /* oe_on */
1509         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1510         if (mux) {
1511                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1512                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1513                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1514         }
1515         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1516
1517         /* access */
1518         /* XXX: any scope for improvement ?, by combining oe_on
1519          * and clk_activation, need to check whether
1520          * access = clk_activation + round to sync clk ?
1521          */
1522         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1523         temp += gpmc_t->clk_activation;
1524         if (dev_t->cyc_oe)
1525                 temp = max_t(u32, temp, gpmc_t->oe_on +
1526                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1527         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1528
1529         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1530         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1531
1532         /* rd_cycle */
1533         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1534         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1535                                                         gpmc_t->access;
1536         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1537         if (dev_t->t_ce_rdyz)
1538                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1539         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1540
1541         return 0;
1542 }
1543
1544 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1545                                         struct gpmc_device_timings *dev_t,
1546                                         bool mux)
1547 {
1548         u32 temp;
1549
1550         /* adv_wr_off */
1551         temp = dev_t->t_avdp_w;
1552         if (mux) {
1553                 temp = max_t(u32, temp,
1554                         gpmc_t->clk_activation + dev_t->t_avdh);
1555                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1556         }
1557         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1558
1559         /* wr_data_mux_bus */
1560         temp = max_t(u32, dev_t->t_weasu,
1561                         gpmc_t->clk_activation + dev_t->t_rdyo);
1562         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1563          * and in that case remember to handle we_on properly
1564          */
1565         if (mux) {
1566                 temp = max_t(u32, temp,
1567                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1568                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1569                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1570         }
1571         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1572
1573         /* we_on */
1574         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1575                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1576         else
1577                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1578
1579         /* wr_access */
1580         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1581         gpmc_t->wr_access = gpmc_t->access;
1582
1583         /* we_off */
1584         temp = gpmc_t->we_on + dev_t->t_wpl;
1585         temp = max_t(u32, temp,
1586                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1587         temp = max_t(u32, temp,
1588                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1589         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1590
1591         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1592                                                         dev_t->t_wph);
1593
1594         /* wr_cycle */
1595         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1596         temp += gpmc_t->wr_access;
1597         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1598         if (dev_t->t_ce_rdyz)
1599                 temp = max_t(u32, temp,
1600                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1601         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1602
1603         return 0;
1604 }
1605
1606 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1607                                         struct gpmc_device_timings *dev_t,
1608                                         bool mux)
1609 {
1610         u32 temp;
1611
1612         /* adv_rd_off */
1613         temp = dev_t->t_avdp_r;
1614         if (mux)
1615                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1616         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1617
1618         /* oe_on */
1619         temp = dev_t->t_oeasu;
1620         if (mux)
1621                 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
1622         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1623
1624         /* access */
1625         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1626                      gpmc_t->oe_on + dev_t->t_oe);
1627         temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1628         temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
1629         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1630
1631         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1632         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1633
1634         /* rd_cycle */
1635         temp = max_t(u32, dev_t->t_rd_cycle,
1636                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1637         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1638         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1639
1640         return 0;
1641 }
1642
1643 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1644                                          struct gpmc_device_timings *dev_t,
1645                                          bool mux)
1646 {
1647         u32 temp;
1648
1649         /* adv_wr_off */
1650         temp = dev_t->t_avdp_w;
1651         if (mux)
1652                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1653         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1654
1655         /* wr_data_mux_bus */
1656         temp = dev_t->t_weasu;
1657         if (mux) {
1658                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1659                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1660                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1661         }
1662         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1663
1664         /* we_on */
1665         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1666                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1667         else
1668                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1669
1670         /* we_off */
1671         temp = gpmc_t->we_on + dev_t->t_wpl;
1672         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1673
1674         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1675                                                         dev_t->t_wph);
1676
1677         /* wr_cycle */
1678         temp = max_t(u32, dev_t->t_wr_cycle,
1679                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1680         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1681
1682         return 0;
1683 }
1684
1685 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1686                         struct gpmc_device_timings *dev_t)
1687 {
1688         u32 temp;
1689
1690         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1691                                                 gpmc_get_fclk_period();
1692
1693         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1694                                         dev_t->t_bacc,
1695                                         gpmc_t->sync_clk);
1696
1697         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1698         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1699
1700         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1701                 return 0;
1702
1703         if (dev_t->ce_xdelay)
1704                 gpmc_t->bool_timings.cs_extra_delay = true;
1705         if (dev_t->avd_xdelay)
1706                 gpmc_t->bool_timings.adv_extra_delay = true;
1707         if (dev_t->oe_xdelay)
1708                 gpmc_t->bool_timings.oe_extra_delay = true;
1709         if (dev_t->we_xdelay)
1710                 gpmc_t->bool_timings.we_extra_delay = true;
1711
1712         return 0;
1713 }
1714
1715 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1716                                     struct gpmc_device_timings *dev_t,
1717                                     bool sync)
1718 {
1719         u32 temp;
1720
1721         /* cs_on */
1722         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1723
1724         /* adv_on */
1725         temp = dev_t->t_avdasu;
1726         if (dev_t->t_ce_avd)
1727                 temp = max_t(u32, temp,
1728                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1729         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1730
1731         if (sync)
1732                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1733
1734         return 0;
1735 }
1736
1737 /*
1738  * TODO: remove this function once all peripherals are confirmed to
1739  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1740  * has to be modified to handle timings in ps instead of ns
1741  */
1742 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1743 {
1744         t->cs_on /= 1000;
1745         t->cs_rd_off /= 1000;
1746         t->cs_wr_off /= 1000;
1747         t->adv_on /= 1000;
1748         t->adv_rd_off /= 1000;
1749         t->adv_wr_off /= 1000;
1750         t->we_on /= 1000;
1751         t->we_off /= 1000;
1752         t->oe_on /= 1000;
1753         t->oe_off /= 1000;
1754         t->page_burst_access /= 1000;
1755         t->access /= 1000;
1756         t->rd_cycle /= 1000;
1757         t->wr_cycle /= 1000;
1758         t->bus_turnaround /= 1000;
1759         t->cycle2cycle_delay /= 1000;
1760         t->wait_monitoring /= 1000;
1761         t->clk_activation /= 1000;
1762         t->wr_access /= 1000;
1763         t->wr_data_mux_bus /= 1000;
1764 }
1765
1766 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1767                       struct gpmc_settings *gpmc_s,
1768                       struct gpmc_device_timings *dev_t)
1769 {
1770         bool mux = false, sync = false;
1771
1772         if (gpmc_s) {
1773                 mux = gpmc_s->mux_add_data ? true : false;
1774                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1775         }
1776
1777         memset(gpmc_t, 0, sizeof(*gpmc_t));
1778
1779         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1780
1781         if (gpmc_s && gpmc_s->sync_read)
1782                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1783         else
1784                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1785
1786         if (gpmc_s && gpmc_s->sync_write)
1787                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1788         else
1789                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1790
1791         /* TODO: remove, see function definition */
1792         gpmc_convert_ps_to_ns(gpmc_t);
1793
1794         return 0;
1795 }
1796
1797 /**
1798  * gpmc_cs_program_settings - programs non-timing related settings
1799  * @cs:         GPMC chip-select to program
1800  * @p:          pointer to GPMC settings structure
1801  *
1802  * Programs non-timing related settings for a GPMC chip-select, such as
1803  * bus-width, burst configuration, etc. Function should be called once
1804  * for each chip-select that is being used and must be called before
1805  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1806  * register will be initialised to zero by this function. Returns 0 on
1807  * success and appropriate negative error code on failure.
1808  */
1809 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1810 {
1811         u32 config1;
1812
1813         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1814                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1815                 return -EINVAL;
1816         }
1817
1818         /* Address-data multiplexing not supported for NAND devices */
1819         if (p->device_nand && p->mux_add_data) {
1820                 pr_err("%s: invalid configuration!\n", __func__);
1821                 return -EINVAL;
1822         }
1823
1824         if ((p->mux_add_data > GPMC_MUX_AD) ||
1825             ((p->mux_add_data == GPMC_MUX_AAD) &&
1826              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1827                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1828                 return -EINVAL;
1829         }
1830
1831         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1832         if (p->burst_read || p->burst_write) {
1833                 switch (p->burst_len) {
1834                 case GPMC_BURST_4:
1835                 case GPMC_BURST_8:
1836                 case GPMC_BURST_16:
1837                         break;
1838                 default:
1839                         pr_err("%s: invalid page/burst-length (%d)\n",
1840                                __func__, p->burst_len);
1841                         return -EINVAL;
1842                 }
1843         }
1844
1845         if (p->wait_pin > gpmc_nr_waitpins) {
1846                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1847                 return -EINVAL;
1848         }
1849
1850         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1851
1852         if (p->sync_read)
1853                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1854         if (p->sync_write)
1855                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1856         if (p->wait_on_read)
1857                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1858         if (p->wait_on_write)
1859                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1860         if (p->wait_on_read || p->wait_on_write)
1861                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1862         if (p->device_nand)
1863                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1864         if (p->mux_add_data)
1865                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1866         if (p->burst_read)
1867                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1868         if (p->burst_write)
1869                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1870         if (p->burst_read || p->burst_write) {
1871                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1872                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1873         }
1874
1875         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1876
1877         return 0;
1878 }
1879
1880 #ifdef CONFIG_OF
1881 static const struct of_device_id gpmc_dt_ids[] = {
1882         { .compatible = "ti,omap2420-gpmc" },
1883         { .compatible = "ti,omap2430-gpmc" },
1884         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1885         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1886         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1887         { }
1888 };
1889
1890 static void gpmc_cs_set_name(int cs, const char *name)
1891 {
1892         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1893
1894         gpmc->name = name;
1895 }
1896
1897 static const char *gpmc_cs_get_name(int cs)
1898 {
1899         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1900
1901         return gpmc->name;
1902 }
1903
1904 /**
1905  * gpmc_cs_remap - remaps a chip-select physical base address
1906  * @cs:         chip-select to remap
1907  * @base:       physical base address to re-map chip-select to
1908  *
1909  * Re-maps a chip-select to a new physical base address specified by
1910  * "base". Returns 0 on success and appropriate negative error code
1911  * on failure.
1912  */
1913 static int gpmc_cs_remap(int cs, u32 base)
1914 {
1915         int ret;
1916         u32 old_base, size;
1917
1918         if (cs >= gpmc_cs_num) {
1919                 pr_err("%s: requested chip-select is disabled\n", __func__);
1920                 return -ENODEV;
1921         }
1922
1923         /*
1924          * Make sure we ignore any device offsets from the GPMC partition
1925          * allocated for the chip select and that the new base confirms
1926          * to the GPMC 16MB minimum granularity.
1927          */
1928         base &= ~(SZ_16M - 1);
1929
1930         gpmc_cs_get_memconf(cs, &old_base, &size);
1931         if (base == old_base)
1932                 return 0;
1933
1934         ret = gpmc_cs_delete_mem(cs);
1935         if (ret < 0)
1936                 return ret;
1937
1938         ret = gpmc_cs_insert_mem(cs, base, size);
1939         if (ret < 0)
1940                 return ret;
1941
1942         ret = gpmc_cs_set_memconf(cs, base, size);
1943
1944         return ret;
1945 }
1946
1947 /**
1948  * gpmc_read_settings_dt - read gpmc settings from device-tree
1949  * @np:         pointer to device-tree node for a gpmc child device
1950  * @p:          pointer to gpmc settings structure
1951  *
1952  * Reads the GPMC settings for a GPMC child device from device-tree and
1953  * stores them in the GPMC settings structure passed. The GPMC settings
1954  * structure is initialised to zero by this function and so any
1955  * previously stored settings will be cleared.
1956  */
1957 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1958 {
1959         memset(p, 0, sizeof(struct gpmc_settings));
1960
1961         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1962         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1963         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1964         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1965
1966         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1967                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1968                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1969                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1970                 if (!p->burst_read && !p->burst_write)
1971                         pr_warn("%s: page/burst-length set but not used!\n",
1972                                 __func__);
1973         }
1974
1975         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1976                 p->wait_on_read = of_property_read_bool(np,
1977                                                         "gpmc,wait-on-read");
1978                 p->wait_on_write = of_property_read_bool(np,
1979                                                          "gpmc,wait-on-write");
1980                 if (!p->wait_on_read && !p->wait_on_write)
1981                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1982                                  __func__);
1983         }
1984 }
1985
1986 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1987                                                 struct gpmc_timings *gpmc_t)
1988 {
1989         struct gpmc_bool_timings *p;
1990
1991         if (!np || !gpmc_t)
1992                 return;
1993
1994         memset(gpmc_t, 0, sizeof(*gpmc_t));
1995
1996         /* minimum clock period for syncronous mode */
1997         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1998
1999         /* chip select timtings */
2000         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
2001         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
2002         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
2003
2004         /* ADV signal timings */
2005         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
2006         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
2007         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2008         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
2009                              &gpmc_t->adv_aad_mux_on);
2010         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
2011                              &gpmc_t->adv_aad_mux_rd_off);
2012         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
2013                              &gpmc_t->adv_aad_mux_wr_off);
2014
2015         /* WE signal timings */
2016         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
2017         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
2018
2019         /* OE signal timings */
2020         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
2021         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2022         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
2023                              &gpmc_t->oe_aad_mux_on);
2024         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
2025                              &gpmc_t->oe_aad_mux_off);
2026
2027         /* access and cycle timings */
2028         of_property_read_u32(np, "gpmc,page-burst-access-ns",
2029                              &gpmc_t->page_burst_access);
2030         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
2031         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
2032         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
2033         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
2034                              &gpmc_t->bus_turnaround);
2035         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2036                              &gpmc_t->cycle2cycle_delay);
2037         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2038                              &gpmc_t->wait_monitoring);
2039         of_property_read_u32(np, "gpmc,clk-activation-ns",
2040                              &gpmc_t->clk_activation);
2041
2042         /* only applicable to OMAP3+ */
2043         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2044         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2045                              &gpmc_t->wr_data_mux_bus);
2046
2047         /* bool timing parameters */
2048         p = &gpmc_t->bool_timings;
2049
2050         p->cycle2cyclediffcsen =
2051                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2052         p->cycle2cyclesamecsen =
2053                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2054         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2055         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2056         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2057         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2058         p->time_para_granularity =
2059                 of_property_read_bool(np, "gpmc,time-para-granularity");
2060 }
2061
2062 /**
2063  * gpmc_probe_generic_child - configures the gpmc for a child device
2064  * @pdev:       pointer to gpmc platform device
2065  * @child:      pointer to device-tree node for child device
2066  *
2067  * Allocates and configures a GPMC chip-select for a child device.
2068  * Returns 0 on success and appropriate negative error code on failure.
2069  */
2070 static int gpmc_probe_generic_child(struct platform_device *pdev,
2071                                 struct device_node *child)
2072 {
2073         struct gpmc_settings gpmc_s;
2074         struct gpmc_timings gpmc_t;
2075         struct resource res;
2076         unsigned long base;
2077         const char *name;
2078         int ret, cs;
2079         u32 val;
2080         struct gpio_desc *waitpin_desc = NULL;
2081         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2082
2083         if (of_property_read_u32(child, "reg", &cs) < 0) {
2084                 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2085                         child);
2086                 return -ENODEV;
2087         }
2088
2089         if (of_address_to_resource(child, 0, &res) < 0) {
2090                 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2091                         child);
2092                 return -ENODEV;
2093         }
2094
2095         /*
2096          * Check if we have multiple instances of the same device
2097          * on a single chip select. If so, use the already initialized
2098          * timings.
2099          */
2100         name = gpmc_cs_get_name(cs);
2101         if (name && of_node_name_eq(child, name))
2102                 goto no_timings;
2103
2104         ret = gpmc_cs_request(cs, resource_size(&res), &base);
2105         if (ret < 0) {
2106                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2107                 return ret;
2108         }
2109         gpmc_cs_set_name(cs, child->full_name);
2110
2111         gpmc_read_settings_dt(child, &gpmc_s);
2112         gpmc_read_timings_dt(child, &gpmc_t);
2113
2114         /*
2115          * For some GPMC devices we still need to rely on the bootloader
2116          * timings because the devices can be connected via FPGA.
2117          * REVISIT: Add timing support from slls644g.pdf.
2118          */
2119         if (!gpmc_t.cs_rd_off) {
2120                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2121                         cs);
2122                 gpmc_cs_show_timings(cs,
2123                                      "please add GPMC bootloader timings to .dts");
2124                 goto no_timings;
2125         }
2126
2127         /* CS must be disabled while making changes to gpmc configuration */
2128         gpmc_cs_disable_mem(cs);
2129
2130         /*
2131          * FIXME: gpmc_cs_request() will map the CS to an arbitrary
2132          * location in the gpmc address space. When booting with
2133          * device-tree we want the NOR flash to be mapped to the
2134          * location specified in the device-tree blob. So remap the
2135          * CS to this location. Once DT migration is complete should
2136          * just make gpmc_cs_request() map a specific address.
2137          */
2138         ret = gpmc_cs_remap(cs, res.start);
2139         if (ret < 0) {
2140                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2141                         cs, &res.start);
2142                 if (res.start < GPMC_MEM_START) {
2143                         dev_info(&pdev->dev,
2144                                  "GPMC CS %d start cannot be lesser than 0x%x\n",
2145                                  cs, GPMC_MEM_START);
2146                 } else if (res.end > GPMC_MEM_END) {
2147                         dev_info(&pdev->dev,
2148                                  "GPMC CS %d end cannot be greater than 0x%x\n",
2149                                  cs, GPMC_MEM_END);
2150                 }
2151                 goto err;
2152         }
2153
2154         if (of_node_name_eq(child, "nand")) {
2155                 /* Warn about older DT blobs with no compatible property */
2156                 if (!of_property_read_bool(child, "compatible")) {
2157                         dev_warn(&pdev->dev,
2158                                  "Incompatible NAND node: missing compatible");
2159                         ret = -EINVAL;
2160                         goto err;
2161                 }
2162         }
2163
2164         if (of_node_name_eq(child, "onenand")) {
2165                 /* Warn about older DT blobs with no compatible property */
2166                 if (!of_property_read_bool(child, "compatible")) {
2167                         dev_warn(&pdev->dev,
2168                                  "Incompatible OneNAND node: missing compatible");
2169                         ret = -EINVAL;
2170                         goto err;
2171                 }
2172         }
2173
2174         if (of_device_is_compatible(child, "ti,omap2-nand")) {
2175                 /* NAND specific setup */
2176                 val = 8;
2177                 of_property_read_u32(child, "nand-bus-width", &val);
2178                 switch (val) {
2179                 case 8:
2180                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2181                         break;
2182                 case 16:
2183                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2184                         break;
2185                 default:
2186                         dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2187                                 child);
2188                         ret = -EINVAL;
2189                         goto err;
2190                 }
2191
2192                 /* disable write protect */
2193                 gpmc_configure(GPMC_CONFIG_WP, 0);
2194                 gpmc_s.device_nand = true;
2195         } else {
2196                 ret = of_property_read_u32(child, "bank-width",
2197                                            &gpmc_s.device_width);
2198                 if (ret < 0 && !gpmc_s.device_width) {
2199                         dev_err(&pdev->dev,
2200                                 "%pOF has no 'gpmc,device-width' property\n",
2201                                 child);
2202                         goto err;
2203                 }
2204         }
2205
2206         /* Reserve wait pin if it is required and valid */
2207         if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2208                 unsigned int wait_pin = gpmc_s.wait_pin;
2209
2210                 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2211                                                          wait_pin, "WAITPIN",
2212                                                          GPIO_ACTIVE_HIGH,
2213                                                          GPIOD_IN);
2214                 if (IS_ERR(waitpin_desc)) {
2215                         dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2216                         ret = PTR_ERR(waitpin_desc);
2217                         goto err;
2218                 }
2219         }
2220
2221         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2222
2223         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2224         if (ret < 0)
2225                 goto err_cs;
2226
2227         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2228         if (ret) {
2229                 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2230                         child);
2231                 goto err_cs;
2232         }
2233
2234         /* Clear limited address i.e. enable A26-A11 */
2235         val = gpmc_read_reg(GPMC_CONFIG);
2236         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2237         gpmc_write_reg(GPMC_CONFIG, val);
2238
2239         /* Enable CS region */
2240         gpmc_cs_enable_mem(cs);
2241
2242 no_timings:
2243
2244         /* create platform device, NULL on error or when disabled */
2245         if (!of_platform_device_create(child, NULL, &pdev->dev))
2246                 goto err_child_fail;
2247
2248         /* is child a common bus? */
2249         if (of_match_node(of_default_bus_match_table, child))
2250                 /* create children and other common bus children */
2251                 if (of_platform_default_populate(child, NULL, &pdev->dev))
2252                         goto err_child_fail;
2253
2254         return 0;
2255
2256 err_child_fail:
2257
2258         dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2259         ret = -ENODEV;
2260
2261 err_cs:
2262         gpiochip_free_own_desc(waitpin_desc);
2263 err:
2264         gpmc_cs_free(cs);
2265
2266         return ret;
2267 }
2268
2269 static int gpmc_probe_dt(struct platform_device *pdev)
2270 {
2271         int ret;
2272         const struct of_device_id *of_id =
2273                 of_match_device(gpmc_dt_ids, &pdev->dev);
2274
2275         if (!of_id)
2276                 return 0;
2277
2278         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2279                                    &gpmc_cs_num);
2280         if (ret < 0) {
2281                 pr_err("%s: number of chip-selects not defined\n", __func__);
2282                 return ret;
2283         } else if (gpmc_cs_num < 1) {
2284                 pr_err("%s: all chip-selects are disabled\n", __func__);
2285                 return -EINVAL;
2286         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2287                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2288                                          __func__, GPMC_CS_NUM);
2289                 return -EINVAL;
2290         }
2291
2292         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2293                                    &gpmc_nr_waitpins);
2294         if (ret < 0) {
2295                 pr_err("%s: number of wait pins not found!\n", __func__);
2296                 return ret;
2297         }
2298
2299         return 0;
2300 }
2301
2302 static void gpmc_probe_dt_children(struct platform_device *pdev)
2303 {
2304         int ret;
2305         struct device_node *child;
2306
2307         for_each_available_child_of_node(pdev->dev.of_node, child) {
2308                 ret = gpmc_probe_generic_child(pdev, child);
2309                 if (ret) {
2310                         dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2311                                 child, ret);
2312                 }
2313         }
2314 }
2315 #else
2316 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2317 {
2318         memset(p, 0, sizeof(*p));
2319 }
2320 static int gpmc_probe_dt(struct platform_device *pdev)
2321 {
2322         return 0;
2323 }
2324
2325 static void gpmc_probe_dt_children(struct platform_device *pdev)
2326 {
2327 }
2328 #endif /* CONFIG_OF */
2329
2330 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2331 {
2332         return 1;       /* we're input only */
2333 }
2334
2335 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2336                                      unsigned int offset)
2337 {
2338         return 0;       /* we're input only */
2339 }
2340
2341 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2342                                       unsigned int offset, int value)
2343 {
2344         return -EINVAL; /* we're input only */
2345 }
2346
2347 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2348                           int value)
2349 {
2350 }
2351
2352 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2353 {
2354         u32 reg;
2355
2356         offset += 8;
2357
2358         reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2359
2360         return !!reg;
2361 }
2362
2363 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2364 {
2365         int ret;
2366
2367         gpmc->gpio_chip.parent = gpmc->dev;
2368         gpmc->gpio_chip.owner = THIS_MODULE;
2369         gpmc->gpio_chip.label = DEVICE_NAME;
2370         gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2371         gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2372         gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2373         gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2374         gpmc->gpio_chip.set = gpmc_gpio_set;
2375         gpmc->gpio_chip.get = gpmc_gpio_get;
2376         gpmc->gpio_chip.base = -1;
2377
2378         ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2379         if (ret < 0) {
2380                 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2381                 return ret;
2382         }
2383
2384         return 0;
2385 }
2386
2387 static int gpmc_probe(struct platform_device *pdev)
2388 {
2389         int rc;
2390         u32 l;
2391         struct resource *res;
2392         struct gpmc_device *gpmc;
2393
2394         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2395         if (!gpmc)
2396                 return -ENOMEM;
2397
2398         gpmc->dev = &pdev->dev;
2399         platform_set_drvdata(pdev, gpmc);
2400
2401         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2402         if (!res)
2403                 return -ENOENT;
2404
2405         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2406         if (IS_ERR(gpmc_base))
2407                 return PTR_ERR(gpmc_base);
2408
2409         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2410         if (!res) {
2411                 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2412                 return -ENOENT;
2413         }
2414
2415         gpmc->irq = res->start;
2416
2417         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2418         if (IS_ERR(gpmc_l3_clk)) {
2419                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2420                 return PTR_ERR(gpmc_l3_clk);
2421         }
2422
2423         if (!clk_get_rate(gpmc_l3_clk)) {
2424                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2425                 return -EINVAL;
2426         }
2427
2428         if (pdev->dev.of_node) {
2429                 rc = gpmc_probe_dt(pdev);
2430                 if (rc)
2431                         return rc;
2432         } else {
2433                 gpmc_cs_num = GPMC_CS_NUM;
2434                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2435         }
2436
2437         pm_runtime_enable(&pdev->dev);
2438         pm_runtime_get_sync(&pdev->dev);
2439
2440         l = gpmc_read_reg(GPMC_REVISION);
2441
2442         /*
2443          * FIXME: Once device-tree migration is complete the below flags
2444          * should be populated based upon the device-tree compatible
2445          * string. For now just use the IP revision. OMAP3+ devices have
2446          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2447          * devices support the addr-addr-data multiplex protocol.
2448          *
2449          * GPMC IP revisions:
2450          * - OMAP24xx                   = 2.0
2451          * - OMAP3xxx                   = 5.0
2452          * - OMAP44xx/54xx/AM335x       = 6.0
2453          */
2454         if (GPMC_REVISION_MAJOR(l) > 0x4)
2455                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2456         if (GPMC_REVISION_MAJOR(l) > 0x5)
2457                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2458         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2459                  GPMC_REVISION_MINOR(l));
2460
2461         gpmc_mem_init();
2462         rc = gpmc_gpio_init(gpmc);
2463         if (rc)
2464                 goto gpio_init_failed;
2465
2466         gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2467         rc = gpmc_setup_irq(gpmc);
2468         if (rc) {
2469                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2470                 goto gpio_init_failed;
2471         }
2472
2473         gpmc_probe_dt_children(pdev);
2474
2475         return 0;
2476
2477 gpio_init_failed:
2478         gpmc_mem_exit();
2479         pm_runtime_put_sync(&pdev->dev);
2480         pm_runtime_disable(&pdev->dev);
2481
2482         return rc;
2483 }
2484
2485 static int gpmc_remove(struct platform_device *pdev)
2486 {
2487         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2488
2489         gpmc_free_irq(gpmc);
2490         gpmc_mem_exit();
2491         pm_runtime_put_sync(&pdev->dev);
2492         pm_runtime_disable(&pdev->dev);
2493
2494         return 0;
2495 }
2496
2497 #ifdef CONFIG_PM_SLEEP
2498 static int gpmc_suspend(struct device *dev)
2499 {
2500         omap3_gpmc_save_context();
2501         pm_runtime_put_sync(dev);
2502         return 0;
2503 }
2504
2505 static int gpmc_resume(struct device *dev)
2506 {
2507         pm_runtime_get_sync(dev);
2508         omap3_gpmc_restore_context();
2509         return 0;
2510 }
2511 #endif
2512
2513 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2514
2515 static struct platform_driver gpmc_driver = {
2516         .probe          = gpmc_probe,
2517         .remove         = gpmc_remove,
2518         .driver         = {
2519                 .name   = DEVICE_NAME,
2520                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2521                 .pm     = &gpmc_pm_ops,
2522         },
2523 };
2524
2525 static __init int gpmc_init(void)
2526 {
2527         return platform_driver_register(&gpmc_driver);
2528 }
2529 postcore_initcall(gpmc_init);
2530
2531 static struct omap3_gpmc_regs gpmc_context;
2532
2533 void omap3_gpmc_save_context(void)
2534 {
2535         int i;
2536
2537         if (!gpmc_base)
2538                 return;
2539
2540         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2541         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2542         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2543         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2544         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2545         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2546         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2547         for (i = 0; i < gpmc_cs_num; i++) {
2548                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2549                 if (gpmc_context.cs_context[i].is_valid) {
2550                         gpmc_context.cs_context[i].config1 =
2551                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2552                         gpmc_context.cs_context[i].config2 =
2553                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2554                         gpmc_context.cs_context[i].config3 =
2555                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2556                         gpmc_context.cs_context[i].config4 =
2557                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2558                         gpmc_context.cs_context[i].config5 =
2559                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2560                         gpmc_context.cs_context[i].config6 =
2561                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2562                         gpmc_context.cs_context[i].config7 =
2563                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2564                 }
2565         }
2566 }
2567
2568 void omap3_gpmc_restore_context(void)
2569 {
2570         int i;
2571
2572         if (!gpmc_base)
2573                 return;
2574
2575         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2576         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2577         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2578         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2579         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2580         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2581         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2582         for (i = 0; i < gpmc_cs_num; i++) {
2583                 if (gpmc_context.cs_context[i].is_valid) {
2584                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2585                                 gpmc_context.cs_context[i].config1);
2586                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2587                                 gpmc_context.cs_context[i].config2);
2588                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2589                                 gpmc_context.cs_context[i].config3);
2590                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2591                                 gpmc_context.cs_context[i].config4);
2592                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2593                                 gpmc_context.cs_context[i].config5);
2594                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2595                                 gpmc_context.cs_context[i].config6);
2596                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2597                                 gpmc_context.cs_context[i].config7);
2598                 }
2599         }
2600 }