drivers/infiniband/hw/bnxt_re/roce_hsi.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: RoCE HSI File - Autogenerated
  37  */
  38
  39 #ifndef __BNXT_RE_HSI_H__
  40 #define __BNXT_RE_HSI_H__
  41
  42 /* include bnxt_hsi.h from bnxt_en driver */
  43 #include "bnxt_hsi.h"
  44
  45 /* CMP Door Bell Format (4 bytes) */
  46 struct cmpl_doorbell {
  47         __le32 key_mask_valid_idx;
  48         #define CMPL_DOORBELL_IDX_MASK                              0xffffffUL
  49         #define CMPL_DOORBELL_IDX_SFT                               0
  50         #define CMPL_DOORBELL_RESERVED_MASK                         0x3000000UL
  51         #define CMPL_DOORBELL_RESERVED_SFT                          24
  52         #define CMPL_DOORBELL_IDX_VALID                             0x4000000UL
  53         #define CMPL_DOORBELL_MASK                                  0x8000000UL
  54         #define CMPL_DOORBELL_KEY_MASK                              0xf0000000UL
  55         #define CMPL_DOORBELL_KEY_SFT                               28
  56         #define CMPL_DOORBELL_KEY_CMPL                          (0x2UL << 28)
  57 };
  58
  59 /* Status Door Bell Format (4 bytes) */
  60 struct status_doorbell {
  61         __le32 key_idx;
  62         #define STATUS_DOORBELL_IDX_MASK                            0xffffffUL
  63         #define STATUS_DOORBELL_IDX_SFT                     0
  64         #define STATUS_DOORBELL_RESERVED_MASK                       0xf000000UL
  65         #define STATUS_DOORBELL_RESERVED_SFT                        24
  66         #define STATUS_DOORBELL_KEY_MASK                            0xf0000000UL
  67         #define STATUS_DOORBELL_KEY_SFT                     28
  68         #define STATUS_DOORBELL_KEY_STAT                           (0x3UL << 28)
  69 };
  70
  71 /* RoCE Host Structures */
  72
  73 /* Doorbell Structures */
  74 /* dbc_dbc (size:64b/8B) */
  75 struct dbc_dbc {
  76         __le32  index;
  77         #define DBC_DBC_INDEX_MASK              0xffffffUL
  78         #define DBC_DBC_INDEX_SFT               0
  79         __le32  type_path_xid;
  80         #define DBC_DBC_XID_MASK                0xfffffUL
  81         #define DBC_DBC_XID_SFT                 0
  82         #define DBC_DBC_PATH_MASK               0x3000000UL
  83         #define DBC_DBC_PATH_SFT                24
  84         #define DBC_DBC_PATH_ROCE               (0x0UL << 24)
  85         #define DBC_DBC_PATH_L2                 (0x1UL << 24)
  86         #define DBC_DBC_PATH_ENGINE             (0x2UL << 24)
  87         #define DBC_DBC_PATH_LAST               DBC_DBC_PATH_ENGINE
  88         #define DBC_DBC_DEBUG_TRACE             0x8000000UL
  89         #define DBC_DBC_TYPE_MASK               0xf0000000UL
  90         #define DBC_DBC_TYPE_SFT                28
  91         #define DBC_DBC_TYPE_SQ                 (0x0UL << 28)
  92         #define DBC_DBC_TYPE_RQ                 (0x1UL << 28)
  93         #define DBC_DBC_TYPE_SRQ                (0x2UL << 28)
  94         #define DBC_DBC_TYPE_SRQ_ARM            (0x3UL << 28)
  95         #define DBC_DBC_TYPE_CQ                 (0x4UL << 28)
  96         #define DBC_DBC_TYPE_CQ_ARMSE           (0x5UL << 28)
  97         #define DBC_DBC_TYPE_CQ_ARMALL          (0x6UL << 28)
  98         #define DBC_DBC_TYPE_CQ_ARMENA          (0x7UL << 28)
  99         #define DBC_DBC_TYPE_SRQ_ARMENA         (0x8UL << 28)
 100         #define DBC_DBC_TYPE_CQ_CUTOFF_ACK      (0x9UL << 28)
 101         #define DBC_DBC_TYPE_NQ                 (0xaUL << 28)
 102         #define DBC_DBC_TYPE_NQ_ARM             (0xbUL << 28)
 103         #define DBC_DBC_TYPE_NULL               (0xfUL << 28)
 104         #define DBC_DBC_TYPE_LAST               DBC_DBC_TYPE_NULL
 105 };
 106
 107 /* dbc_dbc32 (size:32b/4B) */
 108 struct dbc_dbc32 {
 109         __le32  type_abs_incr_xid;
 110         #define DBC_DBC32_XID_MASK              0xfffffUL
 111         #define DBC_DBC32_XID_SFT               0
 112         #define DBC_DBC32_PATH_MASK             0xc00000UL
 113         #define DBC_DBC32_PATH_SFT              22
 114         #define DBC_DBC32_PATH_ROCE             (0x0UL << 22)
 115         #define DBC_DBC32_PATH_L2               (0x1UL << 22)
 116         #define DBC_DBC32_PATH_LAST             DBC_DBC32_PATH_L2
 117         #define DBC_DBC32_INCR_MASK             0xf000000UL
 118         #define DBC_DBC32_INCR_SFT              24
 119         #define DBC_DBC32_ABS                   0x10000000UL
 120         #define DBC_DBC32_TYPE_MASK             0xe0000000UL
 121         #define DBC_DBC32_TYPE_SFT              29
 122         #define DBC_DBC32_TYPE_SQ               (0x0UL << 29)
 123         #define DBC_DBC32_TYPE_LAST             DBC_DBC32_TYPE_SQ
 124 };
 125
 126 /* SQ WQE Structures */
 127 /* Base SQ WQE (8 bytes) */
 128 struct sq_base {
 129         u8 wqe_type;
 130         #define SQ_BASE_WQE_TYPE_SEND                              0x0UL
 131         #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD                     0x1UL
 132         #define SQ_BASE_WQE_TYPE_SEND_W_INVALID            0x2UL
 133         #define SQ_BASE_WQE_TYPE_WRITE_WQE                         0x4UL
 134         #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD            0x5UL
 135         #define SQ_BASE_WQE_TYPE_READ_WQE                          0x6UL
 136         #define SQ_BASE_WQE_TYPE_ATOMIC_CS                         0x8UL
 137         #define SQ_BASE_WQE_TYPE_ATOMIC_FA                         0xbUL
 138         #define SQ_BASE_WQE_TYPE_LOCAL_INVALID                     0xcUL
 139         #define SQ_BASE_WQE_TYPE_FR_PMR                    0xdUL
 140         #define SQ_BASE_WQE_TYPE_BIND                              0xeUL
 141         u8 unused_0[7];
 142 };
 143
 144 /* WQE SGE (16 bytes) */
 145 struct sq_sge {
 146         __le64 va_or_pa;
 147         __le32 l_key;
 148         __le32 size;
 149 };
 150
 151 /* PSN Search Structure (8 bytes) */
 152 struct sq_psn_search {
 153         __le32 opcode_start_psn;
 154         #define SQ_PSN_SEARCH_START_PSN_MASK                        0xffffffUL
 155         #define SQ_PSN_SEARCH_START_PSN_SFT                         0
 156         #define SQ_PSN_SEARCH_OPCODE_MASK                           0xff000000UL
 157         #define SQ_PSN_SEARCH_OPCODE_SFT                            24
 158         __le32 flags_next_psn;
 159         #define SQ_PSN_SEARCH_NEXT_PSN_MASK                         0xffffffUL
 160         #define SQ_PSN_SEARCH_NEXT_PSN_SFT                          0
 161         #define SQ_PSN_SEARCH_FLAGS_MASK                            0xff000000UL
 162         #define SQ_PSN_SEARCH_FLAGS_SFT                             24
 163 };
 164
 165 /* sq_psn_search_ext (size:128b/16B) */
 166 struct sq_psn_search_ext {
 167         __le32  opcode_start_psn;
 168         #define SQ_PSN_SEARCH_EXT_START_PSN_MASK                    0xffffffUL
 169         #define SQ_PSN_SEARCH_EXT_START_PSN_SFT                     0
 170         #define SQ_PSN_SEARCH_EXT_OPCODE_MASK                       0xff000000UL
 171         #define SQ_PSN_SEARCH_EXT_OPCODE_SFT                        24
 172         __le32  flags_next_psn;
 173         #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK                     0xffffffUL
 174         #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT                      0
 175         #define SQ_PSN_SEARCH_EXT_FLAGS_MASK                        0xff000000UL
 176         #define SQ_PSN_SEARCH_EXT_FLAGS_SFT                         24
 177         __le16  start_slot_idx;
 178         __le16  reserved16;
 179         __le32  reserved32;
 180 };
 181
 182 /* Send SQ WQE (40 bytes) */
 183 struct sq_send {
 184         u8 wqe_type;
 185         #define SQ_SEND_WQE_TYPE_SEND                              0x0UL
 186         #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD                     0x1UL
 187         #define SQ_SEND_WQE_TYPE_SEND_W_INVALID            0x2UL
 188         u8 flags;
 189         #define SQ_SEND_FLAGS_SIGNAL_COMP                           0x1UL
 190         #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE                    0x2UL
 191         #define SQ_SEND_FLAGS_UC_FENCE                              0x4UL
 192         #define SQ_SEND_FLAGS_SE                                    0x8UL
 193         #define SQ_SEND_FLAGS_INLINE                                0x10UL
 194         u8 wqe_size;
 195         u8 reserved8_1;
 196         __le32 inv_key_or_imm_data;
 197         __le32 length;
 198         __le32 q_key;
 199         __le32 dst_qp;
 200         #define SQ_SEND_DST_QP_MASK                                 0xffffffUL
 201         #define SQ_SEND_DST_QP_SFT                                  0
 202         #define SQ_SEND_RESERVED8_2_MASK                            0xff000000UL
 203         #define SQ_SEND_RESERVED8_2_SFT                     24
 204         __le32 avid;
 205         #define SQ_SEND_AVID_MASK                                   0xfffffUL
 206         #define SQ_SEND_AVID_SFT                                    0
 207         #define SQ_SEND_RESERVED_AVID_MASK                          0xfff00000UL
 208         #define SQ_SEND_RESERVED_AVID_SFT                           20
 209         __le64 reserved64;
 210         __le32 data[24];
 211 };
 212
 213 /* sq_send_hdr (size:256b/32B) */
 214 struct sq_send_hdr {
 215         u8      wqe_type;
 216         u8      flags;
 217         u8      wqe_size;
 218         u8      reserved8_1;
 219         __le32  inv_key_or_imm_data;
 220         __le32  length;
 221         __le32  q_key;
 222         __le32  dst_qp;
 223         __le32  avid;
 224         __le64  reserved64;
 225 };
 226
 227 /* Send Raw Ethernet and QP1 SQ WQE (40 bytes) */
 228 struct sq_send_raweth_qp1 {
 229         u8 wqe_type;
 230         #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND                   0x0UL
 231         u8 flags;
 232         #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP                0x1UL
 233         #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE         0x2UL
 234         #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE                   0x4UL
 235         #define SQ_SEND_RAWETH_QP1_FLAGS_SE                         0x8UL
 236         #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE             0x10UL
 237         u8 wqe_size;
 238         u8 reserved8;
 239         __le16 lflags;
 240         #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM            0x1UL
 241         #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM                 0x2UL
 242         #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC             0x4UL
 243         #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP             0x8UL
 244         #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM               0x10UL
 245         #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_1               0x20UL
 246         #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_2               0x40UL
 247         #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_3               0x80UL
 248         #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC                  0x100UL
 249         #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC                  0x200UL
 250         __le16 cfa_action;
 251         __le32 length;
 252         __le32 reserved32_1;
 253         __le32 cfa_meta;
 254         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK           0xfffUL
 255         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT            0
 256         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE                 0x1000UL
 257         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK           0xe000UL
 258         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT            13
 259         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK          0x70000UL
 260         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT           16
 261         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8    (0x0UL << 16)
 262         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100    (0x1UL << 16)
 263         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100    (0x2UL << 16)
 264         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200    (0x3UL << 16)
 265         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300    (0x4UL << 16)
 266         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG     (0x5UL << 16)
 267         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST      \
 268                                 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG
 269         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK     0xff80000UL
 270         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT      19
 271         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK                0xf0000000UL
 272         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT                 28
 273         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE               (0x0UL << 28)
 274         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG           (0x1UL << 28)
 275         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST            \
 276                                 SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG
 277         __le32 reserved32_2;
 278         __le64 reserved64;
 279         __le32 data[24];
 280 };
 281
 282 /* sq_send_raweth_qp1_hdr (size:256b/32B) */
 283 struct sq_send_raweth_qp1_hdr {
 284         u8      wqe_type;
 285         u8      flags;
 286         u8      wqe_size;
 287         u8      reserved8;
 288         __le16  lflags;
 289         __le16  cfa_action;
 290         __le32  length;
 291         __le32  reserved32_1;
 292         __le32  cfa_meta;
 293         __le32  reserved32_2;
 294         __le64  reserved64;
 295 };
 296
 297 /* RDMA SQ WQE (40 bytes) */
 298 struct sq_rdma {
 299         u8 wqe_type;
 300         #define SQ_RDMA_WQE_TYPE_WRITE_WQE                         0x4UL
 301         #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD            0x5UL
 302         #define SQ_RDMA_WQE_TYPE_READ_WQE                          0x6UL
 303         u8 flags;
 304         #define SQ_RDMA_FLAGS_SIGNAL_COMP                           0x1UL
 305         #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE                    0x2UL
 306         #define SQ_RDMA_FLAGS_UC_FENCE                              0x4UL
 307         #define SQ_RDMA_FLAGS_SE                                    0x8UL
 308         #define SQ_RDMA_FLAGS_INLINE                                0x10UL
 309         u8 wqe_size;
 310         u8 reserved8;
 311         __le32 imm_data;
 312         __le32 length;
 313         __le32 reserved32_1;
 314         __le64 remote_va;
 315         __le32 remote_key;
 316         __le32 reserved32_2;
 317         __le32 data[24];
 318 };
 319
 320 /* sq_rdma_hdr (size:256b/32B) */
 321 struct sq_rdma_hdr {
 322         u8      wqe_type;
 323         u8      flags;
 324         u8      wqe_size;
 325         u8      reserved8;
 326         __le32  imm_data;
 327         __le32  length;
 328         __le32  reserved32_1;
 329         __le64  remote_va;
 330         __le32  remote_key;
 331         __le32  reserved32_2;
 332 };
 333
 334 /* Atomic SQ WQE (40 bytes) */
 335 struct sq_atomic {
 336         u8 wqe_type;
 337         #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS                       0x8UL
 338         #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA                       0xbUL
 339         u8 flags;
 340         #define SQ_ATOMIC_FLAGS_SIGNAL_COMP                         0x1UL
 341         #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE                  0x2UL
 342         #define SQ_ATOMIC_FLAGS_UC_FENCE                            0x4UL
 343         #define SQ_ATOMIC_FLAGS_SE                                  0x8UL
 344         #define SQ_ATOMIC_FLAGS_INLINE                              0x10UL
 345         __le16 reserved16;
 346         __le32 remote_key;
 347         __le64 remote_va;
 348         __le64 swap_data;
 349         __le64 cmp_data;
 350         __le32 data[24];
 351 };
 352
 353 /* sq_atomic_hdr (size:256b/32B) */
 354 struct sq_atomic_hdr {
 355         u8      wqe_type;
 356         u8      flags;
 357         __le16  reserved16;
 358         __le32  remote_key;
 359         __le64  remote_va;
 360         __le64  swap_data;
 361         __le64  cmp_data;
 362 };
 363
 364 /* Local Invalidate SQ WQE (40 bytes) */
 365 struct sq_localinvalidate {
 366         u8 wqe_type;
 367         #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID          0xcUL
 368         u8 flags;
 369         #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP                0x1UL
 370         #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE         0x2UL
 371         #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE                   0x4UL
 372         #define SQ_LOCALINVALIDATE_FLAGS_SE                         0x8UL
 373         #define SQ_LOCALINVALIDATE_FLAGS_INLINE             0x10UL
 374         __le16 reserved16;
 375         __le32 inv_l_key;
 376         __le64 reserved64;
 377         __le32 reserved128[4];
 378         __le32 data[24];
 379 };
 380
 381 /* sq_localinvalidate_hdr (size:256b/32B) */
 382 struct sq_localinvalidate_hdr {
 383         u8      wqe_type;
 384         u8      flags;
 385         __le16  reserved16;
 386         __le32  inv_l_key;
 387         __le64  reserved64;
 388         u8      reserved128[16];
 389 };
 390
 391 /* FR-PMR SQ WQE (40 bytes) */
 392 struct sq_fr_pmr {
 393         u8 wqe_type;
 394         #define SQ_FR_PMR_WQE_TYPE_FR_PMR                          0xdUL
 395         u8 flags;
 396         #define SQ_FR_PMR_FLAGS_SIGNAL_COMP                         0x1UL
 397         #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE                  0x2UL
 398         #define SQ_FR_PMR_FLAGS_UC_FENCE                            0x4UL
 399         #define SQ_FR_PMR_FLAGS_SE                                  0x8UL
 400         #define SQ_FR_PMR_FLAGS_INLINE                              0x10UL
 401         u8 access_cntl;
 402         #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE                   0x1UL
 403         #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ                   0x2UL
 404         #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE                  0x4UL
 405         #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC                 0x8UL
 406         #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND                   0x10UL
 407         u8 zero_based_page_size_log;
 408         #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK                        0x1fUL
 409         #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT                         0
 410         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K            0x0UL
 411         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K            0x1UL
 412         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K                   0x4UL
 413         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K                  0x6UL
 414         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M            0x8UL
 415         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M            0x9UL
 416         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M            0xaUL
 417         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G            0x12UL
 418         #define SQ_FR_PMR_ZERO_BASED                                0x20UL
 419         #define SQ_FR_PMR_RESERVED2_MASK                            0xc0UL
 420         #define SQ_FR_PMR_RESERVED2_SFT                     6
 421         __le32 l_key;
 422         u8 length[5];
 423         u8 reserved8_1;
 424         u8 reserved8_2;
 425         u8 numlevels_pbl_page_size_log;
 426         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK                    0x1fUL
 427         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT             0
 428         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K                0x0UL
 429         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K                0x1UL
 430         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K               0x4UL
 431         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K              0x6UL
 432         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M                0x8UL
 433         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M                0x9UL
 434         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M                0xaUL
 435         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G                0x12UL
 436         #define SQ_FR_PMR_RESERVED1                                 0x20UL
 437         #define SQ_FR_PMR_NUMLEVELS_MASK                            0xc0UL
 438         #define SQ_FR_PMR_NUMLEVELS_SFT                     6
 439         #define SQ_FR_PMR_NUMLEVELS_PHYSICAL                       (0x0UL << 6)
 440         #define SQ_FR_PMR_NUMLEVELS_LAYER1                         (0x1UL << 6)
 441         #define SQ_FR_PMR_NUMLEVELS_LAYER2                         (0x2UL << 6)
 442         __le64 pblptr;
 443         __le64 va;
 444         __le32 data[24];
 445 };
 446
 447 /* sq_fr_pmr_hdr (size:256b/32B) */
 448 struct sq_fr_pmr_hdr {
 449         u8      wqe_type;
 450         u8      flags;
 451         u8      access_cntl;
 452         u8      zero_based_page_size_log;
 453         __le32  l_key;
 454         u8      length[5];
 455         u8      reserved8_1;
 456         u8      reserved8_2;
 457         u8      numlevels_pbl_page_size_log;
 458         __le64  pblptr;
 459         __le64  va;
 460 };
 461
 462 /* Bind SQ WQE (40 bytes) */
 463 struct sq_bind {
 464         u8 wqe_type;
 465         #define SQ_BIND_WQE_TYPE_BIND                              0xeUL
 466         u8 flags;
 467         #define SQ_BIND_FLAGS_SIGNAL_COMP                           0x1UL
 468         #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE                    0x2UL
 469         #define SQ_BIND_FLAGS_UC_FENCE                              0x4UL
 470         #define SQ_BIND_FLAGS_SE                                    0x8UL
 471         #define SQ_BIND_FLAGS_INLINE                                0x10UL
 472         u8 access_cntl;
 473         #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE             0x1UL
 474         #define SQ_BIND_ACCESS_CNTL_REMOTE_READ             0x2UL
 475         #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE                    0x4UL
 476         #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC                   0x8UL
 477         #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND             0x10UL
 478         u8 reserved8_1;
 479         u8 mw_type_zero_based;
 480         #define SQ_BIND_ZERO_BASED                                  0x1UL
 481         #define SQ_BIND_MW_TYPE                             0x2UL
 482         #define SQ_BIND_MW_TYPE_TYPE1                              (0x0UL << 1)
 483         #define SQ_BIND_MW_TYPE_TYPE2                              (0x1UL << 1)
 484         #define SQ_BIND_RESERVED6_MASK                              0xfcUL
 485         #define SQ_BIND_RESERVED6_SFT                               2
 486         u8 reserved8_2;
 487         __le16 reserved16;
 488         __le32 parent_l_key;
 489         __le32 l_key;
 490         __le64 va;
 491         u8 length[5];
 492         u8 data_reserved24[99];
 493         #define SQ_BIND_RESERVED24_MASK                     0xffffff00UL
 494         #define SQ_BIND_RESERVED24_SFT                              8
 495         #define SQ_BIND_DATA_MASK                                   0xffffffffUL
 496         #define SQ_BIND_DATA_SFT                                    0
 497 };
 498
 499 /* sq_bind_hdr (size:256b/32B) */
 500 struct sq_bind_hdr {
 501         u8      wqe_type;
 502         u8      flags;
 503         u8      access_cntl;
 504         u8      reserved8_1;
 505         u8      mw_type_zero_based;
 506         u8      reserved8_2;
 507         __le16  reserved16;
 508         __le32  parent_l_key;
 509         __le32  l_key;
 510         __le64  va;
 511         u8      length[5];
 512         u8      reserved24[3];
 513 };
 514
 515 /* RQ/SRQ WQE Structures */
 516 /* RQ/SRQ WQE (40 bytes) */
 517 struct rq_wqe {
 518         u8 wqe_type;
 519         #define RQ_WQE_WQE_TYPE_RCV                                0x80UL
 520         u8 flags;
 521         u8 wqe_size;
 522         u8 reserved8;
 523         __le32 reserved32;
 524         __le32 wr_id[2];
 525         #define RQ_WQE_WR_ID_MASK                                   0xfffffUL
 526         #define RQ_WQE_WR_ID_SFT                                    0
 527         #define RQ_WQE_RESERVED44_MASK                              0xfff00000UL
 528         #define RQ_WQE_RESERVED44_SFT                               20
 529         __le32 reserved128[4];
 530         __le32 data[24];
 531 };
 532
 533 /* rq_wqe_hdr (size:256b/32B) */
 534 struct rq_wqe_hdr {
 535         u8      wqe_type;
 536         u8      flags;
 537         u8      wqe_size;
 538         u8      reserved8;
 539         __le32  reserved32;
 540         __le32  wr_id[2];
 541         u8      reserved128[16];
 542 };
 543
 544 /* CQ CQE Structures */
 545 /* Base CQE (32 bytes) */
 546 struct cq_base {
 547         __le64 reserved64_1;
 548         __le64 reserved64_2;
 549         __le64 reserved64_3;
 550         u8 cqe_type_toggle;
 551         #define CQ_BASE_TOGGLE                                      0x1UL
 552         #define CQ_BASE_CQE_TYPE_MASK                               0x1eUL
 553         #define CQ_BASE_CQE_TYPE_SFT                                1
 554         #define CQ_BASE_CQE_TYPE_REQ                               (0x0UL << 1)
 555         #define CQ_BASE_CQE_TYPE_RES_RC                    (0x1UL << 1)
 556         #define CQ_BASE_CQE_TYPE_RES_UD                    (0x2UL << 1)
 557         #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1            (0x3UL << 1)
 558         #define CQ_BASE_CQE_TYPE_TERMINAL                          (0xeUL << 1)
 559         #define CQ_BASE_CQE_TYPE_CUT_OFF                           (0xfUL << 1)
 560         #define CQ_BASE_RESERVED3_MASK                              0xe0UL
 561         #define CQ_BASE_RESERVED3_SFT                               5
 562         u8 status;
 563         __le16 reserved16;
 564         __le32 reserved32;
 565 };
 566
 567 /* Requester CQ CQE (32 bytes) */
 568 struct cq_req {
 569         __le64 qp_handle;
 570         __le16 sq_cons_idx;
 571         __le16 reserved16_1;
 572         __le32 reserved32_2;
 573         __le64 reserved64;
 574         u8 cqe_type_toggle;
 575         #define CQ_REQ_TOGGLE                                       0x1UL
 576         #define CQ_REQ_CQE_TYPE_MASK                                0x1eUL
 577         #define CQ_REQ_CQE_TYPE_SFT                                 1
 578         #define CQ_REQ_CQE_TYPE_REQ                                (0x0UL << 1)
 579         #define CQ_REQ_RESERVED3_MASK                               0xe0UL
 580         #define CQ_REQ_RESERVED3_SFT                                5
 581         u8 status;
 582         #define CQ_REQ_STATUS_OK                                   0x0UL
 583         #define CQ_REQ_STATUS_BAD_RESPONSE_ERR                     0x1UL
 584         #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR                     0x2UL
 585         #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR               0x3UL
 586         #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR                 0x4UL
 587         #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR             0x5UL
 588         #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR           0x6UL
 589         #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR            0x7UL
 590         #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR                 0x8UL
 591         #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR                0x9UL
 592         #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR              0xaUL
 593         #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR             0xbUL
 594         __le16 reserved16_2;
 595         __le32 reserved32_1;
 596 };
 597
 598 /* Responder RC CQE (32 bytes) */
 599 struct cq_res_rc {
 600         __le32 length;
 601         __le32 imm_data_or_inv_r_key;
 602         __le64 qp_handle;
 603         __le64 mr_handle;
 604         u8 cqe_type_toggle;
 605         #define CQ_RES_RC_TOGGLE                                    0x1UL
 606         #define CQ_RES_RC_CQE_TYPE_MASK                     0x1eUL
 607         #define CQ_RES_RC_CQE_TYPE_SFT                              1
 608         #define CQ_RES_RC_CQE_TYPE_RES_RC                          (0x1UL << 1)
 609         #define CQ_RES_RC_RESERVED3_MASK                            0xe0UL
 610         #define CQ_RES_RC_RESERVED3_SFT                     5
 611         u8 status;
 612         #define CQ_RES_RC_STATUS_OK                                0x0UL
 613         #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR                0x1UL
 614         #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR                  0x2UL
 615         #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR              0x3UL
 616         #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR    0x4UL
 617         #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR          0x5UL
 618         #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR       0x6UL
 619         #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR          0x7UL
 620         #define CQ_RES_RC_STATUS_HW_FLUSH_ERR                      0x8UL
 621         __le16 flags;
 622         #define CQ_RES_RC_FLAGS_SRQ                                 0x1UL
 623         #define CQ_RES_RC_FLAGS_SRQ_RQ                             (0x0UL << 0)
 624         #define CQ_RES_RC_FLAGS_SRQ_SRQ                    (0x1UL << 0)
 625         #define CQ_RES_RC_FLAGS_SRQ_LAST    CQ_RES_RC_FLAGS_SRQ_SRQ
 626         #define CQ_RES_RC_FLAGS_IMM                                 0x2UL
 627         #define CQ_RES_RC_FLAGS_INV                                 0x4UL
 628         #define CQ_RES_RC_FLAGS_RDMA                                0x8UL
 629         #define CQ_RES_RC_FLAGS_RDMA_SEND                          (0x0UL << 3)
 630         #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE            (0x1UL << 3)
 631         #define CQ_RES_RC_FLAGS_RDMA_LAST    CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE
 632         __le32 srq_or_rq_wr_id;
 633         #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK                      0xfffffUL
 634         #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT                       0
 635         #define CQ_RES_RC_RESERVED12_MASK                           0xfff00000UL
 636         #define CQ_RES_RC_RESERVED12_SFT                            20
 637 };
 638
 639 /* Responder UD CQE (32 bytes) */
 640 struct cq_res_ud {
 641         __le16 length;
 642         #define CQ_RES_UD_LENGTH_MASK                               0x3fffUL
 643         #define CQ_RES_UD_LENGTH_SFT                                0
 644         __le16 cfa_metadata;
 645         #define CQ_RES_UD_CFA_METADATA_VID_MASK                 0xfffUL
 646         #define CQ_RES_UD_CFA_METADATA_VID_SFT                  0
 647         #define CQ_RES_UD_CFA_METADATA_DE                       0x1000UL
 648         #define CQ_RES_UD_CFA_METADATA_PRI_MASK                 0xe000UL
 649         #define CQ_RES_UD_CFA_METADATA_PRI_SFT                  13
 650         __le32 imm_data;
 651         __le64 qp_handle;
 652         __le16 src_mac[3];
 653         __le16 src_qp_low;
 654         u8 cqe_type_toggle;
 655         #define CQ_RES_UD_TOGGLE                                   0x1UL
 656         #define CQ_RES_UD_CQE_TYPE_MASK                            0x1eUL
 657         #define CQ_RES_UD_CQE_TYPE_SFT                             1
 658         #define CQ_RES_UD_CQE_TYPE_RES_UD                          (0x2UL << 1)
 659         u8 status;
 660         #define CQ_RES_UD_STATUS_OK                                0x0UL
 661         #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR                0x1UL
 662         #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR               0x2UL
 663         #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR              0x3UL
 664         #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR    0x4UL
 665         #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR          0x5UL
 666         #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR          0x7UL
 667         #define CQ_RES_UD_STATUS_HW_FLUSH_ERR                      0x8UL
 668         __le16 flags;
 669         #define CQ_RES_UD_FLAGS_SRQ                                 0x1UL
 670         #define CQ_RES_UD_FLAGS_SRQ_RQ                             (0x0UL << 0)
 671         #define CQ_RES_UD_FLAGS_SRQ_SRQ                    (0x1UL << 0)
 672         #define CQ_RES_UD_FLAGS_SRQ_LAST    CQ_RES_UD_FLAGS_SRQ_SRQ
 673         #define CQ_RES_UD_FLAGS_IMM                                 0x2UL
 674         #define CQ_RES_UD_FLAGS_UNUSED_MASK                     0xcUL
 675         #define CQ_RES_UD_FLAGS_UNUSED_SFT                      2
 676         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK                0x30UL
 677         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT                 4
 678         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1                  (0x0UL << 4)
 679         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4              (0x2UL << 4)
 680         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6              (0x3UL << 4)
 681         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST                \
 682                                         CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
 683         #define CQ_RES_UD_FLAGS_META_FORMAT_MASK                0x3c0UL
 684         #define CQ_RES_UD_FLAGS_META_FORMAT_SFT                 6
 685         #define CQ_RES_UD_FLAGS_META_FORMAT_NONE                (0x0UL << 6)
 686         #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN                (0x1UL << 6)
 687         #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID           (0x2UL << 6)
 688         #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA           (0x3UL << 6)
 689         #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET          (0x4UL << 6)
 690         #define CQ_RES_UD_FLAGS_META_FORMAT_LAST                \
 691                                         CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET
 692         #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK            0xc00UL
 693         #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT             10
 694
 695         __le32 src_qp_high_srq_or_rq_wr_id;
 696         #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK                      0xfffffUL
 697         #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT                       0
 698         #define CQ_RES_UD_SRC_QP_HIGH_MASK                          0xff000000UL
 699         #define CQ_RES_UD_SRC_QP_HIGH_SFT                           24
 700 };
 701
 702 /* Responder RawEth and QP1 CQE (32 bytes) */
 703 struct cq_res_raweth_qp1 {
 704         __le16 length;
 705         #define CQ_RES_RAWETH_QP1_LENGTH_MASK                       0x3fffUL
 706         #define CQ_RES_RAWETH_QP1_LENGTH_SFT                        0
 707         #define CQ_RES_RAWETH_QP1_RESERVED2_MASK                    0xc000UL
 708         #define CQ_RES_RAWETH_QP1_RESERVED2_SFT             14
 709         __le16 raweth_qp1_flags;
 710         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR            0x1UL
 711         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_MASK 0x3eUL
 712         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_SFT 1
 713         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK      0x3c0UL
 714         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT       6
 715         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
 716         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP       (0x1UL << 6)
 717         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP      (0x2UL << 6)
 718         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP      (0x3UL << 6)
 719         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE     (0x4UL << 6)
 720         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE     (0x5UL << 6)
 721         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP     (0x7UL << 6)
 722         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
 723                                                                  (0x8UL << 6)
 724         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP \
 725                                                                  (0x9UL << 6)
 726         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST   \
 727                 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
 728         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK     0x3ffUL
 729         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT              0
 730         #define CQ_RES_RAWETH_QP1_RESERVED6_MASK                    0xfc00UL
 731         #define CQ_RES_RAWETH_QP1_RESERVED6_SFT             10
 732         __le16 raweth_qp1_errors;
 733         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_MASK 0xfUL
 734         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_SFT  0
 735         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR    0x10UL
 736         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR    0x20UL
 737         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR  0x40UL
 738         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR  0x80UL
 739         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR      0x100UL
 740         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
 741         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
 742         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR \
 743                                                                 (0x0UL << 9)
 744         #define \
 745            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
 746                                                                 (0x1UL << 9)
 747         #define \
 748            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
 749                                                                 (0x2UL << 9)
 750         #define \
 751            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
 752                                                                 (0x3UL << 9)
 753         #define \
 754            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
 755                                                                 (0x4UL << 9)
 756         #define \
 757            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
 758                                                                 (0x5UL << 9)
 759         #define \
 760            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
 761                                                                 (0x6UL << 9)
 762         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \
 763                 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
 764         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
 765         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT  12
 766         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR \
 767                                                                 (0x0UL << 12)
 768         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION \
 769                                                                 (0x1UL << 12)
 770         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
 771                                                                  (0x2UL << 12)
 772         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL \
 773                                                                  (0x3UL << 12)
 774         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
 775                                                                  (0x4UL << 12)
 776         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
 777                                                                  (0x5UL << 12)
 778         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
 779                                                                  (0x6UL << 12)
 780         #define \
 781          CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL\
 782                                                                  (0x7UL << 12)
 783         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
 784                                                                  (0x8UL << 12)
 785         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \
 786                 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
 787         __le16 raweth_qp1_cfa_code;
 788         __le64 qp_handle;
 789         __le32 raweth_qp1_flags2;
 790         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC     0x1UL
 791         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC     0x2UL
 792         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC   0x4UL
 793         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC   0x8UL
 794         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
 795         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
 796         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE \
 797                                                                 (0x0UL << 4)
 798         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN \
 799                                                                 (0x1UL << 4)
 800         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST\
 801                         CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN
 802         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE         0x100UL
 803         __le32 raweth_qp1_metadata;
 804         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK     0xfffUL
 805         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT      0
 806         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE            0x1000UL
 807         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK     0xe000UL
 808         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT      13
 809         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK    0xffff0000UL
 810         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT     16
 811         u8 cqe_type_toggle;
 812         #define CQ_RES_RAWETH_QP1_TOGGLE                            0x1UL
 813         #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK             0x1eUL
 814         #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT                      1
 815         #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1          (0x3UL << 1)
 816         #define CQ_RES_RAWETH_QP1_RESERVED3_MASK                    0xe0UL
 817         #define CQ_RES_RAWETH_QP1_RESERVED3_SFT             5
 818         u8 status;
 819         #define CQ_RES_RAWETH_QP1_STATUS_OK                        0x0UL
 820         #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR       0x1UL
 821         #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR      0x2UL
 822         #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR     0x3UL
 823         #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR   0x4UL
 824         #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
 825         #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
 826         #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR              0x8UL
 827         __le16 flags;
 828         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ                         0x1UL
 829         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ                     0x0UL
 830         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ            0x1UL
 831         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST \
 832                                         CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ
 833         __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
 834         #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK              0xfffffUL
 835         #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT               0
 836         #define CQ_RES_RAWETH_QP1_RESERVED4_MASK                    0xf00000UL
 837         #define CQ_RES_RAWETH_QP1_RESERVED4_SFT             20
 838         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK   0xff000000UL
 839         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT    24
 840 };
 841
 842 /* Terminal CQE (32 bytes) */
 843 struct cq_terminal {
 844         __le64 qp_handle;
 845         __le16 sq_cons_idx;
 846         __le16 rq_cons_idx;
 847         __le32 reserved32_1;
 848         __le64 reserved64_3;
 849         u8 cqe_type_toggle;
 850         #define CQ_TERMINAL_TOGGLE                                  0x1UL
 851         #define CQ_TERMINAL_CQE_TYPE_MASK                           0x1eUL
 852         #define CQ_TERMINAL_CQE_TYPE_SFT                            1
 853         #define CQ_TERMINAL_CQE_TYPE_TERMINAL                      (0xeUL << 1)
 854         #define CQ_TERMINAL_RESERVED3_MASK                          0xe0UL
 855         #define CQ_TERMINAL_RESERVED3_SFT                           5
 856         u8 status;
 857         #define CQ_TERMINAL_STATUS_OK                              0x0UL
 858         __le16 reserved16;
 859         __le32 reserved32_2;
 860 };
 861
 862 /* Cutoff CQE (32 bytes) */
 863 struct cq_cutoff {
 864         __le64 reserved64_1;
 865         __le64 reserved64_2;
 866         __le64 reserved64_3;
 867         u8 cqe_type_toggle;
 868         #define CQ_CUTOFF_TOGGLE                                    0x1UL
 869         #define CQ_CUTOFF_CQE_TYPE_MASK                     0x1eUL
 870         #define CQ_CUTOFF_CQE_TYPE_SFT                              1
 871         #define CQ_CUTOFF_CQE_TYPE_CUT_OFF                         (0xfUL << 1)
 872         #define CQ_CUTOFF_RESERVED3_MASK                            0xe0UL
 873         #define CQ_CUTOFF_RESERVED3_SFT                     5
 874         u8 status;
 875         #define CQ_CUTOFF_STATUS_OK                                0x0UL
 876         __le16 reserved16;
 877         __le32 reserved32;
 878 };
 879
 880 /* Notification Queue (NQ) Structures */
 881 /* Base NQ Record (16 bytes) */
 882 struct nq_base {
 883         __le16 info10_type;
 884         #define NQ_BASE_TYPE_MASK                                   0x3fUL
 885         #define NQ_BASE_TYPE_SFT                                    0
 886         #define NQ_BASE_TYPE_CQ_NOTIFICATION                       0x30UL
 887         #define NQ_BASE_TYPE_SRQ_EVENT                             0x32UL
 888         #define NQ_BASE_TYPE_DBQ_EVENT                             0x34UL
 889         #define NQ_BASE_TYPE_QP_EVENT                              0x38UL
 890         #define NQ_BASE_TYPE_FUNC_EVENT                    0x3aUL
 891         #define NQ_BASE_INFO10_MASK                                 0xffc0UL
 892         #define NQ_BASE_INFO10_SFT                                  6
 893         __le16 info16;
 894         __le32 info32;
 895         __le32 info63_v[2];
 896         #define NQ_BASE_V                                           0x1UL
 897         #define NQ_BASE_INFO63_MASK                                 0xfffffffeUL
 898         #define NQ_BASE_INFO63_SFT                                  1
 899 };
 900
 901 /* Completion Queue Notification (16 bytes) */
 902 struct nq_cn {
 903         __le16 type;
 904         #define NQ_CN_TYPE_MASK                             0x3fUL
 905         #define NQ_CN_TYPE_SFT                                      0
 906         #define NQ_CN_TYPE_CQ_NOTIFICATION                         0x30UL
 907         #define NQ_CN_RESERVED9_MASK                                0xffc0UL
 908         #define NQ_CN_RESERVED9_SFT                                 6
 909         __le16 reserved16;
 910         __le32 cq_handle_low;
 911         __le32 v;
 912         #define NQ_CN_V                                     0x1UL
 913         #define NQ_CN_RESERVED31_MASK                               0xfffffffeUL
 914         #define NQ_CN_RESERVED31_SFT                                1
 915         __le32 cq_handle_high;
 916 };
 917
 918 /* SRQ Event Notification (16 bytes) */
 919 struct nq_srq_event {
 920         u8 type;
 921         #define NQ_SRQ_EVENT_TYPE_MASK                              0x3fUL
 922         #define NQ_SRQ_EVENT_TYPE_SFT                               0
 923         #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT                        0x32UL
 924         #define NQ_SRQ_EVENT_RESERVED1_MASK                         0xc0UL
 925         #define NQ_SRQ_EVENT_RESERVED1_SFT                          6
 926         u8 event;
 927         #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT             0x1UL
 928         __le16 reserved16;
 929         __le32 srq_handle_low;
 930         __le32 v;
 931         #define NQ_SRQ_EVENT_V                                      0x1UL
 932         #define NQ_SRQ_EVENT_RESERVED31_MASK                        0xfffffffeUL
 933         #define NQ_SRQ_EVENT_RESERVED31_SFT                         1
 934         __le32 srq_handle_high;
 935 };
 936
 937 /* DBQ Async Event Notification (16 bytes) */
 938 struct nq_dbq_event {
 939         u8 type;
 940         #define NQ_DBQ_EVENT_TYPE_MASK                              0x3fUL
 941         #define NQ_DBQ_EVENT_TYPE_SFT                               0
 942         #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT                        0x34UL
 943         #define NQ_DBQ_EVENT_RESERVED1_MASK                         0xc0UL
 944         #define NQ_DBQ_EVENT_RESERVED1_SFT                          6
 945         u8 event;
 946         #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT             0x1UL
 947         __le16 db_pfid;
 948         #define NQ_DBQ_EVENT_DB_PFID_MASK                           0xfUL
 949         #define NQ_DBQ_EVENT_DB_PFID_SFT                            0
 950         #define NQ_DBQ_EVENT_RESERVED12_MASK                        0xfff0UL
 951         #define NQ_DBQ_EVENT_RESERVED12_SFT                         4
 952         __le32 db_dpi;
 953         #define NQ_DBQ_EVENT_DB_DPI_MASK                            0xfffffUL
 954         #define NQ_DBQ_EVENT_DB_DPI_SFT                     0
 955         #define NQ_DBQ_EVENT_RESERVED12_2_MASK                      0xfff00000UL
 956         #define NQ_DBQ_EVENT_RESERVED12_2_SFT                       20
 957         __le32 v;
 958         #define NQ_DBQ_EVENT_V                                      0x1UL
 959         #define NQ_DBQ_EVENT_RESERVED32_MASK                        0xfffffffeUL
 960         #define NQ_DBQ_EVENT_RESERVED32_SFT                         1
 961         __le32 db_type_db_xid;
 962         #define NQ_DBQ_EVENT_DB_XID_MASK                            0xfffffUL
 963         #define NQ_DBQ_EVENT_DB_XID_SFT                     0
 964         #define NQ_DBQ_EVENT_RESERVED8_MASK                         0xff00000UL
 965         #define NQ_DBQ_EVENT_RESERVED8_SFT                          20
 966         #define NQ_DBQ_EVENT_DB_TYPE_MASK                           0xf0000000UL
 967         #define NQ_DBQ_EVENT_DB_TYPE_SFT                            28
 968 };
 969
 970 /* Read Request/Response Queue Structures */
 971 /* Input Read Request Queue (IRRQ) Message (32 bytes) */
 972 struct xrrq_irrq {
 973         __le16 credits_type;
 974         #define XRRQ_IRRQ_TYPE                                      0x1UL
 975         #define XRRQ_IRRQ_TYPE_READ_REQ                    0x0UL
 976         #define XRRQ_IRRQ_TYPE_ATOMIC_REQ                          0x1UL
 977         #define XRRQ_IRRQ_RESERVED10_MASK                           0x7feUL
 978         #define XRRQ_IRRQ_RESERVED10_SFT                            1
 979         #define XRRQ_IRRQ_CREDITS_MASK                              0xf800UL
 980         #define XRRQ_IRRQ_CREDITS_SFT                               11
 981         __le16 reserved16;
 982         __le32 reserved32;
 983         __le32 psn;
 984         #define XRRQ_IRRQ_PSN_MASK                                  0xffffffUL
 985         #define XRRQ_IRRQ_PSN_SFT                                   0
 986         #define XRRQ_IRRQ_RESERVED8_1_MASK                          0xff000000UL
 987         #define XRRQ_IRRQ_RESERVED8_1_SFT                           24
 988         __le32 msn;
 989         #define XRRQ_IRRQ_MSN_MASK                                  0xffffffUL
 990         #define XRRQ_IRRQ_MSN_SFT                                   0
 991         #define XRRQ_IRRQ_RESERVED8_2_MASK                          0xff000000UL
 992         #define XRRQ_IRRQ_RESERVED8_2_SFT                           24
 993         __le64 va_or_atomic_result;
 994         __le32 rdma_r_key;
 995         __le32 length;
 996 };
 997
 998 /* Output Read Request Queue (ORRQ) Message (32 bytes) */
 999 struct xrrq_orrq {
1000         __le16 num_sges_type;
1001         #define XRRQ_ORRQ_TYPE                                      0x1UL
1002         #define XRRQ_ORRQ_TYPE_READ_REQ                    0x0UL
1003         #define XRRQ_ORRQ_TYPE_ATOMIC_REQ                          0x1UL
1004         #define XRRQ_ORRQ_RESERVED10_MASK                           0x7feUL
1005         #define XRRQ_ORRQ_RESERVED10_SFT                            1
1006         #define XRRQ_ORRQ_NUM_SGES_MASK                     0xf800UL
1007         #define XRRQ_ORRQ_NUM_SGES_SFT                              11
1008         __le16 reserved16;
1009         __le32 length;
1010         __le32 psn;
1011         #define XRRQ_ORRQ_PSN_MASK                                  0xffffffUL
1012         #define XRRQ_ORRQ_PSN_SFT                                   0
1013         #define XRRQ_ORRQ_RESERVED8_1_MASK                          0xff000000UL
1014         #define XRRQ_ORRQ_RESERVED8_1_SFT                           24
1015         __le32 end_psn;
1016         #define XRRQ_ORRQ_END_PSN_MASK                              0xffffffUL
1017         #define XRRQ_ORRQ_END_PSN_SFT                               0
1018         #define XRRQ_ORRQ_RESERVED8_2_MASK                          0xff000000UL
1019         #define XRRQ_ORRQ_RESERVED8_2_SFT                           24
1020         __le64 first_sge_phy_or_sing_sge_va;
1021         __le32 single_sge_l_key;
1022         __le32 single_sge_size;
1023 };
1024
1025 /* Page Buffer List Memory Structures (PBL) */
1026 /* Page Table Entry (PTE) (8 bytes) */
1027 struct ptu_pte {
1028         __le32 page_next_to_last_last_valid[2];
1029         #define PTU_PTE_VALID                                       0x1UL
1030         #define PTU_PTE_LAST                                        0x2UL
1031         #define PTU_PTE_NEXT_TO_LAST                                0x4UL
1032         #define PTU_PTE_PAGE_MASK                                   0xfffff000UL
1033         #define PTU_PTE_PAGE_SFT                                    12
1034 };
1035
1036 /* Page Directory Entry (PDE) (8 bytes) */
1037 struct ptu_pde {
1038         __le32 page_valid[2];
1039         #define PTU_PDE_VALID                                       0x1UL
1040         #define PTU_PDE_PAGE_MASK                                   0xfffff000UL
1041         #define PTU_PDE_PAGE_SFT                                    12
1042 };
1043
1044 /* RoCE Fastpath Host Structures */
1045 /* Command Queue (CMDQ) Interface */
1046 /* Init CMDQ (16 bytes) */
1047 struct cmdq_init {
1048         __le64 cmdq_pbl;
1049         __le16 cmdq_size_cmdq_lvl;
1050         #define CMDQ_INIT_CMDQ_LVL_MASK                     0x3UL
1051         #define CMDQ_INIT_CMDQ_LVL_SFT                              0
1052         #define CMDQ_INIT_CMDQ_SIZE_MASK                            0xfffcUL
1053         #define CMDQ_INIT_CMDQ_SIZE_SFT                     2
1054         __le16 creq_ring_id;
1055         __le32 prod_idx;
1056 };
1057
1058 /* Update CMDQ producer index (16 bytes) */
1059 struct cmdq_update {
1060         __le64 reserved64;
1061         __le32 reserved32;
1062         __le32 prod_idx;
1063 };
1064
1065 /* CMDQ common header structure (16 bytes) */
1066 struct cmdq_base {
1067         u8 opcode;
1068         #define CMDQ_BASE_OPCODE_CREATE_QP                         0x1UL
1069         #define CMDQ_BASE_OPCODE_DESTROY_QP                        0x2UL
1070         #define CMDQ_BASE_OPCODE_MODIFY_QP                         0x3UL
1071         #define CMDQ_BASE_OPCODE_QUERY_QP                          0x4UL
1072         #define CMDQ_BASE_OPCODE_CREATE_SRQ                        0x5UL
1073         #define CMDQ_BASE_OPCODE_DESTROY_SRQ                       0x6UL
1074         #define CMDQ_BASE_OPCODE_QUERY_SRQ                         0x8UL
1075         #define CMDQ_BASE_OPCODE_CREATE_CQ                         0x9UL
1076         #define CMDQ_BASE_OPCODE_DESTROY_CQ                        0xaUL
1077         #define CMDQ_BASE_OPCODE_RESIZE_CQ                         0xcUL
1078         #define CMDQ_BASE_OPCODE_ALLOCATE_MRW                      0xdUL
1079         #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY            0xeUL
1080         #define CMDQ_BASE_OPCODE_REGISTER_MR                       0xfUL
1081         #define CMDQ_BASE_OPCODE_DEREGISTER_MR                     0x10UL
1082         #define CMDQ_BASE_OPCODE_ADD_GID                           0x11UL
1083         #define CMDQ_BASE_OPCODE_DELETE_GID                        0x12UL
1084         #define CMDQ_BASE_OPCODE_MODIFY_GID                        0x17UL
1085         #define CMDQ_BASE_OPCODE_QUERY_GID                         0x18UL
1086         #define CMDQ_BASE_OPCODE_CREATE_QP1                        0x13UL
1087         #define CMDQ_BASE_OPCODE_DESTROY_QP1                       0x14UL
1088         #define CMDQ_BASE_OPCODE_CREATE_AH                         0x15UL
1089         #define CMDQ_BASE_OPCODE_DESTROY_AH                        0x16UL
1090         #define CMDQ_BASE_OPCODE_INITIALIZE_FW                     0x80UL
1091         #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW                   0x81UL
1092         #define CMDQ_BASE_OPCODE_STOP_FUNC                         0x82UL
1093         #define CMDQ_BASE_OPCODE_QUERY_FUNC                        0x83UL
1094         #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES                0x84UL
1095         #define CMDQ_BASE_OPCODE_READ_CONTEXT                      0x85UL
1096         #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST    0x86UL
1097         #define CMDQ_BASE_OPCODE_READ_VF_MEMORY            0x87UL
1098         #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST               0x88UL
1099         #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY             0x89UL
1100         #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS                     0x8aUL
1101         #define CMDQ_BASE_OPCODE_QUERY_VERSION                     0x8bUL
1102         #define CMDQ_BASE_OPCODE_MODIFY_CC                         0x8cUL
1103         #define CMDQ_BASE_OPCODE_QUERY_CC                          0x8dUL
1104         #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS          0x8eUL
1105         u8 cmd_size;
1106         __le16 flags;
1107         __le16 cookie;
1108         u8 resp_size;
1109         u8 reserved8;
1110         __le64 resp_addr;
1111 };
1112
1113 /* Create QP command (96 bytes) */
1114 struct cmdq_create_qp {
1115         u8 opcode;
1116         #define CMDQ_CREATE_QP_OPCODE_CREATE_QP            0x1UL
1117         u8 cmd_size;
1118         __le16 flags;
1119         __le16 cookie;
1120         u8 resp_size;
1121         u8 reserved8;
1122         __le64 resp_addr;
1123         __le64 qp_handle;
1124         __le32 qp_flags;
1125         #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED                   0x1UL
1126         #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION           0x2UL
1127         #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE      0x4UL
1128         #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED             0x8UL
1129         #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL
1130         u8 type;
1131         #define CMDQ_CREATE_QP_TYPE_RC                             0x2UL
1132         #define CMDQ_CREATE_QP_TYPE_UD                             0x4UL
1133         #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE                  0x6UL
1134         #define CMDQ_CREATE_QP_TYPE_GSI                            0x7UL
1135         u8 sq_pg_size_sq_lvl;
1136         #define CMDQ_CREATE_QP_SQ_LVL_MASK                          0xfUL
1137         #define CMDQ_CREATE_QP_SQ_LVL_SFT                           0
1138         #define CMDQ_CREATE_QP_SQ_LVL_LVL_0                        0x0UL
1139         #define CMDQ_CREATE_QP_SQ_LVL_LVL_1                        0x1UL
1140         #define CMDQ_CREATE_QP_SQ_LVL_LVL_2                        0x2UL
1141         #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK                      0xf0UL
1142         #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT                       4
1143         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K            (0x0UL << 4)
1144         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K            (0x1UL << 4)
1145         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K                   (0x2UL << 4)
1146         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M            (0x3UL << 4)
1147         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M            (0x4UL << 4)
1148         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G            (0x5UL << 4)
1149         u8 rq_pg_size_rq_lvl;
1150         #define CMDQ_CREATE_QP_RQ_LVL_MASK                          0xfUL
1151         #define CMDQ_CREATE_QP_RQ_LVL_SFT                           0
1152         #define CMDQ_CREATE_QP_RQ_LVL_LVL_0                        0x0UL
1153         #define CMDQ_CREATE_QP_RQ_LVL_LVL_1                        0x1UL
1154         #define CMDQ_CREATE_QP_RQ_LVL_LVL_2                        0x2UL
1155         #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK                      0xf0UL
1156         #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT                       4
1157         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K            (0x0UL << 4)
1158         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K            (0x1UL << 4)
1159         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K                   (0x2UL << 4)
1160         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M            (0x3UL << 4)
1161         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M            (0x4UL << 4)
1162         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G            (0x5UL << 4)
1163         u8 unused_0;
1164         __le32 dpi;
1165         __le32 sq_size;
1166         __le32 rq_size;
1167         __le16 sq_fwo_sq_sge;
1168         #define CMDQ_CREATE_QP_SQ_SGE_MASK                          0xfUL
1169         #define CMDQ_CREATE_QP_SQ_SGE_SFT                           0
1170         #define CMDQ_CREATE_QP_SQ_FWO_MASK                          0xfff0UL
1171         #define CMDQ_CREATE_QP_SQ_FWO_SFT                           4
1172         __le16 rq_fwo_rq_sge;
1173         #define CMDQ_CREATE_QP_RQ_SGE_MASK                          0xfUL
1174         #define CMDQ_CREATE_QP_RQ_SGE_SFT                           0
1175         #define CMDQ_CREATE_QP_RQ_FWO_MASK                          0xfff0UL
1176         #define CMDQ_CREATE_QP_RQ_FWO_SFT                           4
1177         __le32 scq_cid;
1178         __le32 rcq_cid;
1179         __le32 srq_cid;
1180         __le32 pd_id;
1181         __le64 sq_pbl;
1182         __le64 rq_pbl;
1183         __le64 irrq_addr;
1184         __le64 orrq_addr;
1185 };
1186
1187 /* Destroy QP command (24 bytes) */
1188 struct cmdq_destroy_qp {
1189         u8 opcode;
1190         #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP                  0x2UL
1191         u8 cmd_size;
1192         __le16 flags;
1193         __le16 cookie;
1194         u8 resp_size;
1195         u8 reserved8;
1196         __le64 resp_addr;
1197         __le32 qp_cid;
1198         __le32 unused_0;
1199 };
1200
1201 /* Modify QP command (112 bytes) */
1202 struct cmdq_modify_qp {
1203         u8 opcode;
1204         #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP            0x3UL
1205         u8 cmd_size;
1206         __le16 flags;
1207         __le16 cookie;
1208         u8 resp_size;
1209         u8 reserved8;
1210         __le64 resp_addr;
1211         __le32 modify_mask;
1212         #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE                    0x1UL
1213         #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY     0x2UL
1214         #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS                   0x4UL
1215         #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY             0x8UL
1216         #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY             0x10UL
1217         #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID             0x20UL
1218         #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL               0x40UL
1219         #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX               0x80UL
1220         #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT                0x100UL
1221         #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS            0x200UL
1222         #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC                 0x400UL
1223         #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU                 0x1000UL
1224         #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT                  0x2000UL
1225         #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT                0x4000UL
1226         #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY                0x8000UL
1227         #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN                   0x10000UL
1228         #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC            0x20000UL
1229         #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER            0x40000UL
1230         #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN                   0x80000UL
1231         #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC      0x100000UL
1232         #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE                  0x200000UL
1233         #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE                  0x400000UL
1234         #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE                   0x800000UL
1235         #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE                   0x1000000UL
1236         #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA          0x2000000UL
1237         #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID               0x4000000UL
1238         #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC                  0x8000000UL
1239         #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID                  0x10000000UL
1240         #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC                0x20000000UL
1241         #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN                  0x40000000UL
1242         #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP                 0x80000000UL
1243         __le32 qp_cid;
1244         u8 network_type_en_sqd_async_notify_new_state;
1245         #define CMDQ_MODIFY_QP_NEW_STATE_MASK                       0xfUL
1246         #define CMDQ_MODIFY_QP_NEW_STATE_SFT                        0
1247         #define CMDQ_MODIFY_QP_NEW_STATE_RESET                     0x0UL
1248         #define CMDQ_MODIFY_QP_NEW_STATE_INIT                      0x1UL
1249         #define CMDQ_MODIFY_QP_NEW_STATE_RTR                       0x2UL
1250         #define CMDQ_MODIFY_QP_NEW_STATE_RTS                       0x3UL
1251         #define CMDQ_MODIFY_QP_NEW_STATE_SQD                       0x4UL
1252         #define CMDQ_MODIFY_QP_NEW_STATE_SQE                       0x5UL
1253         #define CMDQ_MODIFY_QP_NEW_STATE_ERR                       0x6UL
1254         #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY                  0x10UL
1255         #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK                    0xc0UL
1256         #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT             6
1257         #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1                 (0x0UL << 6)
1258         #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4    (0x2UL << 6)
1259         #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6    (0x3UL << 6)
1260         u8 access;
1261         #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE                   0x1UL
1262         #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE                  0x2UL
1263         #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ                   0x4UL
1264         #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC                 0x8UL
1265         __le16 pkey;
1266         __le32 qkey;
1267         __le32 dgid[4];
1268         __le32 flow_label;
1269         __le16 sgid_index;
1270         u8 hop_limit;
1271         u8 traffic_class;
1272         __le16 dest_mac[3];
1273         u8 tos_dscp_tos_ecn;
1274         #define CMDQ_MODIFY_QP_TOS_ECN_MASK                         0x3UL
1275         #define CMDQ_MODIFY_QP_TOS_ECN_SFT                          0
1276         #define CMDQ_MODIFY_QP_TOS_DSCP_MASK                        0xfcUL
1277         #define CMDQ_MODIFY_QP_TOS_DSCP_SFT                         2
1278         u8 path_mtu;
1279         #define CMDQ_MODIFY_QP_PATH_MTU_MASK                        0xf0UL
1280         #define CMDQ_MODIFY_QP_PATH_MTU_SFT                         4
1281         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256            (0x0UL << 4)
1282         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512            (0x1UL << 4)
1283         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024                   (0x2UL << 4)
1284         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048                   (0x3UL << 4)
1285         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096                   (0x4UL << 4)
1286         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192                   (0x5UL << 4)
1287         u8 timeout;
1288         u8 retry_cnt;
1289         u8 rnr_retry;
1290         u8 min_rnr_timer;
1291         __le32 rq_psn;
1292         __le32 sq_psn;
1293         u8 max_rd_atomic;
1294         u8 max_dest_rd_atomic;
1295         __le16 enable_cc;
1296         #define CMDQ_MODIFY_QP_ENABLE_CC                            0x1UL
1297         __le32 sq_size;
1298         __le32 rq_size;
1299         __le16 sq_sge;
1300         __le16 rq_sge;
1301         __le32 max_inline_data;
1302         __le32 dest_qp_id;
1303         __le32 unused_3;
1304         __le16 src_mac[3];
1305         __le16 vlan_pcp_vlan_dei_vlan_id;
1306         #define CMDQ_MODIFY_QP_VLAN_ID_MASK                         0xfffUL
1307         #define CMDQ_MODIFY_QP_VLAN_ID_SFT                          0
1308         #define CMDQ_MODIFY_QP_VLAN_DEI                     0x1000UL
1309         #define CMDQ_MODIFY_QP_VLAN_PCP_MASK                        0xe000UL
1310         #define CMDQ_MODIFY_QP_VLAN_PCP_SFT                         13
1311 };
1312
1313 /* Query QP command (24 bytes) */
1314 struct cmdq_query_qp {
1315         u8 opcode;
1316         #define CMDQ_QUERY_QP_OPCODE_QUERY_QP                      0x4UL
1317         u8 cmd_size;
1318         __le16 flags;
1319         __le16 cookie;
1320         u8 resp_size;
1321         u8 reserved8;
1322         __le64 resp_addr;
1323         __le32 qp_cid;
1324         __le32 unused_0;
1325 };
1326
1327 /* Create SRQ command (48 bytes) */
1328 struct cmdq_create_srq {
1329         u8 opcode;
1330         #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ                  0x5UL
1331         u8 cmd_size;
1332         __le16 flags;
1333         __le16 cookie;
1334         u8 resp_size;
1335         u8 reserved8;
1336         __le64 resp_addr;
1337         __le64 srq_handle;
1338         __le16 pg_size_lvl;
1339         #define CMDQ_CREATE_SRQ_LVL_MASK                            0x3UL
1340         #define CMDQ_CREATE_SRQ_LVL_SFT                     0
1341         #define CMDQ_CREATE_SRQ_LVL_LVL_0                          0x0UL
1342         #define CMDQ_CREATE_SRQ_LVL_LVL_1                          0x1UL
1343         #define CMDQ_CREATE_SRQ_LVL_LVL_2                          0x2UL
1344         #define CMDQ_CREATE_SRQ_PG_SIZE_MASK                        0x1cUL
1345         #define CMDQ_CREATE_SRQ_PG_SIZE_SFT                         2
1346         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K                      (0x0UL << 2)
1347         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K                      (0x1UL << 2)
1348         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K                     (0x2UL << 2)
1349         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M                      (0x3UL << 2)
1350         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M                      (0x4UL << 2)
1351         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G                      (0x5UL << 2)
1352         __le16 eventq_id;
1353         #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK                      0xfffUL
1354         #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT                       0
1355         __le16 srq_size;
1356         __le16 srq_fwo;
1357         __le32 dpi;
1358         __le32 pd_id;
1359         __le64 pbl;
1360 };
1361
1362 /* Destroy SRQ command (24 bytes) */
1363 struct cmdq_destroy_srq {
1364         u8 opcode;
1365         #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ                0x6UL
1366         u8 cmd_size;
1367         __le16 flags;
1368         __le16 cookie;
1369         u8 resp_size;
1370         u8 reserved8;
1371         __le64 resp_addr;
1372         __le32 srq_cid;
1373         __le32 unused_0;
1374 };
1375
1376 /* Query SRQ command (24 bytes) */
1377 struct cmdq_query_srq {
1378         u8 opcode;
1379         #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ            0x8UL
1380         u8 cmd_size;
1381         __le16 flags;
1382         __le16 cookie;
1383         u8 resp_size;
1384         u8 reserved8;
1385         __le64 resp_addr;
1386         __le32 srq_cid;
1387         __le32 unused_0;
1388 };
1389
1390 /* Create CQ command (48 bytes) */
1391 struct cmdq_create_cq {
1392         u8 opcode;
1393         #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ            0x9UL
1394         u8 cmd_size;
1395         __le16 flags;
1396         __le16 cookie;
1397         u8 resp_size;
1398         u8 reserved8;
1399         __le64 resp_addr;
1400         __le64 cq_handle;
1401         __le32 pg_size_lvl;
1402         #define CMDQ_CREATE_CQ_LVL_MASK                     0x3UL
1403         #define CMDQ_CREATE_CQ_LVL_SFT                              0
1404         #define CMDQ_CREATE_CQ_LVL_LVL_0                           0x0UL
1405         #define CMDQ_CREATE_CQ_LVL_LVL_1                           0x1UL
1406         #define CMDQ_CREATE_CQ_LVL_LVL_2                           0x2UL
1407         #define CMDQ_CREATE_CQ_PG_SIZE_MASK                         0x1cUL
1408         #define CMDQ_CREATE_CQ_PG_SIZE_SFT                          2
1409         #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K                       (0x0UL << 2)
1410         #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K                       (0x1UL << 2)
1411         #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K                      (0x2UL << 2)
1412         #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M                       (0x3UL << 2)
1413         #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M                       (0x4UL << 2)
1414         #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G                       (0x5UL << 2)
1415         __le32 cq_fco_cnq_id;
1416         #define CMDQ_CREATE_CQ_CNQ_ID_MASK                          0xfffUL
1417         #define CMDQ_CREATE_CQ_CNQ_ID_SFT                           0
1418         #define CMDQ_CREATE_CQ_CQ_FCO_MASK                          0xfffff000UL
1419         #define CMDQ_CREATE_CQ_CQ_FCO_SFT                           12
1420         __le32 dpi;
1421         __le32 cq_size;
1422         __le64 pbl;
1423 };
1424
1425 /* Destroy CQ command (24 bytes) */
1426 struct cmdq_destroy_cq {
1427         u8 opcode;
1428         #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ                  0xaUL
1429         u8 cmd_size;
1430         __le16 flags;
1431         __le16 cookie;
1432         u8 resp_size;
1433         u8 reserved8;
1434         __le64 resp_addr;
1435         __le32 cq_cid;
1436         __le32 unused_0;
1437 };
1438
1439 /* Resize CQ command (40 bytes) */
1440 struct cmdq_resize_cq {
1441         u8 opcode;
1442         #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ            0xcUL
1443         u8 cmd_size;
1444         __le16 flags;
1445         __le16 cookie;
1446         u8 resp_size;
1447         u8 reserved8;
1448         __le64 resp_addr;
1449         __le32 cq_cid;
1450         __le32 new_cq_size_pg_size_lvl;
1451         #define CMDQ_RESIZE_CQ_LVL_MASK                     0x3UL
1452         #define CMDQ_RESIZE_CQ_LVL_SFT                              0
1453         #define CMDQ_RESIZE_CQ_LVL_LVL_0                           0x0UL
1454         #define CMDQ_RESIZE_CQ_LVL_LVL_1                           0x1UL
1455         #define CMDQ_RESIZE_CQ_LVL_LVL_2                           0x2UL
1456         #define CMDQ_RESIZE_CQ_PG_SIZE_MASK                         0x1cUL
1457         #define CMDQ_RESIZE_CQ_PG_SIZE_SFT                          2
1458         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K                       (0x0UL << 2)
1459         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K                       (0x1UL << 2)
1460         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K                      (0x2UL << 2)
1461         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M                       (0x3UL << 2)
1462         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M                       (0x4UL << 2)
1463         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G                       (0x5UL << 2)
1464         #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK             0x1fffe0UL
1465         #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT                      5
1466         __le64 new_pbl;
1467         __le32 new_cq_fco;
1468         __le32 unused_2;
1469 };
1470
1471 /* Allocate MRW command (32 bytes) */
1472 struct cmdq_allocate_mrw {
1473         u8 opcode;
1474         #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW              0xdUL
1475         u8 cmd_size;
1476         __le16 flags;
1477         __le16 cookie;
1478         u8 resp_size;
1479         u8 reserved8;
1480         __le64 resp_addr;
1481         __le64 mrw_handle;
1482         u8 mrw_flags;
1483         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK                    0xfUL
1484         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT             0
1485         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR                     0x0UL
1486         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR            0x1UL
1487         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1               0x2UL
1488         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A              0x3UL
1489         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B              0x4UL
1490         u8 access;
1491         #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_MASK              0x1fUL
1492         #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_SFT               0
1493         #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY         0x20UL
1494         __le16 unused_1;
1495         __le32 pd_id;
1496 };
1497
1498 /* De-allocate key command (24 bytes) */
1499 struct cmdq_deallocate_key {
1500         u8 opcode;
1501         #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY          0xeUL
1502         u8 cmd_size;
1503         __le16 flags;
1504         __le16 cookie;
1505         u8 resp_size;
1506         u8 reserved8;
1507         __le64 resp_addr;
1508         u8 mrw_flags;
1509         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK                  0xfUL
1510         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT                   0
1511         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR                   0x0UL
1512         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR                  0x1UL
1513         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1             0x2UL
1514         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A    0x3UL
1515         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B    0x4UL
1516         u8 unused_1[3];
1517         __le32 key;
1518 };
1519
1520 /* Register MR command (48 bytes) */
1521 struct cmdq_register_mr {
1522         u8 opcode;
1523         #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR                0xfUL
1524         u8 cmd_size;
1525         __le16 flags;
1526         __le16 cookie;
1527         u8 resp_size;
1528         u8 reserved8;
1529         __le64 resp_addr;
1530         u8 log2_pg_size_lvl;
1531         #define CMDQ_REGISTER_MR_LVL_MASK                           0x3UL
1532         #define CMDQ_REGISTER_MR_LVL_SFT                            0
1533         #define CMDQ_REGISTER_MR_LVL_LVL_0                         0x0UL
1534         #define CMDQ_REGISTER_MR_LVL_LVL_1                         0x1UL
1535         #define CMDQ_REGISTER_MR_LVL_LVL_2                         0x2UL
1536         #define CMDQ_REGISTER_MR_LVL_LAST             CMDQ_REGISTER_MR_LVL_LVL_2
1537         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK                  0x7cUL
1538         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT                   2
1539         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K    (0xcUL << 2)
1540         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K    (0xdUL << 2)
1541         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K   (0x10UL << 2)
1542         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K  (0x12UL << 2)
1543         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M    (0x14UL << 2)
1544         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M    (0x15UL << 2)
1545         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M    (0x16UL << 2)
1546         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G    (0x1eUL << 2)
1547         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST      \
1548                                         CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G
1549         #define CMDQ_REGISTER_MR_UNUSED1             0x80UL
1550         u8 access;
1551         #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE                 0x1UL
1552         #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ                 0x2UL
1553         #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE                0x4UL
1554         #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC               0x8UL
1555         #define CMDQ_REGISTER_MR_ACCESS_MW_BIND             0x10UL
1556         #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED                  0x20UL
1557         __le16  log2_pbl_pg_size;
1558         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK   0x1fUL
1559         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT    0
1560         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K    0xcUL
1561         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K    0xdUL
1562         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K   0x10UL
1563         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K  0x12UL
1564         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M    0x14UL
1565         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M    0x15UL
1566         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M    0x16UL
1567         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G    0x1eUL
1568         #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST    \
1569                                 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G
1570         #define CMDQ_REGISTER_MR_UNUSED11_MASK           0xffe0UL
1571         #define CMDQ_REGISTER_MR_UNUSED11_SFT            5
1572         __le32 key;
1573         __le64 pbl;
1574         __le64 va;
1575         __le64 mr_size;
1576 };
1577
1578 /* Deregister MR command (24 bytes) */
1579 struct cmdq_deregister_mr {
1580         u8 opcode;
1581         #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR    0x10UL
1582         u8 cmd_size;
1583         __le16 flags;
1584         __le16 cookie;
1585         u8 resp_size;
1586         u8 reserved8;
1587         __le64 resp_addr;
1588         __le32 lkey;
1589         __le32 unused_0;
1590 };
1591
1592 /* Add GID command (48 bytes) */
1593 struct cmdq_add_gid {
1594         u8 opcode;
1595         #define CMDQ_ADD_GID_OPCODE_ADD_GID                        0x11UL
1596         u8 cmd_size;
1597         __le16 flags;
1598         __le16 cookie;
1599         u8 resp_size;
1600         u8 reserved8;
1601         __le64 resp_addr;
1602         __be32 gid[4];
1603         __be16 src_mac[3];
1604         __le16 vlan;
1605         #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK                      0xfffUL
1606         #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT                       0
1607         #define CMDQ_ADD_GID_VLAN_TPID_MASK                         0x7000UL
1608         #define CMDQ_ADD_GID_VLAN_TPID_SFT                          12
1609         #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8                   (0x0UL << 12)
1610         #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100                   (0x1UL << 12)
1611         #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100                   (0x2UL << 12)
1612         #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200                   (0x3UL << 12)
1613         #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300                   (0x4UL << 12)
1614         #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1                   (0x5UL << 12)
1615         #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2                   (0x6UL << 12)
1616         #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3                   (0x7UL << 12)
1617         #define CMDQ_ADD_GID_VLAN_TPID_LAST    CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
1618         #define CMDQ_ADD_GID_VLAN_VLAN_EN                           0x8000UL
1619         __le16 ipid;
1620         __le16 stats_ctx;
1621         #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK            0x7fffUL
1622         #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT     0
1623         #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID              0x8000UL
1624         __le32 unused_0;
1625 };
1626
1627 /* Delete GID command (24 bytes) */
1628 struct cmdq_delete_gid {
1629         u8 opcode;
1630         #define CMDQ_DELETE_GID_OPCODE_DELETE_GID                  0x12UL
1631         u8 cmd_size;
1632         __le16 flags;
1633         __le16 cookie;
1634         u8 resp_size;
1635         u8 reserved8;
1636         __le64 resp_addr;
1637         __le16 gid_index;
1638         __le16 unused_0;
1639         __le32 unused_1;
1640 };
1641
1642 /* Modify GID command (48 bytes) */
1643 struct cmdq_modify_gid {
1644         u8 opcode;
1645         #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID                  0x17UL
1646         u8 cmd_size;
1647         __le16 flags;
1648         __le16 cookie;
1649         u8 resp_size;
1650         u8 reserved8;
1651         __le64 resp_addr;
1652         __be32 gid[4];
1653         __be16 src_mac[3];
1654         __le16 vlan;
1655         #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK                   0xfffUL
1656         #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT                    0
1657         #define CMDQ_MODIFY_GID_VLAN_TPID_MASK                      0x7000UL
1658         #define CMDQ_MODIFY_GID_VLAN_TPID_SFT                       12
1659         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8                (0x0UL << 12)
1660         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100                (0x1UL << 12)
1661         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100                (0x2UL << 12)
1662         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200                (0x3UL << 12)
1663         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300                (0x4UL << 12)
1664         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1                (0x5UL << 12)
1665         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2                (0x6UL << 12)
1666         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3                (0x7UL << 12)
1667         #define CMDQ_MODIFY_GID_VLAN_TPID_LAST          \
1668                                         CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
1669         #define CMDQ_MODIFY_GID_VLAN_VLAN_EN                        0x8000UL
1670         __le16 ipid;
1671         __le16 gid_index;
1672         __le16 stats_ctx;
1673         #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK         0x7fffUL
1674         #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT          0
1675         #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID           0x8000UL
1676         __le16 unused_0;
1677 };
1678
1679 /* Query GID command (24 bytes) */
1680 struct cmdq_query_gid {
1681         u8 opcode;
1682         #define CMDQ_QUERY_GID_OPCODE_QUERY_GID            0x18UL
1683         u8 cmd_size;
1684         __le16 flags;
1685         __le16 cookie;
1686         u8 resp_size;
1687         u8 reserved8;
1688         __le64 resp_addr;
1689         __le16 gid_index;
1690         __le16 unused_0;
1691         __le32 unused_1;
1692 };
1693
1694 /* Create QP1 command (80 bytes) */
1695 struct cmdq_create_qp1 {
1696         u8 opcode;
1697         #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1                  0x13UL
1698         u8 cmd_size;
1699         __le16 flags;
1700         __le16 cookie;
1701         u8 resp_size;
1702         u8 reserved8;
1703         __le64 resp_addr;
1704         __le64 qp_handle;
1705         __le32 qp_flags;
1706         #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED                  0x1UL
1707         #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION          0x2UL
1708         #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE     0x4UL
1709         u8 type;
1710         #define CMDQ_CREATE_QP1_TYPE_GSI                           0x1UL
1711         u8 sq_pg_size_sq_lvl;
1712         #define CMDQ_CREATE_QP1_SQ_LVL_MASK                         0xfUL
1713         #define CMDQ_CREATE_QP1_SQ_LVL_SFT                          0
1714         #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0                       0x0UL
1715         #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1                       0x1UL
1716         #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2                       0x2UL
1717         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK             0xf0UL
1718         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT                      4
1719         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K                   (0x0UL << 4)
1720         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K                   (0x1UL << 4)
1721         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K                  (0x2UL << 4)
1722         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M                   (0x3UL << 4)
1723         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M                   (0x4UL << 4)
1724         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G                   (0x5UL << 4)
1725         u8 rq_pg_size_rq_lvl;
1726         #define CMDQ_CREATE_QP1_RQ_LVL_MASK                         0xfUL
1727         #define CMDQ_CREATE_QP1_RQ_LVL_SFT                          0
1728         #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0                       0x0UL
1729         #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1                       0x1UL
1730         #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2                       0x2UL
1731         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK             0xf0UL
1732         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT                      4
1733         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K                   (0x0UL << 4)
1734         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K                   (0x1UL << 4)
1735         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K                  (0x2UL << 4)
1736         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M                   (0x3UL << 4)
1737         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M                   (0x4UL << 4)
1738         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G                   (0x5UL << 4)
1739         u8 unused_0;
1740         __le32 dpi;
1741         __le32 sq_size;
1742         __le32 rq_size;
1743         __le16 sq_fwo_sq_sge;
1744         #define CMDQ_CREATE_QP1_SQ_SGE_MASK                         0xfUL
1745         #define CMDQ_CREATE_QP1_SQ_SGE_SFT                          0
1746         #define CMDQ_CREATE_QP1_SQ_FWO_MASK                         0xfff0UL
1747         #define CMDQ_CREATE_QP1_SQ_FWO_SFT                          4
1748         __le16 rq_fwo_rq_sge;
1749         #define CMDQ_CREATE_QP1_RQ_SGE_MASK                         0xfUL
1750         #define CMDQ_CREATE_QP1_RQ_SGE_SFT                          0
1751         #define CMDQ_CREATE_QP1_RQ_FWO_MASK                         0xfff0UL
1752         #define CMDQ_CREATE_QP1_RQ_FWO_SFT                          4
1753         __le32 scq_cid;
1754         __le32 rcq_cid;
1755         __le32 srq_cid;
1756         __le32 pd_id;
1757         __le64 sq_pbl;
1758         __le64 rq_pbl;
1759 };
1760
1761 /* Destroy QP1 command (24 bytes) */
1762 struct cmdq_destroy_qp1 {
1763         u8 opcode;
1764         #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1                0x14UL
1765         u8 cmd_size;
1766         __le16 flags;
1767         __le16 cookie;
1768         u8 resp_size;
1769         u8 reserved8;
1770         __le64 resp_addr;
1771         __le32 qp1_cid;
1772         __le32 unused_0;
1773 };
1774
1775 /* Create AH command (64 bytes) */
1776 struct cmdq_create_ah {
1777         u8 opcode;
1778         #define CMDQ_CREATE_AH_OPCODE_CREATE_AH            0x15UL
1779         u8 cmd_size;
1780         __le16 flags;
1781         __le16 cookie;
1782         u8 resp_size;
1783         u8 reserved8;
1784         __le64 resp_addr;
1785         __le64 ah_handle;
1786         __le32 dgid[4];
1787         u8 type;
1788         #define CMDQ_CREATE_AH_TYPE_V1                             0x0UL
1789         #define CMDQ_CREATE_AH_TYPE_V2IPV4                         0x2UL
1790         #define CMDQ_CREATE_AH_TYPE_V2IPV6                         0x3UL
1791         u8 hop_limit;
1792         __le16 sgid_index;
1793         __le32 dest_vlan_id_flow_label;
1794         #define CMDQ_CREATE_AH_FLOW_LABEL_MASK                      0xfffffUL
1795         #define CMDQ_CREATE_AH_FLOW_LABEL_SFT                       0
1796         #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK                    0xfff00000UL
1797         #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT             20
1798         __le32 pd_id;
1799         __le32 unused_0;
1800         __le16 dest_mac[3];
1801         u8 traffic_class;
1802         u8 unused_1;
1803 };
1804
1805 /* Destroy AH command (24 bytes) */
1806 struct cmdq_destroy_ah {
1807         u8 opcode;
1808         #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH                  0x16UL
1809         u8 cmd_size;
1810         __le16 flags;
1811         __le16 cookie;
1812         u8 resp_size;
1813         u8 reserved8;
1814         __le64 resp_addr;
1815         __le32 ah_cid;
1816         __le32 unused_0;
1817 };
1818
1819 /* Initialize Firmware command (112 bytes) */
1820 struct cmdq_initialize_fw {
1821         u8 opcode;
1822         #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW    0x80UL
1823         u8 cmd_size;
1824         __le16 flags;
1825         __le16 cookie;
1826         u8 resp_size;
1827         u8 reserved8;
1828         __le64 resp_addr;
1829         u8 qpc_pg_size_qpc_lvl;
1830         #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK             0xfUL
1831         #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT                      0
1832         #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0                   0x0UL
1833         #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1                   0x1UL
1834         #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2                   0x2UL
1835         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK                 0xf0UL
1836         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT                  4
1837         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K               (0x0UL << 4)
1838         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K               (0x1UL << 4)
1839         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K              (0x2UL << 4)
1840         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M               (0x3UL << 4)
1841         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M               (0x4UL << 4)
1842         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G               (0x5UL << 4)
1843         u8 mrw_pg_size_mrw_lvl;
1844         #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK             0xfUL
1845         #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT                      0
1846         #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0                   0x0UL
1847         #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1                   0x1UL
1848         #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2                   0x2UL
1849         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK                 0xf0UL
1850         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT                  4
1851         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K               (0x0UL << 4)
1852         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K               (0x1UL << 4)
1853         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K              (0x2UL << 4)
1854         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M               (0x3UL << 4)
1855         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M               (0x4UL << 4)
1856         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G               (0x5UL << 4)
1857         u8 srq_pg_size_srq_lvl;
1858         #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK             0xfUL
1859         #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT                      0
1860         #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0                   0x0UL
1861         #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1                   0x1UL
1862         #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2                   0x2UL
1863         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK                 0xf0UL
1864         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT                  4
1865         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K               (0x0UL << 4)
1866         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K               (0x1UL << 4)
1867         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K              (0x2UL << 4)
1868         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M               (0x3UL << 4)
1869         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M               (0x4UL << 4)
1870         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G               (0x5UL << 4)
1871         u8 cq_pg_size_cq_lvl;
1872         #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK                      0xfUL
1873         #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT                       0
1874         #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0            0x0UL
1875         #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1            0x1UL
1876         #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2            0x2UL
1877         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK                  0xf0UL
1878         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT                   4
1879         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K                (0x0UL << 4)
1880         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K                (0x1UL << 4)
1881         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K               (0x2UL << 4)
1882         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M                (0x3UL << 4)
1883         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M                (0x4UL << 4)
1884         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G                (0x5UL << 4)
1885         u8 tqm_pg_size_tqm_lvl;
1886         #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK             0xfUL
1887         #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT                      0
1888         #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0                   0x0UL
1889         #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1                   0x1UL
1890         #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2                   0x2UL
1891         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK                 0xf0UL
1892         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT                  4
1893         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K               (0x0UL << 4)
1894         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K               (0x1UL << 4)
1895         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K              (0x2UL << 4)
1896         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M               (0x3UL << 4)
1897         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M               (0x4UL << 4)
1898         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G               (0x5UL << 4)
1899         u8 tim_pg_size_tim_lvl;
1900         #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK             0xfUL
1901         #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT                      0
1902         #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0                   0x0UL
1903         #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1                   0x1UL
1904         #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2                   0x2UL
1905         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK                 0xf0UL
1906         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT                  4
1907         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K               (0x0UL << 4)
1908         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K               (0x1UL << 4)
1909         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K              (0x2UL << 4)
1910         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M               (0x3UL << 4)
1911         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M               (0x4UL << 4)
1912         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G               (0x5UL << 4)
1913         /* This value is (log-base-2-of-DBR-page-size - 12).
1914          * 0 for 4KB. HW supported values are enumerated below.
1915          */
1916         __le16  log2_dbr_pg_size;
1917         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK        0xfUL
1918         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT         0
1919         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K       0x0UL
1920         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K       0x1UL
1921         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K      0x2UL
1922         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K      0x3UL
1923         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K      0x4UL
1924         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K     0x5UL
1925         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K     0x6UL
1926         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K     0x7UL
1927         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M       0x8UL
1928         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M       0x9UL
1929         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M       0xaUL
1930         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M       0xbUL
1931         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M      0xcUL
1932         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M      0xdUL
1933         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M      0xeUL
1934         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M     0xfUL
1935         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST                \
1936                         CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M
1937         __le64 qpc_page_dir;
1938         __le64 mrw_page_dir;
1939         __le64 srq_page_dir;
1940         __le64 cq_page_dir;
1941         __le64 tqm_page_dir;
1942         __le64 tim_page_dir;
1943         __le32 number_of_qp;
1944         __le32 number_of_mrw;
1945         __le32 number_of_srq;
1946         __le32 number_of_cq;
1947         __le32 max_qp_per_vf;
1948         __le32 max_mrw_per_vf;
1949         __le32 max_srq_per_vf;
1950         __le32 max_cq_per_vf;
1951         __le32 max_gid_per_vf;
1952         __le32 stat_ctx_id;
1953 };
1954
1955 /* De-initialize Firmware command (16 bytes) */
1956 struct cmdq_deinitialize_fw {
1957         u8 opcode;
1958         #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW       0x81UL
1959         u8 cmd_size;
1960         __le16 flags;
1961         __le16 cookie;
1962         u8 resp_size;
1963         u8 reserved8;
1964         __le64 resp_addr;
1965 };
1966
1967 /* Stop function command (16 bytes) */
1968 struct cmdq_stop_func {
1969         u8 opcode;
1970         #define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC            0x82UL
1971         u8 cmd_size;
1972         __le16 flags;
1973         __le16 cookie;
1974         u8 resp_size;
1975         u8 reserved8;
1976         __le64 resp_addr;
1977 };
1978
1979 /* Query function command (16 bytes) */
1980 struct cmdq_query_func {
1981         u8 opcode;
1982         #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC                  0x83UL
1983         u8 cmd_size;
1984         __le16 flags;
1985         __le16 cookie;
1986         u8 resp_size;
1987         u8 reserved8;
1988         __le64 resp_addr;
1989 };
1990
1991 /* Set function resources command (16 bytes) */
1992 struct cmdq_set_func_resources {
1993         u8 opcode;
1994         #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL
1995         u8 cmd_size;
1996         __le16 flags;
1997         __le16 cookie;
1998         u8 resp_size;
1999         u8 reserved8;
2000         __le64 resp_addr;
2001         __le32 number_of_qp;
2002         __le32 number_of_mrw;
2003         __le32 number_of_srq;
2004         __le32 number_of_cq;
2005         __le32 max_qp_per_vf;
2006         __le32 max_mrw_per_vf;
2007         __le32 max_srq_per_vf;
2008         __le32 max_cq_per_vf;
2009         __le32 max_gid_per_vf;
2010         __le32 stat_ctx_id;
2011 };
2012
2013 /* Read hardware resource context command (24 bytes) */
2014 struct cmdq_read_context {
2015         u8 opcode;
2016         #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT              0x85UL
2017         u8 cmd_size;
2018         __le16 flags;
2019         __le16 cookie;
2020         u8 resp_size;
2021         u8 reserved8;
2022         __le64 resp_addr;
2023         __le32 type_xid;
2024         #define CMDQ_READ_CONTEXT_XID_MASK                          0xffffffUL
2025         #define CMDQ_READ_CONTEXT_XID_SFT                           0
2026         #define CMDQ_READ_CONTEXT_TYPE_MASK                         0xff000000UL
2027         #define CMDQ_READ_CONTEXT_TYPE_SFT                          24
2028         #define CMDQ_READ_CONTEXT_TYPE_QPC                         (0x0UL << 24)
2029         #define CMDQ_READ_CONTEXT_TYPE_CQ                          (0x1UL << 24)
2030         #define CMDQ_READ_CONTEXT_TYPE_MRW                         (0x2UL << 24)
2031         #define CMDQ_READ_CONTEXT_TYPE_SRQ                         (0x3UL << 24)
2032         __le32 unused_0;
2033 };
2034
2035 /* Map TC to COS. Can only be issued from a PF (24 bytes) */
2036 struct cmdq_map_tc_to_cos {
2037         u8 opcode;
2038         #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS    0x8aUL
2039         u8 cmd_size;
2040         __le16 flags;
2041         __le16 cookie;
2042         u8 resp_size;
2043         u8 reserved8;
2044         __le64 resp_addr;
2045         __le16 cos0;
2046         #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE                  0xffffUL
2047         __le16 cos1;
2048         #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE            0x8000UL
2049         #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE                  0xffffUL
2050         __le32 unused_0;
2051 };
2052
2053 /* Query version command (16 bytes) */
2054 struct cmdq_query_version {
2055         u8 opcode;
2056         #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION    0x8bUL
2057         u8 cmd_size;
2058         __le16 flags;
2059         __le16 cookie;
2060         u8 resp_size;
2061         u8 reserved8;
2062         __le64 resp_addr;
2063 };
2064
2065 /* Command-Response Event Queue (CREQ) Structures */
2066 /* Base CREQ Record (16 bytes) */
2067 struct creq_base {
2068         u8 type;
2069         #define CREQ_BASE_TYPE_MASK                                 0x3fUL
2070         #define CREQ_BASE_TYPE_SFT                                  0
2071         #define CREQ_BASE_TYPE_QP_EVENT                    0x38UL
2072         #define CREQ_BASE_TYPE_FUNC_EVENT                          0x3aUL
2073         #define CREQ_BASE_RESERVED2_MASK                            0xc0UL
2074         #define CREQ_BASE_RESERVED2_SFT                     6
2075         u8 reserved56[7];
2076         u8 v;
2077         #define CREQ_BASE_V                                         0x1UL
2078         #define CREQ_BASE_RESERVED7_MASK                            0xfeUL
2079         #define CREQ_BASE_RESERVED7_SFT                     1
2080         u8 event;
2081         __le16 reserved48[3];
2082 };
2083
2084 /* RoCE Function Async Event Notification (16 bytes) */
2085 struct creq_func_event {
2086         u8 type;
2087         #define CREQ_FUNC_EVENT_TYPE_MASK                           0x3fUL
2088         #define CREQ_FUNC_EVENT_TYPE_SFT                            0
2089         #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT            0x3aUL
2090         #define CREQ_FUNC_EVENT_RESERVED2_MASK                      0xc0UL
2091         #define CREQ_FUNC_EVENT_RESERVED2_SFT                       6
2092         u8 reserved56[7];
2093         u8 v;
2094         #define CREQ_FUNC_EVENT_V                                   0x1UL
2095         #define CREQ_FUNC_EVENT_RESERVED7_MASK                      0xfeUL
2096         #define CREQ_FUNC_EVENT_RESERVED7_SFT                       1
2097         u8 event;
2098         #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR                 0x1UL
2099         #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR                0x2UL
2100         #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR                 0x3UL
2101         #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR                0x4UL
2102         #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR                     0x5UL
2103         #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR            0x6UL
2104         #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR                   0x7UL
2105         #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR                   0x8UL
2106         #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR                   0x9UL
2107         #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR                   0xaUL
2108         #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR            0xbUL
2109         #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST              0x80UL
2110         #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED           0x81UL
2111         __le16 reserved48[3];
2112 };
2113
2114 /* RoCE Slowpath Command Completion (16 bytes) */
2115 struct creq_qp_event {
2116         u8 type;
2117         #define CREQ_QP_EVENT_TYPE_MASK                     0x3fUL
2118         #define CREQ_QP_EVENT_TYPE_SFT                              0
2119         #define CREQ_QP_EVENT_TYPE_QP_EVENT                        0x38UL
2120         #define CREQ_QP_EVENT_RESERVED2_MASK                        0xc0UL
2121         #define CREQ_QP_EVENT_RESERVED2_SFT                         6
2122         u8 status;
2123         __le16 cookie;
2124         __le32 reserved32;
2125         u8 v;
2126         #define CREQ_QP_EVENT_V                             0x1UL
2127         #define CREQ_QP_EVENT_RESERVED7_MASK                        0xfeUL
2128         #define CREQ_QP_EVENT_RESERVED7_SFT                         1
2129         u8 event;
2130         #define CREQ_QP_EVENT_EVENT_CREATE_QP                      0x1UL
2131         #define CREQ_QP_EVENT_EVENT_DESTROY_QP                     0x2UL
2132         #define CREQ_QP_EVENT_EVENT_MODIFY_QP                      0x3UL
2133         #define CREQ_QP_EVENT_EVENT_QUERY_QP                       0x4UL
2134         #define CREQ_QP_EVENT_EVENT_CREATE_SRQ                     0x5UL
2135         #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ            0x6UL
2136         #define CREQ_QP_EVENT_EVENT_QUERY_SRQ                      0x8UL
2137         #define CREQ_QP_EVENT_EVENT_CREATE_CQ                      0x9UL
2138         #define CREQ_QP_EVENT_EVENT_DESTROY_CQ                     0xaUL
2139         #define CREQ_QP_EVENT_EVENT_RESIZE_CQ                      0xcUL
2140         #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW                   0xdUL
2141         #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY                 0xeUL
2142         #define CREQ_QP_EVENT_EVENT_REGISTER_MR            0xfUL
2143         #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR                  0x10UL
2144         #define CREQ_QP_EVENT_EVENT_ADD_GID                        0x11UL
2145         #define CREQ_QP_EVENT_EVENT_DELETE_GID                     0x12UL
2146         #define CREQ_QP_EVENT_EVENT_MODIFY_GID                     0x17UL
2147         #define CREQ_QP_EVENT_EVENT_QUERY_GID                      0x18UL
2148         #define CREQ_QP_EVENT_EVENT_CREATE_QP1                     0x13UL
2149         #define CREQ_QP_EVENT_EVENT_DESTROY_QP1            0x14UL
2150         #define CREQ_QP_EVENT_EVENT_CREATE_AH                      0x15UL
2151         #define CREQ_QP_EVENT_EVENT_DESTROY_AH                     0x16UL
2152         #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW                  0x80UL
2153         #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW                0x81UL
2154         #define CREQ_QP_EVENT_EVENT_STOP_FUNC                      0x82UL
2155         #define CREQ_QP_EVENT_EVENT_QUERY_FUNC                     0x83UL
2156         #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES             0x84UL
2157         #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS                  0x8aUL
2158         #define CREQ_QP_EVENT_EVENT_QUERY_VERSION                  0x8bUL
2159         #define CREQ_QP_EVENT_EVENT_MODIFY_CC                      0x8cUL
2160         #define CREQ_QP_EVENT_EVENT_QUERY_CC                       0x8dUL
2161         #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION          0xc0UL
2162         __le16 reserved48[3];
2163 };
2164
2165 /* Create QP command response (16 bytes) */
2166 struct creq_create_qp_resp {
2167         u8 type;
2168         #define CREQ_CREATE_QP_RESP_TYPE_MASK                       0x3fUL
2169         #define CREQ_CREATE_QP_RESP_TYPE_SFT                        0
2170         #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT                  0x38UL
2171         #define CREQ_CREATE_QP_RESP_RESERVED2_MASK                  0xc0UL
2172         #define CREQ_CREATE_QP_RESP_RESERVED2_SFT                   6
2173         u8 status;
2174         __le16 cookie;
2175         __le32 xid;
2176         u8 v;
2177         #define CREQ_CREATE_QP_RESP_V                               0x1UL
2178         #define CREQ_CREATE_QP_RESP_RESERVED7_MASK                  0xfeUL
2179         #define CREQ_CREATE_QP_RESP_RESERVED7_SFT                   1
2180         u8 event;
2181         #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP                0x1UL
2182         __le16 reserved48[3];
2183 };
2184
2185 /* Destroy QP command response (16 bytes) */
2186 struct creq_destroy_qp_resp {
2187         u8 type;
2188         #define CREQ_DESTROY_QP_RESP_TYPE_MASK                      0x3fUL
2189         #define CREQ_DESTROY_QP_RESP_TYPE_SFT                       0
2190         #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT                 0x38UL
2191         #define CREQ_DESTROY_QP_RESP_RESERVED2_MASK                 0xc0UL
2192         #define CREQ_DESTROY_QP_RESP_RESERVED2_SFT                  6
2193         u8 status;
2194         __le16 cookie;
2195         __le32 xid;
2196         u8 v;
2197         #define CREQ_DESTROY_QP_RESP_V                              0x1UL
2198         #define CREQ_DESTROY_QP_RESP_RESERVED7_MASK                 0xfeUL
2199         #define CREQ_DESTROY_QP_RESP_RESERVED7_SFT                  1
2200         u8 event;
2201         #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP              0x2UL
2202         __le16 reserved48[3];
2203 };
2204
2205 /* Modify QP command response (16 bytes) */
2206 struct creq_modify_qp_resp {
2207         u8 type;
2208         #define CREQ_MODIFY_QP_RESP_TYPE_MASK                       0x3fUL
2209         #define CREQ_MODIFY_QP_RESP_TYPE_SFT                        0
2210         #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT                  0x38UL
2211         #define CREQ_MODIFY_QP_RESP_RESERVED2_MASK                  0xc0UL
2212         #define CREQ_MODIFY_QP_RESP_RESERVED2_SFT                   6
2213         u8 status;
2214         __le16 cookie;
2215         __le32 xid;
2216         u8 v;
2217         #define CREQ_MODIFY_QP_RESP_V                               0x1UL
2218         #define CREQ_MODIFY_QP_RESP_RESERVED7_MASK                  0xfeUL
2219         #define CREQ_MODIFY_QP_RESP_RESERVED7_SFT                   1
2220         u8 event;
2221         #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP                0x3UL
2222         __le16 reserved48[3];
2223 };
2224
2225 /* cmdq_query_roce_stats (size:128b/16B) */
2226 struct cmdq_query_roce_stats {
2227         u8      opcode;
2228         #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL
2229         #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST       \
2230                                 CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS
2231         u8      cmd_size;
2232         __le16  flags;
2233         __le16  cookie;
2234         u8      resp_size;
2235         u8      reserved8;
2236         __le64  resp_addr;
2237 };
2238
2239 /* Query QP command response (16 bytes) */
2240 struct creq_query_qp_resp {
2241         u8 type;
2242         #define CREQ_QUERY_QP_RESP_TYPE_MASK                        0x3fUL
2243         #define CREQ_QUERY_QP_RESP_TYPE_SFT                         0
2244         #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT                   0x38UL
2245         #define CREQ_QUERY_QP_RESP_RESERVED2_MASK                   0xc0UL
2246         #define CREQ_QUERY_QP_RESP_RESERVED2_SFT                    6
2247         u8 status;
2248         __le16 cookie;
2249         __le32 size;
2250         u8 v;
2251         #define CREQ_QUERY_QP_RESP_V                                0x1UL
2252         #define CREQ_QUERY_QP_RESP_RESERVED7_MASK                   0xfeUL
2253         #define CREQ_QUERY_QP_RESP_RESERVED7_SFT                    1
2254         u8 event;
2255         #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP                  0x4UL
2256         __le16 reserved48[3];
2257 };
2258
2259 /* Query QP command response side buffer structure (104 bytes) */
2260 struct creq_query_qp_resp_sb {
2261         u8 opcode;
2262         #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP              0x4UL
2263         u8 status;
2264         __le16 cookie;
2265         __le16 flags;
2266         u8 resp_size;
2267         u8 reserved8;
2268         __le32 xid;
2269         u8 en_sqd_async_notify_state;
2270         #define CREQ_QUERY_QP_RESP_SB_STATE_MASK                    0xfUL
2271         #define CREQ_QUERY_QP_RESP_SB_STATE_SFT             0
2272         #define CREQ_QUERY_QP_RESP_SB_STATE_RESET                  0x0UL
2273         #define CREQ_QUERY_QP_RESP_SB_STATE_INIT                   0x1UL
2274         #define CREQ_QUERY_QP_RESP_SB_STATE_RTR            0x2UL
2275         #define CREQ_QUERY_QP_RESP_SB_STATE_RTS            0x3UL
2276         #define CREQ_QUERY_QP_RESP_SB_STATE_SQD            0x4UL
2277         #define CREQ_QUERY_QP_RESP_SB_STATE_SQE            0x5UL
2278         #define CREQ_QUERY_QP_RESP_SB_STATE_ERR            0x6UL
2279         #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY           0x10UL
2280         u8 access;
2281         #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE            0x1UL
2282         #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE           0x2UL
2283         #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ            0x4UL
2284         #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC          0x8UL
2285         __le16 pkey;
2286         __le32 qkey;
2287         __le32 reserved32;
2288         __le32 dgid[4];
2289         __le32 flow_label;
2290         __le16 sgid_index;
2291         u8 hop_limit;
2292         u8 traffic_class;
2293         __le16 dest_mac[3];
2294         __le16 path_mtu_dest_vlan_id;
2295         #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK     0xfffUL
2296         #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT              0
2297         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK                 0xf000UL
2298         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT                  12
2299         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256             (0x0UL << 12)
2300         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512             (0x1UL << 12)
2301         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024    (0x2UL << 12)
2302         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048    (0x3UL << 12)
2303         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096    (0x4UL << 12)
2304         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192    (0x5UL << 12)
2305         u8 timeout;
2306         u8 retry_cnt;
2307         u8 rnr_retry;
2308         u8 min_rnr_timer;
2309         __le32 rq_psn;
2310         __le32 sq_psn;
2311         u8 max_rd_atomic;
2312         u8 max_dest_rd_atomic;
2313         u8 tos_dscp_tos_ecn;
2314         #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK                  0x3UL
2315         #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT                   0
2316         #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK                 0xfcUL
2317         #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT                  2
2318         u8 enable_cc;
2319         #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC             0x1UL
2320         #define CREQ_QUERY_QP_RESP_SB_RESERVED7_MASK                0xfeUL
2321         #define CREQ_QUERY_QP_RESP_SB_RESERVED7_SFT                 1
2322         __le32 sq_size;
2323         __le32 rq_size;
2324         __le16 sq_sge;
2325         __le16 rq_sge;
2326         __le32 max_inline_data;
2327         __le32 dest_qp_id;
2328         __le32 unused_1;
2329         __le16 src_mac[3];
2330         __le16 vlan_pcp_vlan_dei_vlan_id;
2331         #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK                  0xfffUL
2332         #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT                   0
2333         #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI                      0x1000UL
2334         #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK                 0xe000UL
2335         #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT                  13
2336 };
2337
2338 /* Create SRQ command response (16 bytes) */
2339 struct creq_create_srq_resp {
2340         u8 type;
2341         #define CREQ_CREATE_SRQ_RESP_TYPE_MASK                      0x3fUL
2342         #define CREQ_CREATE_SRQ_RESP_TYPE_SFT                       0
2343         #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT                 0x38UL
2344         #define CREQ_CREATE_SRQ_RESP_RESERVED2_MASK                 0xc0UL
2345         #define CREQ_CREATE_SRQ_RESP_RESERVED2_SFT                  6
2346         u8 status;
2347         __le16 cookie;
2348         __le32 xid;
2349         u8 v;
2350         #define CREQ_CREATE_SRQ_RESP_V                              0x1UL
2351         #define CREQ_CREATE_SRQ_RESP_RESERVED7_MASK                 0xfeUL
2352         #define CREQ_CREATE_SRQ_RESP_RESERVED7_SFT                  1
2353         u8 event;
2354         #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ              0x5UL
2355         __le16 reserved48[3];
2356 };
2357
2358 /* Destroy SRQ command response (16 bytes) */
2359 struct creq_destroy_srq_resp {
2360         u8 type;
2361         #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK             0x3fUL
2362         #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT                      0
2363         #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT                0x38UL
2364         #define CREQ_DESTROY_SRQ_RESP_RESERVED2_MASK                0xc0UL
2365         #define CREQ_DESTROY_SRQ_RESP_RESERVED2_SFT                 6
2366         u8 status;
2367         __le16 cookie;
2368         __le32 xid;
2369         u8 v;
2370         #define CREQ_DESTROY_SRQ_RESP_V                     0x1UL
2371         #define CREQ_DESTROY_SRQ_RESP_RESERVED7_MASK                0xfeUL
2372         #define CREQ_DESTROY_SRQ_RESP_RESERVED7_SFT                 1
2373         u8 event;
2374         #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ    0x6UL
2375         __le16 enable_for_arm[3];
2376         #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK           0x30000UL
2377         #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT            16
2378         #define CREQ_DESTROY_SRQ_RESP_RESERVED46_MASK               0xfffc0000UL
2379         #define CREQ_DESTROY_SRQ_RESP_RESERVED46_SFT                18
2380 };
2381
2382 /* Query SRQ command response (16 bytes) */
2383 struct creq_query_srq_resp {
2384         u8 type;
2385         #define CREQ_QUERY_SRQ_RESP_TYPE_MASK                       0x3fUL
2386         #define CREQ_QUERY_SRQ_RESP_TYPE_SFT                        0
2387         #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT                  0x38UL
2388         #define CREQ_QUERY_SRQ_RESP_RESERVED2_MASK                  0xc0UL
2389         #define CREQ_QUERY_SRQ_RESP_RESERVED2_SFT                   6
2390         u8 status;
2391         __le16 cookie;
2392         __le32 size;
2393         u8 v;
2394         #define CREQ_QUERY_SRQ_RESP_V                               0x1UL
2395         #define CREQ_QUERY_SRQ_RESP_RESERVED7_MASK                  0xfeUL
2396         #define CREQ_QUERY_SRQ_RESP_RESERVED7_SFT                   1
2397         u8 event;
2398         #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ                0x8UL
2399         __le16 reserved48[3];
2400 };
2401
2402 /* Query SRQ command response side buffer structure (24 bytes) */
2403 struct creq_query_srq_resp_sb {
2404         u8 opcode;
2405         #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ    0x8UL
2406         u8 status;
2407         __le16 cookie;
2408         __le16 flags;
2409         u8 resp_size;
2410         u8 reserved8;
2411         __le32 xid;
2412         __le16 srq_limit;
2413         __le16 reserved16;
2414         __le32 data[4];
2415 };
2416
2417 /* Create CQ command Response (16 bytes) */
2418 struct creq_create_cq_resp {
2419         u8 type;
2420         #define CREQ_CREATE_CQ_RESP_TYPE_MASK                       0x3fUL
2421         #define CREQ_CREATE_CQ_RESP_TYPE_SFT                        0
2422         #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT                  0x38UL
2423         #define CREQ_CREATE_CQ_RESP_RESERVED2_MASK                  0xc0UL
2424         #define CREQ_CREATE_CQ_RESP_RESERVED2_SFT                   6
2425         u8 status;
2426         __le16 cookie;
2427         __le32 xid;
2428         u8 v;
2429         #define CREQ_CREATE_CQ_RESP_V                               0x1UL
2430         #define CREQ_CREATE_CQ_RESP_RESERVED7_MASK                  0xfeUL
2431         #define CREQ_CREATE_CQ_RESP_RESERVED7_SFT                   1
2432         u8 event;
2433         #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ                0x9UL
2434         __le16 reserved48[3];
2435 };
2436
2437 /* Destroy CQ command response (16 bytes) */
2438 struct creq_destroy_cq_resp {
2439         u8 type;
2440         #define CREQ_DESTROY_CQ_RESP_TYPE_MASK                      0x3fUL
2441         #define CREQ_DESTROY_CQ_RESP_TYPE_SFT                       0
2442         #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT                 0x38UL
2443         #define CREQ_DESTROY_CQ_RESP_RESERVED2_MASK                 0xc0UL
2444         #define CREQ_DESTROY_CQ_RESP_RESERVED2_SFT                  6
2445         u8 status;
2446         __le16 cookie;
2447         __le32 xid;
2448         u8 v;
2449         #define CREQ_DESTROY_CQ_RESP_V                              0x1UL
2450         #define CREQ_DESTROY_CQ_RESP_RESERVED7_MASK                 0xfeUL
2451         #define CREQ_DESTROY_CQ_RESP_RESERVED7_SFT                  1
2452         u8 event;
2453         #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ              0xaUL
2454         __le16 cq_arm_lvl;
2455         #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK                0x3UL
2456         #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT                 0
2457         #define CREQ_DESTROY_CQ_RESP_RESERVED14_MASK                0xfffcUL
2458         #define CREQ_DESTROY_CQ_RESP_RESERVED14_SFT                 2
2459         __le16 total_cnq_events;
2460         __le16 reserved16;
2461 };
2462
2463 /* Resize CQ command response (16 bytes) */
2464 struct creq_resize_cq_resp {
2465         u8 type;
2466         #define CREQ_RESIZE_CQ_RESP_TYPE_MASK                       0x3fUL
2467         #define CREQ_RESIZE_CQ_RESP_TYPE_SFT                        0
2468         #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT                  0x38UL
2469         #define CREQ_RESIZE_CQ_RESP_RESERVED2_MASK                  0xc0UL
2470         #define CREQ_RESIZE_CQ_RESP_RESERVED2_SFT                   6
2471         u8 status;
2472         __le16 cookie;
2473         __le32 xid;
2474         u8 v;
2475         #define CREQ_RESIZE_CQ_RESP_V                               0x1UL
2476         #define CREQ_RESIZE_CQ_RESP_RESERVED7_MASK                  0xfeUL
2477         #define CREQ_RESIZE_CQ_RESP_RESERVED7_SFT                   1
2478         u8 event;
2479         #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ                0xcUL
2480         __le16 reserved48[3];
2481 };
2482
2483 /* Allocate MRW command response (16 bytes) */
2484 struct creq_allocate_mrw_resp {
2485         u8 type;
2486         #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK                    0x3fUL
2487         #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT             0
2488         #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT               0x38UL
2489         #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_MASK               0xc0UL
2490         #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_SFT                6
2491         u8 status;
2492         __le16 cookie;
2493         __le32 xid;
2494         u8 v;
2495         #define CREQ_ALLOCATE_MRW_RESP_V                            0x1UL
2496         #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_MASK               0xfeUL
2497         #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_SFT                1
2498         u8 event;
2499         #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW          0xdUL
2500         __le16 reserved48[3];
2501 };
2502
2503 /* De-allocate key command response (16 bytes) */
2504 struct creq_deallocate_key_resp {
2505         u8 type;
2506         #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK                  0x3fUL
2507         #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT                   0
2508         #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT             0x38UL
2509         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_MASK     0xc0UL
2510         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_SFT              6
2511         u8 status;
2512         __le16 cookie;
2513         __le32 xid;
2514         u8 v;
2515         #define CREQ_DEALLOCATE_KEY_RESP_V                          0x1UL
2516         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_MASK     0xfeUL
2517         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_SFT              1
2518         u8 event;
2519         #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY     0xeUL
2520         __le16 reserved16;
2521         __le32 bound_window_info;
2522 };
2523
2524 /* Register MR command response (16 bytes) */
2525 struct creq_register_mr_resp {
2526         u8 type;
2527         #define CREQ_REGISTER_MR_RESP_TYPE_MASK             0x3fUL
2528         #define CREQ_REGISTER_MR_RESP_TYPE_SFT                      0
2529         #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT                0x38UL
2530         #define CREQ_REGISTER_MR_RESP_RESERVED2_MASK                0xc0UL
2531         #define CREQ_REGISTER_MR_RESP_RESERVED2_SFT                 6
2532         u8 status;
2533         __le16 cookie;
2534         __le32 xid;
2535         u8 v;
2536         #define CREQ_REGISTER_MR_RESP_V                     0x1UL
2537         #define CREQ_REGISTER_MR_RESP_RESERVED7_MASK                0xfeUL
2538         #define CREQ_REGISTER_MR_RESP_RESERVED7_SFT                 1
2539         u8 event;
2540         #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR    0xfUL
2541         __le16 reserved48[3];
2542 };
2543
2544 /* Deregister MR command response (16 bytes) */
2545 struct creq_deregister_mr_resp {
2546         u8 type;
2547         #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK                   0x3fUL
2548         #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT                    0
2549         #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT              0x38UL
2550         #define CREQ_DEREGISTER_MR_RESP_RESERVED2_MASK              0xc0UL
2551         #define CREQ_DEREGISTER_MR_RESP_RESERVED2_SFT               6
2552         u8 status;
2553         __le16 cookie;
2554         __le32 xid;
2555         u8 v;
2556         #define CREQ_DEREGISTER_MR_RESP_V                           0x1UL
2557         #define CREQ_DEREGISTER_MR_RESP_RESERVED7_MASK              0xfeUL
2558         #define CREQ_DEREGISTER_MR_RESP_RESERVED7_SFT               1
2559         u8 event;
2560         #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR       0x10UL
2561         __le16 reserved16;
2562         __le32 bound_windows;
2563 };
2564
2565 /* Add GID command response (16 bytes) */
2566 struct creq_add_gid_resp {
2567         u8 type;
2568         #define CREQ_ADD_GID_RESP_TYPE_MASK                         0x3fUL
2569         #define CREQ_ADD_GID_RESP_TYPE_SFT                          0
2570         #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT            0x38UL
2571         #define CREQ_ADD_GID_RESP_RESERVED2_MASK                    0xc0UL
2572         #define CREQ_ADD_GID_RESP_RESERVED2_SFT             6
2573         u8 status;
2574         __le16 cookie;
2575         __le32 xid;
2576         u8 v;
2577         #define CREQ_ADD_GID_RESP_V                                 0x1UL
2578         #define CREQ_ADD_GID_RESP_RESERVED7_MASK                    0xfeUL
2579         #define CREQ_ADD_GID_RESP_RESERVED7_SFT             1
2580         u8 event;
2581         #define CREQ_ADD_GID_RESP_EVENT_ADD_GID            0x11UL
2582         __le16 reserved48[3];
2583 };
2584
2585 /* Delete GID command response (16 bytes) */
2586 struct creq_delete_gid_resp {
2587         u8 type;
2588         #define CREQ_DELETE_GID_RESP_TYPE_MASK                      0x3fUL
2589         #define CREQ_DELETE_GID_RESP_TYPE_SFT                       0
2590         #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT                 0x38UL
2591         #define CREQ_DELETE_GID_RESP_RESERVED2_MASK                 0xc0UL
2592         #define CREQ_DELETE_GID_RESP_RESERVED2_SFT                  6
2593         u8 status;
2594         __le16 cookie;
2595         __le32 xid;
2596         u8 v;
2597         #define CREQ_DELETE_GID_RESP_V                              0x1UL
2598         #define CREQ_DELETE_GID_RESP_RESERVED7_MASK                 0xfeUL
2599         #define CREQ_DELETE_GID_RESP_RESERVED7_SFT                  1
2600         u8 event;
2601         #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID              0x12UL
2602         __le16 reserved48[3];
2603 };
2604
2605 /* Modify GID command response (16 bytes) */
2606 struct creq_modify_gid_resp {
2607         u8 type;
2608         #define CREQ_MODIFY_GID_RESP_TYPE_MASK                      0x3fUL
2609         #define CREQ_MODIFY_GID_RESP_TYPE_SFT                       0
2610         #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT                 0x38UL
2611         #define CREQ_MODIFY_GID_RESP_RESERVED2_MASK                 0xc0UL
2612         #define CREQ_MODIFY_GID_RESP_RESERVED2_SFT                  6
2613         u8 status;
2614         __le16 cookie;
2615         __le32 xid;
2616         u8 v;
2617         #define CREQ_MODIFY_GID_RESP_V                              0x1UL
2618         #define CREQ_MODIFY_GID_RESP_RESERVED7_MASK                 0xfeUL
2619         #define CREQ_MODIFY_GID_RESP_RESERVED7_SFT                  1
2620         u8 event;
2621         #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID                 0x11UL
2622         __le16 reserved48[3];
2623 };
2624
2625 /* Query GID command response (16 bytes) */
2626 struct creq_query_gid_resp {
2627         u8 type;
2628         #define CREQ_QUERY_GID_RESP_TYPE_MASK                       0x3fUL
2629         #define CREQ_QUERY_GID_RESP_TYPE_SFT                        0
2630         #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT                  0x38UL
2631         #define CREQ_QUERY_GID_RESP_RESERVED2_MASK                  0xc0UL
2632         #define CREQ_QUERY_GID_RESP_RESERVED2_SFT                   6
2633         u8 status;
2634         __le16 cookie;
2635         __le32 size;
2636         u8 v;
2637         #define CREQ_QUERY_GID_RESP_V                               0x1UL
2638         #define CREQ_QUERY_GID_RESP_RESERVED7_MASK                  0xfeUL
2639         #define CREQ_QUERY_GID_RESP_RESERVED7_SFT                   1
2640         u8 event;
2641         #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID                0x18UL
2642         __le16 reserved48[3];
2643 };
2644
2645 /* Query GID command response side buffer structure (40 bytes) */
2646 struct creq_query_gid_resp_sb {
2647         u8 opcode;
2648         #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID    0x18UL
2649         u8 status;
2650         __le16 cookie;
2651         __le16 flags;
2652         u8 resp_size;
2653         u8 reserved8;
2654         __le32 gid[4];
2655         __le16 src_mac[3];
2656         __le16 vlan;
2657         #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK            0xfffUL
2658         #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT     0
2659         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK               0x7000UL
2660         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT                12
2661         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8         (0x0UL << 12)
2662         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100         (0x1UL << 12)
2663         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100         (0x2UL << 12)
2664         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200         (0x3UL << 12)
2665         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300         (0x4UL << 12)
2666         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1         (0x5UL << 12)
2667         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2         (0x6UL << 12)
2668         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3         (0x7UL << 12)
2669         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST   \
2670                                 CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
2671         #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN                 0x8000UL
2672         __le16 ipid;
2673         __le16 gid_index;
2674         __le32 unused_0;
2675 };
2676
2677 /* Create QP1 command response (16 bytes) */
2678 struct creq_create_qp1_resp {
2679         u8 type;
2680         #define CREQ_CREATE_QP1_RESP_TYPE_MASK                      0x3fUL
2681         #define CREQ_CREATE_QP1_RESP_TYPE_SFT                       0
2682         #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT                 0x38UL
2683         #define CREQ_CREATE_QP1_RESP_RESERVED2_MASK                 0xc0UL
2684         #define CREQ_CREATE_QP1_RESP_RESERVED2_SFT                  6
2685         u8 status;
2686         __le16 cookie;
2687         __le32 xid;
2688         u8 v;
2689         #define CREQ_CREATE_QP1_RESP_V                              0x1UL
2690         #define CREQ_CREATE_QP1_RESP_RESERVED7_MASK                 0xfeUL
2691         #define CREQ_CREATE_QP1_RESP_RESERVED7_SFT                  1
2692         u8 event;
2693         #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1              0x13UL
2694         __le16 reserved48[3];
2695 };
2696
2697 /* Destroy QP1 command response (16 bytes) */
2698 struct creq_destroy_qp1_resp {
2699         u8 type;
2700         #define CREQ_DESTROY_QP1_RESP_TYPE_MASK             0x3fUL
2701         #define CREQ_DESTROY_QP1_RESP_TYPE_SFT                      0
2702         #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT                0x38UL
2703         #define CREQ_DESTROY_QP1_RESP_RESERVED2_MASK                0xc0UL
2704         #define CREQ_DESTROY_QP1_RESP_RESERVED2_SFT                 6
2705         u8 status;
2706         __le16 cookie;
2707         __le32 xid;
2708         u8 v;
2709         #define CREQ_DESTROY_QP1_RESP_V                     0x1UL
2710         #define CREQ_DESTROY_QP1_RESP_RESERVED7_MASK                0xfeUL
2711         #define CREQ_DESTROY_QP1_RESP_RESERVED7_SFT                 1
2712         u8 event;
2713         #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1    0x14UL
2714         __le16 reserved48[3];
2715 };
2716
2717 /* Create AH command response (16 bytes) */
2718 struct creq_create_ah_resp {
2719         u8 type;
2720         #define CREQ_CREATE_AH_RESP_TYPE_MASK                       0x3fUL
2721         #define CREQ_CREATE_AH_RESP_TYPE_SFT                        0
2722         #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT                  0x38UL
2723         #define CREQ_CREATE_AH_RESP_RESERVED2_MASK                  0xc0UL
2724         #define CREQ_CREATE_AH_RESP_RESERVED2_SFT                   6
2725         u8 status;
2726         __le16 cookie;
2727         __le32 xid;
2728         u8 v;
2729         #define CREQ_CREATE_AH_RESP_V                               0x1UL
2730         #define CREQ_CREATE_AH_RESP_RESERVED7_MASK                  0xfeUL
2731         #define CREQ_CREATE_AH_RESP_RESERVED7_SFT                   1
2732         u8 event;
2733         #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH                0x15UL
2734         __le16 reserved48[3];
2735 };
2736
2737 /* Destroy AH command response (16 bytes) */
2738 struct creq_destroy_ah_resp {
2739         u8 type;
2740         #define CREQ_DESTROY_AH_RESP_TYPE_MASK                      0x3fUL
2741         #define CREQ_DESTROY_AH_RESP_TYPE_SFT                       0
2742         #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT                 0x38UL
2743         #define CREQ_DESTROY_AH_RESP_RESERVED2_MASK                 0xc0UL
2744         #define CREQ_DESTROY_AH_RESP_RESERVED2_SFT                  6
2745         u8 status;
2746         __le16 cookie;
2747         __le32 xid;
2748         u8 v;
2749         #define CREQ_DESTROY_AH_RESP_V                              0x1UL
2750         #define CREQ_DESTROY_AH_RESP_RESERVED7_MASK                 0xfeUL
2751         #define CREQ_DESTROY_AH_RESP_RESERVED7_SFT                  1
2752         u8 event;
2753         #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH              0x16UL
2754         __le16 reserved48[3];
2755 };
2756
2757 /* Initialize Firmware command response (16 bytes) */
2758 struct creq_initialize_fw_resp {
2759         u8 type;
2760         #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK                   0x3fUL
2761         #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT                    0
2762         #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT              0x38UL
2763         #define CREQ_INITIALIZE_FW_RESP_RESERVED2_MASK              0xc0UL
2764         #define CREQ_INITIALIZE_FW_RESP_RESERVED2_SFT               6
2765         u8 status;
2766         __le16 cookie;
2767         __le32 reserved32;
2768         u8 v;
2769         #define CREQ_INITIALIZE_FW_RESP_V                           0x1UL
2770         #define CREQ_INITIALIZE_FW_RESP_RESERVED7_MASK              0xfeUL
2771         #define CREQ_INITIALIZE_FW_RESP_RESERVED7_SFT               1
2772         u8 event;
2773         #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW       0x80UL
2774         __le16 reserved48[3];
2775 };
2776
2777 /* De-initialize Firmware command response (16 bytes) */
2778 struct creq_deinitialize_fw_resp {
2779         u8 type;
2780         #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK                 0x3fUL
2781         #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT                  0
2782         #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT    0x38UL
2783         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_MASK            0xc0UL
2784         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_SFT     6
2785         u8 status;
2786         __le16 cookie;
2787         __le32 reserved32;
2788         u8 v;
2789         #define CREQ_DEINITIALIZE_FW_RESP_V                         0x1UL
2790         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_MASK            0xfeUL
2791         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_SFT     1
2792         u8 event;
2793         #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW   0x81UL
2794         __le16 reserved48[3];
2795 };
2796
2797 /* Stop function command response (16 bytes) */
2798 struct creq_stop_func_resp {
2799         u8 type;
2800         #define CREQ_STOP_FUNC_RESP_TYPE_MASK                       0x3fUL
2801         #define CREQ_STOP_FUNC_RESP_TYPE_SFT                        0
2802         #define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT                  0x38UL
2803         #define CREQ_STOP_FUNC_RESP_RESERVED2_MASK                  0xc0UL
2804         #define CREQ_STOP_FUNC_RESP_RESERVED2_SFT                   6
2805         u8 status;
2806         __le16 cookie;
2807         __le32 reserved32;
2808         u8 v;
2809         #define CREQ_STOP_FUNC_RESP_V                               0x1UL
2810         #define CREQ_STOP_FUNC_RESP_RESERVED7_MASK                  0xfeUL
2811         #define CREQ_STOP_FUNC_RESP_RESERVED7_SFT                   1
2812         u8 event;
2813         #define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC                0x82UL
2814         __le16 reserved48[3];
2815 };
2816
2817 /* Query function command response (16 bytes) */
2818 struct creq_query_func_resp {
2819         u8 type;
2820         #define CREQ_QUERY_FUNC_RESP_TYPE_MASK                      0x3fUL
2821         #define CREQ_QUERY_FUNC_RESP_TYPE_SFT                       0
2822         #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT                 0x38UL
2823         #define CREQ_QUERY_FUNC_RESP_RESERVED2_MASK                 0xc0UL
2824         #define CREQ_QUERY_FUNC_RESP_RESERVED2_SFT                  6
2825         u8 status;
2826         __le16 cookie;
2827         __le32 size;
2828         u8 v;
2829         #define CREQ_QUERY_FUNC_RESP_V                              0x1UL
2830         #define CREQ_QUERY_FUNC_RESP_RESERVED7_MASK                 0xfeUL
2831         #define CREQ_QUERY_FUNC_RESP_RESERVED7_SFT                  1
2832         u8 event;
2833         #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC              0x83UL
2834         __le16 reserved48[3];
2835 };
2836
2837 /* Query function command response side buffer structure (88 bytes) */
2838 struct creq_query_func_resp_sb {
2839         u8 opcode;
2840         #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC          0x83UL
2841         u8 status;
2842         __le16 cookie;
2843         __le16 flags;
2844         u8 resp_size;
2845         u8 reserved8;
2846         __le64 max_mr_size;
2847         __le32 max_qp;
2848         __le16 max_qp_wr;
2849         __le16 dev_cap_flags;
2850         #define CREQ_QUERY_FUNC_RESP_SB_DEV_CAP_FLAGS_RESIZE_QP   0x1UL
2851         __le32 max_cq;
2852         __le32 max_cqe;
2853         __le32 max_pd;
2854         u8 max_sge;
2855         u8 max_srq_sge;
2856         u8 max_qp_rd_atom;
2857         u8 max_qp_init_rd_atom;
2858         __le32 max_mr;
2859         __le32 max_mw;
2860         __le32 max_raw_eth_qp;
2861         __le32 max_ah;
2862         __le32 max_fmr;
2863         __le32 max_srq_wr;
2864         __le32 max_pkeys;
2865         __le32 max_inline_data;
2866         u8 max_map_per_fmr;
2867         u8 l2_db_space_size;
2868         __le16 max_srq;
2869         __le32 max_gid;
2870         __le32 tqm_alloc_reqs[12];
2871         __le32 max_dpi;
2872         __le32 reserved_32;
2873 };
2874
2875 /* Set resources command response (16 bytes) */
2876 struct creq_set_func_resources_resp {
2877         u8 type;
2878         #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK              0x3fUL
2879         #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT               0
2880         #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT         0x38UL
2881         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_MASK         0xc0UL
2882         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_SFT          6
2883         u8 status;
2884         __le16 cookie;
2885         __le32 reserved32;
2886         u8 v;
2887         #define CREQ_SET_FUNC_RESOURCES_RESP_V                      0x1UL
2888         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_MASK         0xfeUL
2889         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_SFT          1
2890         u8 event;
2891         #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL
2892         __le16 reserved48[3];
2893 };
2894
2895 /* Map TC to COS response (16 bytes) */
2896 struct creq_map_tc_to_cos_resp {
2897         u8 type;
2898         #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK                   0x3fUL
2899         #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT                    0
2900         #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT              0x38UL
2901         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_MASK              0xc0UL
2902         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_SFT               6
2903         u8 status;
2904         __le16 cookie;
2905         __le32 reserved32;
2906         u8 v;
2907         #define CREQ_MAP_TC_TO_COS_RESP_V                           0x1UL
2908         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_MASK              0xfeUL
2909         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_SFT               1
2910         u8 event;
2911         #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS       0x8aUL
2912         __le16 reserved48[3];
2913 };
2914
2915 /* Query version response (16 bytes) */
2916 struct creq_query_version_resp {
2917         u8 type;
2918         #define CREQ_QUERY_VERSION_RESP_TYPE_MASK                   0x3fUL
2919         #define CREQ_QUERY_VERSION_RESP_TYPE_SFT                    0
2920         #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT              0x38UL
2921         #define CREQ_QUERY_VERSION_RESP_RESERVED2_MASK              0xc0UL
2922         #define CREQ_QUERY_VERSION_RESP_RESERVED2_SFT               6
2923         u8 status;
2924         __le16 cookie;
2925         u8 fw_maj;
2926         u8 fw_minor;
2927         u8 fw_bld;
2928         u8 fw_rsvd;
2929         u8 v;
2930         #define CREQ_QUERY_VERSION_RESP_V                           0x1UL
2931         #define CREQ_QUERY_VERSION_RESP_RESERVED7_MASK              0xfeUL
2932         #define CREQ_QUERY_VERSION_RESP_RESERVED7_SFT               1
2933         u8 event;
2934         #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION       0x8bUL
2935         __le16 reserved16;
2936         u8 intf_maj;
2937         u8 intf_minor;
2938         u8 intf_bld;
2939         u8 intf_rsvd;
2940 };
2941
2942 /* Modify congestion control command response (16 bytes) */
2943 struct creq_modify_cc_resp {
2944         u8 type;
2945         #define CREQ_MODIFY_CC_RESP_TYPE_MASK                       0x3fUL
2946         #define CREQ_MODIFY_CC_RESP_TYPE_SFT                        0
2947         #define CREQ_MODIFY_CC_RESP_TYPE_QP_EVENT                  0x38UL
2948         #define CREQ_MODIFY_CC_RESP_RESERVED2_MASK                  0xc0UL
2949         #define CREQ_MODIFY_CC_RESP_RESERVED2_SFT                   6
2950         u8 status;
2951         __le16 cookie;
2952         __le32 reserved32;
2953         u8 v;
2954         #define CREQ_MODIFY_CC_RESP_V                               0x1UL
2955         #define CREQ_MODIFY_CC_RESP_RESERVED7_MASK                  0xfeUL
2956         #define CREQ_MODIFY_CC_RESP_RESERVED7_SFT                   1
2957         u8 event;
2958         #define CREQ_MODIFY_CC_RESP_EVENT_MODIFY_CC                0x8cUL
2959         __le16 reserved48[3];
2960 };
2961
2962 /* Query congestion control command response (16 bytes) */
2963 struct creq_query_cc_resp {
2964         u8 type;
2965         #define CREQ_QUERY_CC_RESP_TYPE_MASK                        0x3fUL
2966         #define CREQ_QUERY_CC_RESP_TYPE_SFT                         0
2967         #define CREQ_QUERY_CC_RESP_TYPE_QP_EVENT                   0x38UL
2968         #define CREQ_QUERY_CC_RESP_RESERVED2_MASK                   0xc0UL
2969         #define CREQ_QUERY_CC_RESP_RESERVED2_SFT                    6
2970         u8 status;
2971         __le16 cookie;
2972         __le32 size;
2973         u8 v;
2974         #define CREQ_QUERY_CC_RESP_V                                0x1UL
2975         #define CREQ_QUERY_CC_RESP_RESERVED7_MASK                   0xfeUL
2976         #define CREQ_QUERY_CC_RESP_RESERVED7_SFT                    1
2977         u8 event;
2978         #define CREQ_QUERY_CC_RESP_EVENT_QUERY_CC                  0x8dUL
2979         __le16 reserved48[3];
2980 };
2981
2982 /* Query congestion control command response side buffer structure (32 bytes) */
2983 struct creq_query_cc_resp_sb {
2984         u8 opcode;
2985         #define CREQ_QUERY_CC_RESP_SB_OPCODE_QUERY_CC              0x8dUL
2986         u8 status;
2987         __le16 cookie;
2988         __le16 flags;
2989         u8 resp_size;
2990         u8 reserved8;
2991         u8 enable_cc;
2992         #define CREQ_QUERY_CC_RESP_SB_ENABLE_CC             0x1UL
2993         u8 g;
2994         #define CREQ_QUERY_CC_RESP_SB_G_MASK                        0x7UL
2995         #define CREQ_QUERY_CC_RESP_SB_G_SFT                         0
2996         u8 num_phases_per_state;
2997         __le16 init_cr;
2998         u8 unused_2;
2999         __le16 unused_3;
3000         u8 unused_4;
3001         __le16 init_tr;
3002         u8 tos_dscp_tos_ecn;
3003         #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_MASK                  0x3UL
3004         #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_SFT                   0
3005         #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_MASK                 0xfcUL
3006         #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_SFT                  2
3007         __le64 reserved64;
3008         __le64 reserved64_1;
3009 };
3010
3011 /* creq_query_roce_stats_resp (size:128b/16B) */
3012 struct creq_query_roce_stats_resp {
3013         u8      type;
3014         #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK    0x3fUL
3015         #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT     0
3016         #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT  0x38UL
3017         #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST    \
3018                                 CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT
3019         u8      status;
3020         __le16  cookie;
3021         __le32  size;
3022         u8      v;
3023         #define CREQ_QUERY_ROCE_STATS_RESP_V     0x1UL
3024         u8      event;
3025         #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL
3026         #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST   \
3027                         CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS
3028         u8      reserved48[6];
3029 };
3030
3031 /* creq_query_roce_stats_resp_sb (size:2624b/328B) */
3032 struct creq_query_roce_stats_resp_sb {
3033         u8      opcode;
3034         #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL
3035         #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \
3036                         CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS
3037         u8      status;
3038         __le16  cookie;
3039         __le16  flags;
3040         u8      resp_size;
3041         u8      rsvd;
3042         __le32  num_counters;
3043         __le32  rsvd1;
3044         __le64  to_retransmits;
3045         __le64  seq_err_naks_rcvd;
3046         __le64  max_retry_exceeded;
3047         __le64  rnr_naks_rcvd;
3048         __le64  missing_resp;
3049         __le64  unrecoverable_err;
3050         __le64  bad_resp_err;
3051         __le64  local_qp_op_err;
3052         __le64  local_protection_err;
3053         __le64  mem_mgmt_op_err;
3054         __le64  remote_invalid_req_err;
3055         __le64  remote_access_err;
3056         __le64  remote_op_err;
3057         __le64  dup_req;
3058         __le64  res_exceed_max;
3059         __le64  res_length_mismatch;
3060         __le64  res_exceeds_wqe;
3061         __le64  res_opcode_err;
3062         __le64  res_rx_invalid_rkey;
3063         __le64  res_rx_domain_err;
3064         __le64  res_rx_no_perm;
3065         __le64  res_rx_range_err;
3066         __le64  res_tx_invalid_rkey;
3067         __le64  res_tx_domain_err;
3068         __le64  res_tx_no_perm;
3069         __le64  res_tx_range_err;
3070         __le64  res_irrq_oflow;
3071         __le64  res_unsup_opcode;
3072         __le64  res_unaligned_atomic;
3073         __le64  res_rem_inv_err;
3074         __le64  res_mem_error;
3075         __le64  res_srq_err;
3076         __le64  res_cmp_err;
3077         __le64  res_invalid_dup_rkey;
3078         __le64  res_wqe_format_err;
3079         __le64  res_cq_load_err;
3080         __le64  res_srq_load_err;
3081         __le64  res_tx_pci_err;
3082         __le64  res_rx_pci_err;
3083         __le64  res_oos_drop_count;
3084         __le64  active_qp_count_p0;
3085         __le64  active_qp_count_p1;
3086         __le64  active_qp_count_p2;
3087         __le64  active_qp_count_p3;
3088 };
3089
3090 /* QP error notification event (16 bytes) */
3091 struct creq_qp_error_notification {
3092         u8 type;
3093         #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK                0x3fUL
3094         #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT                 0
3095         #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT           0x38UL
3096         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_MASK           0xc0UL
3097         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_SFT            6
3098         u8 status;
3099         u8 req_slow_path_state;
3100         u8 req_err_state_reason;
3101         __le32 xid;
3102         u8 v;
3103         #define CREQ_QP_ERROR_NOTIFICATION_V                        0x1UL
3104         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_MASK           0xfeUL
3105         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_SFT            1
3106         u8 event;
3107         #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
3108         u8 res_slow_path_state;
3109         u8 res_err_state_reason;
3110         __le16 sq_cons_idx;
3111         __le16 rq_cons_idx;
3112 };
3113
3114 /* RoCE Slowpath HSI Specification 1.6.0 */
3115 #define ROCE_SP_HSI_VERSION_MAJOR       1
3116 #define ROCE_SP_HSI_VERSION_MINOR       6
3117 #define ROCE_SP_HSI_VERSION_UPDATE      0
3118
3119 #define ROCE_SP_HSI_VERSION_STR "1.6.0"
3120 /*
3121  * Following is the signature for ROCE_SP_HSI message field that indicates not
3122  * applicable (All F's). Need to cast it the size of the field if needed.
3123  */
3124 #define ROCE_SP_HSI_NA_SIGNATURE        ((__le32)(-1))
3125 #endif /* __BNXT_RE_HSI_H__ */