1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
10 * DOC: VC4 Falcon HDMI module
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <linux/clk.h>
40 #include <linux/component.h>
41 #include <linux/i2c.h>
42 #include <linux/of_address.h>
43 #include <linux/of_gpio.h>
44 #include <linux/of_platform.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/rational.h>
47 #include <linux/reset.h>
48 #include <sound/dmaengine_pcm.h>
49 #include <sound/hdmi-codec.h>
50 #include <sound/pcm_drm_eld.h>
51 #include <sound/pcm_params.h>
52 #include <sound/soc.h>
53 #include "media/cec.h"
56 #include "vc4_hdmi_regs.h"
59 #define VC5_HDMI_HORZA_HFP_SHIFT 16
60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
61 #define VC5_HDMI_HORZA_VPOS BIT(15)
62 #define VC5_HDMI_HORZA_HPOS BIT(14)
63 #define VC5_HDMI_HORZA_HAP_SHIFT 0
64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
66 #define VC5_HDMI_HORZB_HBP_SHIFT 16
67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
68 #define VC5_HDMI_HORZB_HSP_SHIFT 0
69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
71 #define VC5_HDMI_VERTA_VSP_SHIFT 24
72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
73 #define VC5_HDMI_VERTA_VFP_SHIFT 16
74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
75 #define VC5_HDMI_VERTA_VAL_SHIFT 0
76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
94 # define VC4_HD_M_SW_RST BIT(2)
95 # define VC4_HD_M_ENABLE BIT(0)
97 #define CEC_CLOCK_FREQ 40000
99 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
101 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
103 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
106 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
108 struct drm_info_node *node = (struct drm_info_node *)m->private;
109 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
110 struct drm_printer p = drm_seq_file_printer(m);
112 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
113 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
118 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
120 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
122 HDMI_WRITE(HDMI_M_CTL, 0);
124 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
126 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
127 VC4_HDMI_SW_RESET_HDMI |
128 VC4_HDMI_SW_RESET_FORMAT_DETECT);
130 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
133 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
135 reset_control_reset(vc4_hdmi->reset);
137 HDMI_WRITE(HDMI_DVP_CTL, 0);
139 HDMI_WRITE(HDMI_CLOCK_STOP,
140 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
143 #ifdef CONFIG_DRM_VC4_HDMI_CEC
144 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
149 value = HDMI_READ(HDMI_CEC_CNTRL_1);
150 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
153 * Set the clock divider: the hsm_clock rate and this divider
154 * setting will give a 40 kHz CEC clock.
156 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
157 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
158 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
161 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
164 static enum drm_connector_status
165 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
167 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
168 bool connected = false;
170 if (vc4_hdmi->hpd_gpio &&
171 gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
173 } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
175 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
180 if (connector->status != connector_status_connected) {
181 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
184 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
185 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
190 return connector_status_connected;
193 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
194 return connector_status_disconnected;
197 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
199 drm_connector_unregister(connector);
200 drm_connector_cleanup(connector);
203 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
205 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
206 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
210 edid = drm_get_edid(connector, vc4_hdmi->ddc);
211 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
215 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
217 drm_connector_update_edid_property(connector, edid);
218 ret = drm_add_edid_modes(connector, edid);
221 if (vc4_hdmi->disable_4kp60) {
222 struct drm_device *drm = connector->dev;
223 struct drm_display_mode *mode;
225 list_for_each_entry(mode, &connector->probed_modes, head) {
226 if (vc4_hdmi_mode_needs_scrambling(mode)) {
227 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
228 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
236 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
237 struct drm_atomic_state *state)
239 struct drm_connector_state *old_state =
240 drm_atomic_get_old_connector_state(state, connector);
241 struct drm_connector_state *new_state =
242 drm_atomic_get_new_connector_state(state, connector);
243 struct drm_crtc *crtc = new_state->crtc;
248 if (old_state->colorspace != new_state->colorspace ||
249 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
250 struct drm_crtc_state *crtc_state;
252 crtc_state = drm_atomic_get_crtc_state(state, crtc);
253 if (IS_ERR(crtc_state))
254 return PTR_ERR(crtc_state);
256 crtc_state->mode_changed = true;
262 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
264 struct vc4_hdmi_connector_state *old_state =
265 conn_state_to_vc4_hdmi_conn_state(connector->state);
266 struct vc4_hdmi_connector_state *new_state =
267 kzalloc(sizeof(*new_state), GFP_KERNEL);
269 if (connector->state)
270 __drm_atomic_helper_connector_destroy_state(connector->state);
273 __drm_atomic_helper_connector_reset(connector, &new_state->base);
278 new_state->base.max_bpc = 8;
279 new_state->base.max_requested_bpc = 8;
280 drm_atomic_helper_connector_tv_reset(connector);
283 static struct drm_connector_state *
284 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
286 struct drm_connector_state *conn_state = connector->state;
287 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
288 struct vc4_hdmi_connector_state *new_state;
290 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
294 new_state->pixel_rate = vc4_state->pixel_rate;
295 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
297 return &new_state->base;
300 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
301 .detect = vc4_hdmi_connector_detect,
302 .fill_modes = drm_helper_probe_single_connector_modes,
303 .destroy = vc4_hdmi_connector_destroy,
304 .reset = vc4_hdmi_connector_reset,
305 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
306 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
309 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
310 .get_modes = vc4_hdmi_connector_get_modes,
311 .atomic_check = vc4_hdmi_connector_atomic_check,
314 static int vc4_hdmi_connector_init(struct drm_device *dev,
315 struct vc4_hdmi *vc4_hdmi)
317 struct drm_connector *connector = &vc4_hdmi->connector;
318 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
321 drm_connector_init_with_ddc(dev, connector,
322 &vc4_hdmi_connector_funcs,
323 DRM_MODE_CONNECTOR_HDMIA,
325 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
328 * Some of the properties below require access to state, like bpc.
329 * Allocate some default initial connector state with our reset helper.
331 if (connector->funcs->reset)
332 connector->funcs->reset(connector);
334 /* Create and attach TV margin props to this connector. */
335 ret = drm_mode_create_tv_margin_properties(dev);
339 ret = drm_mode_create_hdmi_colorspace_property(connector);
343 drm_connector_attach_colorspace_property(connector);
344 drm_connector_attach_tv_margin_properties(connector);
345 drm_connector_attach_max_bpc_property(connector, 8, 12);
347 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
348 DRM_CONNECTOR_POLL_DISCONNECT);
350 connector->interlace_allowed = 1;
351 connector->doublescan_allowed = 0;
353 if (vc4_hdmi->variant->supports_hdr)
354 drm_connector_attach_hdr_output_metadata_property(connector);
356 drm_connector_attach_encoder(connector, encoder);
361 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
362 enum hdmi_infoframe_type type,
365 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
366 u32 packet_id = type - 0x80;
368 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
369 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
374 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
375 BIT(packet_id)), 100);
378 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
379 union hdmi_infoframe *frame)
381 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
382 u32 packet_id = frame->any.type - 0x80;
383 const struct vc4_hdmi_register *ram_packet_start =
384 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
385 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
386 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
387 ram_packet_start->reg);
388 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
392 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
393 VC4_HDMI_RAM_PACKET_ENABLE),
394 "Packet RAM has to be on to store the packet.");
396 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
400 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
402 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
406 for (i = 0; i < len; i += 7) {
407 writel(buffer[i + 0] << 0 |
413 writel(buffer[i + 3] << 0 |
415 buffer[i + 5] << 16 |
421 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
422 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
423 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
424 BIT(packet_id)), 100);
426 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
429 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
431 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
432 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
433 struct drm_connector *connector = &vc4_hdmi->connector;
434 struct drm_connector_state *cstate = connector->state;
435 struct drm_crtc *crtc = cstate->crtc;
436 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
437 union hdmi_infoframe frame;
440 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
443 DRM_ERROR("couldn't fill AVI infoframe\n");
447 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
449 vc4_encoder->limited_rgb_range ?
450 HDMI_QUANTIZATION_RANGE_LIMITED :
451 HDMI_QUANTIZATION_RANGE_FULL);
452 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
453 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
455 vc4_hdmi_write_infoframe(encoder, &frame);
458 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
460 union hdmi_infoframe frame;
463 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
465 DRM_ERROR("couldn't fill SPD infoframe\n");
469 frame.spd.sdi = HDMI_SPD_SDI_PC;
471 vc4_hdmi_write_infoframe(encoder, &frame);
474 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
476 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
477 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
478 union hdmi_infoframe frame;
480 memcpy(&frame.audio, audio, sizeof(*audio));
481 vc4_hdmi_write_infoframe(encoder, &frame);
484 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
486 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
487 struct drm_connector *connector = &vc4_hdmi->connector;
488 struct drm_connector_state *conn_state = connector->state;
489 union hdmi_infoframe frame;
491 if (!vc4_hdmi->variant->supports_hdr)
494 if (!conn_state->hdr_output_metadata)
497 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
500 vc4_hdmi_write_infoframe(encoder, &frame);
503 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
505 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
507 vc4_hdmi_set_avi_infoframe(encoder);
508 vc4_hdmi_set_spd_infoframe(encoder);
510 * If audio was streaming, then we need to reenabled the audio
511 * infoframe here during encoder_enable.
513 if (vc4_hdmi->audio.streaming)
514 vc4_hdmi_set_audio_infoframe(encoder);
516 vc4_hdmi_set_hdr_infoframe(encoder);
519 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
520 struct drm_display_mode *mode)
522 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
523 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
524 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
526 if (!vc4_encoder->hdmi_monitor)
529 if (!display->hdmi.scdc.supported ||
530 !display->hdmi.scdc.scrambling.supported)
536 #define SCRAMBLING_POLLING_DELAY_MS 1000
538 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
540 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
541 struct drm_connector *connector = &vc4_hdmi->connector;
542 struct drm_connector_state *cstate = connector->state;
543 struct drm_crtc *crtc = cstate->crtc;
544 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
546 if (!vc4_hdmi_supports_scrambling(encoder, mode))
549 if (!vc4_hdmi_mode_needs_scrambling(mode))
552 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
553 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
555 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
556 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
558 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
559 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
562 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
564 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
565 struct drm_connector *connector = &vc4_hdmi->connector;
566 struct drm_connector_state *cstate = connector->state;
569 * At boot, connector->state will be NULL. Since we don't know the
570 * state of the scrambler and in order to avoid any
571 * inconsistency, let's disable it all the time.
573 if (cstate && !vc4_hdmi_supports_scrambling(encoder, &cstate->crtc->mode))
576 if (cstate && !vc4_hdmi_mode_needs_scrambling(&cstate->crtc->mode))
579 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
580 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
582 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
583 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
585 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
586 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
589 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
591 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
595 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
598 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
599 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
601 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
602 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
605 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
606 struct drm_atomic_state *state)
608 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
610 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
612 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
616 HDMI_WRITE(HDMI_VID_CTL,
617 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
618 vc4_hdmi_disable_scrambling(encoder);
621 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
622 struct drm_atomic_state *state)
624 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
627 HDMI_WRITE(HDMI_VID_CTL,
628 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
630 if (vc4_hdmi->variant->phy_disable)
631 vc4_hdmi->variant->phy_disable(vc4_hdmi);
633 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
634 clk_disable_unprepare(vc4_hdmi->hsm_clock);
635 clk_disable_unprepare(vc4_hdmi->pixel_clock);
637 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
639 DRM_ERROR("Failed to release power domain: %d\n", ret);
642 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
646 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
650 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
651 VC4_HD_CSC_CTL_ORDER);
654 /* CEA VICs other than #1 requre limited range RGB
655 * output unless overridden by an AVI infoframe.
656 * Apply a colorspace conversion to squash 0-255 down
657 * to 16-235. The matrix here is:
664 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
665 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
666 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
667 VC4_HD_CSC_CTL_MODE);
669 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
670 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
671 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
672 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
673 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
674 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
677 /* The RGB order applies even when CSC is disabled. */
678 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
681 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
685 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
688 /* CEA VICs other than #1 requre limited range RGB
689 * output unless overridden by an AVI infoframe.
690 * Apply a colorspace conversion to squash 0-255 down
691 * to 16-235. The matrix here is:
697 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
699 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
700 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
701 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
702 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
703 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
704 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
706 /* Still use the matrix for full range, but make it unity.
707 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
709 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
710 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
711 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
712 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
713 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
714 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
717 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
720 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
721 struct drm_connector_state *state,
722 struct drm_display_mode *mode)
724 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
725 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
726 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
727 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
728 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
729 VC4_HDMI_VERTA_VSP) |
730 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
731 VC4_HDMI_VERTA_VFP) |
732 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
733 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
734 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
735 VC4_HDMI_VERTB_VBP));
736 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
737 VC4_SET_FIELD(mode->crtc_vtotal -
738 mode->crtc_vsync_end -
740 VC4_HDMI_VERTB_VBP));
742 HDMI_WRITE(HDMI_HORZA,
743 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
744 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
745 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
746 VC4_HDMI_HORZA_HAP));
748 HDMI_WRITE(HDMI_HORZB,
749 VC4_SET_FIELD((mode->htotal -
750 mode->hsync_end) * pixel_rep,
751 VC4_HDMI_HORZB_HBP) |
752 VC4_SET_FIELD((mode->hsync_end -
753 mode->hsync_start) * pixel_rep,
754 VC4_HDMI_HORZB_HSP) |
755 VC4_SET_FIELD((mode->hsync_start -
756 mode->hdisplay) * pixel_rep,
757 VC4_HDMI_HORZB_HFP));
759 HDMI_WRITE(HDMI_VERTA0, verta);
760 HDMI_WRITE(HDMI_VERTA1, verta);
762 HDMI_WRITE(HDMI_VERTB0, vertb_even);
763 HDMI_WRITE(HDMI_VERTB1, vertb);
766 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
767 struct drm_connector_state *state,
768 struct drm_display_mode *mode)
770 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
771 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
772 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
773 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
774 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
775 VC5_HDMI_VERTA_VSP) |
776 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
777 VC5_HDMI_VERTA_VFP) |
778 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
779 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
780 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
781 VC4_HDMI_VERTB_VBP));
782 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
783 VC4_SET_FIELD(mode->crtc_vtotal -
784 mode->crtc_vsync_end -
786 VC4_HDMI_VERTB_VBP));
791 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
792 HDMI_WRITE(HDMI_HORZA,
793 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
794 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
795 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
796 VC5_HDMI_HORZA_HAP) |
797 VC4_SET_FIELD((mode->hsync_start -
798 mode->hdisplay) * pixel_rep,
799 VC5_HDMI_HORZA_HFP));
801 HDMI_WRITE(HDMI_HORZB,
802 VC4_SET_FIELD((mode->htotal -
803 mode->hsync_end) * pixel_rep,
804 VC5_HDMI_HORZB_HBP) |
805 VC4_SET_FIELD((mode->hsync_end -
806 mode->hsync_start) * pixel_rep,
807 VC5_HDMI_HORZB_HSP));
809 HDMI_WRITE(HDMI_VERTA0, verta);
810 HDMI_WRITE(HDMI_VERTA1, verta);
812 HDMI_WRITE(HDMI_VERTB0, vertb_even);
813 HDMI_WRITE(HDMI_VERTB1, vertb);
815 switch (state->max_bpc) {
831 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
832 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
833 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
834 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
835 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
836 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
838 reg = HDMI_READ(HDMI_GCP_WORD_1);
839 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
840 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
841 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
843 reg = HDMI_READ(HDMI_GCP_CONFIG);
844 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
845 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
846 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
848 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
851 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
856 drift = HDMI_READ(HDMI_FIFO_CTL);
857 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
859 HDMI_WRITE(HDMI_FIFO_CTL,
860 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
861 HDMI_WRITE(HDMI_FIFO_CTL,
862 drift | VC4_HDMI_FIFO_CTL_RECENTER);
863 usleep_range(1000, 1100);
864 HDMI_WRITE(HDMI_FIFO_CTL,
865 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
866 HDMI_WRITE(HDMI_FIFO_CTL,
867 drift | VC4_HDMI_FIFO_CTL_RECENTER);
869 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
870 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
871 WARN_ONCE(ret, "Timeout waiting for "
872 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
875 static struct drm_connector_state *
876 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
877 struct drm_atomic_state *state)
879 struct drm_connector_state *conn_state;
880 struct drm_connector *connector;
883 for_each_new_connector_in_state(state, connector, conn_state, i) {
884 if (conn_state->best_encoder == encoder)
891 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
892 struct drm_atomic_state *state)
894 struct drm_connector_state *conn_state =
895 vc4_hdmi_encoder_get_connector_state(encoder, state);
896 struct vc4_hdmi_connector_state *vc4_conn_state =
897 conn_state_to_vc4_hdmi_conn_state(conn_state);
898 struct drm_crtc_state *crtc_state =
899 drm_atomic_get_new_crtc_state(state, conn_state->crtc);
900 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
901 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
902 unsigned long bvb_rate, pixel_rate, hsm_rate;
905 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
907 DRM_ERROR("Failed to retain power domain: %d\n", ret);
911 pixel_rate = vc4_conn_state->pixel_rate;
912 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
914 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
918 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
920 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
925 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
926 * be faster than pixel clock, infinitesimally faster, tested in
927 * simulation. Otherwise, exact value is unimportant for HDMI
928 * operation." This conflicts with bcm2835's vc4 documentation, which
929 * states HSM's clock has to be at least 108% of the pixel clock.
931 * Real life tests reveal that vc4's firmware statement holds up, and
932 * users are able to use pixel clocks closer to HSM's, namely for
933 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
934 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
937 * Additionally, the AXI clock needs to be at least 25% of
938 * pixel clock, but HSM ends up being the limiting factor.
940 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
941 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
943 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
947 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
949 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
950 clk_disable_unprepare(vc4_hdmi->pixel_clock);
954 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
956 if (pixel_rate > 297000000)
957 bvb_rate = 300000000;
958 else if (pixel_rate > 148500000)
959 bvb_rate = 150000000;
963 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
965 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
966 clk_disable_unprepare(vc4_hdmi->hsm_clock);
967 clk_disable_unprepare(vc4_hdmi->pixel_clock);
971 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
973 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
974 clk_disable_unprepare(vc4_hdmi->hsm_clock);
975 clk_disable_unprepare(vc4_hdmi->pixel_clock);
979 if (vc4_hdmi->variant->phy_init)
980 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
982 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
983 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
984 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
985 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
987 if (vc4_hdmi->variant->set_timings)
988 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
991 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
992 struct drm_atomic_state *state)
994 struct drm_connector_state *conn_state =
995 vc4_hdmi_encoder_get_connector_state(encoder, state);
996 struct drm_crtc_state *crtc_state =
997 drm_atomic_get_new_crtc_state(state, conn_state->crtc);
998 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
999 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1000 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1002 if (vc4_encoder->hdmi_monitor &&
1003 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
1004 if (vc4_hdmi->variant->csc_setup)
1005 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1007 vc4_encoder->limited_rgb_range = true;
1009 if (vc4_hdmi->variant->csc_setup)
1010 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1012 vc4_encoder->limited_rgb_range = false;
1015 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1018 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1019 struct drm_atomic_state *state)
1021 struct drm_connector_state *conn_state =
1022 vc4_hdmi_encoder_get_connector_state(encoder, state);
1023 struct drm_crtc_state *crtc_state =
1024 drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1025 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1026 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1027 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1028 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1029 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1032 HDMI_WRITE(HDMI_VID_CTL,
1033 VC4_HD_VID_CTL_ENABLE |
1034 VC4_HD_VID_CTL_CLRRGB |
1035 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1036 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1037 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1038 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1040 HDMI_WRITE(HDMI_VID_CTL,
1041 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1043 if (vc4_encoder->hdmi_monitor) {
1044 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1045 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1046 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1048 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1049 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1050 WARN_ONCE(ret, "Timeout waiting for "
1051 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1053 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1054 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1055 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1056 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1057 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1058 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1060 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1061 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1062 WARN_ONCE(ret, "Timeout waiting for "
1063 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1066 if (vc4_encoder->hdmi_monitor) {
1067 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1068 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1069 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1070 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1071 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1073 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1074 VC4_HDMI_RAM_PACKET_ENABLE);
1076 vc4_hdmi_set_infoframes(encoder);
1079 vc4_hdmi_recenter_fifo(vc4_hdmi);
1080 vc4_hdmi_enable_scrambling(encoder);
1083 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1087 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1088 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1090 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1091 struct drm_crtc_state *crtc_state,
1092 struct drm_connector_state *conn_state)
1094 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1095 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1096 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1097 unsigned long long pixel_rate = mode->clock * 1000;
1098 unsigned long long tmds_rate;
1100 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1101 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1102 (mode->hsync_end % 2) || (mode->htotal % 2)))
1106 * The 1440p@60 pixel rate is in the same range than the first
1107 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1108 * bandwidth). Slightly lower the frequency to bring it out of
1111 tmds_rate = pixel_rate * 10;
1112 if (vc4_hdmi->disable_wifi_frequencies &&
1113 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1114 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1115 mode->clock = 238560;
1116 pixel_rate = mode->clock * 1000;
1119 if (conn_state->max_bpc == 12) {
1120 pixel_rate = pixel_rate * 150;
1121 do_div(pixel_rate, 100);
1122 } else if (conn_state->max_bpc == 10) {
1123 pixel_rate = pixel_rate * 125;
1124 do_div(pixel_rate, 100);
1127 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1128 pixel_rate = pixel_rate * 2;
1130 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1133 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1136 vc4_state->pixel_rate = pixel_rate;
1141 static enum drm_mode_status
1142 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1143 const struct drm_display_mode *mode)
1145 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1147 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1148 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1149 (mode->hsync_end % 2) || (mode->htotal % 2)))
1150 return MODE_H_ILLEGAL;
1152 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1153 return MODE_CLOCK_HIGH;
1155 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1156 return MODE_CLOCK_HIGH;
1161 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1162 .atomic_check = vc4_hdmi_encoder_atomic_check,
1163 .mode_valid = vc4_hdmi_encoder_mode_valid,
1164 .disable = vc4_hdmi_encoder_disable,
1165 .enable = vc4_hdmi_encoder_enable,
1168 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1171 u32 channel_map = 0;
1173 for (i = 0; i < 8; i++) {
1174 if (channel_mask & BIT(i))
1175 channel_map |= i << (3 * i);
1180 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1183 u32 channel_map = 0;
1185 for (i = 0; i < 8; i++) {
1186 if (channel_mask & BIT(i))
1187 channel_map |= i << (4 * i);
1192 /* HDMI audio codec callbacks */
1193 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
1195 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1198 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
1199 VC4_HD_MAI_SMP_N_MASK >>
1200 VC4_HD_MAI_SMP_N_SHIFT,
1201 (VC4_HD_MAI_SMP_M_MASK >>
1202 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1205 HDMI_WRITE(HDMI_MAI_SMP,
1206 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1207 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1210 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
1212 struct drm_connector *connector = &vc4_hdmi->connector;
1213 struct drm_crtc *crtc = connector->state->crtc;
1214 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1215 u32 samplerate = vc4_hdmi->audio.samplerate;
1219 n = 128 * samplerate / 1000;
1220 tmp = (u64)(mode->clock * 1000) * n;
1221 do_div(tmp, 128 * samplerate);
1224 HDMI_WRITE(HDMI_CRP_CFG,
1225 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1226 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1229 * We could get slightly more accurate clocks in some cases by
1230 * providing a CTS_1 value. The two CTS values are alternated
1231 * between based on the period fields
1233 HDMI_WRITE(HDMI_CTS_0, cts);
1234 HDMI_WRITE(HDMI_CTS_1, cts);
1237 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1239 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1241 return snd_soc_card_get_drvdata(card);
1244 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1246 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1247 struct drm_connector *connector = &vc4_hdmi->connector;
1250 * If the HDMI encoder hasn't probed, or the encoder is
1251 * currently in DVI mode, treat the codec dai as missing.
1253 if (!connector->state || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1254 VC4_HDMI_RAM_PACKET_ENABLE))
1257 vc4_hdmi->audio.streaming = true;
1259 HDMI_WRITE(HDMI_MAI_CTL,
1260 VC4_HD_MAI_CTL_RESET |
1261 VC4_HD_MAI_CTL_FLUSH |
1262 VC4_HD_MAI_CTL_DLATE |
1263 VC4_HD_MAI_CTL_ERRORE |
1264 VC4_HD_MAI_CTL_ERRORF);
1266 if (vc4_hdmi->variant->phy_rng_enable)
1267 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1272 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1274 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1275 struct device *dev = &vc4_hdmi->pdev->dev;
1278 vc4_hdmi->audio.streaming = false;
1279 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1281 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1283 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1284 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1285 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1288 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1290 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1292 HDMI_WRITE(HDMI_MAI_CTL,
1293 VC4_HD_MAI_CTL_DLATE |
1294 VC4_HD_MAI_CTL_ERRORE |
1295 VC4_HD_MAI_CTL_ERRORF);
1297 if (vc4_hdmi->variant->phy_rng_disable)
1298 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1300 vc4_hdmi->audio.streaming = false;
1301 vc4_hdmi_audio_reset(vc4_hdmi);
1304 static int sample_rate_to_mai_fmt(int samplerate)
1306 switch (samplerate) {
1308 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1310 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1312 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1314 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1316 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1318 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1320 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1322 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1324 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1326 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1328 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1330 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1332 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1334 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1336 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1338 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1342 /* HDMI audio codec callbacks */
1343 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1344 struct hdmi_codec_daifmt *daifmt,
1345 struct hdmi_codec_params *params)
1347 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1348 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1349 u32 audio_packet_config, channel_mask;
1351 u32 mai_audio_format;
1352 u32 mai_sample_rate;
1354 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1355 params->sample_rate, params->sample_width,
1358 vc4_hdmi->audio.channels = params->channels;
1359 vc4_hdmi->audio.samplerate = params->sample_rate;
1361 HDMI_WRITE(HDMI_MAI_CTL,
1362 VC4_SET_FIELD(params->channels, VC4_HD_MAI_CTL_CHNUM) |
1363 VC4_HD_MAI_CTL_WHOLSMP |
1364 VC4_HD_MAI_CTL_CHALIGN |
1365 VC4_HD_MAI_CTL_ENABLE);
1367 vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1369 mai_sample_rate = sample_rate_to_mai_fmt(vc4_hdmi->audio.samplerate);
1370 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1371 params->channels == 8)
1372 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1374 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1375 HDMI_WRITE(HDMI_MAI_FMT,
1376 VC4_SET_FIELD(mai_sample_rate,
1377 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1378 VC4_SET_FIELD(mai_audio_format,
1379 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1381 /* The B frame identifier should match the value used by alsa-lib (8) */
1382 audio_packet_config =
1383 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1384 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1385 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1387 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1388 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1389 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1391 /* Set the MAI threshold */
1392 HDMI_WRITE(HDMI_MAI_THR,
1393 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1394 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1395 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1396 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1398 HDMI_WRITE(HDMI_MAI_CONFIG,
1399 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1400 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1401 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1403 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1404 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1405 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1406 vc4_hdmi_set_n_cts(vc4_hdmi);
1408 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
1409 vc4_hdmi_set_audio_infoframe(encoder);
1414 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1415 SND_SOC_DAPM_OUTPUT("TX"),
1418 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1419 { "TX", NULL, "Playback" },
1422 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1423 .name = "vc4-hdmi-codec-dai-component",
1424 .dapm_widgets = vc4_hdmi_audio_widgets,
1425 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1426 .dapm_routes = vc4_hdmi_audio_routes,
1427 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
1429 .use_pmdown_time = 1,
1431 .non_legacy_dai_naming = 1,
1434 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1435 .name = "vc4-hdmi-cpu-dai-component",
1438 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1440 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1442 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1447 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1448 .name = "vc4-hdmi-cpu-dai",
1449 .probe = vc4_hdmi_audio_cpu_dai_probe,
1451 .stream_name = "Playback",
1454 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1455 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1456 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1457 SNDRV_PCM_RATE_192000,
1458 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1462 static const struct snd_dmaengine_pcm_config pcm_conf = {
1463 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1464 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1467 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1468 uint8_t *buf, size_t len)
1470 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1471 struct drm_connector *connector = &vc4_hdmi->connector;
1473 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1478 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1479 .get_eld = vc4_hdmi_audio_get_eld,
1480 .prepare = vc4_hdmi_audio_prepare,
1481 .audio_shutdown = vc4_hdmi_audio_shutdown,
1482 .audio_startup = vc4_hdmi_audio_startup,
1485 struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1486 .ops = &vc4_hdmi_codec_ops,
1487 .max_i2s_channels = 8,
1491 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1493 const struct vc4_hdmi_register *mai_data =
1494 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1495 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1496 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1497 struct device *dev = &vc4_hdmi->pdev->dev;
1498 struct platform_device *codec_pdev;
1503 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1505 "'dmas' DT property is missing, no HDMI audio\n");
1509 if (mai_data->reg != VC4_HD) {
1510 WARN_ONCE(true, "MAI isn't in the HD block\n");
1515 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1516 * the bus address specified in the DT, because the physical address
1517 * (the one returned by platform_get_resource()) is not appropriate
1518 * for DMA transfers.
1519 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1521 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1522 /* Before BCM2711, we don't have a named register range */
1526 addr = of_get_address(dev->of_node, index, NULL, NULL);
1528 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1529 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1530 vc4_hdmi->audio.dma_data.maxburst = 2;
1532 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1534 dev_err(dev, "Could not register PCM component: %d\n", ret);
1538 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1539 &vc4_hdmi_audio_cpu_dai_drv, 1);
1541 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1545 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1546 PLATFORM_DEVID_AUTO,
1547 &vc4_hdmi_codec_pdata,
1548 sizeof(vc4_hdmi_codec_pdata));
1549 if (IS_ERR(codec_pdev)) {
1550 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1551 return PTR_ERR(codec_pdev);
1554 dai_link->cpus = &vc4_hdmi->audio.cpu;
1555 dai_link->codecs = &vc4_hdmi->audio.codec;
1556 dai_link->platforms = &vc4_hdmi->audio.platform;
1558 dai_link->num_cpus = 1;
1559 dai_link->num_codecs = 1;
1560 dai_link->num_platforms = 1;
1562 dai_link->name = "MAI";
1563 dai_link->stream_name = "MAI PCM";
1564 dai_link->codecs->dai_name = "i2s-hifi";
1565 dai_link->cpus->dai_name = dev_name(dev);
1566 dai_link->codecs->name = dev_name(&codec_pdev->dev);
1567 dai_link->platforms->name = dev_name(dev);
1569 card->dai_link = dai_link;
1570 card->num_links = 1;
1571 card->name = vc4_hdmi->variant->card_name;
1572 card->driver_name = "vc4-hdmi";
1574 card->owner = THIS_MODULE;
1577 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1578 * stores a pointer to the snd card object in dev->driver_data. This
1579 * means we cannot use it for something else. The hdmi back-pointer is
1580 * now stored in card->drvdata and should be retrieved with
1581 * snd_soc_card_get_drvdata() if needed.
1583 snd_soc_card_set_drvdata(card, vc4_hdmi);
1584 ret = devm_snd_soc_register_card(dev, card);
1586 dev_err_probe(dev, ret, "Could not register sound card\n");
1592 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1594 struct vc4_hdmi *vc4_hdmi = priv;
1595 struct drm_device *dev = vc4_hdmi->connector.dev;
1597 if (dev && dev->registered)
1598 drm_kms_helper_hotplug_event(dev);
1603 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1605 struct drm_connector *connector = &vc4_hdmi->connector;
1606 struct platform_device *pdev = vc4_hdmi->pdev;
1609 if (vc4_hdmi->variant->external_irq_controller) {
1610 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1611 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1613 ret = request_threaded_irq(hpd_con,
1615 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1616 "vc4 hdmi hpd connected", vc4_hdmi);
1620 ret = request_threaded_irq(hpd_rm,
1622 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1623 "vc4 hdmi hpd disconnected", vc4_hdmi);
1625 free_irq(hpd_con, vc4_hdmi);
1629 connector->polled = DRM_CONNECTOR_POLL_HPD;
1635 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1637 struct platform_device *pdev = vc4_hdmi->pdev;
1639 if (vc4_hdmi->variant->external_irq_controller) {
1640 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1641 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1645 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1646 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1648 struct vc4_hdmi *vc4_hdmi = priv;
1650 if (vc4_hdmi->cec_rx_msg.len)
1651 cec_received_msg(vc4_hdmi->cec_adap,
1652 &vc4_hdmi->cec_rx_msg);
1657 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1659 struct vc4_hdmi *vc4_hdmi = priv;
1661 if (vc4_hdmi->cec_tx_ok) {
1662 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1666 * This CEC implementation makes 1 retry, so if we
1667 * get a NACK, then that means it made 2 attempts.
1669 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1675 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1677 struct vc4_hdmi *vc4_hdmi = priv;
1680 if (vc4_hdmi->cec_irq_was_rx)
1681 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1683 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1688 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1690 struct drm_device *dev = vc4_hdmi->connector.dev;
1691 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1694 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1695 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1697 if (msg->len > 16) {
1698 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1702 for (i = 0; i < msg->len; i += 4) {
1703 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1705 msg->msg[i] = val & 0xff;
1706 msg->msg[i + 1] = (val >> 8) & 0xff;
1707 msg->msg[i + 2] = (val >> 16) & 0xff;
1708 msg->msg[i + 3] = (val >> 24) & 0xff;
1712 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1714 struct vc4_hdmi *vc4_hdmi = priv;
1717 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1718 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1719 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1720 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1722 return IRQ_WAKE_THREAD;
1725 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1727 struct vc4_hdmi *vc4_hdmi = priv;
1730 vc4_hdmi->cec_rx_msg.len = 0;
1731 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1732 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1733 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1734 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1735 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1737 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1739 return IRQ_WAKE_THREAD;
1742 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1744 struct vc4_hdmi *vc4_hdmi = priv;
1745 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1749 if (!(stat & VC4_HDMI_CPU_CEC))
1752 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1753 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1754 if (vc4_hdmi->cec_irq_was_rx)
1755 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1757 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1759 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1763 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1765 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1766 /* clock period in microseconds */
1767 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1768 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1770 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1771 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1772 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1773 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1774 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1777 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1778 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1779 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1780 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1781 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1782 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1783 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1784 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1785 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1786 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1787 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1788 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1789 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1790 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1791 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1792 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1793 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1794 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1795 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1797 if (!vc4_hdmi->variant->external_irq_controller)
1798 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1800 if (!vc4_hdmi->variant->external_irq_controller)
1801 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1802 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1803 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1808 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1810 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1812 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1813 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1814 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1818 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1819 u32 signal_free_time, struct cec_msg *msg)
1821 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1822 struct drm_device *dev = vc4_hdmi->connector.dev;
1826 if (msg->len > 16) {
1827 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1831 for (i = 0; i < msg->len; i += 4)
1832 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1834 (msg->msg[i + 1] << 8) |
1835 (msg->msg[i + 2] << 16) |
1836 (msg->msg[i + 3] << 24));
1838 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1839 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1840 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1841 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1842 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1843 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1845 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1849 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1850 .adap_enable = vc4_hdmi_cec_adap_enable,
1851 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1852 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1855 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1857 struct cec_connector_info conn_info;
1858 struct platform_device *pdev = vc4_hdmi->pdev;
1859 struct device *dev = &pdev->dev;
1863 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1864 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1868 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1871 CEC_CAP_CONNECTOR_INFO, 1);
1872 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1876 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1877 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1879 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1880 /* Set the logical address to Unregistered */
1881 value |= VC4_HDMI_CEC_ADDR_MASK;
1882 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1884 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1886 if (vc4_hdmi->variant->external_irq_controller) {
1887 ret = devm_request_threaded_irq(&pdev->dev,
1888 platform_get_irq_byname(pdev, "cec-rx"),
1889 vc4_cec_irq_handler_rx_bare,
1890 vc4_cec_irq_handler_rx_thread, 0,
1891 "vc4 hdmi cec rx", vc4_hdmi);
1893 goto err_delete_cec_adap;
1895 ret = devm_request_threaded_irq(&pdev->dev,
1896 platform_get_irq_byname(pdev, "cec-tx"),
1897 vc4_cec_irq_handler_tx_bare,
1898 vc4_cec_irq_handler_tx_thread, 0,
1899 "vc4 hdmi cec tx", vc4_hdmi);
1901 goto err_delete_cec_adap;
1903 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1905 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1906 vc4_cec_irq_handler,
1907 vc4_cec_irq_handler_thread, 0,
1908 "vc4 hdmi cec", vc4_hdmi);
1910 goto err_delete_cec_adap;
1913 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1915 goto err_delete_cec_adap;
1919 err_delete_cec_adap:
1920 cec_delete_adapter(vc4_hdmi->cec_adap);
1925 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1927 cec_unregister_adapter(vc4_hdmi->cec_adap);
1930 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1935 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1939 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1940 struct debugfs_regset32 *regset,
1941 enum vc4_hdmi_regs reg)
1943 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1944 struct debugfs_reg32 *regs, *new_regs;
1945 unsigned int count = 0;
1948 regs = kcalloc(variant->num_registers, sizeof(*regs),
1953 for (i = 0; i < variant->num_registers; i++) {
1954 const struct vc4_hdmi_register *field = &variant->registers[i];
1956 if (field->reg != reg)
1959 regs[count].name = field->name;
1960 regs[count].offset = field->offset;
1964 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1968 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1969 regset->regs = new_regs;
1970 regset->nregs = count;
1975 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1977 struct platform_device *pdev = vc4_hdmi->pdev;
1978 struct device *dev = &pdev->dev;
1981 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1982 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1983 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1985 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1986 if (IS_ERR(vc4_hdmi->hd_regs))
1987 return PTR_ERR(vc4_hdmi->hd_regs);
1989 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1993 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1997 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1998 if (IS_ERR(vc4_hdmi->pixel_clock)) {
1999 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2000 if (ret != -EPROBE_DEFER)
2001 DRM_ERROR("Failed to get pixel clock\n");
2005 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2006 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2007 DRM_ERROR("Failed to get HDMI state machine clock\n");
2008 return PTR_ERR(vc4_hdmi->hsm_clock);
2010 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2011 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2016 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2018 struct platform_device *pdev = vc4_hdmi->pdev;
2019 struct device *dev = &pdev->dev;
2020 struct resource *res;
2022 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2026 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2027 resource_size(res));
2028 if (!vc4_hdmi->hdmicore_regs)
2031 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2035 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2036 if (!vc4_hdmi->hd_regs)
2039 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2043 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2044 if (!vc4_hdmi->cec_regs)
2047 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2051 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2052 if (!vc4_hdmi->csc_regs)
2055 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2059 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2060 if (!vc4_hdmi->dvp_regs)
2063 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2067 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2068 if (!vc4_hdmi->phy_regs)
2071 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2075 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2076 if (!vc4_hdmi->ram_regs)
2079 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2083 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2084 if (!vc4_hdmi->rm_regs)
2087 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2088 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2089 DRM_ERROR("Failed to get HDMI state machine clock\n");
2090 return PTR_ERR(vc4_hdmi->hsm_clock);
2093 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2094 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2095 DRM_ERROR("Failed to get pixel bvb clock\n");
2096 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2099 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2100 if (IS_ERR(vc4_hdmi->audio_clock)) {
2101 DRM_ERROR("Failed to get audio clock\n");
2102 return PTR_ERR(vc4_hdmi->audio_clock);
2105 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2106 if (IS_ERR(vc4_hdmi->cec_clock)) {
2107 DRM_ERROR("Failed to get CEC clock\n");
2108 return PTR_ERR(vc4_hdmi->cec_clock);
2111 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2112 if (IS_ERR(vc4_hdmi->reset)) {
2113 DRM_ERROR("Failed to get HDMI reset line\n");
2114 return PTR_ERR(vc4_hdmi->reset);
2120 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2122 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2123 struct platform_device *pdev = to_platform_device(dev);
2124 struct drm_device *drm = dev_get_drvdata(master);
2125 struct vc4_hdmi *vc4_hdmi;
2126 struct drm_encoder *encoder;
2127 struct device_node *ddc_node;
2130 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2133 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2135 dev_set_drvdata(dev, vc4_hdmi);
2136 encoder = &vc4_hdmi->encoder.base.base;
2137 vc4_hdmi->encoder.base.type = variant->encoder_type;
2138 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2139 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2140 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2141 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2142 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2143 vc4_hdmi->pdev = pdev;
2144 vc4_hdmi->variant = variant;
2146 ret = variant->init_resources(vc4_hdmi);
2150 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2152 DRM_ERROR("Failed to find ddc node in device tree\n");
2156 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2157 of_node_put(ddc_node);
2158 if (!vc4_hdmi->ddc) {
2159 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2160 return -EPROBE_DEFER;
2163 /* Only use the GPIO HPD pin if present in the DT, otherwise
2164 * we'll use the HDMI core's register.
2166 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2167 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2168 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2172 vc4_hdmi->disable_wifi_frequencies =
2173 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2175 if (variant->max_pixel_clock == 600000000) {
2176 struct vc4_dev *vc4 = to_vc4_dev(drm);
2177 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2179 if (max_rate < 550000000)
2180 vc4_hdmi->disable_4kp60 = true;
2183 if (vc4_hdmi->variant->reset)
2184 vc4_hdmi->variant->reset(vc4_hdmi);
2186 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2187 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2188 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2189 clk_prepare_enable(vc4_hdmi->pixel_clock);
2190 clk_prepare_enable(vc4_hdmi->hsm_clock);
2191 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2194 pm_runtime_enable(dev);
2196 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2197 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2199 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2201 goto err_destroy_encoder;
2203 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2205 goto err_destroy_conn;
2207 ret = vc4_hdmi_cec_init(vc4_hdmi);
2209 goto err_free_hotplug;
2211 ret = vc4_hdmi_audio_init(vc4_hdmi);
2215 vc4_debugfs_add_file(drm, variant->debugfs_name,
2216 vc4_hdmi_debugfs_regs,
2222 vc4_hdmi_cec_exit(vc4_hdmi);
2224 vc4_hdmi_hotplug_exit(vc4_hdmi);
2226 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2227 err_destroy_encoder:
2228 drm_encoder_cleanup(encoder);
2229 pm_runtime_disable(dev);
2231 put_device(&vc4_hdmi->ddc->dev);
2236 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2239 struct vc4_hdmi *vc4_hdmi;
2242 * ASoC makes it a bit hard to retrieve a pointer to the
2243 * vc4_hdmi structure. Registering the card will overwrite our
2244 * device drvdata with a pointer to the snd_soc_card structure,
2245 * which can then be used to retrieve whatever drvdata we want
2248 * However, that doesn't fly in the case where we wouldn't
2249 * register an ASoC card (because of an old DT that is missing
2250 * the dmas properties for example), then the card isn't
2251 * registered and the device drvdata wouldn't be set.
2253 * We can deal with both cases by making sure a snd_soc_card
2254 * pointer and a vc4_hdmi structure are pointing to the same
2255 * memory address, so we can treat them indistinctly without any
2258 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2259 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2260 vc4_hdmi = dev_get_drvdata(dev);
2262 kfree(vc4_hdmi->hdmi_regset.regs);
2263 kfree(vc4_hdmi->hd_regset.regs);
2265 vc4_hdmi_cec_exit(vc4_hdmi);
2266 vc4_hdmi_hotplug_exit(vc4_hdmi);
2267 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2268 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2270 pm_runtime_disable(dev);
2272 put_device(&vc4_hdmi->ddc->dev);
2275 static const struct component_ops vc4_hdmi_ops = {
2276 .bind = vc4_hdmi_bind,
2277 .unbind = vc4_hdmi_unbind,
2280 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2282 return component_add(&pdev->dev, &vc4_hdmi_ops);
2285 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2287 component_del(&pdev->dev, &vc4_hdmi_ops);
2291 static const struct vc4_hdmi_variant bcm2835_variant = {
2292 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2293 .debugfs_name = "hdmi_regs",
2294 .card_name = "vc4-hdmi",
2295 .max_pixel_clock = 162000000,
2296 .registers = vc4_hdmi_fields,
2297 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
2299 .init_resources = vc4_hdmi_init_resources,
2300 .csc_setup = vc4_hdmi_csc_setup,
2301 .reset = vc4_hdmi_reset,
2302 .set_timings = vc4_hdmi_set_timings,
2303 .phy_init = vc4_hdmi_phy_init,
2304 .phy_disable = vc4_hdmi_phy_disable,
2305 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
2306 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
2307 .channel_map = vc4_hdmi_channel_map,
2308 .supports_hdr = false,
2311 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2312 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2313 .debugfs_name = "hdmi0_regs",
2314 .card_name = "vc4-hdmi-0",
2315 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2316 .registers = vc5_hdmi_hdmi0_fields,
2317 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2318 .phy_lane_mapping = {
2324 .unsupported_odd_h_timings = true,
2325 .external_irq_controller = true,
2327 .init_resources = vc5_hdmi_init_resources,
2328 .csc_setup = vc5_hdmi_csc_setup,
2329 .reset = vc5_hdmi_reset,
2330 .set_timings = vc5_hdmi_set_timings,
2331 .phy_init = vc5_hdmi_phy_init,
2332 .phy_disable = vc5_hdmi_phy_disable,
2333 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2334 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2335 .channel_map = vc5_hdmi_channel_map,
2336 .supports_hdr = true,
2339 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2340 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
2341 .debugfs_name = "hdmi1_regs",
2342 .card_name = "vc4-hdmi-1",
2343 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2344 .registers = vc5_hdmi_hdmi1_fields,
2345 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2346 .phy_lane_mapping = {
2352 .unsupported_odd_h_timings = true,
2353 .external_irq_controller = true,
2355 .init_resources = vc5_hdmi_init_resources,
2356 .csc_setup = vc5_hdmi_csc_setup,
2357 .reset = vc5_hdmi_reset,
2358 .set_timings = vc5_hdmi_set_timings,
2359 .phy_init = vc5_hdmi_phy_init,
2360 .phy_disable = vc5_hdmi_phy_disable,
2361 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2362 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2363 .channel_map = vc5_hdmi_channel_map,
2364 .supports_hdr = true,
2367 static const struct of_device_id vc4_hdmi_dt_match[] = {
2368 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2369 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2370 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2374 struct platform_driver vc4_hdmi_driver = {
2375 .probe = vc4_hdmi_dev_probe,
2376 .remove = vc4_hdmi_dev_remove,
2379 .of_match_table = vc4_hdmi_dt_match,