1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
4 #include <drm/panfrost_drm.h>
6 #include <linux/atomic.h>
7 #include <linux/bitfield.h>
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/interrupt.h>
12 #include <linux/iopoll.h>
13 #include <linux/io-pgtable.h>
14 #include <linux/iommu.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/shmem_fs.h>
18 #include <linux/sizes.h>
20 #include "panfrost_device.h"
21 #include "panfrost_mmu.h"
22 #include "panfrost_gem.h"
23 #include "panfrost_features.h"
24 #include "panfrost_regs.h"
26 #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg)
27 #define mmu_read(dev, reg) readl(dev->iomem + reg)
29 static int wait_ready(struct panfrost_device *pfdev, u32 as_nr)
34 /* Wait for the MMU status to indicate there is no active command, in
35 * case one is pending. */
36 ret = readl_relaxed_poll_timeout_atomic(pfdev->iomem + AS_STATUS(as_nr),
37 val, !(val & AS_STATUS_AS_ACTIVE), 10, 100000);
40 /* The GPU hung, let's trigger a reset */
41 panfrost_device_schedule_reset(pfdev);
42 dev_err(pfdev->dev, "AS_ACTIVE bit stuck\n");
48 static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd)
52 /* write AS_COMMAND when MMU is ready to accept another command */
53 status = wait_ready(pfdev, as_nr);
55 mmu_write(pfdev, AS_COMMAND(as_nr), cmd);
60 static void lock_region(struct panfrost_device *pfdev, u32 as_nr,
64 u64 region = iova & PAGE_MASK;
66 /* The size is encoded as ceil(log2) minus(1), which may be calculated
67 * with fls. The size must be clamped to hardware bounds.
69 size = max_t(u64, size, AS_LOCK_REGION_MIN_SIZE);
70 region_width = fls64(size - 1) - 1;
71 region |= region_width;
73 /* Lock the region that needs to be updated */
74 mmu_write(pfdev, AS_LOCKADDR_LO(as_nr), region & 0xFFFFFFFFUL);
75 mmu_write(pfdev, AS_LOCKADDR_HI(as_nr), (region >> 32) & 0xFFFFFFFFUL);
76 write_cmd(pfdev, as_nr, AS_COMMAND_LOCK);
80 static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr,
81 u64 iova, u64 size, u32 op)
86 if (op != AS_COMMAND_UNLOCK)
87 lock_region(pfdev, as_nr, iova, size);
89 /* Run the MMU operation */
90 write_cmd(pfdev, as_nr, op);
92 /* Wait for the flush to complete */
93 return wait_ready(pfdev, as_nr);
96 static int mmu_hw_do_operation(struct panfrost_device *pfdev,
97 struct panfrost_mmu *mmu,
98 u64 iova, u64 size, u32 op)
102 spin_lock(&pfdev->as_lock);
103 ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op);
104 spin_unlock(&pfdev->as_lock);
108 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
111 struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg;
112 u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
113 u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
115 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
117 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL);
118 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), transtab >> 32);
120 /* Need to revisit mem attrs.
121 * NC is the default, Mali driver is inner WT.
123 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), memattr & 0xffffffffUL);
124 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), memattr >> 32);
126 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
129 static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr)
131 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
133 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0);
134 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0);
136 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0);
137 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0);
139 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
142 u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
146 spin_lock(&pfdev->as_lock);
150 int en = atomic_inc_return(&mmu->as_count);
151 u32 mask = BIT(as) | BIT(16 + as);
154 * AS can be retained by active jobs or a perfcnt context,
155 * hence the '+ 1' here.
157 WARN_ON(en >= (NUM_JOB_SLOTS + 1));
159 list_move(&mmu->list, &pfdev->as_lru_list);
161 if (pfdev->as_faulty_mask & mask) {
162 /* Unhandled pagefault on this AS, the MMU was
163 * disabled. We need to re-enable the MMU after
164 * clearing+unmasking the AS interrupts.
166 mmu_write(pfdev, MMU_INT_CLEAR, mask);
167 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask);
168 pfdev->as_faulty_mask &= ~mask;
169 panfrost_mmu_enable(pfdev, mmu);
175 /* Check for a free AS */
176 as = ffz(pfdev->as_alloc_mask);
177 if (!(BIT(as) & pfdev->features.as_present)) {
178 struct panfrost_mmu *lru_mmu;
180 list_for_each_entry_reverse(lru_mmu, &pfdev->as_lru_list, list) {
181 if (!atomic_read(&lru_mmu->as_count))
184 WARN_ON(&lru_mmu->list == &pfdev->as_lru_list);
186 list_del_init(&lru_mmu->list);
193 /* Assign the free or reclaimed AS to the FD */
195 set_bit(as, &pfdev->as_alloc_mask);
196 atomic_set(&mmu->as_count, 1);
197 list_add(&mmu->list, &pfdev->as_lru_list);
199 dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask);
201 panfrost_mmu_enable(pfdev, mmu);
204 spin_unlock(&pfdev->as_lock);
208 void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
210 atomic_dec(&mmu->as_count);
211 WARN_ON(atomic_read(&mmu->as_count) < 0);
214 void panfrost_mmu_reset(struct panfrost_device *pfdev)
216 struct panfrost_mmu *mmu, *mmu_tmp;
218 spin_lock(&pfdev->as_lock);
220 pfdev->as_alloc_mask = 0;
221 pfdev->as_faulty_mask = 0;
223 list_for_each_entry_safe(mmu, mmu_tmp, &pfdev->as_lru_list, list) {
225 atomic_set(&mmu->as_count, 0);
226 list_del_init(&mmu->list);
229 spin_unlock(&pfdev->as_lock);
231 mmu_write(pfdev, MMU_INT_CLEAR, ~0);
232 mmu_write(pfdev, MMU_INT_MASK, ~0);
235 static size_t get_pgsize(u64 addr, size_t size)
237 if (addr & (SZ_2M - 1) || size < SZ_2M)
243 static void panfrost_mmu_flush_range(struct panfrost_device *pfdev,
244 struct panfrost_mmu *mmu,
250 pm_runtime_get_noresume(pfdev->dev);
252 /* Flush the PTs only if we're already awake */
253 if (pm_runtime_active(pfdev->dev))
254 mmu_hw_do_operation(pfdev, mmu, iova, size, AS_COMMAND_FLUSH_PT);
256 pm_runtime_put_sync_autosuspend(pfdev->dev);
259 static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu,
260 u64 iova, int prot, struct sg_table *sgt)
263 struct scatterlist *sgl;
264 struct io_pgtable_ops *ops = mmu->pgtbl_ops;
265 u64 start_iova = iova;
267 for_each_sgtable_dma_sg(sgt, sgl, count) {
268 unsigned long paddr = sg_dma_address(sgl);
269 size_t len = sg_dma_len(sgl);
271 dev_dbg(pfdev->dev, "map: as=%d, iova=%llx, paddr=%lx, len=%zx", mmu->as, iova, paddr, len);
274 size_t pgsize = get_pgsize(iova | paddr, len);
276 ops->map(ops, iova, paddr, pgsize, prot, GFP_KERNEL);
283 panfrost_mmu_flush_range(pfdev, mmu, start_iova, iova - start_iova);
288 int panfrost_mmu_map(struct panfrost_gem_mapping *mapping)
290 struct panfrost_gem_object *bo = mapping->obj;
291 struct drm_gem_object *obj = &bo->base.base;
292 struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
293 struct sg_table *sgt;
294 int prot = IOMMU_READ | IOMMU_WRITE;
296 if (WARN_ON(mapping->active))
300 prot |= IOMMU_NOEXEC;
302 sgt = drm_gem_shmem_get_pages_sgt(obj);
303 if (WARN_ON(IS_ERR(sgt)))
306 mmu_map_sg(pfdev, mapping->mmu, mapping->mmnode.start << PAGE_SHIFT,
308 mapping->active = true;
313 void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping)
315 struct panfrost_gem_object *bo = mapping->obj;
316 struct drm_gem_object *obj = &bo->base.base;
317 struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
318 struct io_pgtable_ops *ops = mapping->mmu->pgtbl_ops;
319 u64 iova = mapping->mmnode.start << PAGE_SHIFT;
320 size_t len = mapping->mmnode.size << PAGE_SHIFT;
321 size_t unmapped_len = 0;
323 if (WARN_ON(!mapping->active))
326 dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx",
327 mapping->mmu->as, iova, len);
329 while (unmapped_len < len) {
330 size_t unmapped_page;
331 size_t pgsize = get_pgsize(iova, len - unmapped_len);
333 if (ops->iova_to_phys(ops, iova)) {
334 unmapped_page = ops->unmap(ops, iova, pgsize, NULL);
335 WARN_ON(unmapped_page != pgsize);
338 unmapped_len += pgsize;
341 panfrost_mmu_flush_range(pfdev, mapping->mmu,
342 mapping->mmnode.start << PAGE_SHIFT, len);
343 mapping->active = false;
346 static void mmu_tlb_inv_context_s1(void *cookie)
349 static void mmu_tlb_sync_context(void *cookie)
351 //struct panfrost_mmu *mmu = cookie;
352 // TODO: Wait 1000 GPU cycles for HW_ISSUE_6367/T60X
355 static void mmu_tlb_flush_walk(unsigned long iova, size_t size, size_t granule,
358 mmu_tlb_sync_context(cookie);
361 static const struct iommu_flush_ops mmu_tlb_ops = {
362 .tlb_flush_all = mmu_tlb_inv_context_s1,
363 .tlb_flush_walk = mmu_tlb_flush_walk,
366 static struct panfrost_gem_mapping *
367 addr_to_mapping(struct panfrost_device *pfdev, int as, u64 addr)
369 struct panfrost_gem_mapping *mapping = NULL;
370 struct drm_mm_node *node;
371 u64 offset = addr >> PAGE_SHIFT;
372 struct panfrost_mmu *mmu;
374 spin_lock(&pfdev->as_lock);
375 list_for_each_entry(mmu, &pfdev->as_lru_list, list) {
383 spin_lock(&mmu->mm_lock);
385 drm_mm_for_each_node(node, &mmu->mm) {
386 if (offset >= node->start &&
387 offset < (node->start + node->size)) {
388 mapping = drm_mm_node_to_panfrost_mapping(node);
390 kref_get(&mapping->refcount);
395 spin_unlock(&mmu->mm_lock);
397 spin_unlock(&pfdev->as_lock);
401 #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE)
403 static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as,
407 struct panfrost_gem_mapping *bomapping;
408 struct panfrost_gem_object *bo;
409 struct address_space *mapping;
411 struct sg_table *sgt;
414 bomapping = addr_to_mapping(pfdev, as, addr);
420 dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)",
421 bomapping->mmnode.start << PAGE_SHIFT);
425 WARN_ON(bomapping->mmu->as != as);
427 /* Assume 2MB alignment and size multiple */
428 addr &= ~((u64)SZ_2M - 1);
429 page_offset = addr >> PAGE_SHIFT;
430 page_offset -= bomapping->mmnode.start;
432 mutex_lock(&bo->base.pages_lock);
434 if (!bo->base.pages) {
435 bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M,
436 sizeof(struct sg_table), GFP_KERNEL | __GFP_ZERO);
438 mutex_unlock(&bo->base.pages_lock);
443 pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT,
444 sizeof(struct page *), GFP_KERNEL | __GFP_ZERO);
448 mutex_unlock(&bo->base.pages_lock);
452 bo->base.pages = pages;
453 bo->base.pages_use_count = 1;
455 pages = bo->base.pages;
456 if (pages[page_offset]) {
457 /* Pages are already mapped, bail out. */
458 mutex_unlock(&bo->base.pages_lock);
463 mapping = bo->base.base.filp->f_mapping;
464 mapping_set_unevictable(mapping);
466 for (i = page_offset; i < page_offset + NUM_FAULT_PAGES; i++) {
467 pages[i] = shmem_read_mapping_page(mapping, i);
468 if (IS_ERR(pages[i])) {
469 mutex_unlock(&bo->base.pages_lock);
470 ret = PTR_ERR(pages[i]);
475 mutex_unlock(&bo->base.pages_lock);
477 sgt = &bo->sgts[page_offset / (SZ_2M / PAGE_SIZE)];
478 ret = sg_alloc_table_from_pages(sgt, pages + page_offset,
479 NUM_FAULT_PAGES, 0, SZ_2M, GFP_KERNEL);
483 ret = dma_map_sgtable(pfdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
487 mmu_map_sg(pfdev, bomapping->mmu, addr,
488 IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt);
490 bomapping->active = true;
492 dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr);
495 panfrost_gem_mapping_put(bomapping);
502 drm_gem_shmem_put_pages(&bo->base);
504 drm_gem_object_put(&bo->base.base);
508 static void panfrost_mmu_release_ctx(struct kref *kref)
510 struct panfrost_mmu *mmu = container_of(kref, struct panfrost_mmu,
512 struct panfrost_device *pfdev = mmu->pfdev;
514 spin_lock(&pfdev->as_lock);
516 pm_runtime_get_noresume(pfdev->dev);
517 if (pm_runtime_active(pfdev->dev))
518 panfrost_mmu_disable(pfdev, mmu->as);
519 pm_runtime_put_autosuspend(pfdev->dev);
521 clear_bit(mmu->as, &pfdev->as_alloc_mask);
522 clear_bit(mmu->as, &pfdev->as_in_use_mask);
523 list_del(&mmu->list);
525 spin_unlock(&pfdev->as_lock);
527 free_io_pgtable_ops(mmu->pgtbl_ops);
528 drm_mm_takedown(&mmu->mm);
532 void panfrost_mmu_ctx_put(struct panfrost_mmu *mmu)
534 kref_put(&mmu->refcount, panfrost_mmu_release_ctx);
537 struct panfrost_mmu *panfrost_mmu_ctx_get(struct panfrost_mmu *mmu)
539 kref_get(&mmu->refcount);
544 #define PFN_4G (SZ_4G >> PAGE_SHIFT)
545 #define PFN_4G_MASK (PFN_4G - 1)
546 #define PFN_16M (SZ_16M >> PAGE_SHIFT)
548 static void panfrost_drm_mm_color_adjust(const struct drm_mm_node *node,
550 u64 *start, u64 *end)
552 /* Executable buffers can't start or end on a 4GB boundary */
553 if (!(color & PANFROST_BO_NOEXEC)) {
556 if ((*start & PFN_4G_MASK) == 0)
559 if ((*end & PFN_4G_MASK) == 0)
562 next_seg = ALIGN(*start, PFN_4G);
563 if (next_seg - *start <= PFN_16M)
564 *start = next_seg + 1;
566 *end = min(*end, ALIGN(*start, PFN_4G) - 1);
570 struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev)
572 struct panfrost_mmu *mmu;
574 mmu = kzalloc(sizeof(*mmu), GFP_KERNEL);
576 return ERR_PTR(-ENOMEM);
579 spin_lock_init(&mmu->mm_lock);
581 /* 4G enough for now. can be 48-bit */
582 drm_mm_init(&mmu->mm, SZ_32M >> PAGE_SHIFT, (SZ_4G - SZ_32M) >> PAGE_SHIFT);
583 mmu->mm.color_adjust = panfrost_drm_mm_color_adjust;
585 INIT_LIST_HEAD(&mmu->list);
588 mmu->pgtbl_cfg = (struct io_pgtable_cfg) {
589 .pgsize_bitmap = SZ_4K | SZ_2M,
590 .ias = FIELD_GET(0xff, pfdev->features.mmu_features),
591 .oas = FIELD_GET(0xff00, pfdev->features.mmu_features),
592 .coherent_walk = pfdev->coherent,
594 .iommu_dev = pfdev->dev,
597 mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg,
599 if (!mmu->pgtbl_ops) {
601 return ERR_PTR(-EINVAL);
604 kref_init(&mmu->refcount);
609 static const char *access_type_name(struct panfrost_device *pfdev,
612 switch (fault_status & AS_FAULTSTATUS_ACCESS_TYPE_MASK) {
613 case AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC:
614 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU))
618 case AS_FAULTSTATUS_ACCESS_TYPE_READ:
620 case AS_FAULTSTATUS_ACCESS_TYPE_WRITE:
622 case AS_FAULTSTATUS_ACCESS_TYPE_EX:
630 static irqreturn_t panfrost_mmu_irq_handler(int irq, void *data)
632 struct panfrost_device *pfdev = data;
634 if (!mmu_read(pfdev, MMU_INT_STAT))
637 mmu_write(pfdev, MMU_INT_MASK, 0);
638 return IRQ_WAKE_THREAD;
641 static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data)
643 struct panfrost_device *pfdev = data;
644 u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT);
648 u32 as = ffs(status | (status >> 16)) - 1;
649 u32 mask = BIT(as) | BIT(as + 16);
656 fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as));
657 addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as));
658 addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32;
660 /* decode the fault status */
661 exception_type = fault_status & 0xFF;
662 access_type = (fault_status >> 8) & 0x3;
663 source_id = (fault_status >> 16);
665 mmu_write(pfdev, MMU_INT_CLEAR, mask);
667 /* Page fault only */
669 if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0)
670 ret = panfrost_mmu_map_fault_addr(pfdev, as, addr);
673 /* terminal fault, print info about the fault */
675 "Unhandled Page fault in AS%d at VA 0x%016llX\n"
677 "raw fault status: 0x%X\n"
678 "decoded fault status: %s\n"
679 "exception type 0x%X: %s\n"
680 "access type 0x%X: %s\n"
685 (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),
686 exception_type, panfrost_exception_name(exception_type),
687 access_type, access_type_name(pfdev, fault_status),
690 spin_lock(&pfdev->as_lock);
691 /* Ignore MMU interrupts on this AS until it's been
694 pfdev->as_faulty_mask |= mask;
696 /* Disable the MMU to kill jobs on this AS. */
697 panfrost_mmu_disable(pfdev, as);
698 spin_unlock(&pfdev->as_lock);
703 /* If we received new MMU interrupts, process them before returning. */
705 status = mmu_read(pfdev, MMU_INT_RAWSTAT) & ~pfdev->as_faulty_mask;
708 spin_lock(&pfdev->as_lock);
709 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask);
710 spin_unlock(&pfdev->as_lock);
715 int panfrost_mmu_init(struct panfrost_device *pfdev)
719 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu");
723 err = devm_request_threaded_irq(pfdev->dev, irq,
724 panfrost_mmu_irq_handler,
725 panfrost_mmu_irq_handler_thread,
726 IRQF_SHARED, KBUILD_MODNAME "-mmu",
730 dev_err(pfdev->dev, "failed to request mmu irq");
737 void panfrost_mmu_fini(struct panfrost_device *pfdev)
739 mmu_write(pfdev, MMU_INT_MASK, 0);