drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29 #include "handles.h"
  30
  31 #include <linux/dma-mapping.h>
  32 #include <linux/hdmi.h>
  33 #include <linux/component.h>
  34 #include <linux/iopoll.h>
  35
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fb_helper.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_scdc_helper.h>
  44 #include <drm/drm_vblank.h>
  45
  46 #include <nvif/push507c.h>
  47
  48 #include <nvif/class.h>
  49 #include <nvif/cl0002.h>
  50 #include <nvif/cl5070.h>
  51 #include <nvif/cl507d.h>
  52 #include <nvif/event.h>
  53 #include <nvif/timer.h>
  54
  55 #include <nvhw/class/cl507c.h>
  56 #include <nvhw/class/cl507d.h>
  57 #include <nvhw/class/cl837d.h>
  58 #include <nvhw/class/cl887d.h>
  59 #include <nvhw/class/cl907d.h>
  60 #include <nvhw/class/cl917d.h>
  61
  62 #include "nouveau_drv.h"
  63 #include "nouveau_dma.h"
  64 #include "nouveau_gem.h"
  65 #include "nouveau_connector.h"
  66 #include "nouveau_encoder.h"
  67 #include "nouveau_fence.h"
  68 #include "nouveau_fbcon.h"
  69
  70 #include <subdev/bios/dp.h>
  71
  72 /******************************************************************************
  73  * EVO channel
  74  *****************************************************************************/
  75
  76 static int
  77 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  78                  const s32 *oclass, u8 head, void *data, u32 size,
  79                  struct nv50_chan *chan)
  80 {
  81         struct nvif_sclass *sclass;
  82         int ret, i, n;
  83
  84         chan->device = device;
  85
  86         ret = n = nvif_object_sclass_get(disp, &sclass);
  87         if (ret < 0)
  88                 return ret;
  89
  90         while (oclass[0]) {
  91                 for (i = 0; i < n; i++) {
  92                         if (sclass[i].oclass == oclass[0]) {
  93                                 ret = nvif_object_ctor(disp, "kmsChan", 0,
  94                                                        oclass[0], data, size,
  95                                                        &chan->user);
  96                                 if (ret == 0)
  97                                         nvif_object_map(&chan->user, NULL, 0);
  98                                 nvif_object_sclass_put(&sclass);
  99                                 return ret;
 100                         }
 101                 }
 102                 oclass++;
 103         }
 104
 105         nvif_object_sclass_put(&sclass);
 106         return -ENOSYS;
 107 }
 108
 109 static void
 110 nv50_chan_destroy(struct nv50_chan *chan)
 111 {
 112         nvif_object_dtor(&chan->user);
 113 }
 114
 115 /******************************************************************************
 116  * DMA EVO channel
 117  *****************************************************************************/
 118
 119 void
 120 nv50_dmac_destroy(struct nv50_dmac *dmac)
 121 {
 122         nvif_object_dtor(&dmac->vram);
 123         nvif_object_dtor(&dmac->sync);
 124
 125         nv50_chan_destroy(&dmac->base);
 126
 127         nvif_mem_dtor(&dmac->_push.mem);
 128 }
 129
 130 static void
 131 nv50_dmac_kick(struct nvif_push *push)
 132 {
 133         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 134
 135         dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
 136         if (dmac->put != dmac->cur) {
 137                 /* Push buffer fetches are not coherent with BAR1, we need to ensure
 138                  * writes have been flushed right through to VRAM before writing PUT.
 139                  */
 140                 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
 141                         struct nvif_device *device = dmac->base.device;
 142                         nvif_wr32(&device->object, 0x070000, 0x00000001);
 143                         nvif_msec(device, 2000,
 144                                 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 145                                         break;
 146                         );
 147                 }
 148
 149                 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
 150                 dmac->put = dmac->cur;
 151         }
 152
 153         push->bgn = push->cur;
 154 }
 155
 156 static int
 157 nv50_dmac_free(struct nv50_dmac *dmac)
 158 {
 159         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 160         if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
 161                 return get - dmac->cur - 5;
 162         return dmac->max - dmac->cur;
 163 }
 164
 165 static int
 166 nv50_dmac_wind(struct nv50_dmac *dmac)
 167 {
 168         /* Wait for GET to depart from the beginning of the push buffer to
 169          * prevent writing PUT == GET, which would be ignored by HW.
 170          */
 171         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 172         if (get == 0) {
 173                 /* Corner-case, HW idle, but non-committed work pending. */
 174                 if (dmac->put == 0)
 175                         nv50_dmac_kick(dmac->push);
 176
 177                 if (nvif_msec(dmac->base.device, 2000,
 178                         if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
 179                                 break;
 180                 ) < 0)
 181                         return -ETIMEDOUT;
 182         }
 183
 184         PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
 185         dmac->cur = 0;
 186         return 0;
 187 }
 188
 189 static int
 190 nv50_dmac_wait(struct nvif_push *push, u32 size)
 191 {
 192         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 193         int free;
 194
 195         if (WARN_ON(size > dmac->max))
 196                 return -EINVAL;
 197
 198         dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
 199         if (dmac->cur + size >= dmac->max) {
 200                 int ret = nv50_dmac_wind(dmac);
 201                 if (ret)
 202                         return ret;
 203
 204                 push->cur = dmac->_push.mem.object.map.ptr;
 205                 push->cur = push->cur + dmac->cur;
 206                 nv50_dmac_kick(push);
 207         }
 208
 209         if (nvif_msec(dmac->base.device, 2000,
 210                 if ((free = nv50_dmac_free(dmac)) >= size)
 211                         break;
 212         ) < 0) {
 213                 WARN_ON(1);
 214                 return -ETIMEDOUT;
 215         }
 216
 217         push->bgn = dmac->_push.mem.object.map.ptr;
 218         push->bgn = push->bgn + dmac->cur;
 219         push->cur = push->bgn;
 220         push->end = push->cur + free;
 221         return 0;
 222 }
 223
 224 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)");
 225 static int nv50_dmac_vram_pushbuf = -1;
 226 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400);
 227
 228 int
 229 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 230                  const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
 231                  struct nv50_dmac *dmac)
 232 {
 233         struct nouveau_cli *cli = (void *)device->object.client;
 234         struct nv50_disp_core_channel_dma_v0 *args = data;
 235         u8 type = NVIF_MEM_COHERENT;
 236         int ret;
 237
 238         mutex_init(&dmac->lock);
 239
 240         /* Pascal added support for 47-bit physical addresses, but some
 241          * parts of EVO still only accept 40-bit PAs.
 242          *
 243          * To avoid issues on systems with large amounts of RAM, and on
 244          * systems where an IOMMU maps pages at a high address, we need
 245          * to allocate push buffers in VRAM instead.
 246          *
 247          * This appears to match NVIDIA's behaviour on Pascal.
 248          */
 249         if ((nv50_dmac_vram_pushbuf > 0) ||
 250             (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL))
 251                 type |= NVIF_MEM_VRAM;
 252
 253         ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
 254                                 &dmac->_push.mem);
 255         if (ret)
 256                 return ret;
 257
 258         dmac->ptr = dmac->_push.mem.object.map.ptr;
 259         dmac->_push.wait = nv50_dmac_wait;
 260         dmac->_push.kick = nv50_dmac_kick;
 261         dmac->push = &dmac->_push;
 262         dmac->push->bgn = dmac->_push.mem.object.map.ptr;
 263         dmac->push->cur = dmac->push->bgn;
 264         dmac->push->end = dmac->push->bgn;
 265         dmac->max = 0x1000/4 - 1;
 266
 267         /* EVO channels are affected by a HW bug where the last 12 DWORDs
 268          * of the push buffer aren't able to be used safely.
 269          */
 270         if (disp->oclass < GV100_DISP)
 271                 dmac->max -= 12;
 272
 273         args->pushbuf = nvif_handle(&dmac->_push.mem.object);
 274
 275         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 276                                &dmac->base);
 277         if (ret)
 278                 return ret;
 279
 280         if (syncbuf < 0)
 281                 return 0;
 282
 283         ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
 284                                NV_DMA_IN_MEMORY,
 285                                &(struct nv_dma_v0) {
 286                                         .target = NV_DMA_V0_TARGET_VRAM,
 287                                         .access = NV_DMA_V0_ACCESS_RDWR,
 288                                         .start = syncbuf + 0x0000,
 289                                         .limit = syncbuf + 0x0fff,
 290                                }, sizeof(struct nv_dma_v0),
 291                                &dmac->sync);
 292         if (ret)
 293                 return ret;
 294
 295         ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
 296                                NV_DMA_IN_MEMORY,
 297                                &(struct nv_dma_v0) {
 298                                         .target = NV_DMA_V0_TARGET_VRAM,
 299                                         .access = NV_DMA_V0_ACCESS_RDWR,
 300                                         .start = 0,
 301                                         .limit = device->info.ram_user - 1,
 302                                }, sizeof(struct nv_dma_v0),
 303                                &dmac->vram);
 304         if (ret)
 305                 return ret;
 306
 307         return ret;
 308 }
 309
 310 /******************************************************************************
 311  * Output path helpers
 312  *****************************************************************************/
 313 static void
 314 nv50_outp_dump_caps(struct nouveau_drm *drm,
 315                     struct nouveau_encoder *outp)
 316 {
 317         NV_DEBUG(drm, "%s caps: dp_interlace=%d\n",
 318                  outp->base.base.name, outp->caps.dp_interlace);
 319 }
 320
 321 static void
 322 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 323 {
 324         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 325         struct {
 326                 struct nv50_disp_mthd_v1 base;
 327         } args = {
 328                 .base.version = 1,
 329                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 330                 .base.hasht  = nv_encoder->dcb->hasht,
 331                 .base.hashm  = nv_encoder->dcb->hashm,
 332         };
 333
 334         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 335         nv_encoder->or = -1;
 336         nv_encoder->link = 0;
 337 }
 338
 339 static int
 340 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
 341 {
 342         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 343         struct nv50_disp *disp = nv50_disp(drm->dev);
 344         struct {
 345                 struct nv50_disp_mthd_v1 base;
 346                 struct nv50_disp_acquire_v0 info;
 347         } args = {
 348                 .base.version = 1,
 349                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 350                 .base.hasht  = nv_encoder->dcb->hasht,
 351                 .base.hashm  = nv_encoder->dcb->hashm,
 352                 .info.hda = hda,
 353         };
 354         int ret;
 355
 356         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 357         if (ret) {
 358                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 359                 return ret;
 360         }
 361
 362         nv_encoder->or = args.info.or;
 363         nv_encoder->link = args.info.link;
 364         return 0;
 365 }
 366
 367 static int
 368 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 369                             struct drm_crtc_state *crtc_state,
 370                             struct drm_connector_state *conn_state,
 371                             struct drm_display_mode *native_mode)
 372 {
 373         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 374         struct drm_display_mode *mode = &crtc_state->mode;
 375         struct drm_connector *connector = conn_state->connector;
 376         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 377         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 378
 379         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 380         asyc->scaler.full = false;
 381         if (!native_mode)
 382                 return 0;
 383
 384         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 385                 switch (connector->connector_type) {
 386                 case DRM_MODE_CONNECTOR_LVDS:
 387                 case DRM_MODE_CONNECTOR_eDP:
 388                         /* Don't force scaler for EDID modes with
 389                          * same size as the native one (e.g. different
 390                          * refresh rate)
 391                          */
 392                         if (mode->hdisplay == native_mode->hdisplay &&
 393                             mode->vdisplay == native_mode->vdisplay &&
 394                             mode->type & DRM_MODE_TYPE_DRIVER)
 395                                 break;
 396                         mode = native_mode;
 397                         asyc->scaler.full = true;
 398                         break;
 399                 default:
 400                         break;
 401                 }
 402         } else {
 403                 mode = native_mode;
 404         }
 405
 406         if (!drm_mode_equal(adjusted_mode, mode)) {
 407                 drm_mode_copy(adjusted_mode, mode);
 408                 crtc_state->mode_changed = true;
 409         }
 410
 411         return 0;
 412 }
 413
 414 static int
 415 nv50_outp_atomic_check(struct drm_encoder *encoder,
 416                        struct drm_crtc_state *crtc_state,
 417                        struct drm_connector_state *conn_state)
 418 {
 419         struct drm_connector *connector = conn_state->connector;
 420         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 421         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 422         int ret;
 423
 424         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 425                                           nv_connector->native_mode);
 426         if (ret)
 427                 return ret;
 428
 429         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 430                 asyh->or.bpc = connector->display_info.bpc;
 431
 432         return 0;
 433 }
 434
 435 struct nouveau_connector *
 436 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
 437 {
 438         struct drm_connector *connector;
 439         struct drm_connector_state *connector_state;
 440         struct drm_encoder *encoder = to_drm_encoder(outp);
 441         int i;
 442
 443         for_each_new_connector_in_state(state, connector, connector_state, i) {
 444                 if (connector_state->best_encoder == encoder)
 445                         return nouveau_connector(connector);
 446         }
 447
 448         return NULL;
 449 }
 450
 451 struct nouveau_connector *
 452 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
 453 {
 454         struct drm_connector *connector;
 455         struct drm_connector_state *connector_state;
 456         struct drm_encoder *encoder = to_drm_encoder(outp);
 457         int i;
 458
 459         for_each_old_connector_in_state(state, connector, connector_state, i) {
 460                 if (connector_state->best_encoder == encoder)
 461                         return nouveau_connector(connector);
 462         }
 463
 464         return NULL;
 465 }
 466
 467 static struct nouveau_crtc *
 468 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp)
 469 {
 470         struct drm_crtc *crtc;
 471         struct drm_crtc_state *crtc_state;
 472         const u32 mask = drm_encoder_mask(&outp->base.base);
 473         int i;
 474
 475         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 476                 if (crtc_state->encoder_mask & mask)
 477                         return nouveau_crtc(crtc);
 478         }
 479
 480         return NULL;
 481 }
 482
 483 /******************************************************************************
 484  * DAC
 485  *****************************************************************************/
 486 static void
 487 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
 488 {
 489         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 490         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 491         const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
 492
 493         core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL);
 494         nv_encoder->crtc = NULL;
 495         nv50_outp_release(nv_encoder);
 496 }
 497
 498 static void
 499 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
 500 {
 501         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 502         struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
 503         struct nv50_head_atom *asyh =
 504                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
 505         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 506         u32 ctrl = 0;
 507
 508         switch (nv_crtc->index) {
 509         case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
 510         case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
 511         case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
 512         case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
 513         default:
 514                 WARN_ON(1);
 515                 break;
 516         }
 517
 518         ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
 519
 520         nv50_outp_acquire(nv_encoder, false);
 521
 522         core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);
 523         asyh->or.depth = 0;
 524
 525         nv_encoder->crtc = &nv_crtc->base;
 526 }
 527
 528 static enum drm_connector_status
 529 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 530 {
 531         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 532         struct nv50_disp *disp = nv50_disp(encoder->dev);
 533         struct {
 534                 struct nv50_disp_mthd_v1 base;
 535                 struct nv50_disp_dac_load_v0 load;
 536         } args = {
 537                 .base.version = 1,
 538                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 539                 .base.hasht  = nv_encoder->dcb->hasht,
 540                 .base.hashm  = nv_encoder->dcb->hashm,
 541         };
 542         int ret;
 543
 544         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 545         if (args.load.data == 0)
 546                 args.load.data = 340;
 547
 548         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 549         if (ret || !args.load.load)
 550                 return connector_status_disconnected;
 551
 552         return connector_status_connected;
 553 }
 554
 555 static const struct drm_encoder_helper_funcs
 556 nv50_dac_help = {
 557         .atomic_check = nv50_outp_atomic_check,
 558         .atomic_enable = nv50_dac_atomic_enable,
 559         .atomic_disable = nv50_dac_atomic_disable,
 560         .detect = nv50_dac_detect
 561 };
 562
 563 static void
 564 nv50_dac_destroy(struct drm_encoder *encoder)
 565 {
 566         drm_encoder_cleanup(encoder);
 567         kfree(encoder);
 568 }
 569
 570 static const struct drm_encoder_funcs
 571 nv50_dac_func = {
 572         .destroy = nv50_dac_destroy,
 573 };
 574
 575 static int
 576 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 577 {
 578         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 579         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 580         struct nvkm_i2c_bus *bus;
 581         struct nouveau_encoder *nv_encoder;
 582         struct drm_encoder *encoder;
 583         int type = DRM_MODE_ENCODER_DAC;
 584
 585         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 586         if (!nv_encoder)
 587                 return -ENOMEM;
 588         nv_encoder->dcb = dcbe;
 589
 590         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 591         if (bus)
 592                 nv_encoder->i2c = &bus->i2c;
 593
 594         encoder = to_drm_encoder(nv_encoder);
 595         encoder->possible_crtcs = dcbe->heads;
 596         encoder->possible_clones = 0;
 597         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 598                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 599         drm_encoder_helper_add(encoder, &nv50_dac_help);
 600
 601         drm_connector_attach_encoder(connector, encoder);
 602         return 0;
 603 }
 604
 605 /*
 606  * audio component binding for ELD notification
 607  */
 608 static void
 609 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
 610                                 int dev_id)
 611 {
 612         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 613                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 614                                                  port, dev_id);
 615 }
 616
 617 static int
 618 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
 619                              bool *enabled, unsigned char *buf, int max_bytes)
 620 {
 621         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 622         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 623         struct drm_encoder *encoder;
 624         struct nouveau_encoder *nv_encoder;
 625         struct nouveau_crtc *nv_crtc;
 626         int ret = 0;
 627
 628         *enabled = false;
 629
 630         mutex_lock(&drm->audio.lock);
 631
 632         drm_for_each_encoder(encoder, drm->dev) {
 633                 struct nouveau_connector *nv_connector = NULL;
 634
 635                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
 636                         continue; /* TODO */
 637
 638                 nv_encoder = nouveau_encoder(encoder);
 639                 nv_connector = nouveau_connector(nv_encoder->audio.connector);
 640                 nv_crtc = nouveau_crtc(nv_encoder->crtc);
 641
 642                 if (!nv_crtc || nv_encoder->or != port || nv_crtc->index != dev_id)
 643                         continue;
 644
 645                 *enabled = nv_encoder->audio.enabled;
 646                 if (*enabled) {
 647                         ret = drm_eld_size(nv_connector->base.eld);
 648                         memcpy(buf, nv_connector->base.eld,
 649                                min(max_bytes, ret));
 650                 }
 651                 break;
 652         }
 653
 654         mutex_unlock(&drm->audio.lock);
 655
 656         return ret;
 657 }
 658
 659 static const struct drm_audio_component_ops nv50_audio_component_ops = {
 660         .get_eld = nv50_audio_component_get_eld,
 661 };
 662
 663 static int
 664 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
 665                           void *data)
 666 {
 667         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 668         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 669         struct drm_audio_component *acomp = data;
 670
 671         if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
 672                 return -ENOMEM;
 673
 674         drm_modeset_lock_all(drm_dev);
 675         acomp->ops = &nv50_audio_component_ops;
 676         acomp->dev = kdev;
 677         drm->audio.component = acomp;
 678         drm_modeset_unlock_all(drm_dev);
 679         return 0;
 680 }
 681
 682 static void
 683 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
 684                             void *data)
 685 {
 686         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 687         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 688         struct drm_audio_component *acomp = data;
 689
 690         drm_modeset_lock_all(drm_dev);
 691         drm->audio.component = NULL;
 692         acomp->ops = NULL;
 693         acomp->dev = NULL;
 694         drm_modeset_unlock_all(drm_dev);
 695 }
 696
 697 static const struct component_ops nv50_audio_component_bind_ops = {
 698         .bind   = nv50_audio_component_bind,
 699         .unbind = nv50_audio_component_unbind,
 700 };
 701
 702 static void
 703 nv50_audio_component_init(struct nouveau_drm *drm)
 704 {
 705         if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
 706                 return;
 707
 708         drm->audio.component_registered = true;
 709         mutex_init(&drm->audio.lock);
 710 }
 711
 712 static void
 713 nv50_audio_component_fini(struct nouveau_drm *drm)
 714 {
 715         if (!drm->audio.component_registered)
 716                 return;
 717
 718         component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
 719         drm->audio.component_registered = false;
 720         mutex_destroy(&drm->audio.lock);
 721 }
 722
 723 /******************************************************************************
 724  * Audio
 725  *****************************************************************************/
 726 static void
 727 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 728 {
 729         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 730         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 731         struct nv50_disp *disp = nv50_disp(encoder->dev);
 732         struct {
 733                 struct nv50_disp_mthd_v1 base;
 734                 struct nv50_disp_sor_hda_eld_v0 eld;
 735         } args = {
 736                 .base.version = 1,
 737                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 738                 .base.hasht   = nv_encoder->dcb->hasht,
 739                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 740                                 (0x0100 << nv_crtc->index),
 741         };
 742
 743         mutex_lock(&drm->audio.lock);
 744         if (nv_encoder->audio.enabled) {
 745                 nv_encoder->audio.enabled = false;
 746                 nv_encoder->audio.connector = NULL;
 747                 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 748         }
 749         mutex_unlock(&drm->audio.lock);
 750
 751         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 752                                         nv_crtc->index);
 753 }
 754
 755 static void
 756 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 757                   struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
 758                   struct drm_display_mode *mode)
 759 {
 760         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 761         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 762         struct nv50_disp *disp = nv50_disp(encoder->dev);
 763         struct __packed {
 764                 struct {
 765                         struct nv50_disp_mthd_v1 mthd;
 766                         struct nv50_disp_sor_hda_eld_v0 eld;
 767                 } base;
 768                 u8 data[sizeof(nv_connector->base.eld)];
 769         } args = {
 770                 .base.mthd.version = 1,
 771                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 772                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 773                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 774                                      (0x0100 << nv_crtc->index),
 775         };
 776
 777         if (!drm_detect_monitor_audio(nv_connector->edid))
 778                 return;
 779
 780         mutex_lock(&drm->audio.lock);
 781
 782         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 783
 784         nvif_mthd(&disp->disp->object, 0, &args,
 785                   sizeof(args.base) + drm_eld_size(args.data));
 786         nv_encoder->audio.enabled = true;
 787         nv_encoder->audio.connector = &nv_connector->base;
 788
 789         mutex_unlock(&drm->audio.lock);
 790
 791         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 792                                         nv_crtc->index);
 793 }
 794
 795 /******************************************************************************
 796  * HDMI
 797  *****************************************************************************/
 798 static void
 799 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 800 {
 801         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 802         struct nv50_disp *disp = nv50_disp(encoder->dev);
 803         struct {
 804                 struct nv50_disp_mthd_v1 base;
 805                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 806         } args = {
 807                 .base.version = 1,
 808                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 809                 .base.hasht  = nv_encoder->dcb->hasht,
 810                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 811                                (0x0100 << nv_crtc->index),
 812         };
 813
 814         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 815 }
 816
 817 static void
 818 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 819                  struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
 820                  struct drm_display_mode *mode)
 821 {
 822         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 823         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 824         struct nv50_disp *disp = nv50_disp(encoder->dev);
 825         struct {
 826                 struct nv50_disp_mthd_v1 base;
 827                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 828                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 829         } args = {
 830                 .base.version = 1,
 831                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 832                 .base.hasht  = nv_encoder->dcb->hasht,
 833                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 834                                (0x0100 << nv_crtc->index),
 835                 .pwr.state = 1,
 836                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 837         };
 838         struct drm_hdmi_info *hdmi;
 839         u32 max_ac_packet;
 840         union hdmi_infoframe avi_frame;
 841         union hdmi_infoframe vendor_frame;
 842         bool high_tmds_clock_ratio = false, scrambling = false;
 843         u8 config;
 844         int ret;
 845         int size;
 846
 847         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 848                 return;
 849
 850         hdmi = &nv_connector->base.display_info.hdmi;
 851
 852         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 853                                                        &nv_connector->base, mode);
 854         if (!ret) {
 855                 /* We have an AVI InfoFrame, populate it to the display */
 856                 args.pwr.avi_infoframe_length
 857                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 858         }
 859
 860         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 861                                                           &nv_connector->base, mode);
 862         if (!ret) {
 863                 /* We have a Vendor InfoFrame, populate it to the display */
 864                 args.pwr.vendor_infoframe_length
 865                         = hdmi_infoframe_pack(&vendor_frame,
 866                                               args.infoframes
 867                                               + args.pwr.avi_infoframe_length,
 868                                               17);
 869         }
 870
 871         max_ac_packet  = mode->htotal - mode->hdisplay;
 872         max_ac_packet -= args.pwr.rekey;
 873         max_ac_packet -= 18; /* constant from tegra */
 874         args.pwr.max_ac_packet = max_ac_packet / 32;
 875
 876         if (hdmi->scdc.scrambling.supported) {
 877                 high_tmds_clock_ratio = mode->clock > 340000;
 878                 scrambling = high_tmds_clock_ratio ||
 879                         hdmi->scdc.scrambling.low_rates;
 880         }
 881
 882         args.pwr.scdc =
 883                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 884                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 885
 886         size = sizeof(args.base)
 887                 + sizeof(args.pwr)
 888                 + args.pwr.avi_infoframe_length
 889                 + args.pwr.vendor_infoframe_length;
 890         nvif_mthd(&disp->disp->object, 0, &args, size);
 891
 892         nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
 893
 894         /* If SCDC is supported by the downstream monitor, update
 895          * divider / scrambling settings to what we programmed above.
 896          */
 897         if (!hdmi->scdc.scrambling.supported)
 898                 return;
 899
 900         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 901         if (ret < 0) {
 902                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 903                 return;
 904         }
 905         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 906         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 907         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 908         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 909         if (ret < 0)
 910                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 911                          config, ret);
 912 }
 913
 914 /******************************************************************************
 915  * MST
 916  *****************************************************************************/
 917 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 918 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 919 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 920
 921 struct nv50_mstc {
 922         struct nv50_mstm *mstm;
 923         struct drm_dp_mst_port *port;
 924         struct drm_connector connector;
 925
 926         struct drm_display_mode *native;
 927         struct edid *edid;
 928 };
 929
 930 struct nv50_msto {
 931         struct drm_encoder encoder;
 932
 933         /* head is statically assigned on msto creation */
 934         struct nv50_head *head;
 935         struct nv50_mstc *mstc;
 936         bool disabled;
 937 };
 938
 939 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
 940 {
 941         struct nv50_msto *msto;
 942
 943         if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
 944                 return nouveau_encoder(encoder);
 945
 946         msto = nv50_msto(encoder);
 947         if (!msto->mstc)
 948                 return NULL;
 949         return msto->mstc->mstm->outp;
 950 }
 951
 952 static struct drm_dp_payload *
 953 nv50_msto_payload(struct nv50_msto *msto)
 954 {
 955         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 956         struct nv50_mstc *mstc = msto->mstc;
 957         struct nv50_mstm *mstm = mstc->mstm;
 958         int vcpi = mstc->port->vcpi.vcpi, i;
 959
 960         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 961
 962         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 963         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 964                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 965                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 966                           mstm->outp->base.base.name, i, payload->vcpi,
 967                           payload->start_slot, payload->num_slots);
 968         }
 969
 970         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 971                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 972                 if (payload->vcpi == vcpi)
 973                         return payload;
 974         }
 975
 976         return NULL;
 977 }
 978
 979 static void
 980 nv50_msto_cleanup(struct nv50_msto *msto)
 981 {
 982         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 983         struct nv50_mstc *mstc = msto->mstc;
 984         struct nv50_mstm *mstm = mstc->mstm;
 985
 986         if (!msto->disabled)
 987                 return;
 988
 989         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 990
 991         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 992
 993         msto->mstc = NULL;
 994         msto->disabled = false;
 995 }
 996
 997 static void
 998 nv50_msto_prepare(struct nv50_msto *msto)
 999 {
1000         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
1001         struct nv50_mstc *mstc = msto->mstc;
1002         struct nv50_mstm *mstm = mstc->mstm;
1003         struct {
1004                 struct nv50_disp_mthd_v1 base;
1005                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
1006         } args = {
1007                 .base.version = 1,
1008                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
1009                 .base.hasht  = mstm->outp->dcb->hasht,
1010                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
1011                                (0x0100 << msto->head->base.index),
1012         };
1013
1014         mutex_lock(&mstm->mgr.payload_lock);
1015
1016         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
1017         if (mstc->port->vcpi.vcpi > 0) {
1018                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
1019                 if (payload) {
1020                         args.vcpi.start_slot = payload->start_slot;
1021                         args.vcpi.num_slots = payload->num_slots;
1022                         args.vcpi.pbn = mstc->port->vcpi.pbn;
1023                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
1024                 }
1025         }
1026
1027         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
1028                   msto->encoder.name, msto->head->base.base.name,
1029                   args.vcpi.start_slot, args.vcpi.num_slots,
1030                   args.vcpi.pbn, args.vcpi.aligned_pbn);
1031
1032         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
1033         mutex_unlock(&mstm->mgr.payload_lock);
1034 }
1035
1036 static int
1037 nv50_msto_atomic_check(struct drm_encoder *encoder,
1038                        struct drm_crtc_state *crtc_state,
1039                        struct drm_connector_state *conn_state)
1040 {
1041         struct drm_atomic_state *state = crtc_state->state;
1042         struct drm_connector *connector = conn_state->connector;
1043         struct nv50_mstc *mstc = nv50_mstc(connector);
1044         struct nv50_mstm *mstm = mstc->mstm;
1045         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
1046         int slots;
1047         int ret;
1048
1049         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
1050                                           mstc->native);
1051         if (ret)
1052                 return ret;
1053
1054         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
1055                 return 0;
1056
1057         /*
1058          * When restoring duplicated states, we need to make sure that the bw
1059          * remains the same and avoid recalculating it, as the connector's bpc
1060          * may have changed after the state was duplicated
1061          */
1062         if (!state->duplicated) {
1063                 const int clock = crtc_state->adjusted_mode.clock;
1064
1065                 asyh->or.bpc = connector->display_info.bpc;
1066                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
1067                                                     false);
1068         }
1069
1070         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
1071                                               asyh->dp.pbn, 0);
1072         if (slots < 0)
1073                 return slots;
1074
1075         asyh->dp.tu = slots;
1076
1077         return 0;
1078 }
1079
1080 static u8
1081 nv50_dp_bpc_to_depth(unsigned int bpc)
1082 {
1083         switch (bpc) {
1084         case  6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
1085         case  8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
1086         case 10:
1087         default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1088         }
1089 }
1090
1091 static void
1092 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1093 {
1094         struct nv50_msto *msto = nv50_msto(encoder);
1095         struct nv50_head *head = msto->head;
1096         struct nv50_head_atom *asyh =
1097                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base));
1098         struct nv50_mstc *mstc = NULL;
1099         struct nv50_mstm *mstm = NULL;
1100         struct drm_connector *connector;
1101         struct drm_connector_list_iter conn_iter;
1102         u8 proto;
1103         bool r;
1104
1105         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1106         drm_for_each_connector_iter(connector, &conn_iter) {
1107                 if (connector->state->best_encoder == &msto->encoder) {
1108                         mstc = nv50_mstc(connector);
1109                         mstm = mstc->mstm;
1110                         break;
1111                 }
1112         }
1113         drm_connector_list_iter_end(&conn_iter);
1114
1115         if (WARN_ON(!mstc))
1116                 return;
1117
1118         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, asyh->dp.pbn, asyh->dp.tu);
1119         if (!r)
1120                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
1121
1122         if (!mstm->links++)
1123                 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/);
1124
1125         if (mstm->outp->link & 1)
1126                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1127         else
1128                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1129
1130         mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1131                            nv50_dp_bpc_to_depth(asyh->or.bpc));
1132
1133         msto->mstc = mstc;
1134         mstm->modified = true;
1135 }
1136
1137 static void
1138 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1139 {
1140         struct nv50_msto *msto = nv50_msto(encoder);
1141         struct nv50_mstc *mstc = msto->mstc;
1142         struct nv50_mstm *mstm = mstc->mstm;
1143
1144         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
1145
1146         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1147         mstm->modified = true;
1148         if (!--mstm->links)
1149                 mstm->disabled = true;
1150         msto->disabled = true;
1151 }
1152
1153 static const struct drm_encoder_helper_funcs
1154 nv50_msto_help = {
1155         .atomic_disable = nv50_msto_atomic_disable,
1156         .atomic_enable = nv50_msto_atomic_enable,
1157         .atomic_check = nv50_msto_atomic_check,
1158 };
1159
1160 static void
1161 nv50_msto_destroy(struct drm_encoder *encoder)
1162 {
1163         struct nv50_msto *msto = nv50_msto(encoder);
1164         drm_encoder_cleanup(&msto->encoder);
1165         kfree(msto);
1166 }
1167
1168 static const struct drm_encoder_funcs
1169 nv50_msto = {
1170         .destroy = nv50_msto_destroy,
1171 };
1172
1173 static struct nv50_msto *
1174 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1175 {
1176         struct nv50_msto *msto;
1177         int ret;
1178
1179         msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1180         if (!msto)
1181                 return ERR_PTR(-ENOMEM);
1182
1183         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1184                                DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1185         if (ret) {
1186                 kfree(msto);
1187                 return ERR_PTR(ret);
1188         }
1189
1190         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1191         msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1192         msto->head = head;
1193         return msto;
1194 }
1195
1196 static struct drm_encoder *
1197 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1198                               struct drm_atomic_state *state)
1199 {
1200         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1201                                                                                          connector);
1202         struct nv50_mstc *mstc = nv50_mstc(connector);
1203         struct drm_crtc *crtc = connector_state->crtc;
1204
1205         if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1206                 return NULL;
1207
1208         return &nv50_head(crtc)->msto->encoder;
1209 }
1210
1211 static enum drm_mode_status
1212 nv50_mstc_mode_valid(struct drm_connector *connector,
1213                      struct drm_display_mode *mode)
1214 {
1215         struct nv50_mstc *mstc = nv50_mstc(connector);
1216         struct nouveau_encoder *outp = mstc->mstm->outp;
1217
1218         /* TODO: calculate the PBN from the dotclock and validate against the
1219          * MSTB's max possible PBN
1220          */
1221
1222         return nv50_dp_mode_valid(connector, outp, mode, NULL);
1223 }
1224
1225 static int
1226 nv50_mstc_get_modes(struct drm_connector *connector)
1227 {
1228         struct nv50_mstc *mstc = nv50_mstc(connector);
1229         int ret = 0;
1230
1231         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1232         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1233         if (mstc->edid)
1234                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1235
1236         /*
1237          * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1238          * to 8 to save bandwidth on the topology. In the future, we'll want
1239          * to properly fix this by dynamically selecting the highest possible
1240          * bpc that would fit in the topology
1241          */
1242         if (connector->display_info.bpc)
1243                 connector->display_info.bpc =
1244                         clamp(connector->display_info.bpc, 6U, 8U);
1245         else
1246                 connector->display_info.bpc = 8;
1247
1248         if (mstc->native)
1249                 drm_mode_destroy(mstc->connector.dev, mstc->native);
1250         mstc->native = nouveau_conn_native_mode(&mstc->connector);
1251         return ret;
1252 }
1253
1254 static int
1255 nv50_mstc_atomic_check(struct drm_connector *connector,
1256                        struct drm_atomic_state *state)
1257 {
1258         struct nv50_mstc *mstc = nv50_mstc(connector);
1259         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1260         struct drm_connector_state *new_conn_state =
1261                 drm_atomic_get_new_connector_state(state, connector);
1262         struct drm_connector_state *old_conn_state =
1263                 drm_atomic_get_old_connector_state(state, connector);
1264         struct drm_crtc_state *crtc_state;
1265         struct drm_crtc *new_crtc = new_conn_state->crtc;
1266
1267         if (!old_conn_state->crtc)
1268                 return 0;
1269
1270         /* We only want to free VCPI if this state disables the CRTC on this
1271          * connector
1272          */
1273         if (new_crtc) {
1274                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1275
1276                 if (!crtc_state ||
1277                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1278                     crtc_state->enable)
1279                         return 0;
1280         }
1281
1282         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1283 }
1284
1285 static int
1286 nv50_mstc_detect(struct drm_connector *connector,
1287                  struct drm_modeset_acquire_ctx *ctx, bool force)
1288 {
1289         struct nv50_mstc *mstc = nv50_mstc(connector);
1290         int ret;
1291
1292         if (drm_connector_is_unregistered(connector))
1293                 return connector_status_disconnected;
1294
1295         ret = pm_runtime_get_sync(connector->dev->dev);
1296         if (ret < 0 && ret != -EACCES) {
1297                 pm_runtime_put_autosuspend(connector->dev->dev);
1298                 return connector_status_disconnected;
1299         }
1300
1301         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1302                                      mstc->port);
1303         if (ret != connector_status_connected)
1304                 goto out;
1305
1306 out:
1307         pm_runtime_mark_last_busy(connector->dev->dev);
1308         pm_runtime_put_autosuspend(connector->dev->dev);
1309         return ret;
1310 }
1311
1312 static const struct drm_connector_helper_funcs
1313 nv50_mstc_help = {
1314         .get_modes = nv50_mstc_get_modes,
1315         .mode_valid = nv50_mstc_mode_valid,
1316         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1317         .atomic_check = nv50_mstc_atomic_check,
1318         .detect_ctx = nv50_mstc_detect,
1319 };
1320
1321 static void
1322 nv50_mstc_destroy(struct drm_connector *connector)
1323 {
1324         struct nv50_mstc *mstc = nv50_mstc(connector);
1325
1326         drm_connector_cleanup(&mstc->connector);
1327         drm_dp_mst_put_port_malloc(mstc->port);
1328
1329         kfree(mstc);
1330 }
1331
1332 static const struct drm_connector_funcs
1333 nv50_mstc = {
1334         .reset = nouveau_conn_reset,
1335         .fill_modes = drm_helper_probe_single_connector_modes,
1336         .destroy = nv50_mstc_destroy,
1337         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1338         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1339         .atomic_set_property = nouveau_conn_atomic_set_property,
1340         .atomic_get_property = nouveau_conn_atomic_get_property,
1341 };
1342
1343 static int
1344 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1345               const char *path, struct nv50_mstc **pmstc)
1346 {
1347         struct drm_device *dev = mstm->outp->base.base.dev;
1348         struct drm_crtc *crtc;
1349         struct nv50_mstc *mstc;
1350         int ret;
1351
1352         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1353                 return -ENOMEM;
1354         mstc->mstm = mstm;
1355         mstc->port = port;
1356
1357         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1358                                  DRM_MODE_CONNECTOR_DisplayPort);
1359         if (ret) {
1360                 kfree(*pmstc);
1361                 *pmstc = NULL;
1362                 return ret;
1363         }
1364
1365         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1366
1367         mstc->connector.funcs->reset(&mstc->connector);
1368         nouveau_conn_attach_properties(&mstc->connector);
1369
1370         drm_for_each_crtc(crtc, dev) {
1371                 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1372                         continue;
1373
1374                 drm_connector_attach_encoder(&mstc->connector,
1375                                              &nv50_head(crtc)->msto->encoder);
1376         }
1377
1378         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1379         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1380         drm_connector_set_path_property(&mstc->connector, path);
1381         drm_dp_mst_get_port_malloc(port);
1382         return 0;
1383 }
1384
1385 static void
1386 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1387 {
1388         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1389         struct drm_encoder *encoder;
1390         int ret;
1391
1392         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1393         ret = drm_dp_check_act_status(&mstm->mgr);
1394
1395         ret = drm_dp_update_payload_part2(&mstm->mgr);
1396
1397         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1398                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1399                         struct nv50_msto *msto = nv50_msto(encoder);
1400                         struct nv50_mstc *mstc = msto->mstc;
1401                         if (mstc && mstc->mstm == mstm)
1402                                 nv50_msto_cleanup(msto);
1403                 }
1404         }
1405
1406         mstm->modified = false;
1407 }
1408
1409 static void
1410 nv50_mstm_prepare(struct nv50_mstm *mstm)
1411 {
1412         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1413         struct drm_encoder *encoder;
1414         int ret;
1415
1416         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1417         ret = drm_dp_update_payload_part1(&mstm->mgr);
1418
1419         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1420                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1421                         struct nv50_msto *msto = nv50_msto(encoder);
1422                         struct nv50_mstc *mstc = msto->mstc;
1423                         if (mstc && mstc->mstm == mstm)
1424                                 nv50_msto_prepare(msto);
1425                 }
1426         }
1427
1428         if (mstm->disabled) {
1429                 if (!mstm->links)
1430                         nv50_outp_release(mstm->outp);
1431                 mstm->disabled = false;
1432         }
1433 }
1434
1435 static struct drm_connector *
1436 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1437                         struct drm_dp_mst_port *port, const char *path)
1438 {
1439         struct nv50_mstm *mstm = nv50_mstm(mgr);
1440         struct nv50_mstc *mstc;
1441         int ret;
1442
1443         ret = nv50_mstc_new(mstm, port, path, &mstc);
1444         if (ret)
1445                 return NULL;
1446
1447         return &mstc->connector;
1448 }
1449
1450 static const struct drm_dp_mst_topology_cbs
1451 nv50_mstm = {
1452         .add_connector = nv50_mstm_add_connector,
1453 };
1454
1455 bool
1456 nv50_mstm_service(struct nouveau_drm *drm,
1457                   struct nouveau_connector *nv_connector,
1458                   struct nv50_mstm *mstm)
1459 {
1460         struct drm_dp_aux *aux = &nv_connector->aux;
1461         bool handled = true, ret = true;
1462         int rc;
1463         u8 esi[8] = {};
1464
1465         while (handled) {
1466                 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1467                 if (rc != 8) {
1468                         ret = false;
1469                         break;
1470                 }
1471
1472                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1473                 if (!handled)
1474                         break;
1475
1476                 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1],
1477                                        3);
1478                 if (rc != 3) {
1479                         ret = false;
1480                         break;
1481                 }
1482         }
1483
1484         if (!ret)
1485                 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
1486                          nv_connector->base.name, rc);
1487
1488         return ret;
1489 }
1490
1491 void
1492 nv50_mstm_remove(struct nv50_mstm *mstm)
1493 {
1494         mstm->is_mst = false;
1495         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1496 }
1497
1498 static int
1499 nv50_mstm_enable(struct nv50_mstm *mstm, int state)
1500 {
1501         struct nouveau_encoder *outp = mstm->outp;
1502         struct {
1503                 struct nv50_disp_mthd_v1 base;
1504                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1505         } args = {
1506                 .base.version = 1,
1507                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1508                 .base.hasht = outp->dcb->hasht,
1509                 .base.hashm = outp->dcb->hashm,
1510                 .mst.state = state,
1511         };
1512         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1513         struct nvif_object *disp = &drm->display->disp.object;
1514
1515         return nvif_mthd(disp, 0, &args, sizeof(args));
1516 }
1517
1518 int
1519 nv50_mstm_detect(struct nouveau_encoder *outp)
1520 {
1521         struct nv50_mstm *mstm = outp->dp.mstm;
1522         struct drm_dp_aux *aux;
1523         int ret;
1524
1525         if (!mstm || !mstm->can_mst)
1526                 return 0;
1527
1528         aux = mstm->mgr.aux;
1529
1530         /* Clear any leftover MST state we didn't set ourselves by first
1531          * disabling MST if it was already enabled
1532          */
1533         ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1534         if (ret < 0)
1535                 return ret;
1536
1537         /* And start enabling */
1538         ret = nv50_mstm_enable(mstm, true);
1539         if (ret)
1540                 return ret;
1541
1542         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
1543         if (ret) {
1544                 nv50_mstm_enable(mstm, false);
1545                 return ret;
1546         }
1547
1548         mstm->is_mst = true;
1549         return 1;
1550 }
1551
1552 static void
1553 nv50_mstm_fini(struct nouveau_encoder *outp)
1554 {
1555         struct nv50_mstm *mstm = outp->dp.mstm;
1556
1557         if (!mstm)
1558                 return;
1559
1560         /* Don't change the MST state of this connector until we've finished
1561          * resuming, since we can't safely grab hpd_irq_lock in our resume
1562          * path to protect mstm->is_mst without potentially deadlocking
1563          */
1564         mutex_lock(&outp->dp.hpd_irq_lock);
1565         mstm->suspended = true;
1566         mutex_unlock(&outp->dp.hpd_irq_lock);
1567
1568         if (mstm->is_mst)
1569                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1570 }
1571
1572 static void
1573 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1574 {
1575         struct nv50_mstm *mstm = outp->dp.mstm;
1576         int ret = 0;
1577
1578         if (!mstm)
1579                 return;
1580
1581         if (mstm->is_mst) {
1582                 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1583                 if (ret == -1)
1584                         nv50_mstm_remove(mstm);
1585         }
1586
1587         mutex_lock(&outp->dp.hpd_irq_lock);
1588         mstm->suspended = false;
1589         mutex_unlock(&outp->dp.hpd_irq_lock);
1590
1591         if (ret == -1)
1592                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1593 }
1594
1595 static void
1596 nv50_mstm_del(struct nv50_mstm **pmstm)
1597 {
1598         struct nv50_mstm *mstm = *pmstm;
1599         if (mstm) {
1600                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1601                 kfree(*pmstm);
1602                 *pmstm = NULL;
1603         }
1604 }
1605
1606 static int
1607 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1608               int conn_base_id, struct nv50_mstm **pmstm)
1609 {
1610         const int max_payloads = hweight8(outp->dcb->heads);
1611         struct drm_device *dev = outp->base.base.dev;
1612         struct nv50_mstm *mstm;
1613         int ret;
1614
1615         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1616                 return -ENOMEM;
1617         mstm->outp = outp;
1618         mstm->mgr.cbs = &nv50_mstm;
1619
1620         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1621                                            max_payloads, outp->dcb->dpconf.link_nr,
1622                                            drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw),
1623                                            conn_base_id);
1624         if (ret)
1625                 return ret;
1626
1627         return 0;
1628 }
1629
1630 /******************************************************************************
1631  * SOR
1632  *****************************************************************************/
1633 static void
1634 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1635                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1636 {
1637         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1638         struct nv50_core *core = disp->core;
1639
1640         if (!asyh) {
1641                 nv_encoder->ctrl &= ~BIT(head);
1642                 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1643                         nv_encoder->ctrl = 0;
1644         } else {
1645                 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1646                 nv_encoder->ctrl |= BIT(head);
1647                 asyh->or.depth = depth;
1648         }
1649
1650         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1651 }
1652
1653 /* TODO: Should we extend this to PWM-only backlights?
1654  * As well, should we add a DRM helper for waiting for the backlight to acknowledge
1655  * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
1656  * fixed time delay from the vbios…
1657  */
1658 static void
1659 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1660 {
1661         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1662         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1663         struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
1664 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1665         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
1666         struct nouveau_backlight *backlight = nv_connector->backlight;
1667 #endif
1668         struct drm_dp_aux *aux = &nv_connector->aux;
1669         int ret;
1670         u8 pwr;
1671
1672 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1673         if (backlight && backlight->uses_dpcd) {
1674                 ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
1675                 if (ret < 0)
1676                         NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
1677                                  nv_connector->base.base.id, nv_connector->base.name, ret);
1678         }
1679 #endif
1680
1681         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1682                 ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
1683
1684                 if (ret == 0) {
1685                         pwr &= ~DP_SET_POWER_MASK;
1686                         pwr |=  DP_SET_POWER_D3;
1687                         drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1688                 }
1689         }
1690
1691         nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1692         nv50_audio_disable(encoder, nv_crtc);
1693         nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1694         nv50_outp_release(nv_encoder);
1695         nv_encoder->crtc = NULL;
1696 }
1697
1698 static void
1699 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1700 {
1701         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1702         struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1703         struct nv50_head_atom *asyh =
1704                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1705         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1706         struct {
1707                 struct nv50_disp_mthd_v1 base;
1708                 struct nv50_disp_sor_lvds_script_v0 lvds;
1709         } lvds = {
1710                 .base.version = 1,
1711                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1712                 .base.hasht   = nv_encoder->dcb->hasht,
1713                 .base.hashm   = nv_encoder->dcb->hashm,
1714         };
1715         struct nv50_disp *disp = nv50_disp(encoder->dev);
1716         struct drm_device *dev = encoder->dev;
1717         struct nouveau_drm *drm = nouveau_drm(dev);
1718         struct nouveau_connector *nv_connector;
1719 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1720         struct nouveau_backlight *backlight;
1721 #endif
1722         struct nvbios *bios = &drm->vbios;
1723         bool hda = false;
1724         u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1725         u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1726
1727         nv_connector = nv50_outp_get_new_connector(state, nv_encoder);
1728         nv_encoder->crtc = &nv_crtc->base;
1729
1730         if ((disp->disp->object.oclass == GT214_DISP ||
1731              disp->disp->object.oclass >= GF110_DISP) &&
1732             drm_detect_monitor_audio(nv_connector->edid))
1733                 hda = true;
1734         nv50_outp_acquire(nv_encoder, hda);
1735
1736         switch (nv_encoder->dcb->type) {
1737         case DCB_OUTPUT_TMDS:
1738                 if (nv_encoder->link & 1) {
1739                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1740                         /* Only enable dual-link if:
1741                          *  - Need to (i.e. rate > 165MHz)
1742                          *  - DCB says we can
1743                          *  - Not an HDMI monitor, since there's no dual-link
1744                          *    on HDMI.
1745                          */
1746                         if (mode->clock >= 165000 &&
1747                             nv_encoder->dcb->duallink_possible &&
1748                             !drm_detect_hdmi_monitor(nv_connector->edid))
1749                                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1750                 } else {
1751                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1752                 }
1753
1754                 nv50_hdmi_enable(&nv_encoder->base.base, nv_crtc, nv_connector, state, mode);
1755                 break;
1756         case DCB_OUTPUT_LVDS:
1757                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1758
1759                 if (bios->fp_no_ddc) {
1760                         if (bios->fp.dual_link)
1761                                 lvds.lvds.script |= 0x0100;
1762                         if (bios->fp.if_is_24bit)
1763                                 lvds.lvds.script |= 0x0200;
1764                 } else {
1765                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1766                                 if (((u8 *)nv_connector->edid)[121] == 2)
1767                                         lvds.lvds.script |= 0x0100;
1768                         } else
1769                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1770                                 lvds.lvds.script |= 0x0100;
1771                         }
1772
1773                         if (lvds.lvds.script & 0x0100) {
1774                                 if (bios->fp.strapless_is_24bit & 2)
1775                                         lvds.lvds.script |= 0x0200;
1776                         } else {
1777                                 if (bios->fp.strapless_is_24bit & 1)
1778                                         lvds.lvds.script |= 0x0200;
1779                         }
1780
1781                         if (asyh->or.bpc == 8)
1782                                 lvds.lvds.script |= 0x0200;
1783                 }
1784
1785                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1786                 break;
1787         case DCB_OUTPUT_DP:
1788                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1789
1790                 if (nv_encoder->link & 1)
1791                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1792                 else
1793                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1794
1795                 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
1796
1797 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1798                 backlight = nv_connector->backlight;
1799                 if (backlight && backlight->uses_dpcd)
1800                         drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
1801                                                  (u16)backlight->dev->props.brightness);
1802 #endif
1803
1804                 break;
1805         default:
1806                 BUG();
1807                 break;
1808         }
1809
1810         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1811 }
1812
1813 static const struct drm_encoder_helper_funcs
1814 nv50_sor_help = {
1815         .atomic_check = nv50_outp_atomic_check,
1816         .atomic_enable = nv50_sor_atomic_enable,
1817         .atomic_disable = nv50_sor_atomic_disable,
1818 };
1819
1820 static void
1821 nv50_sor_destroy(struct drm_encoder *encoder)
1822 {
1823         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1824         nv50_mstm_del(&nv_encoder->dp.mstm);
1825         drm_encoder_cleanup(encoder);
1826
1827         if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1828                 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1829
1830         kfree(encoder);
1831 }
1832
1833 static const struct drm_encoder_funcs
1834 nv50_sor_func = {
1835         .destroy = nv50_sor_destroy,
1836 };
1837
1838 static bool nv50_has_mst(struct nouveau_drm *drm)
1839 {
1840         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1841         u32 data;
1842         u8 ver, hdr, cnt, len;
1843
1844         data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1845         return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1846 }
1847
1848 static int
1849 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1850 {
1851         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1852         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1853         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1854         struct nouveau_encoder *nv_encoder;
1855         struct drm_encoder *encoder;
1856         struct nv50_disp *disp = nv50_disp(connector->dev);
1857         int type, ret;
1858
1859         switch (dcbe->type) {
1860         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1861         case DCB_OUTPUT_TMDS:
1862         case DCB_OUTPUT_DP:
1863         default:
1864                 type = DRM_MODE_ENCODER_TMDS;
1865                 break;
1866         }
1867
1868         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1869         if (!nv_encoder)
1870                 return -ENOMEM;
1871         nv_encoder->dcb = dcbe;
1872         nv_encoder->update = nv50_sor_update;
1873
1874         encoder = to_drm_encoder(nv_encoder);
1875         encoder->possible_crtcs = dcbe->heads;
1876         encoder->possible_clones = 0;
1877         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1878                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1879         drm_encoder_helper_add(encoder, &nv50_sor_help);
1880
1881         drm_connector_attach_encoder(connector, encoder);
1882
1883         disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1884         nv50_outp_dump_caps(drm, nv_encoder);
1885
1886         if (dcbe->type == DCB_OUTPUT_DP) {
1887                 struct nvkm_i2c_aux *aux =
1888                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1889
1890                 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1891
1892                 if (aux) {
1893                         if (disp->disp->object.oclass < GF110_DISP) {
1894                                 /* HW has no support for address-only
1895                                  * transactions, so we're required to
1896                                  * use custom I2C-over-AUX code.
1897                                  */
1898                                 nv_encoder->i2c = &aux->i2c;
1899                         } else {
1900                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1901                         }
1902                         nv_encoder->aux = aux;
1903                 }
1904
1905                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1906                     nv50_has_mst(drm)) {
1907                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1908                                             16, nv_connector->base.base.id,
1909                                             &nv_encoder->dp.mstm);
1910                         if (ret)
1911                                 return ret;
1912                 }
1913         } else {
1914                 struct nvkm_i2c_bus *bus =
1915                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1916                 if (bus)
1917                         nv_encoder->i2c = &bus->i2c;
1918         }
1919
1920         return 0;
1921 }
1922
1923 /******************************************************************************
1924  * PIOR
1925  *****************************************************************************/
1926 static int
1927 nv50_pior_atomic_check(struct drm_encoder *encoder,
1928                        struct drm_crtc_state *crtc_state,
1929                        struct drm_connector_state *conn_state)
1930 {
1931         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1932         if (ret)
1933                 return ret;
1934         crtc_state->adjusted_mode.clock *= 2;
1935         return 0;
1936 }
1937
1938 static void
1939 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1940 {
1941         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1942         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1943         const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1944
1945         core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL);
1946         nv_encoder->crtc = NULL;
1947         nv50_outp_release(nv_encoder);
1948 }
1949
1950 static void
1951 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1952 {
1953         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1954         struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1955         struct nv50_head_atom *asyh =
1956                 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1957         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1958         u32 ctrl = 0;
1959
1960         switch (nv_crtc->index) {
1961         case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1962         case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1963         default:
1964                 WARN_ON(1);
1965                 break;
1966         }
1967
1968         nv50_outp_acquire(nv_encoder, false);
1969
1970         switch (asyh->or.bpc) {
1971         case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1972         case  8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1973         case  6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1974         default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1975         }
1976
1977         switch (nv_encoder->dcb->type) {
1978         case DCB_OUTPUT_TMDS:
1979         case DCB_OUTPUT_DP:
1980                 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1981                 break;
1982         default:
1983                 BUG();
1984                 break;
1985         }
1986
1987         core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);
1988         nv_encoder->crtc = &nv_crtc->base;
1989 }
1990
1991 static const struct drm_encoder_helper_funcs
1992 nv50_pior_help = {
1993         .atomic_check = nv50_pior_atomic_check,
1994         .atomic_enable = nv50_pior_atomic_enable,
1995         .atomic_disable = nv50_pior_atomic_disable,
1996 };
1997
1998 static void
1999 nv50_pior_destroy(struct drm_encoder *encoder)
2000 {
2001         drm_encoder_cleanup(encoder);
2002         kfree(encoder);
2003 }
2004
2005 static const struct drm_encoder_funcs
2006 nv50_pior_func = {
2007         .destroy = nv50_pior_destroy,
2008 };
2009
2010 static int
2011 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2012 {
2013         struct drm_device *dev = connector->dev;
2014         struct nouveau_drm *drm = nouveau_drm(dev);
2015         struct nv50_disp *disp = nv50_disp(dev);
2016         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2017         struct nvkm_i2c_bus *bus = NULL;
2018         struct nvkm_i2c_aux *aux = NULL;
2019         struct i2c_adapter *ddc;
2020         struct nouveau_encoder *nv_encoder;
2021         struct drm_encoder *encoder;
2022         int type;
2023
2024         switch (dcbe->type) {
2025         case DCB_OUTPUT_TMDS:
2026                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
2027                 ddc  = bus ? &bus->i2c : NULL;
2028                 type = DRM_MODE_ENCODER_TMDS;
2029                 break;
2030         case DCB_OUTPUT_DP:
2031                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
2032                 ddc  = aux ? &aux->i2c : NULL;
2033                 type = DRM_MODE_ENCODER_TMDS;
2034                 break;
2035         default:
2036                 return -ENODEV;
2037         }
2038
2039         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2040         if (!nv_encoder)
2041                 return -ENOMEM;
2042         nv_encoder->dcb = dcbe;
2043         nv_encoder->i2c = ddc;
2044         nv_encoder->aux = aux;
2045
2046         encoder = to_drm_encoder(nv_encoder);
2047         encoder->possible_crtcs = dcbe->heads;
2048         encoder->possible_clones = 0;
2049         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
2050                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
2051         drm_encoder_helper_add(encoder, &nv50_pior_help);
2052
2053         drm_connector_attach_encoder(connector, encoder);
2054
2055         disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
2056         nv50_outp_dump_caps(drm, nv_encoder);
2057
2058         return 0;
2059 }
2060
2061 /******************************************************************************
2062  * Atomic
2063  *****************************************************************************/
2064
2065 static void
2066 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
2067 {
2068         struct nouveau_drm *drm = nouveau_drm(state->dev);
2069         struct nv50_disp *disp = nv50_disp(drm->dev);
2070         struct nv50_core *core = disp->core;
2071         struct nv50_mstm *mstm;
2072         struct drm_encoder *encoder;
2073
2074         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
2075
2076         drm_for_each_encoder(encoder, drm->dev) {
2077                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2078                         mstm = nouveau_encoder(encoder)->dp.mstm;
2079                         if (mstm && mstm->modified)
2080                                 nv50_mstm_prepare(mstm);
2081                 }
2082         }
2083
2084         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
2085         core->func->update(core, interlock, true);
2086         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
2087                                        disp->core->chan.base.device))
2088                 NV_ERROR(drm, "core notifier timeout\n");
2089
2090         drm_for_each_encoder(encoder, drm->dev) {
2091                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2092                         mstm = nouveau_encoder(encoder)->dp.mstm;
2093                         if (mstm && mstm->modified)
2094                                 nv50_mstm_cleanup(mstm);
2095                 }
2096         }
2097 }
2098
2099 static void
2100 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
2101 {
2102         struct drm_plane_state *new_plane_state;
2103         struct drm_plane *plane;
2104         int i;
2105
2106         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2107                 struct nv50_wndw *wndw = nv50_wndw(plane);
2108                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
2109                         if (wndw->func->update)
2110                                 wndw->func->update(wndw, interlock);
2111                 }
2112         }
2113 }
2114
2115 static void
2116 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
2117 {
2118         struct drm_device *dev = state->dev;
2119         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
2120         struct drm_crtc *crtc;
2121         struct drm_plane_state *new_plane_state;
2122         struct drm_plane *plane;
2123         struct nouveau_drm *drm = nouveau_drm(dev);
2124         struct nv50_disp *disp = nv50_disp(dev);
2125         struct nv50_atom *atom = nv50_atom(state);
2126         struct nv50_core *core = disp->core;
2127         struct nv50_outp_atom *outp, *outt;
2128         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2129         int i;
2130         bool flushed = false;
2131
2132         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2133         nv50_crc_atomic_stop_reporting(state);
2134         drm_atomic_helper_wait_for_fences(dev, state, false);
2135         drm_atomic_helper_wait_for_dependencies(state);
2136         drm_atomic_helper_update_legacy_modeset_state(dev, state);
2137         drm_atomic_helper_calc_timestamping_constants(state);
2138
2139         if (atom->lock_core)
2140                 mutex_lock(&disp->mutex);
2141
2142         /* Disable head(s). */
2143         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2144                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2145                 struct nv50_head *head = nv50_head(crtc);
2146
2147                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2148                           asyh->clr.mask, asyh->set.mask);
2149
2150                 if (old_crtc_state->active && !new_crtc_state->active) {
2151                         pm_runtime_put_noidle(dev->dev);
2152                         drm_crtc_vblank_off(crtc);
2153                 }
2154
2155                 if (asyh->clr.mask) {
2156                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
2157                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2158                 }
2159         }
2160
2161         /* Disable plane(s). */
2162         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2163                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2164                 struct nv50_wndw *wndw = nv50_wndw(plane);
2165
2166                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2167                           asyw->clr.mask, asyw->set.mask);
2168                 if (!asyw->clr.mask)
2169                         continue;
2170
2171                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2172         }
2173
2174         /* Disable output path(s). */
2175         list_for_each_entry(outp, &atom->outp, head) {
2176                 const struct drm_encoder_helper_funcs *help;
2177                 struct drm_encoder *encoder;
2178
2179                 encoder = outp->encoder;
2180                 help = encoder->helper_private;
2181
2182                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2183                           outp->clr.mask, outp->set.mask);
2184
2185                 if (outp->clr.mask) {
2186                         help->atomic_disable(encoder, state);
2187                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2188                         if (outp->flush_disable) {
2189                                 nv50_disp_atomic_commit_wndw(state, interlock);
2190                                 nv50_disp_atomic_commit_core(state, interlock);
2191                                 memset(interlock, 0x00, sizeof(interlock));
2192
2193                                 flushed = true;
2194                         }
2195                 }
2196         }
2197
2198         /* Flush disable. */
2199         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2200                 if (atom->flush_disable) {
2201                         nv50_disp_atomic_commit_wndw(state, interlock);
2202                         nv50_disp_atomic_commit_core(state, interlock);
2203                         memset(interlock, 0x00, sizeof(interlock));
2204
2205                         flushed = true;
2206                 }
2207         }
2208
2209         if (flushed)
2210                 nv50_crc_atomic_release_notifier_contexts(state);
2211         nv50_crc_atomic_init_notifier_contexts(state);
2212
2213         /* Update output path(s). */
2214         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2215                 const struct drm_encoder_helper_funcs *help;
2216                 struct drm_encoder *encoder;
2217
2218                 encoder = outp->encoder;
2219                 help = encoder->helper_private;
2220
2221                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2222                           outp->set.mask, outp->clr.mask);
2223
2224                 if (outp->set.mask) {
2225                         help->atomic_enable(encoder, state);
2226                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2227                 }
2228
2229                 list_del(&outp->head);
2230                 kfree(outp);
2231         }
2232
2233         /* Update head(s). */
2234         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2235                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2236                 struct nv50_head *head = nv50_head(crtc);
2237
2238                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2239                           asyh->set.mask, asyh->clr.mask);
2240
2241                 if (asyh->set.mask) {
2242                         nv50_head_flush_set(head, asyh);
2243                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2244                 }
2245
2246                 if (new_crtc_state->active) {
2247                         if (!old_crtc_state->active) {
2248                                 drm_crtc_vblank_on(crtc);
2249                                 pm_runtime_get_noresume(dev->dev);
2250                         }
2251                         if (new_crtc_state->event)
2252                                 drm_crtc_vblank_get(crtc);
2253                 }
2254         }
2255
2256         /* Update window->head assignment.
2257          *
2258          * This has to happen in an update that's not interlocked with
2259          * any window channels to avoid hitting HW error checks.
2260          *
2261          *TODO: Proper handling of window ownership (Turing apparently
2262          *      supports non-fixed mappings).
2263          */
2264         if (core->assign_windows) {
2265                 core->func->wndw.owner(core);
2266                 nv50_disp_atomic_commit_core(state, interlock);
2267                 core->assign_windows = false;
2268                 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2269         }
2270
2271         /* Finish updating head(s)...
2272          *
2273          * NVD is rather picky about both where window assignments can change,
2274          * *and* about certain core and window channel states matching.
2275          *
2276          * The EFI GOP driver on newer GPUs configures window channels with a
2277          * different output format to what we do, and the core channel update
2278          * in the assign_windows case above would result in a state mismatch.
2279          *
2280          * Delay some of the head update until after that point to workaround
2281          * the issue.  This only affects the initial modeset.
2282          *
2283          * TODO: handle this better when adding flexible window mapping
2284          */
2285         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2286                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2287                 struct nv50_head *head = nv50_head(crtc);
2288
2289                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2290                           asyh->set.mask, asyh->clr.mask);
2291
2292                 if (asyh->set.mask) {
2293                         nv50_head_flush_set_wndw(head, asyh);
2294                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2295                 }
2296         }
2297
2298         /* Update plane(s). */
2299         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2300                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2301                 struct nv50_wndw *wndw = nv50_wndw(plane);
2302
2303                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2304                           asyw->set.mask, asyw->clr.mask);
2305                 if ( !asyw->set.mask &&
2306                     (!asyw->clr.mask || atom->flush_disable))
2307                         continue;
2308
2309                 nv50_wndw_flush_set(wndw, interlock, asyw);
2310         }
2311
2312         /* Flush update. */
2313         nv50_disp_atomic_commit_wndw(state, interlock);
2314
2315         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2316                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2317                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
2318                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
2319                     !atom->state.legacy_cursor_update)
2320                         nv50_disp_atomic_commit_core(state, interlock);
2321                 else
2322                         disp->core->func->update(disp->core, interlock, false);
2323         }
2324
2325         if (atom->lock_core)
2326                 mutex_unlock(&disp->mutex);
2327
2328         /* Wait for HW to signal completion. */
2329         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2330                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2331                 struct nv50_wndw *wndw = nv50_wndw(plane);
2332                 int ret = nv50_wndw_wait_armed(wndw, asyw);
2333                 if (ret)
2334                         NV_ERROR(drm, "%s: timeout\n", plane->name);
2335         }
2336
2337         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2338                 if (new_crtc_state->event) {
2339                         unsigned long flags;
2340                         /* Get correct count/ts if racing with vblank irq */
2341                         if (new_crtc_state->active)
2342                                 drm_crtc_accurate_vblank_count(crtc);
2343                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
2344                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2345                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2346
2347                         new_crtc_state->event = NULL;
2348                         if (new_crtc_state->active)
2349                                 drm_crtc_vblank_put(crtc);
2350                 }
2351         }
2352
2353         nv50_crc_atomic_start_reporting(state);
2354         if (!flushed)
2355                 nv50_crc_atomic_release_notifier_contexts(state);
2356
2357         drm_atomic_helper_commit_hw_done(state);
2358         drm_atomic_helper_cleanup_planes(dev, state);
2359         drm_atomic_helper_commit_cleanup_done(state);
2360         drm_atomic_state_put(state);
2361
2362         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2363         pm_runtime_mark_last_busy(dev->dev);
2364         pm_runtime_put_autosuspend(dev->dev);
2365 }
2366
2367 static void
2368 nv50_disp_atomic_commit_work(struct work_struct *work)
2369 {
2370         struct drm_atomic_state *state =
2371                 container_of(work, typeof(*state), commit_work);
2372         nv50_disp_atomic_commit_tail(state);
2373 }
2374
2375 static int
2376 nv50_disp_atomic_commit(struct drm_device *dev,
2377                         struct drm_atomic_state *state, bool nonblock)
2378 {
2379         struct drm_plane_state *new_plane_state;
2380         struct drm_plane *plane;
2381         int ret, i;
2382
2383         ret = pm_runtime_get_sync(dev->dev);
2384         if (ret < 0 && ret != -EACCES) {
2385                 pm_runtime_put_autosuspend(dev->dev);
2386                 return ret;
2387         }
2388
2389         ret = drm_atomic_helper_setup_commit(state, nonblock);
2390         if (ret)
2391                 goto done;
2392
2393         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2394
2395         ret = drm_atomic_helper_prepare_planes(dev, state);
2396         if (ret)
2397                 goto done;
2398
2399         if (!nonblock) {
2400                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2401                 if (ret)
2402                         goto err_cleanup;
2403         }
2404
2405         ret = drm_atomic_helper_swap_state(state, true);
2406         if (ret)
2407                 goto err_cleanup;
2408
2409         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2410                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2411                 struct nv50_wndw *wndw = nv50_wndw(plane);
2412
2413                 if (asyw->set.image)
2414                         nv50_wndw_ntfy_enable(wndw, asyw);
2415         }
2416
2417         drm_atomic_state_get(state);
2418
2419         /*
2420          * Grab another RPM ref for the commit tail, which will release the
2421          * ref when it's finished
2422          */
2423         pm_runtime_get_noresume(dev->dev);
2424
2425         if (nonblock)
2426                 queue_work(system_unbound_wq, &state->commit_work);
2427         else
2428                 nv50_disp_atomic_commit_tail(state);
2429
2430 err_cleanup:
2431         if (ret)
2432                 drm_atomic_helper_cleanup_planes(dev, state);
2433 done:
2434         pm_runtime_put_autosuspend(dev->dev);
2435         return ret;
2436 }
2437
2438 static struct nv50_outp_atom *
2439 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2440 {
2441         struct nv50_outp_atom *outp;
2442
2443         list_for_each_entry(outp, &atom->outp, head) {
2444                 if (outp->encoder == encoder)
2445                         return outp;
2446         }
2447
2448         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2449         if (!outp)
2450                 return ERR_PTR(-ENOMEM);
2451
2452         list_add(&outp->head, &atom->outp);
2453         outp->encoder = encoder;
2454         return outp;
2455 }
2456
2457 static int
2458 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2459                                 struct drm_connector_state *old_connector_state)
2460 {
2461         struct drm_encoder *encoder = old_connector_state->best_encoder;
2462         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2463         struct drm_crtc *crtc;
2464         struct nv50_outp_atom *outp;
2465
2466         if (!(crtc = old_connector_state->crtc))
2467                 return 0;
2468
2469         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2470         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2471         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2472                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2473                 if (IS_ERR(outp))
2474                         return PTR_ERR(outp);
2475
2476                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2477                         outp->flush_disable = true;
2478                         atom->flush_disable = true;
2479                 }
2480                 outp->clr.ctrl = true;
2481                 atom->lock_core = true;
2482         }
2483
2484         return 0;
2485 }
2486
2487 static int
2488 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2489                                 struct drm_connector_state *connector_state)
2490 {
2491         struct drm_encoder *encoder = connector_state->best_encoder;
2492         struct drm_crtc_state *new_crtc_state;
2493         struct drm_crtc *crtc;
2494         struct nv50_outp_atom *outp;
2495
2496         if (!(crtc = connector_state->crtc))
2497                 return 0;
2498
2499         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2500         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2501                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2502                 if (IS_ERR(outp))
2503                         return PTR_ERR(outp);
2504
2505                 outp->set.ctrl = true;
2506                 atom->lock_core = true;
2507         }
2508
2509         return 0;
2510 }
2511
2512 static int
2513 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2514 {
2515         struct nv50_atom *atom = nv50_atom(state);
2516         struct nv50_core *core = nv50_disp(dev)->core;
2517         struct drm_connector_state *old_connector_state, *new_connector_state;
2518         struct drm_connector *connector;
2519         struct drm_crtc_state *new_crtc_state;
2520         struct drm_crtc *crtc;
2521         struct nv50_head *head;
2522         struct nv50_head_atom *asyh;
2523         int ret, i;
2524
2525         if (core->assign_windows && core->func->head->static_wndw_map) {
2526                 drm_for_each_crtc(crtc, dev) {
2527                         new_crtc_state = drm_atomic_get_crtc_state(state,
2528                                                                    crtc);
2529                         if (IS_ERR(new_crtc_state))
2530                                 return PTR_ERR(new_crtc_state);
2531
2532                         head = nv50_head(crtc);
2533                         asyh = nv50_head_atom(new_crtc_state);
2534                         core->func->head->static_wndw_map(head, asyh);
2535                 }
2536         }
2537
2538         /* We need to handle colour management on a per-plane basis. */
2539         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2540                 if (new_crtc_state->color_mgmt_changed) {
2541                         ret = drm_atomic_add_affected_planes(state, crtc);
2542                         if (ret)
2543                                 return ret;
2544                 }
2545         }
2546
2547         ret = drm_atomic_helper_check(dev, state);
2548         if (ret)
2549                 return ret;
2550
2551         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2552                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2553                 if (ret)
2554                         return ret;
2555
2556                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2557                 if (ret)
2558                         return ret;
2559         }
2560
2561         ret = drm_dp_mst_atomic_check(state);
2562         if (ret)
2563                 return ret;
2564
2565         nv50_crc_atomic_check_outp(atom);
2566
2567         return 0;
2568 }
2569
2570 static void
2571 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2572 {
2573         struct nv50_atom *atom = nv50_atom(state);
2574         struct nv50_outp_atom *outp, *outt;
2575
2576         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2577                 list_del(&outp->head);
2578                 kfree(outp);
2579         }
2580
2581         drm_atomic_state_default_clear(state);
2582 }
2583
2584 static void
2585 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2586 {
2587         struct nv50_atom *atom = nv50_atom(state);
2588         drm_atomic_state_default_release(&atom->state);
2589         kfree(atom);
2590 }
2591
2592 static struct drm_atomic_state *
2593 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2594 {
2595         struct nv50_atom *atom;
2596         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2597             drm_atomic_state_init(dev, &atom->state) < 0) {
2598                 kfree(atom);
2599                 return NULL;
2600         }
2601         INIT_LIST_HEAD(&atom->outp);
2602         return &atom->state;
2603 }
2604
2605 static const struct drm_mode_config_funcs
2606 nv50_disp_func = {
2607         .fb_create = nouveau_user_framebuffer_create,
2608         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2609         .atomic_check = nv50_disp_atomic_check,
2610         .atomic_commit = nv50_disp_atomic_commit,
2611         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2612         .atomic_state_clear = nv50_disp_atomic_state_clear,
2613         .atomic_state_free = nv50_disp_atomic_state_free,
2614 };
2615
2616 /******************************************************************************
2617  * Init
2618  *****************************************************************************/
2619
2620 static void
2621 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2622 {
2623         struct nouveau_drm *drm = nouveau_drm(dev);
2624         struct drm_encoder *encoder;
2625         struct drm_plane *plane;
2626
2627         drm_for_each_plane(plane, dev) {
2628                 struct nv50_wndw *wndw = nv50_wndw(plane);
2629                 if (plane->funcs != &nv50_wndw)
2630                         continue;
2631                 nv50_wndw_fini(wndw);
2632         }
2633
2634         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2635                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2636                         nv50_mstm_fini(nouveau_encoder(encoder));
2637         }
2638
2639         if (!runtime)
2640                 cancel_work_sync(&drm->hpd_work);
2641 }
2642
2643 static int
2644 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2645 {
2646         struct nv50_core *core = nv50_disp(dev)->core;
2647         struct drm_encoder *encoder;
2648         struct drm_plane *plane;
2649
2650         if (resume || runtime)
2651                 core->func->init(core);
2652
2653         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2654                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2655                         struct nouveau_encoder *nv_encoder =
2656                                 nouveau_encoder(encoder);
2657                         nv50_mstm_init(nv_encoder, runtime);
2658                 }
2659         }
2660
2661         drm_for_each_plane(plane, dev) {
2662                 struct nv50_wndw *wndw = nv50_wndw(plane);
2663                 if (plane->funcs != &nv50_wndw)
2664                         continue;
2665                 nv50_wndw_init(wndw);
2666         }
2667
2668         return 0;
2669 }
2670
2671 static void
2672 nv50_display_destroy(struct drm_device *dev)
2673 {
2674         struct nv50_disp *disp = nv50_disp(dev);
2675
2676         nv50_audio_component_fini(nouveau_drm(dev));
2677
2678         nvif_object_unmap(&disp->caps);
2679         nvif_object_dtor(&disp->caps);
2680         nv50_core_del(&disp->core);
2681
2682         nouveau_bo_unmap(disp->sync);
2683         if (disp->sync)
2684                 nouveau_bo_unpin(disp->sync);
2685         nouveau_bo_ref(NULL, &disp->sync);
2686
2687         nouveau_display(dev)->priv = NULL;
2688         kfree(disp);
2689 }
2690
2691 int
2692 nv50_display_create(struct drm_device *dev)
2693 {
2694         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2695         struct nouveau_drm *drm = nouveau_drm(dev);
2696         struct dcb_table *dcb = &drm->vbios.dcb;
2697         struct drm_connector *connector, *tmp;
2698         struct nv50_disp *disp;
2699         struct dcb_output *dcbe;
2700         int crtcs, ret, i;
2701         bool has_mst = nv50_has_mst(drm);
2702
2703         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2704         if (!disp)
2705                 return -ENOMEM;
2706
2707         mutex_init(&disp->mutex);
2708
2709         nouveau_display(dev)->priv = disp;
2710         nouveau_display(dev)->dtor = nv50_display_destroy;
2711         nouveau_display(dev)->init = nv50_display_init;
2712         nouveau_display(dev)->fini = nv50_display_fini;
2713         disp->disp = &nouveau_display(dev)->disp;
2714         dev->mode_config.funcs = &nv50_disp_func;
2715         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2716         dev->mode_config.normalize_zpos = true;
2717
2718         /* small shared memory area we use for notifiers and semaphores */
2719         ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
2720                              NOUVEAU_GEM_DOMAIN_VRAM,
2721                              0, 0x0000, NULL, NULL, &disp->sync);
2722         if (!ret) {
2723                 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2724                 if (!ret) {
2725                         ret = nouveau_bo_map(disp->sync);
2726                         if (ret)
2727                                 nouveau_bo_unpin(disp->sync);
2728                 }
2729                 if (ret)
2730                         nouveau_bo_ref(NULL, &disp->sync);
2731         }
2732
2733         if (ret)
2734                 goto out;
2735
2736         /* allocate master evo channel */
2737         ret = nv50_core_new(drm, &disp->core);
2738         if (ret)
2739                 goto out;
2740
2741         disp->core->func->init(disp->core);
2742         if (disp->core->func->caps_init) {
2743                 ret = disp->core->func->caps_init(drm, disp);
2744                 if (ret)
2745                         goto out;
2746         }
2747
2748         /* Assign the correct format modifiers */
2749         if (disp->disp->object.oclass >= TU102_DISP)
2750                 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2751         else
2752         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2753                 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2754         else
2755                 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2756
2757         /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later
2758          * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The
2759          * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to
2760          * small page allocations in prepare_fb(). When this is implemented, we should also force
2761          * large pages (128K) for ovly fbs in order to fix Kepler ovlys.
2762          * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using
2763          * large pages.
2764          */
2765         if (disp->disp->object.oclass >= GM107_DISP) {
2766                 dev->mode_config.cursor_width = 256;
2767                 dev->mode_config.cursor_height = 256;
2768         } else if (disp->disp->object.oclass >= GK104_DISP) {
2769                 dev->mode_config.cursor_width = 128;
2770                 dev->mode_config.cursor_height = 128;
2771         } else {
2772                 dev->mode_config.cursor_width = 64;
2773                 dev->mode_config.cursor_height = 64;
2774         }
2775
2776         /* create crtc objects to represent the hw heads */
2777         if (disp->disp->object.oclass >= GV100_DISP)
2778                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2779         else
2780         if (disp->disp->object.oclass >= GF110_DISP)
2781                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2782         else
2783                 crtcs = 0x3;
2784
2785         for (i = 0; i < fls(crtcs); i++) {
2786                 struct nv50_head *head;
2787
2788                 if (!(crtcs & (1 << i)))
2789                         continue;
2790
2791                 head = nv50_head_create(dev, i);
2792                 if (IS_ERR(head)) {
2793                         ret = PTR_ERR(head);
2794                         goto out;
2795                 }
2796
2797                 if (has_mst) {
2798                         head->msto = nv50_msto_new(dev, head, i);
2799                         if (IS_ERR(head->msto)) {
2800                                 ret = PTR_ERR(head->msto);
2801                                 head->msto = NULL;
2802                                 goto out;
2803                         }
2804
2805                         /*
2806                          * FIXME: This is a hack to workaround the following
2807                          * issues:
2808                          *
2809                          * https://gitlab.gnome.org/GNOME/mutter/issues/759
2810                          * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2811                          *
2812                          * Once these issues are closed, this should be
2813                          * removed
2814                          */
2815                         head->msto->encoder.possible_crtcs = crtcs;
2816                 }
2817         }
2818
2819         /* create encoder/connector objects based on VBIOS DCB table */
2820         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2821                 connector = nouveau_connector_create(dev, dcbe);
2822                 if (IS_ERR(connector))
2823                         continue;
2824
2825                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2826                         switch (dcbe->type) {
2827                         case DCB_OUTPUT_TMDS:
2828                         case DCB_OUTPUT_LVDS:
2829                         case DCB_OUTPUT_DP:
2830                                 ret = nv50_sor_create(connector, dcbe);
2831                                 break;
2832                         case DCB_OUTPUT_ANALOG:
2833                                 ret = nv50_dac_create(connector, dcbe);
2834                                 break;
2835                         default:
2836                                 ret = -ENODEV;
2837                                 break;
2838                         }
2839                 } else {
2840                         ret = nv50_pior_create(connector, dcbe);
2841                 }
2842
2843                 if (ret) {
2844                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2845                                      dcbe->location, dcbe->type,
2846                                      ffs(dcbe->or) - 1, ret);
2847                         ret = 0;
2848                 }
2849         }
2850
2851         /* cull any connectors we created that don't have an encoder */
2852         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2853                 if (connector->possible_encoders)
2854                         continue;
2855
2856                 NV_WARN(drm, "%s has no encoders, removing\n",
2857                         connector->name);
2858                 connector->funcs->destroy(connector);
2859         }
2860
2861         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2862         dev->vblank_disable_immediate = true;
2863
2864         nv50_audio_component_init(drm);
2865
2866 out:
2867         if (ret)
2868                 nv50_display_destroy(dev);
2869         return ret;
2870 }
2871
2872 /******************************************************************************
2873  * Format modifiers
2874  *****************************************************************************/
2875
2876 /****************************************************************
2877  *            Log2(block height) ----------------------------+  *
2878  *            Page Kind ----------------------------------+  |  *
2879  *            Gob Height/Page Kind Generation ------+     |  |  *
2880  *                          Sector layout -------+  |     |  |  *
2881  *                          Compression ------+  |  |     |  |  */
2882 const u64 disp50xx_modifiers[] = { /*         |  |  |     |  |  */
2883         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2884         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2885         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2886         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2887         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2888         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2889         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2890         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2891         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2892         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2893         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2894         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2895         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2896         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2897         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2898         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2899         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2900         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2901         DRM_FORMAT_MOD_LINEAR,
2902         DRM_FORMAT_MOD_INVALID
2903 };
2904
2905 /****************************************************************
2906  *            Log2(block height) ----------------------------+  *
2907  *            Page Kind ----------------------------------+  |  *
2908  *            Gob Height/Page Kind Generation ------+     |  |  *
2909  *                          Sector layout -------+  |     |  |  *
2910  *                          Compression ------+  |  |     |  |  */
2911 const u64 disp90xx_modifiers[] = { /*         |  |  |     |  |  */
2912         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2913         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2914         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2915         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2916         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2917         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2918         DRM_FORMAT_MOD_LINEAR,
2919         DRM_FORMAT_MOD_INVALID
2920 };