1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/kthread.h>
10 #include <linux/sched/mm.h>
11 #include <linux/uaccess.h>
12 #include <uapi/linux/sched/types.h>
14 #include <drm/drm_drv.h>
15 #include <drm/drm_file.h>
16 #include <drm/drm_ioctl.h>
17 #include <drm/drm_prime.h>
18 #include <drm/drm_of.h>
19 #include <drm/drm_vblank.h>
21 #include "disp/msm_disp_snapshot.h"
23 #include "msm_debugfs.h"
24 #include "msm_fence.h"
28 #include "adreno/adreno_gpu.h"
32 * - 1.0.0 - initial interface
33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
34 * - 1.2.0 - adds explicit fence support for submit ioctl
35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
38 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
39 * GEM object's debug name
40 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
41 * - 1.6.0 - Syncobj support
42 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
43 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
45 #define MSM_VERSION_MAJOR 1
46 #define MSM_VERSION_MINOR 8
47 #define MSM_VERSION_PATCHLEVEL 0
49 static const struct drm_mode_config_funcs mode_config_funcs = {
50 .fb_create = msm_framebuffer_create,
51 .output_poll_changed = drm_fb_helper_output_poll_changed,
52 .atomic_check = drm_atomic_helper_check,
53 .atomic_commit = drm_atomic_helper_commit,
56 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
57 .atomic_commit_tail = msm_atomic_commit_tail,
60 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
61 static bool reglog = false;
62 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
63 module_param(reglog, bool, 0600);
68 #ifdef CONFIG_DRM_FBDEV_EMULATION
69 static bool fbdev = true;
70 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
71 module_param(fbdev, bool, 0600);
74 static char *vram = "16m";
75 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
76 module_param(vram, charp, 0);
78 bool dumpstate = false;
79 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
80 module_param(dumpstate, bool, 0600);
82 static bool modeset = true;
83 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
84 module_param(modeset, bool, 0600);
90 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
96 snprintf(n, sizeof(n), "%s_clk", name);
98 for (i = 0; bulk && i < count; i++) {
99 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
107 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
112 clk = devm_clk_get(&pdev->dev, name);
113 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
116 snprintf(name2, sizeof(name2), "%s_clk", name);
118 clk = devm_clk_get(&pdev->dev, name2);
120 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
121 "\"%s\" instead of \"%s\"\n", name, name2);
126 static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
127 const char *dbgname, bool quiet, phys_addr_t *psize)
129 struct resource *res;
134 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
136 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
140 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
141 return ERR_PTR(-EINVAL);
144 size = resource_size(res);
146 ptr = devm_ioremap(&pdev->dev, res->start, size);
149 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
150 return ERR_PTR(-ENOMEM);
154 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
162 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
165 return _msm_ioremap(pdev, name, dbgname, false, NULL);
168 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
171 return _msm_ioremap(pdev, name, dbgname, true, NULL);
174 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
175 const char *dbgname, phys_addr_t *psize)
177 return _msm_ioremap(pdev, name, dbgname, false, psize);
180 void msm_writel(u32 data, void __iomem *addr)
183 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
187 u32 msm_readl(const void __iomem *addr)
189 u32 val = readl(addr);
191 pr_err("IO:R %p %08x\n", addr, val);
195 void msm_rmw(void __iomem *addr, u32 mask, u32 or)
197 u32 val = msm_readl(addr);
200 msm_writel(val | or, addr);
203 static irqreturn_t msm_irq(int irq, void *arg)
205 struct drm_device *dev = arg;
206 struct msm_drm_private *priv = dev->dev_private;
207 struct msm_kms *kms = priv->kms;
211 return kms->funcs->irq(kms);
214 static void msm_irq_preinstall(struct drm_device *dev)
216 struct msm_drm_private *priv = dev->dev_private;
217 struct msm_kms *kms = priv->kms;
221 kms->funcs->irq_preinstall(kms);
224 static int msm_irq_postinstall(struct drm_device *dev)
226 struct msm_drm_private *priv = dev->dev_private;
227 struct msm_kms *kms = priv->kms;
231 if (kms->funcs->irq_postinstall)
232 return kms->funcs->irq_postinstall(kms);
237 static int msm_irq_install(struct drm_device *dev, unsigned int irq)
241 if (irq == IRQ_NOTCONNECTED)
244 msm_irq_preinstall(dev);
246 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
250 ret = msm_irq_postinstall(dev);
259 static void msm_irq_uninstall(struct drm_device *dev)
261 struct msm_drm_private *priv = dev->dev_private;
262 struct msm_kms *kms = priv->kms;
264 kms->funcs->irq_uninstall(kms);
265 free_irq(kms->irq, dev);
268 struct msm_vblank_work {
269 struct work_struct work;
272 struct msm_drm_private *priv;
275 static void vblank_ctrl_worker(struct work_struct *work)
277 struct msm_vblank_work *vbl_work = container_of(work,
278 struct msm_vblank_work, work);
279 struct msm_drm_private *priv = vbl_work->priv;
280 struct msm_kms *kms = priv->kms;
282 if (vbl_work->enable)
283 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
285 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
290 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
291 int crtc_id, bool enable)
293 struct msm_vblank_work *vbl_work;
295 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
299 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
301 vbl_work->crtc_id = crtc_id;
302 vbl_work->enable = enable;
303 vbl_work->priv = priv;
305 queue_work(priv->wq, &vbl_work->work);
310 static int msm_drm_uninit(struct device *dev)
312 struct platform_device *pdev = to_platform_device(dev);
313 struct drm_device *ddev = platform_get_drvdata(pdev);
314 struct msm_drm_private *priv = ddev->dev_private;
315 struct msm_kms *kms = priv->kms;
316 struct msm_mdss *mdss = priv->mdss;
320 * Shutdown the hw if we're far enough along where things might be on.
321 * If we run this too early, we'll end up panicking in any variety of
322 * places. Since we don't register the drm device until late in
323 * msm_drm_init, drm_dev->registered is used as an indicator that the
324 * shutdown will be successful.
326 if (ddev->registered) {
327 drm_dev_unregister(ddev);
328 drm_atomic_helper_shutdown(ddev);
331 /* We must cancel and cleanup any pending vblank enable/disable
332 * work before msm_irq_uninstall() to avoid work re-enabling an
333 * irq after uninstall has disabled it.
336 flush_workqueue(priv->wq);
338 /* clean up event worker threads */
339 for (i = 0; i < priv->num_crtcs; i++) {
340 if (priv->event_thread[i].worker)
341 kthread_destroy_worker(priv->event_thread[i].worker);
344 msm_gem_shrinker_cleanup(ddev);
346 drm_kms_helper_poll_fini(ddev);
348 msm_perf_debugfs_cleanup(priv);
349 msm_rd_debugfs_cleanup(priv);
351 #ifdef CONFIG_DRM_FBDEV_EMULATION
352 if (fbdev && priv->fbdev)
353 msm_fbdev_free(ddev);
356 msm_disp_snapshot_destroy(ddev);
358 drm_mode_config_cleanup(ddev);
360 pm_runtime_get_sync(dev);
361 msm_irq_uninstall(ddev);
362 pm_runtime_put_sync(dev);
364 if (kms && kms->funcs)
365 kms->funcs->destroy(kms);
367 if (priv->vram.paddr) {
368 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
369 drm_mm_takedown(&priv->vram.mm);
370 dma_free_attrs(dev, priv->vram.size, NULL,
371 priv->vram.paddr, attrs);
374 component_unbind_all(dev, ddev);
376 if (mdss && mdss->funcs)
377 mdss->funcs->destroy(ddev);
379 ddev->dev_private = NULL;
382 destroy_workqueue(priv->wq);
392 static int get_mdp_ver(struct platform_device *pdev)
394 struct device *dev = &pdev->dev;
396 return (int) (unsigned long) of_device_get_match_data(dev);
399 #include <linux/of_address.h>
401 bool msm_use_mmu(struct drm_device *dev)
403 struct msm_drm_private *priv = dev->dev_private;
405 /* a2xx comes with its own MMU */
406 return priv->is_a2xx || iommu_present(&platform_bus_type);
409 static int msm_init_vram(struct drm_device *dev)
411 struct msm_drm_private *priv = dev->dev_private;
412 struct device_node *node;
413 unsigned long size = 0;
416 /* In the device-tree world, we could have a 'memory-region'
417 * phandle, which gives us a link to our "vram". Allocating
418 * is all nicely abstracted behind the dma api, but we need
419 * to know the entire size to allocate it all in one go. There
421 * 1) device with no IOMMU, in which case we need exclusive
422 * access to a VRAM carveout big enough for all gpu
424 * 2) device with IOMMU, but where the bootloader puts up
425 * a splash screen. In this case, the VRAM carveout
426 * need only be large enough for fbdev fb. But we need
427 * exclusive access to the buffer to avoid the kernel
428 * using those pages for other purposes (which appears
429 * as corruption on screen before we have a chance to
430 * load and do initial modeset)
433 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
436 ret = of_address_to_resource(node, 0, &r);
440 size = r.end - r.start;
441 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
443 /* if we have no IOMMU, then we need to use carveout allocator.
444 * Grab the entire CMA chunk carved out in early startup in
447 } else if (!msm_use_mmu(dev)) {
448 DRM_INFO("using %s VRAM carveout\n", vram);
449 size = memparse(vram, NULL);
453 unsigned long attrs = 0;
456 priv->vram.size = size;
458 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
459 spin_lock_init(&priv->vram.lock);
461 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
462 attrs |= DMA_ATTR_WRITE_COMBINE;
464 /* note that for no-kernel-mapping, the vaddr returned
465 * is bogus, but non-null if allocation succeeded:
467 p = dma_alloc_attrs(dev->dev, size,
468 &priv->vram.paddr, GFP_KERNEL, attrs);
470 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
471 priv->vram.paddr = 0;
475 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
476 (uint32_t)priv->vram.paddr,
477 (uint32_t)(priv->vram.paddr + size));
483 static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
485 struct platform_device *pdev = to_platform_device(dev);
486 struct drm_device *ddev;
487 struct msm_drm_private *priv;
489 struct msm_mdss *mdss;
492 ddev = drm_dev_alloc(drv, dev);
494 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
495 return PTR_ERR(ddev);
498 platform_set_drvdata(pdev, ddev);
500 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
503 goto err_put_drm_dev;
506 ddev->dev_private = priv;
509 switch (get_mdp_ver(pdev)) {
511 ret = mdp5_mdss_init(ddev);
514 ret = dpu_mdss_init(ddev);
525 priv->wq = alloc_ordered_workqueue("msm", 0);
526 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
528 INIT_LIST_HEAD(&priv->objects);
529 mutex_init(&priv->obj_lock);
531 INIT_LIST_HEAD(&priv->inactive_willneed);
532 INIT_LIST_HEAD(&priv->inactive_dontneed);
533 INIT_LIST_HEAD(&priv->inactive_unpinned);
534 mutex_init(&priv->mm_lock);
536 /* Teach lockdep about lock ordering wrt. shrinker: */
537 fs_reclaim_acquire(GFP_KERNEL);
538 might_lock(&priv->mm_lock);
539 fs_reclaim_release(GFP_KERNEL);
541 drm_mode_config_init(ddev);
543 ret = msm_init_vram(ddev);
545 goto err_destroy_mdss;
547 /* Bind all our sub-components: */
548 ret = component_bind_all(dev, ddev);
550 goto err_destroy_mdss;
552 dma_set_max_seg_size(dev, UINT_MAX);
554 msm_gem_shrinker_init(ddev);
556 switch (get_mdp_ver(pdev)) {
558 kms = mdp4_kms_init(ddev);
562 kms = mdp5_kms_init(ddev);
565 kms = dpu_kms_init(ddev);
569 /* valid only for the dummy headless case, where of_node=NULL */
570 WARN_ON(dev->of_node);
576 DRM_DEV_ERROR(dev, "failed to load kms\n");
582 /* Enable normalization of plane zpos */
583 ddev->mode_config.normalize_zpos = true;
587 ret = kms->funcs->hw_init(kms);
589 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
594 ddev->mode_config.funcs = &mode_config_funcs;
595 ddev->mode_config.helper_private = &mode_config_helper_funcs;
597 for (i = 0; i < priv->num_crtcs; i++) {
598 /* initialize event thread */
599 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
600 priv->event_thread[i].dev = ddev;
601 priv->event_thread[i].worker = kthread_create_worker(0,
602 "crtc_event:%d", priv->event_thread[i].crtc_id);
603 if (IS_ERR(priv->event_thread[i].worker)) {
604 ret = PTR_ERR(priv->event_thread[i].worker);
605 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
606 ret = PTR_ERR(priv->event_thread[i].worker);
610 sched_set_fifo(priv->event_thread[i].worker->task);
613 ret = drm_vblank_init(ddev, priv->num_crtcs);
615 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
620 pm_runtime_get_sync(dev);
621 ret = msm_irq_install(ddev, kms->irq);
622 pm_runtime_put_sync(dev);
624 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
629 ret = drm_dev_register(ddev, 0);
633 ret = msm_disp_snapshot_init(ddev);
635 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
637 drm_mode_config_reset(ddev);
639 #ifdef CONFIG_DRM_FBDEV_EMULATION
641 priv->fbdev = msm_fbdev_init(ddev);
644 ret = msm_debugfs_late_init(ddev);
648 drm_kms_helper_poll_init(ddev);
656 if (mdss && mdss->funcs)
657 mdss->funcs->destroy(ddev);
662 platform_set_drvdata(pdev, NULL);
670 static void load_gpu(struct drm_device *dev)
672 static DEFINE_MUTEX(init_lock);
673 struct msm_drm_private *priv = dev->dev_private;
675 mutex_lock(&init_lock);
678 priv->gpu = adreno_load_gpu(dev);
680 mutex_unlock(&init_lock);
683 static int context_init(struct drm_device *dev, struct drm_file *file)
685 struct msm_drm_private *priv = dev->dev_private;
686 struct msm_file_private *ctx;
688 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
692 kref_init(&ctx->ref);
693 msm_submitqueue_init(dev, ctx);
695 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
696 file->driver_priv = ctx;
701 static int msm_open(struct drm_device *dev, struct drm_file *file)
703 /* For now, load gpu on open.. to avoid the requirement of having
704 * firmware in the initrd.
708 return context_init(dev, file);
711 static void context_close(struct msm_file_private *ctx)
713 msm_submitqueue_close(ctx);
714 msm_file_private_put(ctx);
717 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
719 struct msm_drm_private *priv = dev->dev_private;
720 struct msm_file_private *ctx = file->driver_priv;
722 mutex_lock(&dev->struct_mutex);
723 if (ctx == priv->lastctx)
724 priv->lastctx = NULL;
725 mutex_unlock(&dev->struct_mutex);
730 int msm_crtc_enable_vblank(struct drm_crtc *crtc)
732 struct drm_device *dev = crtc->dev;
733 unsigned int pipe = crtc->index;
734 struct msm_drm_private *priv = dev->dev_private;
735 struct msm_kms *kms = priv->kms;
738 drm_dbg_vbl(dev, "crtc=%u", pipe);
739 return vblank_ctrl_queue_work(priv, pipe, true);
742 void msm_crtc_disable_vblank(struct drm_crtc *crtc)
744 struct drm_device *dev = crtc->dev;
745 unsigned int pipe = crtc->index;
746 struct msm_drm_private *priv = dev->dev_private;
747 struct msm_kms *kms = priv->kms;
750 drm_dbg_vbl(dev, "crtc=%u", pipe);
751 vblank_ctrl_queue_work(priv, pipe, false);
758 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
759 struct drm_file *file)
761 struct msm_drm_private *priv = dev->dev_private;
762 struct drm_msm_param *args = data;
765 /* for now, we just have 3d pipe.. eventually this would need to
766 * be more clever to dispatch to appropriate gpu module:
768 if (args->pipe != MSM_PIPE_3D0)
776 return gpu->funcs->get_param(gpu, args->param, &args->value);
779 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
780 struct drm_file *file)
782 struct drm_msm_gem_new *args = data;
784 if (args->flags & ~MSM_BO_FLAGS) {
785 DRM_ERROR("invalid flags: %08x\n", args->flags);
789 return msm_gem_new_handle(dev, file, args->size,
790 args->flags, &args->handle, NULL);
793 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
795 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
798 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
799 struct drm_file *file)
801 struct drm_msm_gem_cpu_prep *args = data;
802 struct drm_gem_object *obj;
803 ktime_t timeout = to_ktime(args->timeout);
806 if (args->op & ~MSM_PREP_FLAGS) {
807 DRM_ERROR("invalid op: %08x\n", args->op);
811 obj = drm_gem_object_lookup(file, args->handle);
815 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
817 drm_gem_object_put(obj);
822 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
823 struct drm_file *file)
825 struct drm_msm_gem_cpu_fini *args = data;
826 struct drm_gem_object *obj;
829 obj = drm_gem_object_lookup(file, args->handle);
833 ret = msm_gem_cpu_fini(obj);
835 drm_gem_object_put(obj);
840 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
841 struct drm_file *file, struct drm_gem_object *obj,
844 struct msm_drm_private *priv = dev->dev_private;
845 struct msm_file_private *ctx = file->driver_priv;
851 * Don't pin the memory here - just get an address so that userspace can
854 return msm_gem_get_iova(obj, ctx->aspace, iova);
857 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
858 struct drm_file *file)
860 struct drm_msm_gem_info *args = data;
861 struct drm_gem_object *obj;
862 struct msm_gem_object *msm_obj;
868 switch (args->info) {
869 case MSM_INFO_GET_OFFSET:
870 case MSM_INFO_GET_IOVA:
871 /* value returned as immediate, not pointer, so len==0: */
875 case MSM_INFO_SET_NAME:
876 case MSM_INFO_GET_NAME:
882 obj = drm_gem_object_lookup(file, args->handle);
886 msm_obj = to_msm_bo(obj);
888 switch (args->info) {
889 case MSM_INFO_GET_OFFSET:
890 args->value = msm_gem_mmap_offset(obj);
892 case MSM_INFO_GET_IOVA:
893 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
895 case MSM_INFO_SET_NAME:
896 /* length check should leave room for terminating null: */
897 if (args->len >= sizeof(msm_obj->name)) {
901 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
903 msm_obj->name[0] = '\0';
907 msm_obj->name[args->len] = '\0';
908 for (i = 0; i < args->len; i++) {
909 if (!isprint(msm_obj->name[i])) {
910 msm_obj->name[i] = '\0';
915 case MSM_INFO_GET_NAME:
916 if (args->value && (args->len < strlen(msm_obj->name))) {
920 args->len = strlen(msm_obj->name);
922 if (copy_to_user(u64_to_user_ptr(args->value),
923 msm_obj->name, args->len))
929 drm_gem_object_put(obj);
934 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
935 struct drm_file *file)
937 struct msm_drm_private *priv = dev->dev_private;
938 struct drm_msm_wait_fence *args = data;
939 ktime_t timeout = to_ktime(args->timeout);
940 struct msm_gpu_submitqueue *queue;
941 struct msm_gpu *gpu = priv->gpu;
942 struct dma_fence *fence;
946 DRM_ERROR("invalid pad: %08x\n", args->pad);
953 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
958 * Map submitqueue scoped "seqno" (which is actually an idr key)
959 * back to underlying dma-fence
961 * The fence is removed from the fence_idr when the submit is
962 * retired, so if the fence is not found it means there is nothing
965 ret = mutex_lock_interruptible(&queue->lock);
968 fence = idr_find(&queue->fence_idr, args->fence);
970 fence = dma_fence_get_rcu(fence);
971 mutex_unlock(&queue->lock);
976 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
979 } else if (ret != -ERESTARTSYS) {
983 dma_fence_put(fence);
984 msm_submitqueue_put(queue);
989 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
990 struct drm_file *file)
992 struct drm_msm_gem_madvise *args = data;
993 struct drm_gem_object *obj;
996 switch (args->madv) {
997 case MSM_MADV_DONTNEED:
998 case MSM_MADV_WILLNEED:
1004 obj = drm_gem_object_lookup(file, args->handle);
1009 ret = msm_gem_madvise(obj, args->madv);
1011 args->retained = ret;
1015 drm_gem_object_put(obj);
1021 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
1022 struct drm_file *file)
1024 struct drm_msm_submitqueue *args = data;
1026 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
1029 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
1030 args->flags, &args->id);
1033 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
1034 struct drm_file *file)
1036 return msm_submitqueue_query(dev, file->driver_priv, data);
1039 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1040 struct drm_file *file)
1042 u32 id = *(u32 *) data;
1044 return msm_submitqueue_remove(file->driver_priv, id);
1047 static const struct drm_ioctl_desc msm_ioctls[] = {
1048 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
1049 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
1050 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
1051 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1052 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1053 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
1054 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1055 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1056 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1057 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1058 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1061 DEFINE_DRM_GEM_FOPS(fops);
1063 static const struct drm_driver msm_driver = {
1064 .driver_features = DRIVER_GEM |
1070 .postclose = msm_postclose,
1071 .lastclose = drm_fb_helper_lastclose,
1072 .dumb_create = msm_gem_dumb_create,
1073 .dumb_map_offset = msm_gem_dumb_map_offset,
1074 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1075 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1076 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1077 .gem_prime_mmap = drm_gem_prime_mmap,
1078 #ifdef CONFIG_DEBUG_FS
1079 .debugfs_init = msm_debugfs_init,
1081 .ioctls = msm_ioctls,
1082 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1085 .desc = "MSM Snapdragon DRM",
1087 .major = MSM_VERSION_MAJOR,
1088 .minor = MSM_VERSION_MINOR,
1089 .patchlevel = MSM_VERSION_PATCHLEVEL,
1092 static int __maybe_unused msm_runtime_suspend(struct device *dev)
1094 struct drm_device *ddev = dev_get_drvdata(dev);
1095 struct msm_drm_private *priv = ddev->dev_private;
1096 struct msm_mdss *mdss = priv->mdss;
1100 if (mdss && mdss->funcs)
1101 return mdss->funcs->disable(mdss);
1106 static int __maybe_unused msm_runtime_resume(struct device *dev)
1108 struct drm_device *ddev = dev_get_drvdata(dev);
1109 struct msm_drm_private *priv = ddev->dev_private;
1110 struct msm_mdss *mdss = priv->mdss;
1114 if (mdss && mdss->funcs)
1115 return mdss->funcs->enable(mdss);
1120 static int __maybe_unused msm_pm_suspend(struct device *dev)
1123 if (pm_runtime_suspended(dev))
1126 return msm_runtime_suspend(dev);
1129 static int __maybe_unused msm_pm_resume(struct device *dev)
1131 if (pm_runtime_suspended(dev))
1134 return msm_runtime_resume(dev);
1137 static int __maybe_unused msm_pm_prepare(struct device *dev)
1139 struct drm_device *ddev = dev_get_drvdata(dev);
1140 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL;
1142 if (!priv || !priv->kms)
1145 return drm_mode_config_helper_suspend(ddev);
1148 static void __maybe_unused msm_pm_complete(struct device *dev)
1150 struct drm_device *ddev = dev_get_drvdata(dev);
1151 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL;
1153 if (!priv || !priv->kms)
1156 drm_mode_config_helper_resume(ddev);
1159 static const struct dev_pm_ops msm_pm_ops = {
1160 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1161 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1162 .prepare = msm_pm_prepare,
1163 .complete = msm_pm_complete,
1167 * Componentized driver support:
1171 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1172 * so probably some room for some helpers
1174 static int compare_of(struct device *dev, void *data)
1176 return dev->of_node == data;
1180 * Identify what components need to be added by parsing what remote-endpoints
1181 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1182 * is no external component that we need to add since LVDS is within MDP4
1185 static int add_components_mdp(struct device *mdp_dev,
1186 struct component_match **matchptr)
1188 struct device_node *np = mdp_dev->of_node;
1189 struct device_node *ep_node;
1190 struct device *master_dev;
1193 * on MDP4 based platforms, the MDP platform device is the component
1194 * master that adds other display interface components to itself.
1196 * on MDP5 based platforms, the MDSS platform device is the component
1197 * master that adds MDP5 and other display interface components to
1200 if (of_device_is_compatible(np, "qcom,mdp4"))
1201 master_dev = mdp_dev;
1203 master_dev = mdp_dev->parent;
1205 for_each_endpoint_of_node(np, ep_node) {
1206 struct device_node *intf;
1207 struct of_endpoint ep;
1210 ret = of_graph_parse_endpoint(ep_node, &ep);
1212 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1213 of_node_put(ep_node);
1218 * The LCDC/LVDS port on MDP4 is a speacial case where the
1219 * remote-endpoint isn't a component that we need to add
1221 if (of_device_is_compatible(np, "qcom,mdp4") &&
1226 * It's okay if some of the ports don't have a remote endpoint
1227 * specified. It just means that the port isn't connected to
1228 * any external interface.
1230 intf = of_graph_get_remote_port_parent(ep_node);
1234 if (of_device_is_available(intf))
1235 drm_of_component_match_add(master_dev, matchptr,
1244 static int compare_name_mdp(struct device *dev, void *data)
1246 return (strstr(dev_name(dev), "mdp") != NULL);
1249 static int add_display_components(struct platform_device *pdev,
1250 struct component_match **matchptr)
1252 struct device *mdp_dev;
1253 struct device *dev = &pdev->dev;
1257 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1258 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1259 * Populate the children devices, find the MDP5/DPU node, and then add
1260 * the interfaces to our components list.
1262 switch (get_mdp_ver(pdev)) {
1265 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1267 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1271 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1273 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1274 of_platform_depopulate(dev);
1278 put_device(mdp_dev);
1280 /* add the MDP component itself */
1281 drm_of_component_match_add(dev, matchptr, compare_of,
1290 ret = add_components_mdp(mdp_dev, matchptr);
1292 of_platform_depopulate(dev);
1298 * We don't know what's the best binding to link the gpu with the drm device.
1299 * Fow now, we just hunt for all the possible gpus that we support, and add them
1302 static const struct of_device_id msm_gpu_match[] = {
1303 { .compatible = "qcom,adreno" },
1304 { .compatible = "qcom,adreno-3xx" },
1305 { .compatible = "amd,imageon" },
1306 { .compatible = "qcom,kgsl-3d0" },
1310 static int add_gpu_components(struct device *dev,
1311 struct component_match **matchptr)
1313 struct device_node *np;
1315 np = of_find_matching_node(NULL, msm_gpu_match);
1319 if (of_device_is_available(np))
1320 drm_of_component_match_add(dev, matchptr, compare_of, np);
1327 static int msm_drm_bind(struct device *dev)
1329 return msm_drm_init(dev, &msm_driver);
1332 static void msm_drm_unbind(struct device *dev)
1334 msm_drm_uninit(dev);
1337 static const struct component_master_ops msm_drm_ops = {
1338 .bind = msm_drm_bind,
1339 .unbind = msm_drm_unbind,
1346 static int msm_pdev_probe(struct platform_device *pdev)
1348 struct component_match *match = NULL;
1351 if (get_mdp_ver(pdev)) {
1352 ret = add_display_components(pdev, &match);
1357 ret = add_gpu_components(&pdev->dev, &match);
1361 /* on all devices that I am aware of, iommu's which can map
1362 * any address the cpu can see are used:
1364 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1368 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1375 of_platform_depopulate(&pdev->dev);
1379 static int msm_pdev_remove(struct platform_device *pdev)
1381 component_master_del(&pdev->dev, &msm_drm_ops);
1382 of_platform_depopulate(&pdev->dev);
1387 static void msm_pdev_shutdown(struct platform_device *pdev)
1389 struct drm_device *drm = platform_get_drvdata(pdev);
1390 struct msm_drm_private *priv = drm ? drm->dev_private : NULL;
1392 if (!priv || !priv->kms)
1395 drm_atomic_helper_shutdown(drm);
1398 static const struct of_device_id dt_match[] = {
1399 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1400 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1401 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1402 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1403 { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },
1404 { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
1405 { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
1408 MODULE_DEVICE_TABLE(of, dt_match);
1410 static struct platform_driver msm_platform_driver = {
1411 .probe = msm_pdev_probe,
1412 .remove = msm_pdev_remove,
1413 .shutdown = msm_pdev_shutdown,
1416 .of_match_table = dt_match,
1421 static int __init msm_drm_register(void)
1431 msm_hdmi_register();
1434 return platform_driver_register(&msm_platform_driver);
1437 static void __exit msm_drm_unregister(void)
1440 platform_driver_unregister(&msm_platform_driver);
1441 msm_dp_unregister();
1442 msm_hdmi_unregister();
1443 adreno_unregister();
1444 msm_edp_unregister();
1445 msm_dsi_unregister();
1446 msm_mdp_unregister();
1447 msm_dpu_unregister();
1450 module_init(msm_drm_register);
1451 module_exit(msm_drm_unregister);
1453 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1454 MODULE_DESCRIPTION("MSM DRM Driver");
1455 MODULE_LICENSE("GPL");