1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/regulator/consumer.h>
15 #define dsi_phy_read(offset) msm_readl((offset))
16 #define dsi_phy_write(offset, data) msm_writel((data), (offset))
17 #define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
18 #define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
20 struct msm_dsi_phy_ops {
21 int (*pll_init)(struct msm_dsi_phy *phy);
22 int (*enable)(struct msm_dsi_phy *phy,
23 struct msm_dsi_phy_clk_request *clk_req);
24 void (*disable)(struct msm_dsi_phy *phy);
25 void (*save_pll_state)(struct msm_dsi_phy *phy);
26 int (*restore_pll_state)(struct msm_dsi_phy *phy);
27 bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
30 struct msm_dsi_phy_cfg {
31 struct dsi_reg_config reg_cfg;
32 struct msm_dsi_phy_ops ops;
34 unsigned long min_pll_rate;
35 unsigned long max_pll_rate;
37 const resource_size_t io_start[DSI_MAX];
38 const int num_dsi_phy;
40 bool has_phy_regulator;
44 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
45 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
46 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
47 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
48 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
49 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
50 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
51 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
52 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
53 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
54 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
55 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
57 struct msm_dsi_dphy_timing {
70 struct msm_dsi_phy_shared_timings shared_timings;
77 u8 hs_halfbyte_en_ckln;
80 #define DSI_BYTE_PLL_CLK 0
81 #define DSI_PIXEL_PLL_CLK 1
82 #define NUM_PROVIDED_CLKS 2
85 struct platform_device *pdev;
87 void __iomem *pll_base;
88 void __iomem *reg_base;
89 void __iomem *lane_base;
90 phys_addr_t base_size;
93 phys_addr_t lane_size;
97 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
99 struct msm_dsi_dphy_timing timing;
100 const struct msm_dsi_phy_cfg *cfg;
102 enum msm_dsi_phy_usecase usecase;
103 bool regulator_ldo_mode;
106 struct clk_hw *vco_hw;
109 struct clk_hw_onecell_data *provided_clocks;
115 * PHY internal functions
117 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
118 struct msm_dsi_phy_clk_request *clk_req);
119 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
120 struct msm_dsi_phy_clk_request *clk_req);
121 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
122 struct msm_dsi_phy_clk_request *clk_req);
123 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
124 struct msm_dsi_phy_clk_request *clk_req);
125 int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
126 struct msm_dsi_phy_clk_request *clk_req);
128 #endif /* __DSI_PHY_H__ */