drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/of_irq.h>
  11
  12 #include <drm/drm_debugfs.h>
  13 #include <drm/drm_drv.h>
  14 #include <drm/drm_file.h>
  15 #include <drm/drm_vblank.h>
  16
  17 #include "msm_drv.h"
  18 #include "msm_gem.h"
  19 #include "msm_mmu.h"
  20 #include "mdp5_kms.h"
  21
  22 static int mdp5_hw_init(struct msm_kms *kms)
  23 {
  24         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
  25         struct device *dev = &mdp5_kms->pdev->dev;
  26         unsigned long flags;
  27
  28         pm_runtime_get_sync(dev);
  29
  30         /* Magic unknown register writes:
  31          *
  32          *    W VBIF:0x004 00000001      (mdss_mdp.c:839)
  33          *    W MDP5:0x2e0 0xe9          (mdss_mdp.c:839)
  34          *    W MDP5:0x2e4 0x55          (mdss_mdp.c:839)
  35          *    W MDP5:0x3ac 0xc0000ccc    (mdss_mdp.c:839)
  36          *    W MDP5:0x3b4 0xc0000ccc    (mdss_mdp.c:839)
  37          *    W MDP5:0x3bc 0xcccccc      (mdss_mdp.c:839)
  38          *    W MDP5:0x4a8 0xcccc0c0     (mdss_mdp.c:839)
  39          *    W MDP5:0x4b0 0xccccc0c0    (mdss_mdp.c:839)
  40          *    W MDP5:0x4b8 0xccccc000    (mdss_mdp.c:839)
  41          *
  42          * Downstream fbdev driver gets these register offsets/values
  43          * from DT.. not really sure what these registers are or if
  44          * different values for different boards/SoC's, etc.  I guess
  45          * they are the golden registers.
  46          *
  47          * Not setting these does not seem to cause any problem.  But
  48          * we may be getting lucky with the bootloader initializing
  49          * them for us.  OTOH, if we can always count on the bootloader
  50          * setting the golden registers, then perhaps we don't need to
  51          * care.
  52          */
  53
  54         spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
  55         mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
  56         spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
  57
  58         mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
  59
  60         pm_runtime_put_sync(dev);
  61
  62         return 0;
  63 }
  64
  65 /* Global/shared object state funcs */
  66
  67 /*
  68  * This is a helper that returns the private state currently in operation.
  69  * Note that this would return the "old_state" if called in the atomic check
  70  * path, and the "new_state" after the atomic swap has been done.
  71  */
  72 struct mdp5_global_state *
  73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms)
  74 {
  75         return to_mdp5_global_state(mdp5_kms->glob_state.state);
  76 }
  77
  78 /*
  79  * This acquires the modeset lock set aside for global state, creates
  80  * a new duplicated private object state.
  81  */
  82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s)
  83 {
  84         struct msm_drm_private *priv = s->dev->dev_private;
  85         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
  86         struct drm_private_state *priv_state;
  87         int ret;
  88
  89         ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx);
  90         if (ret)
  91                 return ERR_PTR(ret);
  92
  93         priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);
  94         if (IS_ERR(priv_state))
  95                 return ERR_CAST(priv_state);
  96
  97         return to_mdp5_global_state(priv_state);
  98 }
  99
 100 static struct drm_private_state *
 101 mdp5_global_duplicate_state(struct drm_private_obj *obj)
 102 {
 103         struct mdp5_global_state *state;
 104
 105         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 106         if (!state)
 107                 return NULL;
 108
 109         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 110
 111         return &state->base;
 112 }
 113
 114 static void mdp5_global_destroy_state(struct drm_private_obj *obj,
 115                                       struct drm_private_state *state)
 116 {
 117         struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state);
 118
 119         kfree(mdp5_state);
 120 }
 121
 122 static const struct drm_private_state_funcs mdp5_global_state_funcs = {
 123         .atomic_duplicate_state = mdp5_global_duplicate_state,
 124         .atomic_destroy_state = mdp5_global_destroy_state,
 125 };
 126
 127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
 128 {
 129         struct mdp5_global_state *state;
 130
 131         drm_modeset_lock_init(&mdp5_kms->glob_state_lock);
 132
 133         state = kzalloc(sizeof(*state), GFP_KERNEL);
 134         if (!state)
 135                 return -ENOMEM;
 136
 137         state->mdp5_kms = mdp5_kms;
 138
 139         drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state,
 140                                     &state->base,
 141                                     &mdp5_global_state_funcs);
 142         return 0;
 143 }
 144
 145 static void mdp5_enable_commit(struct msm_kms *kms)
 146 {
 147         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 148         pm_runtime_get_sync(&mdp5_kms->pdev->dev);
 149 }
 150
 151 static void mdp5_disable_commit(struct msm_kms *kms)
 152 {
 153         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 154         pm_runtime_put_sync(&mdp5_kms->pdev->dev);
 155 }
 156
 157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
 158 {
 159         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 160         struct mdp5_global_state *global_state;
 161
 162         global_state = mdp5_get_existing_global_state(mdp5_kms);
 163
 164         if (mdp5_kms->smp)
 165                 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp);
 166 }
 167
 168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
 169 {
 170         /* TODO */
 171 }
 172
 173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
 174 {
 175         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 176         struct drm_crtc *crtc;
 177
 178         for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask)
 179                 mdp5_crtc_wait_for_commit_done(crtc);
 180 }
 181
 182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
 183 {
 184         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 185         struct mdp5_global_state *global_state;
 186
 187         global_state = mdp5_get_existing_global_state(mdp5_kms);
 188
 189         if (mdp5_kms->smp)
 190                 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp);
 191 }
 192
 193 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
 194                 struct drm_encoder *encoder)
 195 {
 196         return rate;
 197 }
 198
 199 static int mdp5_set_split_display(struct msm_kms *kms,
 200                 struct drm_encoder *encoder,
 201                 struct drm_encoder *slave_encoder,
 202                 bool is_cmd_mode)
 203 {
 204         if (is_cmd_mode)
 205                 return mdp5_cmd_encoder_set_split_display(encoder,
 206                                                         slave_encoder);
 207         else
 208                 return mdp5_vid_encoder_set_split_display(encoder,
 209                                                           slave_encoder);
 210 }
 211
 212 static void mdp5_kms_destroy(struct msm_kms *kms)
 213 {
 214         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 215         struct msm_gem_address_space *aspace = kms->aspace;
 216         int i;
 217
 218         for (i = 0; i < mdp5_kms->num_hwmixers; i++)
 219                 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]);
 220
 221         for (i = 0; i < mdp5_kms->num_hwpipes; i++)
 222                 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]);
 223
 224         if (aspace) {
 225                 aspace->mmu->funcs->detach(aspace->mmu);
 226                 msm_gem_address_space_put(aspace);
 227         }
 228
 229         mdp_kms_destroy(&mdp5_kms->base);
 230 }
 231
 232 #ifdef CONFIG_DEBUG_FS
 233 static int smp_show(struct seq_file *m, void *arg)
 234 {
 235         struct drm_info_node *node = (struct drm_info_node *) m->private;
 236         struct drm_device *dev = node->minor->dev;
 237         struct msm_drm_private *priv = dev->dev_private;
 238         struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
 239         struct drm_printer p = drm_seq_file_printer(m);
 240
 241         if (!mdp5_kms->smp) {
 242                 drm_printf(&p, "no SMP pool\n");
 243                 return 0;
 244         }
 245
 246         mdp5_smp_dump(mdp5_kms->smp, &p);
 247
 248         return 0;
 249 }
 250
 251 static struct drm_info_list mdp5_debugfs_list[] = {
 252                 {"smp", smp_show },
 253 };
 254
 255 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
 256 {
 257         drm_debugfs_create_files(mdp5_debugfs_list,
 258                                  ARRAY_SIZE(mdp5_debugfs_list),
 259                                  minor->debugfs_root, minor);
 260
 261         return 0;
 262 }
 263 #endif
 264
 265 static const struct mdp_kms_funcs kms_funcs = {
 266         .base = {
 267                 .hw_init         = mdp5_hw_init,
 268                 .irq_preinstall  = mdp5_irq_preinstall,
 269                 .irq_postinstall = mdp5_irq_postinstall,
 270                 .irq_uninstall   = mdp5_irq_uninstall,
 271                 .irq             = mdp5_irq,
 272                 .enable_vblank   = mdp5_enable_vblank,
 273                 .disable_vblank  = mdp5_disable_vblank,
 274                 .flush_commit    = mdp5_flush_commit,
 275                 .enable_commit   = mdp5_enable_commit,
 276                 .disable_commit  = mdp5_disable_commit,
 277                 .prepare_commit  = mdp5_prepare_commit,
 278                 .wait_flush      = mdp5_wait_flush,
 279                 .complete_commit = mdp5_complete_commit,
 280                 .get_format      = mdp_get_format,
 281                 .round_pixclk    = mdp5_round_pixclk,
 282                 .set_split_display = mdp5_set_split_display,
 283                 .destroy         = mdp5_kms_destroy,
 284 #ifdef CONFIG_DEBUG_FS
 285                 .debugfs_init    = mdp5_kms_debugfs_init,
 286 #endif
 287         },
 288         .set_irqmask         = mdp5_set_irqmask,
 289 };
 290
 291 static int mdp5_disable(struct mdp5_kms *mdp5_kms)
 292 {
 293         DBG("");
 294
 295         mdp5_kms->enable_count--;
 296         WARN_ON(mdp5_kms->enable_count < 0);
 297
 298         if (mdp5_kms->tbu_rt_clk)
 299                 clk_disable_unprepare(mdp5_kms->tbu_rt_clk);
 300         if (mdp5_kms->tbu_clk)
 301                 clk_disable_unprepare(mdp5_kms->tbu_clk);
 302         clk_disable_unprepare(mdp5_kms->ahb_clk);
 303         clk_disable_unprepare(mdp5_kms->axi_clk);
 304         clk_disable_unprepare(mdp5_kms->core_clk);
 305         if (mdp5_kms->lut_clk)
 306                 clk_disable_unprepare(mdp5_kms->lut_clk);
 307
 308         return 0;
 309 }
 310
 311 static int mdp5_enable(struct mdp5_kms *mdp5_kms)
 312 {
 313         DBG("");
 314
 315         mdp5_kms->enable_count++;
 316
 317         clk_prepare_enable(mdp5_kms->ahb_clk);
 318         clk_prepare_enable(mdp5_kms->axi_clk);
 319         clk_prepare_enable(mdp5_kms->core_clk);
 320         if (mdp5_kms->lut_clk)
 321                 clk_prepare_enable(mdp5_kms->lut_clk);
 322         if (mdp5_kms->tbu_clk)
 323                 clk_prepare_enable(mdp5_kms->tbu_clk);
 324         if (mdp5_kms->tbu_rt_clk)
 325                 clk_prepare_enable(mdp5_kms->tbu_rt_clk);
 326
 327         return 0;
 328 }
 329
 330 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
 331                                              struct mdp5_interface *intf,
 332                                              struct mdp5_ctl *ctl)
 333 {
 334         struct drm_device *dev = mdp5_kms->dev;
 335         struct msm_drm_private *priv = dev->dev_private;
 336         struct drm_encoder *encoder;
 337
 338         encoder = mdp5_encoder_init(dev, intf, ctl);
 339         if (IS_ERR(encoder)) {
 340                 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n");
 341                 return encoder;
 342         }
 343
 344         priv->encoders[priv->num_encoders++] = encoder;
 345
 346         return encoder;
 347 }
 348
 349 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
 350 {
 351         const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
 352         const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
 353         int id = 0, i;
 354
 355         for (i = 0; i < intf_cnt; i++) {
 356                 if (intfs[i] == INTF_DSI) {
 357                         if (intf_num == i)
 358                                 return id;
 359
 360                         id++;
 361                 }
 362         }
 363
 364         return -EINVAL;
 365 }
 366
 367 static int modeset_init_intf(struct mdp5_kms *mdp5_kms,
 368                              struct mdp5_interface *intf)
 369 {
 370         struct drm_device *dev = mdp5_kms->dev;
 371         struct msm_drm_private *priv = dev->dev_private;
 372         struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
 373         struct mdp5_ctl *ctl;
 374         struct drm_encoder *encoder;
 375         int ret = 0;
 376
 377         switch (intf->type) {
 378         case INTF_eDP:
 379                 if (!priv->edp)
 380                         break;
 381
 382                 ctl = mdp5_ctlm_request(ctlm, intf->num);
 383                 if (!ctl) {
 384                         ret = -EINVAL;
 385                         break;
 386                 }
 387
 388                 encoder = construct_encoder(mdp5_kms, intf, ctl);
 389                 if (IS_ERR(encoder)) {
 390                         ret = PTR_ERR(encoder);
 391                         break;
 392                 }
 393
 394                 ret = msm_edp_modeset_init(priv->edp, dev, encoder);
 395                 break;
 396         case INTF_HDMI:
 397                 if (!priv->hdmi)
 398                         break;
 399
 400                 ctl = mdp5_ctlm_request(ctlm, intf->num);
 401                 if (!ctl) {
 402                         ret = -EINVAL;
 403                         break;
 404                 }
 405
 406                 encoder = construct_encoder(mdp5_kms, intf, ctl);
 407                 if (IS_ERR(encoder)) {
 408                         ret = PTR_ERR(encoder);
 409                         break;
 410                 }
 411
 412                 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
 413                 break;
 414         case INTF_DSI:
 415         {
 416                 const struct mdp5_cfg_hw *hw_cfg =
 417                                         mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 418                 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num);
 419
 420                 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {
 421                         DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n",
 422                                 intf->num);
 423                         ret = -EINVAL;
 424                         break;
 425                 }
 426
 427                 if (!priv->dsi[dsi_id])
 428                         break;
 429
 430                 ctl = mdp5_ctlm_request(ctlm, intf->num);
 431                 if (!ctl) {
 432                         ret = -EINVAL;
 433                         break;
 434                 }
 435
 436                 encoder = construct_encoder(mdp5_kms, intf, ctl);
 437                 if (IS_ERR(encoder)) {
 438                         ret = PTR_ERR(encoder);
 439                         break;
 440                 }
 441
 442                 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
 443                 if (!ret)
 444                         mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_id]));
 445
 446                 break;
 447         }
 448         default:
 449                 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type);
 450                 ret = -EINVAL;
 451                 break;
 452         }
 453
 454         return ret;
 455 }
 456
 457 static int modeset_init(struct mdp5_kms *mdp5_kms)
 458 {
 459         struct drm_device *dev = mdp5_kms->dev;
 460         struct msm_drm_private *priv = dev->dev_private;
 461         unsigned int num_crtcs;
 462         int i, ret, pi = 0, ci = 0;
 463         struct drm_plane *primary[MAX_BASES] = { NULL };
 464         struct drm_plane *cursor[MAX_BASES] = { NULL };
 465
 466         /*
 467          * Construct encoders and modeset initialize connector devices
 468          * for each external display interface.
 469          */
 470         for (i = 0; i < mdp5_kms->num_intfs; i++) {
 471                 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]);
 472                 if (ret)
 473                         goto fail;
 474         }
 475
 476         /*
 477          * We should ideally have less number of encoders (set up by parsing
 478          * the MDP5 interfaces) than the number of layer mixers present in HW,
 479          * but let's be safe here anyway
 480          */
 481         num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers);
 482
 483         /*
 484          * Construct planes equaling the number of hw pipes, and CRTCs for the
 485          * N encoders set up by the driver. The first N planes become primary
 486          * planes for the CRTCs, with the remainder as overlay planes:
 487          */
 488         for (i = 0; i < mdp5_kms->num_hwpipes; i++) {
 489                 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];
 490                 struct drm_plane *plane;
 491                 enum drm_plane_type type;
 492
 493                 if (i < num_crtcs)
 494                         type = DRM_PLANE_TYPE_PRIMARY;
 495                 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR)
 496                         type = DRM_PLANE_TYPE_CURSOR;
 497                 else
 498                         type = DRM_PLANE_TYPE_OVERLAY;
 499
 500                 plane = mdp5_plane_init(dev, type);
 501                 if (IS_ERR(plane)) {
 502                         ret = PTR_ERR(plane);
 503                         DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret);
 504                         goto fail;
 505                 }
 506                 priv->planes[priv->num_planes++] = plane;
 507
 508                 if (type == DRM_PLANE_TYPE_PRIMARY)
 509                         primary[pi++] = plane;
 510                 if (type == DRM_PLANE_TYPE_CURSOR)
 511                         cursor[ci++] = plane;
 512         }
 513
 514         for (i = 0; i < num_crtcs; i++) {
 515                 struct drm_crtc *crtc;
 516
 517                 crtc  = mdp5_crtc_init(dev, primary[i], cursor[i], i);
 518                 if (IS_ERR(crtc)) {
 519                         ret = PTR_ERR(crtc);
 520                         DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);
 521                         goto fail;
 522                 }
 523                 priv->crtcs[priv->num_crtcs++] = crtc;
 524         }
 525
 526         /*
 527          * Now that we know the number of crtcs we've created, set the possible
 528          * crtcs for the encoders
 529          */
 530         for (i = 0; i < priv->num_encoders; i++) {
 531                 struct drm_encoder *encoder = priv->encoders[i];
 532
 533                 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
 534         }
 535
 536         return 0;
 537
 538 fail:
 539         return ret;
 540 }
 541
 542 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,
 543                                  u32 *major, u32 *minor)
 544 {
 545         struct device *dev = &mdp5_kms->pdev->dev;
 546         u32 version;
 547
 548         pm_runtime_get_sync(dev);
 549         version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);
 550         pm_runtime_put_sync(dev);
 551
 552         *major = FIELD(version, MDP5_HW_VERSION_MAJOR);
 553         *minor = FIELD(version, MDP5_HW_VERSION_MINOR);
 554
 555         DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor);
 556 }
 557
 558 static int get_clk(struct platform_device *pdev, struct clk **clkp,
 559                 const char *name, bool mandatory)
 560 {
 561         struct device *dev = &pdev->dev;
 562         struct clk *clk = msm_clk_get(pdev, name);
 563         if (IS_ERR(clk) && mandatory) {
 564                 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
 565                 return PTR_ERR(clk);
 566         }
 567         if (IS_ERR(clk))
 568                 DBG("skipping %s", name);
 569         else
 570                 *clkp = clk;
 571
 572         return 0;
 573 }
 574
 575 struct msm_kms *mdp5_kms_init(struct drm_device *dev)
 576 {
 577         struct msm_drm_private *priv = dev->dev_private;
 578         struct platform_device *pdev;
 579         struct mdp5_kms *mdp5_kms;
 580         struct mdp5_cfg *config;
 581         struct msm_kms *kms;
 582         struct msm_gem_address_space *aspace;
 583         int irq, i, ret;
 584         struct device *iommu_dev;
 585
 586         /* priv->kms would have been populated by the MDP5 driver */
 587         kms = priv->kms;
 588         if (!kms)
 589                 return NULL;
 590
 591         mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
 592         pdev = mdp5_kms->pdev;
 593
 594         ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs);
 595         if (ret) {
 596                 DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n");
 597                 goto fail;
 598         }
 599
 600         irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
 601         if (irq < 0) {
 602                 ret = irq;
 603                 DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret);
 604                 goto fail;
 605         }
 606
 607         kms->irq = irq;
 608
 609         config = mdp5_cfg_get_config(mdp5_kms->cfg);
 610
 611         /* make sure things are off before attaching iommu (bootloader could
 612          * have left things on, in which case we'll start getting faults if
 613          * we don't disable):
 614          */
 615         pm_runtime_get_sync(&pdev->dev);
 616         for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
 617                 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
 618                     !config->hw->intf.base[i])
 619                         continue;
 620                 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
 621
 622                 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);
 623         }
 624         mdelay(16);
 625
 626         if (config->platform.iommu) {
 627                 struct msm_mmu *mmu;
 628
 629                 iommu_dev = &pdev->dev;
 630                 if (!dev_iommu_fwspec_get(iommu_dev))
 631                         iommu_dev = iommu_dev->parent;
 632
 633                 mmu = msm_iommu_new(iommu_dev, config->platform.iommu);
 634
 635                 aspace = msm_gem_address_space_create(mmu, "mdp5",
 636                         0x1000, 0x100000000 - 0x1000);
 637
 638                 if (IS_ERR(aspace)) {
 639                         if (!IS_ERR(mmu))
 640                                 mmu->funcs->destroy(mmu);
 641                         ret = PTR_ERR(aspace);
 642                         goto fail;
 643                 }
 644
 645                 kms->aspace = aspace;
 646         } else {
 647                 DRM_DEV_INFO(&pdev->dev,
 648                          "no iommu, fallback to phys contig buffers for scanout\n");
 649                 aspace = NULL;
 650         }
 651
 652         pm_runtime_put_sync(&pdev->dev);
 653
 654         ret = modeset_init(mdp5_kms);
 655         if (ret) {
 656                 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret);
 657                 goto fail;
 658         }
 659
 660         dev->mode_config.min_width = 0;
 661         dev->mode_config.min_height = 0;
 662         dev->mode_config.max_width = 0xffff;
 663         dev->mode_config.max_height = 0xffff;
 664
 665         dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */
 666         dev->vblank_disable_immediate = true;
 667
 668         return kms;
 669 fail:
 670         if (kms)
 671                 mdp5_kms_destroy(kms);
 672         return ERR_PTR(ret);
 673 }
 674
 675 static void mdp5_destroy(struct platform_device *pdev)
 676 {
 677         struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
 678         int i;
 679
 680         if (mdp5_kms->ctlm)
 681                 mdp5_ctlm_destroy(mdp5_kms->ctlm);
 682         if (mdp5_kms->smp)
 683                 mdp5_smp_destroy(mdp5_kms->smp);
 684         if (mdp5_kms->cfg)
 685                 mdp5_cfg_destroy(mdp5_kms->cfg);
 686
 687         for (i = 0; i < mdp5_kms->num_intfs; i++)
 688                 kfree(mdp5_kms->intfs[i]);
 689
 690         if (mdp5_kms->rpm_enabled)
 691                 pm_runtime_disable(&pdev->dev);
 692
 693         drm_atomic_private_obj_fini(&mdp5_kms->glob_state);
 694         drm_modeset_lock_fini(&mdp5_kms->glob_state_lock);
 695 }
 696
 697 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
 698                 const enum mdp5_pipe *pipes, const uint32_t *offsets,
 699                 uint32_t caps)
 700 {
 701         struct drm_device *dev = mdp5_kms->dev;
 702         int i, ret;
 703
 704         for (i = 0; i < cnt; i++) {
 705                 struct mdp5_hw_pipe *hwpipe;
 706
 707                 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps);
 708                 if (IS_ERR(hwpipe)) {
 709                         ret = PTR_ERR(hwpipe);
 710                         DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n",
 711                                         pipe2name(pipes[i]), ret);
 712                         return ret;
 713                 }
 714                 hwpipe->idx = mdp5_kms->num_hwpipes;
 715                 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;
 716         }
 717
 718         return 0;
 719 }
 720
 721 static int hwpipe_init(struct mdp5_kms *mdp5_kms)
 722 {
 723         static const enum mdp5_pipe rgb_planes[] = {
 724                         SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
 725         };
 726         static const enum mdp5_pipe vig_planes[] = {
 727                         SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
 728         };
 729         static const enum mdp5_pipe dma_planes[] = {
 730                         SSPP_DMA0, SSPP_DMA1,
 731         };
 732         static const enum mdp5_pipe cursor_planes[] = {
 733                         SSPP_CURSOR0, SSPP_CURSOR1,
 734         };
 735         const struct mdp5_cfg_hw *hw_cfg;
 736         int ret;
 737
 738         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 739
 740         /* Construct RGB pipes: */
 741         ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,
 742                         hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);
 743         if (ret)
 744                 return ret;
 745
 746         /* Construct video (VIG) pipes: */
 747         ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
 748                         hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);
 749         if (ret)
 750                 return ret;
 751
 752         /* Construct DMA pipes: */
 753         ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,
 754                         hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);
 755         if (ret)
 756                 return ret;
 757
 758         /* Construct cursor pipes: */
 759         ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,
 760                         cursor_planes, hw_cfg->pipe_cursor.base,
 761                         hw_cfg->pipe_cursor.caps);
 762         if (ret)
 763                 return ret;
 764
 765         return 0;
 766 }
 767
 768 static int hwmixer_init(struct mdp5_kms *mdp5_kms)
 769 {
 770         struct drm_device *dev = mdp5_kms->dev;
 771         const struct mdp5_cfg_hw *hw_cfg;
 772         int i, ret;
 773
 774         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 775
 776         for (i = 0; i < hw_cfg->lm.count; i++) {
 777                 struct mdp5_hw_mixer *mixer;
 778
 779                 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]);
 780                 if (IS_ERR(mixer)) {
 781                         ret = PTR_ERR(mixer);
 782                         DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n",
 783                                 i, ret);
 784                         return ret;
 785                 }
 786
 787                 mixer->idx = mdp5_kms->num_hwmixers;
 788                 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer;
 789         }
 790
 791         return 0;
 792 }
 793
 794 static int interface_init(struct mdp5_kms *mdp5_kms)
 795 {
 796         struct drm_device *dev = mdp5_kms->dev;
 797         const struct mdp5_cfg_hw *hw_cfg;
 798         const enum mdp5_intf_type *intf_types;
 799         int i;
 800
 801         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 802         intf_types = hw_cfg->intf.connect;
 803
 804         for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
 805                 struct mdp5_interface *intf;
 806
 807                 if (intf_types[i] == INTF_DISABLED)
 808                         continue;
 809
 810                 intf = kzalloc(sizeof(*intf), GFP_KERNEL);
 811                 if (!intf) {
 812                         DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i);
 813                         return -ENOMEM;
 814                 }
 815
 816                 intf->num = i;
 817                 intf->type = intf_types[i];
 818                 intf->mode = MDP5_INTF_MODE_NONE;
 819                 intf->idx = mdp5_kms->num_intfs;
 820                 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf;
 821         }
 822
 823         return 0;
 824 }
 825
 826 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
 827 {
 828         struct msm_drm_private *priv = dev->dev_private;
 829         struct mdp5_kms *mdp5_kms;
 830         struct mdp5_cfg *config;
 831         u32 major, minor;
 832         int ret;
 833
 834         mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);
 835         if (!mdp5_kms) {
 836                 ret = -ENOMEM;
 837                 goto fail;
 838         }
 839
 840         platform_set_drvdata(pdev, mdp5_kms);
 841
 842         spin_lock_init(&mdp5_kms->resource_lock);
 843
 844         mdp5_kms->dev = dev;
 845         mdp5_kms->pdev = pdev;
 846
 847         ret = mdp5_global_obj_init(mdp5_kms);
 848         if (ret)
 849                 goto fail;
 850
 851         mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
 852         if (IS_ERR(mdp5_kms->mmio)) {
 853                 ret = PTR_ERR(mdp5_kms->mmio);
 854                 goto fail;
 855         }
 856
 857         /* mandatory clocks: */
 858         ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true);
 859         if (ret)
 860                 goto fail;
 861         ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true);
 862         if (ret)
 863                 goto fail;
 864         ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true);
 865         if (ret)
 866                 goto fail;
 867         ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true);
 868         if (ret)
 869                 goto fail;
 870
 871         /* optional clocks: */
 872         get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);
 873         get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false);
 874         get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false);
 875
 876         /* we need to set a default rate before enabling.  Set a safe
 877          * rate first, then figure out hw revision, and then set a
 878          * more optimal rate:
 879          */
 880         clk_set_rate(mdp5_kms->core_clk, 200000000);
 881
 882         pm_runtime_enable(&pdev->dev);
 883         mdp5_kms->rpm_enabled = true;
 884
 885         read_mdp_hw_revision(mdp5_kms, &major, &minor);
 886
 887         mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
 888         if (IS_ERR(mdp5_kms->cfg)) {
 889                 ret = PTR_ERR(mdp5_kms->cfg);
 890                 mdp5_kms->cfg = NULL;
 891                 goto fail;
 892         }
 893
 894         config = mdp5_cfg_get_config(mdp5_kms->cfg);
 895         mdp5_kms->caps = config->hw->mdp.caps;
 896
 897         /* TODO: compute core clock rate at runtime */
 898         clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
 899
 900         /*
 901          * Some chipsets have a Shared Memory Pool (SMP), while others
 902          * have dedicated latency buffering per source pipe instead;
 903          * this section initializes the SMP:
 904          */
 905         if (mdp5_kms->caps & MDP_CAP_SMP) {
 906                 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);
 907                 if (IS_ERR(mdp5_kms->smp)) {
 908                         ret = PTR_ERR(mdp5_kms->smp);
 909                         mdp5_kms->smp = NULL;
 910                         goto fail;
 911                 }
 912         }
 913
 914         mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
 915         if (IS_ERR(mdp5_kms->ctlm)) {
 916                 ret = PTR_ERR(mdp5_kms->ctlm);
 917                 mdp5_kms->ctlm = NULL;
 918                 goto fail;
 919         }
 920
 921         ret = hwpipe_init(mdp5_kms);
 922         if (ret)
 923                 goto fail;
 924
 925         ret = hwmixer_init(mdp5_kms);
 926         if (ret)
 927                 goto fail;
 928
 929         ret = interface_init(mdp5_kms);
 930         if (ret)
 931                 goto fail;
 932
 933         /* set uninit-ed kms */
 934         priv->kms = &mdp5_kms->base.base;
 935
 936         return 0;
 937 fail:
 938         if (mdp5_kms)
 939                 mdp5_destroy(pdev);
 940         return ret;
 941 }
 942
 943 static int mdp5_bind(struct device *dev, struct device *master, void *data)
 944 {
 945         struct drm_device *ddev = dev_get_drvdata(master);
 946         struct platform_device *pdev = to_platform_device(dev);
 947
 948         DBG("");
 949
 950         return mdp5_init(pdev, ddev);
 951 }
 952
 953 static void mdp5_unbind(struct device *dev, struct device *master,
 954                         void *data)
 955 {
 956         struct platform_device *pdev = to_platform_device(dev);
 957
 958         mdp5_destroy(pdev);
 959 }
 960
 961 static const struct component_ops mdp5_ops = {
 962         .bind   = mdp5_bind,
 963         .unbind = mdp5_unbind,
 964 };
 965
 966 static int mdp5_setup_interconnect(struct platform_device *pdev)
 967 {
 968         struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem");
 969         struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem");
 970         struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem");
 971
 972         if (IS_ERR(path0))
 973                 return PTR_ERR(path0);
 974
 975         if (!path0) {
 976                 /* no interconnect support is not necessarily a fatal
 977                  * condition, the platform may simply not have an
 978                  * interconnect driver yet.  But warn about it in case
 979                  * bootloader didn't setup bus clocks high enough for
 980                  * scanout.
 981                  */
 982                 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n");
 983                 return 0;
 984         }
 985
 986         icc_set_bw(path0, 0, MBps_to_icc(6400));
 987
 988         if (!IS_ERR_OR_NULL(path1))
 989                 icc_set_bw(path1, 0, MBps_to_icc(6400));
 990         if (!IS_ERR_OR_NULL(path_rot))
 991                 icc_set_bw(path_rot, 0, MBps_to_icc(6400));
 992
 993         return 0;
 994 }
 995
 996 static int mdp5_dev_probe(struct platform_device *pdev)
 997 {
 998         int ret;
 999
1000         DBG("");
1001
1002         ret = mdp5_setup_interconnect(pdev);
1003         if (ret)
1004                 return ret;
1005
1006         return component_add(&pdev->dev, &mdp5_ops);
1007 }
1008
1009 static int mdp5_dev_remove(struct platform_device *pdev)
1010 {
1011         DBG("");
1012         component_del(&pdev->dev, &mdp5_ops);
1013         return 0;
1014 }
1015
1016 static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
1017 {
1018         struct platform_device *pdev = to_platform_device(dev);
1019         struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1020
1021         DBG("");
1022
1023         return mdp5_disable(mdp5_kms);
1024 }
1025
1026 static __maybe_unused int mdp5_runtime_resume(struct device *dev)
1027 {
1028         struct platform_device *pdev = to_platform_device(dev);
1029         struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
1030
1031         DBG("");
1032
1033         return mdp5_enable(mdp5_kms);
1034 }
1035
1036 static const struct dev_pm_ops mdp5_pm_ops = {
1037         SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL)
1038 };
1039
1040 static const struct of_device_id mdp5_dt_match[] = {
1041         { .compatible = "qcom,mdp5", },
1042         /* to support downstream DT files */
1043         { .compatible = "qcom,mdss_mdp", },
1044         {}
1045 };
1046 MODULE_DEVICE_TABLE(of, mdp5_dt_match);
1047
1048 static struct platform_driver mdp5_driver = {
1049         .probe = mdp5_dev_probe,
1050         .remove = mdp5_dev_remove,
1051         .driver = {
1052                 .name = "msm_mdp",
1053                 .of_match_table = mdp5_dt_match,
1054                 .pm = &mdp5_pm_ops,
1055         },
1056 };
1057
1058 void __init msm_mdp_register(void)
1059 {
1060         DBG("");
1061         platform_driver_register(&mdp5_driver);
1062 }
1063
1064 void __exit msm_mdp_unregister(void)
1065 {
1066         DBG("");
1067         platform_driver_unregister(&mdp5_driver);
1068 }