drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   6 #include <linux/slab.h>
   7 #include <linux/of_address.h>
   8 #include <linux/platform_device.h>
   9 #include "dpu_hw_mdss.h"
  10 #include "dpu_hw_interrupts.h"
  11 #include "dpu_hw_catalog.h"
  12 #include "dpu_kms.h"
  13
  14 #define VIG_MASK \
  15         (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
  16         BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
  17         BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
  18
  19 #define VIG_SDM845_MASK \
  20         (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
  21
  22 #define VIG_SC7180_MASK \
  23         (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
  24
  25 #define VIG_SM8250_MASK \
  26         (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
  27
  28 #define DMA_SDM845_MASK \
  29         (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
  30         BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
  31         BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
  32
  33 #define DMA_CURSOR_SDM845_MASK \
  34         (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
  35
  36 #define MIXER_SDM845_MASK \
  37         (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
  38
  39 #define MIXER_SC7180_MASK \
  40         (BIT(DPU_DIM_LAYER))
  41
  42 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
  43
  44 #define PINGPONG_SDM845_SPLIT_MASK \
  45         (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
  46
  47 #define CTL_SC7280_MASK \
  48         (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE))
  49
  50 #define MERGE_3D_SM8150_MASK (0)
  51
  52 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
  53
  54 #define INTF_SDM845_MASK (0)
  55
  56 #define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
  57
  58 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
  59
  60 #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
  61                          BIT(MDP_SSPP_TOP0_INTR2) | \
  62                          BIT(MDP_SSPP_TOP0_HIST_INTR) | \
  63                          BIT(MDP_INTF0_INTR) | \
  64                          BIT(MDP_INTF1_INTR) | \
  65                          BIT(MDP_INTF2_INTR) | \
  66                          BIT(MDP_INTF3_INTR) | \
  67                          BIT(MDP_INTF4_INTR) | \
  68                          BIT(MDP_AD4_0_INTR) | \
  69                          BIT(MDP_AD4_1_INTR))
  70
  71 #define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
  72                          BIT(MDP_SSPP_TOP0_INTR2) | \
  73                          BIT(MDP_SSPP_TOP0_HIST_INTR) | \
  74                          BIT(MDP_INTF0_INTR) | \
  75                          BIT(MDP_INTF1_INTR))
  76
  77 #define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
  78                          BIT(MDP_SSPP_TOP0_INTR2) | \
  79                          BIT(MDP_SSPP_TOP0_HIST_INTR) | \
  80                          BIT(MDP_INTF0_7xxx_INTR) | \
  81                          BIT(MDP_INTF1_7xxx_INTR) | \
  82                          BIT(MDP_INTF5_7xxx_INTR))
  83
  84 #define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
  85                          BIT(MDP_SSPP_TOP0_INTR2) | \
  86                          BIT(MDP_SSPP_TOP0_HIST_INTR) | \
  87                          BIT(MDP_INTF0_INTR) | \
  88                          BIT(MDP_INTF1_INTR) | \
  89                          BIT(MDP_INTF2_INTR) | \
  90                          BIT(MDP_INTF3_INTR) | \
  91                          BIT(MDP_INTF4_INTR))
  92
  93
  94 #define DEFAULT_PIXEL_RAM_SIZE          (50 * 1024)
  95 #define DEFAULT_DPU_LINE_WIDTH          2048
  96 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH   2560
  97
  98 #define MAX_HORZ_DECIMATION     4
  99 #define MAX_VERT_DECIMATION     4
 100
 101 #define MAX_UPSCALE_RATIO       20
 102 #define MAX_DOWNSCALE_RATIO     4
 103 #define SSPP_UNITY_SCALE        1
 104
 105 #define STRCAT(X, Y) (X Y)
 106
 107 static const uint32_t plane_formats[] = {
 108         DRM_FORMAT_ARGB8888,
 109         DRM_FORMAT_ABGR8888,
 110         DRM_FORMAT_RGBA8888,
 111         DRM_FORMAT_BGRA8888,
 112         DRM_FORMAT_XRGB8888,
 113         DRM_FORMAT_RGBX8888,
 114         DRM_FORMAT_BGRX8888,
 115         DRM_FORMAT_XBGR8888,
 116         DRM_FORMAT_RGB888,
 117         DRM_FORMAT_BGR888,
 118         DRM_FORMAT_RGB565,
 119         DRM_FORMAT_BGR565,
 120         DRM_FORMAT_ARGB1555,
 121         DRM_FORMAT_ABGR1555,
 122         DRM_FORMAT_RGBA5551,
 123         DRM_FORMAT_BGRA5551,
 124         DRM_FORMAT_XRGB1555,
 125         DRM_FORMAT_XBGR1555,
 126         DRM_FORMAT_RGBX5551,
 127         DRM_FORMAT_BGRX5551,
 128         DRM_FORMAT_ARGB4444,
 129         DRM_FORMAT_ABGR4444,
 130         DRM_FORMAT_RGBA4444,
 131         DRM_FORMAT_BGRA4444,
 132         DRM_FORMAT_XRGB4444,
 133         DRM_FORMAT_XBGR4444,
 134         DRM_FORMAT_RGBX4444,
 135         DRM_FORMAT_BGRX4444,
 136 };
 137
 138 static const uint32_t plane_formats_yuv[] = {
 139         DRM_FORMAT_ARGB8888,
 140         DRM_FORMAT_ABGR8888,
 141         DRM_FORMAT_RGBA8888,
 142         DRM_FORMAT_BGRX8888,
 143         DRM_FORMAT_BGRA8888,
 144         DRM_FORMAT_XRGB8888,
 145         DRM_FORMAT_XBGR8888,
 146         DRM_FORMAT_RGBX8888,
 147         DRM_FORMAT_RGB888,
 148         DRM_FORMAT_BGR888,
 149         DRM_FORMAT_RGB565,
 150         DRM_FORMAT_BGR565,
 151         DRM_FORMAT_ARGB1555,
 152         DRM_FORMAT_ABGR1555,
 153         DRM_FORMAT_RGBA5551,
 154         DRM_FORMAT_BGRA5551,
 155         DRM_FORMAT_XRGB1555,
 156         DRM_FORMAT_XBGR1555,
 157         DRM_FORMAT_RGBX5551,
 158         DRM_FORMAT_BGRX5551,
 159         DRM_FORMAT_ARGB4444,
 160         DRM_FORMAT_ABGR4444,
 161         DRM_FORMAT_RGBA4444,
 162         DRM_FORMAT_BGRA4444,
 163         DRM_FORMAT_XRGB4444,
 164         DRM_FORMAT_XBGR4444,
 165         DRM_FORMAT_RGBX4444,
 166         DRM_FORMAT_BGRX4444,
 167
 168         DRM_FORMAT_NV12,
 169         DRM_FORMAT_NV21,
 170         DRM_FORMAT_NV16,
 171         DRM_FORMAT_NV61,
 172         DRM_FORMAT_VYUY,
 173         DRM_FORMAT_UYVY,
 174         DRM_FORMAT_YUYV,
 175         DRM_FORMAT_YVYU,
 176         DRM_FORMAT_YUV420,
 177         DRM_FORMAT_YVU420,
 178 };
 179
 180 /*************************************************************
 181  * DPU sub blocks config
 182  *************************************************************/
 183 /* DPU top level caps */
 184 static const struct dpu_caps sdm845_dpu_caps = {
 185         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 186         .max_mixer_blendstages = 0xb,
 187         .qseed_type = DPU_SSPP_SCALER_QSEED3,
 188         .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
 189         .ubwc_version = DPU_HW_UBWC_VER_20,
 190         .has_src_split = true,
 191         .has_dim_layer = true,
 192         .has_idle_pc = true,
 193         .has_3d_merge = true,
 194         .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 195         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 196         .max_hdeci_exp = MAX_HORZ_DECIMATION,
 197         .max_vdeci_exp = MAX_VERT_DECIMATION,
 198 };
 199
 200 static const struct dpu_caps sc7180_dpu_caps = {
 201         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 202         .max_mixer_blendstages = 0x9,
 203         .qseed_type = DPU_SSPP_SCALER_QSEED4,
 204         .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
 205         .ubwc_version = DPU_HW_UBWC_VER_20,
 206         .has_dim_layer = true,
 207         .has_idle_pc = true,
 208         .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 209         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 210 };
 211
 212 static const struct dpu_caps sm8150_dpu_caps = {
 213         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 214         .max_mixer_blendstages = 0xb,
 215         .qseed_type = DPU_SSPP_SCALER_QSEED3,
 216         .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
 217         .ubwc_version = DPU_HW_UBWC_VER_30,
 218         .has_src_split = true,
 219         .has_dim_layer = true,
 220         .has_idle_pc = true,
 221         .has_3d_merge = true,
 222         .max_linewidth = 4096,
 223         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 224         .max_hdeci_exp = MAX_HORZ_DECIMATION,
 225         .max_vdeci_exp = MAX_VERT_DECIMATION,
 226 };
 227
 228 static const struct dpu_caps sm8250_dpu_caps = {
 229         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 230         .max_mixer_blendstages = 0xb,
 231         .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
 232         .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
 233         .ubwc_version = DPU_HW_UBWC_VER_40,
 234         .has_src_split = true,
 235         .has_dim_layer = true,
 236         .has_idle_pc = true,
 237         .has_3d_merge = true,
 238         .max_linewidth = 4096,
 239         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 240 };
 241
 242 static const struct dpu_caps sc7280_dpu_caps = {
 243         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 244         .max_mixer_blendstages = 0x7,
 245         .qseed_type = DPU_SSPP_SCALER_QSEED4,
 246         .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
 247         .ubwc_version = DPU_HW_UBWC_VER_30,
 248         .has_dim_layer = true,
 249         .has_idle_pc = true,
 250         .max_linewidth = 2400,
 251         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 252 };
 253
 254 static const struct dpu_mdp_cfg sdm845_mdp[] = {
 255         {
 256         .name = "top_0", .id = MDP_TOP,
 257         .base = 0x0, .len = 0x45C,
 258         .features = 0,
 259         .highest_bank_bit = 0x2,
 260         .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
 261                         .reg_off = 0x2AC, .bit_off = 0},
 262         .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
 263                         .reg_off = 0x2B4, .bit_off = 0},
 264         .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
 265                         .reg_off = 0x2BC, .bit_off = 0},
 266         .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
 267                         .reg_off = 0x2C4, .bit_off = 0},
 268         .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
 269                         .reg_off = 0x2AC, .bit_off = 8},
 270         .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
 271                         .reg_off = 0x2B4, .bit_off = 8},
 272         .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
 273                         .reg_off = 0x2BC, .bit_off = 8},
 274         .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
 275                         .reg_off = 0x2C4, .bit_off = 8},
 276         },
 277 };
 278
 279 static const struct dpu_mdp_cfg sc7180_mdp[] = {
 280         {
 281         .name = "top_0", .id = MDP_TOP,
 282         .base = 0x0, .len = 0x494,
 283         .features = 0,
 284         .highest_bank_bit = 0x3,
 285         .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
 286                 .reg_off = 0x2AC, .bit_off = 0},
 287         .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
 288                 .reg_off = 0x2AC, .bit_off = 8},
 289         .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
 290                 .reg_off = 0x2B4, .bit_off = 8},
 291         .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
 292                 .reg_off = 0x2C4, .bit_off = 8},
 293         },
 294 };
 295
 296 static const struct dpu_mdp_cfg sm8250_mdp[] = {
 297         {
 298         .name = "top_0", .id = MDP_TOP,
 299         .base = 0x0, .len = 0x45C,
 300         .features = 0,
 301         .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
 302         .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
 303                         .reg_off = 0x2AC, .bit_off = 0},
 304         .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
 305                         .reg_off = 0x2B4, .bit_off = 0},
 306         .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
 307                         .reg_off = 0x2BC, .bit_off = 0},
 308         .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
 309                         .reg_off = 0x2C4, .bit_off = 0},
 310         .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
 311                         .reg_off = 0x2AC, .bit_off = 8},
 312         .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
 313                         .reg_off = 0x2B4, .bit_off = 8},
 314         .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
 315                         .reg_off = 0x2BC, .bit_off = 8},
 316         .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
 317                         .reg_off = 0x2C4, .bit_off = 8},
 318         .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
 319                         .reg_off = 0x2BC, .bit_off = 20},
 320         },
 321 };
 322
 323 static const struct dpu_mdp_cfg sc7280_mdp[] = {
 324         {
 325         .name = "top_0", .id = MDP_TOP,
 326         .base = 0x0, .len = 0x2014,
 327         .highest_bank_bit = 0x1,
 328         .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
 329                 .reg_off = 0x2AC, .bit_off = 0},
 330         .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
 331                 .reg_off = 0x2AC, .bit_off = 8},
 332         .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
 333                 .reg_off = 0x2B4, .bit_off = 8},
 334         .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
 335                 .reg_off = 0x2C4, .bit_off = 8},
 336         },
 337 };
 338
 339 /*************************************************************
 340  * CTL sub blocks config
 341  *************************************************************/
 342 static const struct dpu_ctl_cfg sdm845_ctl[] = {
 343         {
 344         .name = "ctl_0", .id = CTL_0,
 345         .base = 0x1000, .len = 0xE4,
 346         .features = BIT(DPU_CTL_SPLIT_DISPLAY),
 347         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 348         },
 349         {
 350         .name = "ctl_1", .id = CTL_1,
 351         .base = 0x1200, .len = 0xE4,
 352         .features = BIT(DPU_CTL_SPLIT_DISPLAY),
 353         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 354         },
 355         {
 356         .name = "ctl_2", .id = CTL_2,
 357         .base = 0x1400, .len = 0xE4,
 358         .features = 0,
 359         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 360         },
 361         {
 362         .name = "ctl_3", .id = CTL_3,
 363         .base = 0x1600, .len = 0xE4,
 364         .features = 0,
 365         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 366         },
 367         {
 368         .name = "ctl_4", .id = CTL_4,
 369         .base = 0x1800, .len = 0xE4,
 370         .features = 0,
 371         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 372         },
 373 };
 374
 375 static const struct dpu_ctl_cfg sc7180_ctl[] = {
 376         {
 377         .name = "ctl_0", .id = CTL_0,
 378         .base = 0x1000, .len = 0xE4,
 379         .features = BIT(DPU_CTL_ACTIVE_CFG),
 380         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 381         },
 382         {
 383         .name = "ctl_1", .id = CTL_1,
 384         .base = 0x1200, .len = 0xE4,
 385         .features = BIT(DPU_CTL_ACTIVE_CFG),
 386         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 387         },
 388         {
 389         .name = "ctl_2", .id = CTL_2,
 390         .base = 0x1400, .len = 0xE4,
 391         .features = BIT(DPU_CTL_ACTIVE_CFG),
 392         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 393         },
 394 };
 395
 396 static const struct dpu_ctl_cfg sm8150_ctl[] = {
 397         {
 398         .name = "ctl_0", .id = CTL_0,
 399         .base = 0x1000, .len = 0x1e0,
 400         .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
 401         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 402         },
 403         {
 404         .name = "ctl_1", .id = CTL_1,
 405         .base = 0x1200, .len = 0x1e0,
 406         .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
 407         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 408         },
 409         {
 410         .name = "ctl_2", .id = CTL_2,
 411         .base = 0x1400, .len = 0x1e0,
 412         .features = BIT(DPU_CTL_ACTIVE_CFG),
 413         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 414         },
 415         {
 416         .name = "ctl_3", .id = CTL_3,
 417         .base = 0x1600, .len = 0x1e0,
 418         .features = BIT(DPU_CTL_ACTIVE_CFG),
 419         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 420         },
 421         {
 422         .name = "ctl_4", .id = CTL_4,
 423         .base = 0x1800, .len = 0x1e0,
 424         .features = BIT(DPU_CTL_ACTIVE_CFG),
 425         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 426         },
 427         {
 428         .name = "ctl_5", .id = CTL_5,
 429         .base = 0x1a00, .len = 0x1e0,
 430         .features = BIT(DPU_CTL_ACTIVE_CFG),
 431         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 432         },
 433 };
 434
 435 static const struct dpu_ctl_cfg sc7280_ctl[] = {
 436         {
 437         .name = "ctl_0", .id = CTL_0,
 438         .base = 0x15000, .len = 0x1E8,
 439         .features = CTL_SC7280_MASK,
 440         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 441         },
 442         {
 443         .name = "ctl_1", .id = CTL_1,
 444         .base = 0x16000, .len = 0x1E8,
 445         .features = CTL_SC7280_MASK,
 446         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 447         },
 448         {
 449         .name = "ctl_2", .id = CTL_2,
 450         .base = 0x17000, .len = 0x1E8,
 451         .features = CTL_SC7280_MASK,
 452         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 453         },
 454         {
 455         .name = "ctl_3", .id = CTL_3,
 456         .base = 0x18000, .len = 0x1E8,
 457         .features = CTL_SC7280_MASK,
 458         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 459         },
 460 };
 461
 462 /*************************************************************
 463  * SSPP sub blocks config
 464  *************************************************************/
 465
 466 /* SSPP common configuration */
 467
 468 #define _VIG_SBLK(num, sdma_pri, qseed_ver) \
 469         { \
 470         .maxdwnscale = MAX_DOWNSCALE_RATIO, \
 471         .maxupscale = MAX_UPSCALE_RATIO, \
 472         .smart_dma_priority = sdma_pri, \
 473         .src_blk = {.name = STRCAT("sspp_src_", num), \
 474                 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
 475         .scaler_blk = {.name = STRCAT("sspp_scaler", num), \
 476                 .id = qseed_ver, \
 477                 .base = 0xa00, .len = 0xa0,}, \
 478         .csc_blk = {.name = STRCAT("sspp_csc", num), \
 479                 .id = DPU_SSPP_CSC_10BIT, \
 480                 .base = 0x1a00, .len = 0x100,}, \
 481         .format_list = plane_formats_yuv, \
 482         .num_formats = ARRAY_SIZE(plane_formats_yuv), \
 483         .virt_format_list = plane_formats, \
 484         .virt_num_formats = ARRAY_SIZE(plane_formats), \
 485         }
 486
 487 #define _DMA_SBLK(num, sdma_pri) \
 488         { \
 489         .maxdwnscale = SSPP_UNITY_SCALE, \
 490         .maxupscale = SSPP_UNITY_SCALE, \
 491         .smart_dma_priority = sdma_pri, \
 492         .src_blk = {.name = STRCAT("sspp_src_", num), \
 493                 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
 494         .format_list = plane_formats, \
 495         .num_formats = ARRAY_SIZE(plane_formats), \
 496         .virt_format_list = plane_formats, \
 497         .virt_num_formats = ARRAY_SIZE(plane_formats), \
 498         }
 499
 500 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
 501                                 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
 502 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
 503                                 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
 504 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
 505                                 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
 506 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
 507                                 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
 508
 509 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
 510 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
 511 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
 512 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
 513
 514 #define SSPP_BLK(_name, _id, _base, _features, \
 515                 _sblk, _xinid, _type, _clkctrl) \
 516         { \
 517         .name = _name, .id = _id, \
 518         .base = _base, .len = 0x1c8, \
 519         .features = _features, \
 520         .sblk = &_sblk, \
 521         .xin_id = _xinid, \
 522         .type = _type, \
 523         .clk_ctrl = _clkctrl \
 524         }
 525
 526 static const struct dpu_sspp_cfg sdm845_sspp[] = {
 527         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
 528                 sdm845_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
 529         SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
 530                 sdm845_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
 531         SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
 532                 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
 533         SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
 534                 sdm845_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
 535         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
 536                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
 537         SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
 538                 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
 539         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
 540                 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
 541         SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_CURSOR_SDM845_MASK,
 542                 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 543 };
 544
 545 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
 546                                 _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
 547
 548 static const struct dpu_sspp_cfg sc7180_sspp[] = {
 549         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
 550                 sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
 551         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
 552                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
 553         SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_CURSOR_SDM845_MASK,
 554                 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
 555         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
 556                 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 557 };
 558
 559 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
 560                                 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
 561 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
 562                                 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
 563 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
 564                                 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
 565 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
 566                                 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
 567
 568 static const struct dpu_sspp_cfg sm8250_sspp[] = {
 569         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
 570                 sm8250_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
 571         SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
 572                 sm8250_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
 573         SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
 574                 sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
 575         SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
 576                 sm8250_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
 577         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
 578                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
 579         SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
 580                 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
 581         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
 582                 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
 583         SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_CURSOR_SDM845_MASK,
 584                 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 585 };
 586
 587 static const struct dpu_sspp_cfg sc7280_sspp[] = {
 588         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
 589                 sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
 590         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
 591                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
 592         SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_CURSOR_SDM845_MASK,
 593                 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
 594         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
 595                 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 596 };
 597
 598 /*************************************************************
 599  * MIXER sub blocks config
 600  *************************************************************/
 601
 602 /* SDM845 */
 603
 604 static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
 605         .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 606         .maxblendstages = 11, /* excluding base layer */
 607         .blendstage_base = { /* offsets relative to mixer base */
 608                 0x20, 0x38, 0x50, 0x68, 0x80, 0x98,
 609                 0xb0, 0xc8, 0xe0, 0xf8, 0x110
 610         },
 611 };
 612
 613 #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
 614         { \
 615         .name = _name, .id = _id, \
 616         .base = _base, .len = 0x320, \
 617         .features = _fmask, \
 618         .sblk = _sblk, \
 619         .pingpong = _pp, \
 620         .lm_pair_mask = (1 << _lmpair), \
 621         .dspp = _dspp \
 622         }
 623
 624 static const struct dpu_lm_cfg sdm845_lm[] = {
 625         LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
 626                 &sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
 627         LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
 628                 &sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
 629         LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
 630                 &sdm845_lm_sblk, PINGPONG_2, LM_5, 0),
 631         LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
 632                 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
 633         LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
 634                 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
 635         LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
 636                 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
 637 };
 638
 639 /* SC7180 */
 640
 641 static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
 642         .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 643         .maxblendstages = 7, /* excluding base layer */
 644         .blendstage_base = { /* offsets relative to mixer base */
 645                 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0
 646         },
 647 };
 648
 649 static const struct dpu_lm_cfg sc7180_lm[] = {
 650         LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
 651                 &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
 652         LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK,
 653                 &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
 654 };
 655
 656 /* SM8150 */
 657
 658 static const struct dpu_lm_cfg sm8150_lm[] = {
 659         LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
 660                 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
 661         LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
 662                 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
 663         LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
 664                 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
 665         LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
 666                 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
 667         LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
 668                 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
 669         LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
 670                 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
 671 };
 672
 673 static const struct dpu_lm_cfg sc7280_lm[] = {
 674         LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
 675                 &sc7180_lm_sblk, PINGPONG_0, 0, 0),
 676         LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
 677                 &sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
 678         LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
 679                 &sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
 680 };
 681
 682 /*************************************************************
 683  * DSPP sub blocks config
 684  *************************************************************/
 685 static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = {
 686         .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
 687                 .len = 0x90, .version = 0x10000},
 688 };
 689
 690 static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
 691         .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
 692                 .len = 0x90, .version = 0x40000},
 693 };
 694
 695 #define DSPP_BLK(_name, _id, _base, _mask, _sblk) \
 696                 {\
 697                 .name = _name, .id = _id, \
 698                 .base = _base, .len = 0x1800, \
 699                 .features = _mask, \
 700                 .sblk = _sblk \
 701                 }
 702
 703 static const struct dpu_dspp_cfg sc7180_dspp[] = {
 704         DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
 705                  &sc7180_dspp_sblk),
 706 };
 707
 708 static const struct dpu_dspp_cfg sm8150_dspp[] = {
 709         DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
 710                  &sm8150_dspp_sblk),
 711         DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
 712                  &sm8150_dspp_sblk),
 713         DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
 714                  &sm8150_dspp_sblk),
 715         DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
 716                  &sm8150_dspp_sblk),
 717 };
 718
 719 /*************************************************************
 720  * PINGPONG sub blocks config
 721  *************************************************************/
 722 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = {
 723         .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0,
 724                 .version = 0x1},
 725         .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
 726                 .len = 0x20, .version = 0x10000},
 727 };
 728
 729 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
 730         .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
 731                 .len = 0x20, .version = 0x10000},
 732 };
 733
 734 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
 735         .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0,
 736         .len = 0x20, .version = 0x20000},
 737 };
 738
 739 #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
 740         {\
 741         .name = _name, .id = _id, \
 742         .base = _base, .len = 0xd4, \
 743         .features = PINGPONG_SDM845_SPLIT_MASK, \
 744         .merge_3d = _merge_3d, \
 745         .sblk = &_sblk, \
 746         .intr_done = _done, \
 747         .intr_rdptr = _rdptr, \
 748         }
 749 #define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
 750         {\
 751         .name = _name, .id = _id, \
 752         .base = _base, .len = 0xd4, \
 753         .features = PINGPONG_SDM845_MASK, \
 754         .merge_3d = _merge_3d, \
 755         .sblk = &_sblk, \
 756         .intr_done = _done, \
 757         .intr_rdptr = _rdptr, \
 758         }
 759
 760 static const struct dpu_pingpong_cfg sdm845_pp[] = {
 761         PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
 762                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
 763                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
 764         PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
 765                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
 766                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
 767         PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
 768                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
 769                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
 770         PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
 771                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
 772                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 773 };
 774
 775 static struct dpu_pingpong_cfg sc7180_pp[] = {
 776         PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
 777         PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
 778 };
 779
 780 static const struct dpu_pingpong_cfg sm8150_pp[] = {
 781         PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
 782                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
 783                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
 784         PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
 785                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
 786                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
 787         PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
 788                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
 789                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
 790         PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
 791                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
 792                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 793         PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
 794                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
 795                         -1),
 796         PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
 797                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
 798                         -1),
 799 };
 800
 801 /*************************************************************
 802  * MERGE_3D sub blocks config
 803  *************************************************************/
 804 #define MERGE_3D_BLK(_name, _id, _base) \
 805         {\
 806         .name = _name, .id = _id, \
 807         .base = _base, .len = 0x100, \
 808         .features = MERGE_3D_SM8150_MASK, \
 809         .sblk = NULL \
 810         }
 811
 812 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
 813         MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
 814         MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
 815         MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
 816 };
 817
 818 static const struct dpu_pingpong_cfg sc7280_pp[] = {
 819         PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
 820         PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
 821         PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
 822         PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
 823 };
 824 /*************************************************************
 825  * INTF sub blocks config
 826  *************************************************************/
 827 #define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
 828         {\
 829         .name = _name, .id = _id, \
 830         .base = _base, .len = 0x280, \
 831         .features = _features, \
 832         .type = _type, \
 833         .controller_id = _ctrl_id, \
 834         .prog_fetch_lines_worst_case = _progfetch, \
 835         .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
 836         .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
 837         }
 838
 839 static const struct dpu_intf_cfg sdm845_intf[] = {
 840         INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
 841         INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
 842         INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
 843         INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 844 };
 845
 846 static const struct dpu_intf_cfg sc7180_intf[] = {
 847         INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
 848         INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
 849 };
 850
 851 static const struct dpu_intf_cfg sm8150_intf[] = {
 852         INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
 853         INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
 854         INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
 855         INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 856 };
 857
 858 static const struct dpu_intf_cfg sc7280_intf[] = {
 859         INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
 860         INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
 861         INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
 862 };
 863
 864 /*************************************************************
 865  * VBIF sub blocks config
 866  *************************************************************/
 867 /* VBIF QOS remap */
 868 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
 869 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
 870
 871 static const struct dpu_vbif_cfg sdm845_vbif[] = {
 872         {
 873         .name = "vbif_0", .id = VBIF_0,
 874         .base = 0, .len = 0x1040,
 875         .features = BIT(DPU_VBIF_QOS_REMAP),
 876         .xin_halt_timeout = 0x4000,
 877         .qos_rt_tbl = {
 878                 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
 879                 .priority_lvl = sdm845_rt_pri_lvl,
 880                 },
 881         .qos_nrt_tbl = {
 882                 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
 883                 .priority_lvl = sdm845_nrt_pri_lvl,
 884                 },
 885         .memtype_count = 14,
 886         .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
 887         },
 888 };
 889
 890 static const struct dpu_reg_dma_cfg sdm845_regdma = {
 891         .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
 892 };
 893
 894 static const struct dpu_reg_dma_cfg sm8150_regdma = {
 895         .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
 896 };
 897
 898 static const struct dpu_reg_dma_cfg sm8250_regdma = {
 899         .base = 0x0,
 900         .version = 0x00010002,
 901         .trigger_sel_off = 0x119c,
 902         .xin_id = 7,
 903         .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
 904 };
 905
 906 /*************************************************************
 907  * PERF data config
 908  *************************************************************/
 909
 910 /* SSPP QOS LUTs */
 911 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
 912         {.fl = 4, .lut = 0x357},
 913         {.fl = 5, .lut = 0x3357},
 914         {.fl = 6, .lut = 0x23357},
 915         {.fl = 7, .lut = 0x223357},
 916         {.fl = 8, .lut = 0x2223357},
 917         {.fl = 9, .lut = 0x22223357},
 918         {.fl = 10, .lut = 0x222223357},
 919         {.fl = 11, .lut = 0x2222223357},
 920         {.fl = 12, .lut = 0x22222223357},
 921         {.fl = 13, .lut = 0x222222223357},
 922         {.fl = 14, .lut = 0x1222222223357},
 923         {.fl = 0, .lut = 0x11222222223357}
 924 };
 925
 926 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
 927         {.fl = 0, .lut = 0x0011222222335777},
 928 };
 929
 930 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
 931         {.fl = 0, .lut = 0x0011222222223357 },
 932 };
 933
 934 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
 935         {.fl = 10, .lut = 0x344556677},
 936         {.fl = 11, .lut = 0x3344556677},
 937         {.fl = 12, .lut = 0x23344556677},
 938         {.fl = 13, .lut = 0x223344556677},
 939         {.fl = 14, .lut = 0x1223344556677},
 940         {.fl = 0, .lut = 0x112233344556677},
 941 };
 942
 943 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
 944         {.fl = 0, .lut = 0x0011223344556677},
 945 };
 946
 947 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
 948         {.fl = 0, .lut = 0x0},
 949 };
 950
 951 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
 952         {.fl = 0, .lut = 0x0},
 953 };
 954
 955 static const struct dpu_perf_cfg sdm845_perf_data = {
 956         .max_bw_low = 6800000,
 957         .max_bw_high = 6800000,
 958         .min_core_ib = 2400000,
 959         .min_llcc_ib = 800000,
 960         .min_dram_ib = 800000,
 961         .core_ib_ff = "6.0",
 962         .core_clk_ff = "1.0",
 963         .comp_ratio_rt =
 964         "NV12/5/1/1.23 AB24/5/1/1.23 XB24/5/1/1.23",
 965         .comp_ratio_nrt =
 966         "NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25",
 967         .undersized_prefill_lines = 2,
 968         .xtra_prefill_lines = 2,
 969         .dest_scale_prefill_lines = 3,
 970         .macrotile_prefill_lines = 4,
 971         .yuv_nv12_prefill_lines = 8,
 972         .linear_prefill_lines = 1,
 973         .downscaling_prefill_lines = 1,
 974         .amortizable_threshold = 25,
 975         .min_prefill_lines = 24,
 976         .danger_lut_tbl = {0xf, 0xffff, 0x0},
 977         .safe_lut_tbl = {0xfff0, 0xf000, 0xffff},
 978         .qos_lut_tbl = {
 979                 {.nentry = ARRAY_SIZE(sdm845_qos_linear),
 980                 .entries = sdm845_qos_linear
 981                 },
 982                 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile),
 983                 .entries = sdm845_qos_macrotile
 984                 },
 985                 {.nentry = ARRAY_SIZE(sdm845_qos_nrt),
 986                 .entries = sdm845_qos_nrt
 987                 },
 988         },
 989         .cdp_cfg = {
 990                 {.rd_enable = 1, .wr_enable = 1},
 991                 {.rd_enable = 1, .wr_enable = 0}
 992         },
 993         .clk_inefficiency_factor = 105,
 994         .bw_inefficiency_factor = 120,
 995 };
 996
 997 static const struct dpu_perf_cfg sc7180_perf_data = {
 998         .max_bw_low = 6800000,
 999         .max_bw_high = 6800000,
1000         .min_core_ib = 2400000,
1001         .min_llcc_ib = 800000,
1002         .min_dram_ib = 1600000,
1003         .min_prefill_lines = 24,
1004         .danger_lut_tbl = {0xff, 0xffff, 0x0},
1005         .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
1006         .qos_lut_tbl = {
1007                 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
1008                 .entries = sc7180_qos_linear
1009                 },
1010                 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1011                 .entries = sc7180_qos_macrotile
1012                 },
1013                 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1014                 .entries = sc7180_qos_nrt
1015                 },
1016         },
1017         .cdp_cfg = {
1018                 {.rd_enable = 1, .wr_enable = 1},
1019                 {.rd_enable = 1, .wr_enable = 0}
1020         },
1021         .clk_inefficiency_factor = 105,
1022         .bw_inefficiency_factor = 120,
1023 };
1024
1025 static const struct dpu_perf_cfg sm8150_perf_data = {
1026         .max_bw_low = 12800000,
1027         .max_bw_high = 12800000,
1028         .min_core_ib = 2400000,
1029         .min_llcc_ib = 800000,
1030         .min_dram_ib = 800000,
1031         .min_prefill_lines = 24,
1032         .danger_lut_tbl = {0xf, 0xffff, 0x0},
1033         .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
1034         .qos_lut_tbl = {
1035                 {.nentry = ARRAY_SIZE(sm8150_qos_linear),
1036                 .entries = sm8150_qos_linear
1037                 },
1038                 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1039                 .entries = sc7180_qos_macrotile
1040                 },
1041                 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1042                 .entries = sc7180_qos_nrt
1043                 },
1044                 /* TODO: macrotile-qseed is different from macrotile */
1045         },
1046         .cdp_cfg = {
1047                 {.rd_enable = 1, .wr_enable = 1},
1048                 {.rd_enable = 1, .wr_enable = 0}
1049         },
1050         .clk_inefficiency_factor = 105,
1051         .bw_inefficiency_factor = 120,
1052 };
1053
1054 static const struct dpu_perf_cfg sm8250_perf_data = {
1055         .max_bw_low = 13700000,
1056         .max_bw_high = 16600000,
1057         .min_core_ib = 4800000,
1058         .min_llcc_ib = 0,
1059         .min_dram_ib = 800000,
1060         .min_prefill_lines = 35,
1061         .danger_lut_tbl = {0xf, 0xffff, 0x0},
1062         .safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
1063         .qos_lut_tbl = {
1064                 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
1065                 .entries = sc7180_qos_linear
1066                 },
1067                 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1068                 .entries = sc7180_qos_macrotile
1069                 },
1070                 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1071                 .entries = sc7180_qos_nrt
1072                 },
1073                 /* TODO: macrotile-qseed is different from macrotile */
1074         },
1075         .cdp_cfg = {
1076                 {.rd_enable = 1, .wr_enable = 1},
1077                 {.rd_enable = 1, .wr_enable = 0}
1078         },
1079         .clk_inefficiency_factor = 105,
1080         .bw_inefficiency_factor = 120,
1081 };
1082
1083 static const struct dpu_perf_cfg sc7280_perf_data = {
1084         .max_bw_low = 4700000,
1085         .max_bw_high = 8800000,
1086         .min_core_ib = 2500000,
1087         .min_llcc_ib = 0,
1088         .min_dram_ib = 1600000,
1089         .min_prefill_lines = 24,
1090         .danger_lut_tbl = {0xffff, 0xffff, 0x0},
1091         .safe_lut_tbl = {0xff00, 0xff00, 0xffff},
1092         .qos_lut_tbl = {
1093                 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1094                 .entries = sc7180_qos_macrotile
1095                 },
1096                 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1097                 .entries = sc7180_qos_macrotile
1098                 },
1099                 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1100                 .entries = sc7180_qos_nrt
1101                 },
1102         },
1103         .cdp_cfg = {
1104                 {.rd_enable = 1, .wr_enable = 1},
1105                 {.rd_enable = 1, .wr_enable = 0}
1106         },
1107         .clk_inefficiency_factor = 105,
1108         .bw_inefficiency_factor = 120,
1109 };
1110
1111 /*************************************************************
1112  * Hardware catalog init
1113  *************************************************************/
1114
1115 /*
1116  * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets
1117  * and instance counts.
1118  */
1119 static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1120 {
1121         *dpu_cfg = (struct dpu_mdss_cfg){
1122                 .caps = &sdm845_dpu_caps,
1123                 .mdp_count = ARRAY_SIZE(sdm845_mdp),
1124                 .mdp = sdm845_mdp,
1125                 .ctl_count = ARRAY_SIZE(sdm845_ctl),
1126                 .ctl = sdm845_ctl,
1127                 .sspp_count = ARRAY_SIZE(sdm845_sspp),
1128                 .sspp = sdm845_sspp,
1129                 .mixer_count = ARRAY_SIZE(sdm845_lm),
1130                 .mixer = sdm845_lm,
1131                 .pingpong_count = ARRAY_SIZE(sdm845_pp),
1132                 .pingpong = sdm845_pp,
1133                 .intf_count = ARRAY_SIZE(sdm845_intf),
1134                 .intf = sdm845_intf,
1135                 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1136                 .vbif = sdm845_vbif,
1137                 .reg_dma_count = 1,
1138                 .dma_cfg = sdm845_regdma,
1139                 .perf = sdm845_perf_data,
1140                 .mdss_irqs = IRQ_SDM845_MASK,
1141         };
1142 }
1143
1144 /*
1145  * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets
1146  * and instance counts.
1147  */
1148 static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1149 {
1150         *dpu_cfg = (struct dpu_mdss_cfg){
1151                 .caps = &sc7180_dpu_caps,
1152                 .mdp_count = ARRAY_SIZE(sc7180_mdp),
1153                 .mdp = sc7180_mdp,
1154                 .ctl_count = ARRAY_SIZE(sc7180_ctl),
1155                 .ctl = sc7180_ctl,
1156                 .sspp_count = ARRAY_SIZE(sc7180_sspp),
1157                 .sspp = sc7180_sspp,
1158                 .mixer_count = ARRAY_SIZE(sc7180_lm),
1159                 .mixer = sc7180_lm,
1160                 .dspp_count = ARRAY_SIZE(sc7180_dspp),
1161                 .dspp = sc7180_dspp,
1162                 .pingpong_count = ARRAY_SIZE(sc7180_pp),
1163                 .pingpong = sc7180_pp,
1164                 .intf_count = ARRAY_SIZE(sc7180_intf),
1165                 .intf = sc7180_intf,
1166                 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1167                 .vbif = sdm845_vbif,
1168                 .reg_dma_count = 1,
1169                 .dma_cfg = sdm845_regdma,
1170                 .perf = sc7180_perf_data,
1171                 .mdss_irqs = IRQ_SC7180_MASK,
1172         };
1173 }
1174
1175 /*
1176  * sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets
1177  * and instance counts.
1178  */
1179 static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1180 {
1181         *dpu_cfg = (struct dpu_mdss_cfg){
1182                 .caps = &sm8150_dpu_caps,
1183                 .mdp_count = ARRAY_SIZE(sdm845_mdp),
1184                 .mdp = sdm845_mdp,
1185                 .ctl_count = ARRAY_SIZE(sm8150_ctl),
1186                 .ctl = sm8150_ctl,
1187                 .sspp_count = ARRAY_SIZE(sdm845_sspp),
1188                 .sspp = sdm845_sspp,
1189                 .mixer_count = ARRAY_SIZE(sm8150_lm),
1190                 .mixer = sm8150_lm,
1191                 .dspp_count = ARRAY_SIZE(sm8150_dspp),
1192                 .dspp = sm8150_dspp,
1193                 .pingpong_count = ARRAY_SIZE(sm8150_pp),
1194                 .pingpong = sm8150_pp,
1195                 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1196                 .merge_3d = sm8150_merge_3d,
1197                 .intf_count = ARRAY_SIZE(sm8150_intf),
1198                 .intf = sm8150_intf,
1199                 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1200                 .vbif = sdm845_vbif,
1201                 .reg_dma_count = 1,
1202                 .dma_cfg = sm8150_regdma,
1203                 .perf = sm8150_perf_data,
1204                 .mdss_irqs = IRQ_SDM845_MASK,
1205         };
1206 }
1207
1208 /*
1209  * sm8250_cfg_init(): populate sm8250 dpu sub-blocks reg offsets
1210  * and instance counts.
1211  */
1212 static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1213 {
1214         *dpu_cfg = (struct dpu_mdss_cfg){
1215                 .caps = &sm8250_dpu_caps,
1216                 .mdp_count = ARRAY_SIZE(sm8250_mdp),
1217                 .mdp = sm8250_mdp,
1218                 .ctl_count = ARRAY_SIZE(sm8150_ctl),
1219                 .ctl = sm8150_ctl,
1220                 .sspp_count = ARRAY_SIZE(sm8250_sspp),
1221                 .sspp = sm8250_sspp,
1222                 .mixer_count = ARRAY_SIZE(sm8150_lm),
1223                 .mixer = sm8150_lm,
1224                 .dspp_count = ARRAY_SIZE(sm8150_dspp),
1225                 .dspp = sm8150_dspp,
1226                 .pingpong_count = ARRAY_SIZE(sm8150_pp),
1227                 .pingpong = sm8150_pp,
1228                 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
1229                 .merge_3d = sm8150_merge_3d,
1230                 .intf_count = ARRAY_SIZE(sm8150_intf),
1231                 .intf = sm8150_intf,
1232                 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1233                 .vbif = sdm845_vbif,
1234                 .reg_dma_count = 1,
1235                 .dma_cfg = sm8250_regdma,
1236                 .perf = sm8250_perf_data,
1237                 .mdss_irqs = IRQ_SM8250_MASK,
1238         };
1239 }
1240
1241 static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1242 {
1243         *dpu_cfg = (struct dpu_mdss_cfg){
1244                 .caps = &sc7280_dpu_caps,
1245                 .mdp_count = ARRAY_SIZE(sc7280_mdp),
1246                 .mdp = sc7280_mdp,
1247                 .ctl_count = ARRAY_SIZE(sc7280_ctl),
1248                 .ctl = sc7280_ctl,
1249                 .sspp_count = ARRAY_SIZE(sc7280_sspp),
1250                 .sspp = sc7280_sspp,
1251                 .mixer_count = ARRAY_SIZE(sc7280_lm),
1252                 .mixer = sc7280_lm,
1253                 .pingpong_count = ARRAY_SIZE(sc7280_pp),
1254                 .pingpong = sc7280_pp,
1255                 .intf_count = ARRAY_SIZE(sc7280_intf),
1256                 .intf = sc7280_intf,
1257                 .vbif_count = ARRAY_SIZE(sdm845_vbif),
1258                 .vbif = sdm845_vbif,
1259                 .perf = sc7280_perf_data,
1260                 .mdss_irqs = IRQ_SC7280_MASK,
1261         };
1262 }
1263
1264 static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
1265         { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
1266         { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
1267         { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init},
1268         { .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
1269         { .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init},
1270         { .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
1271         { .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init},
1272 };
1273
1274 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg)
1275 {
1276         kfree(dpu_cfg);
1277 }
1278
1279 struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
1280 {
1281         int i;
1282         struct dpu_mdss_cfg *dpu_cfg;
1283
1284         dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL);
1285         if (!dpu_cfg)
1286                 return ERR_PTR(-ENOMEM);
1287
1288         for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
1289                 if (cfg_handler[i].hw_rev == hw_rev) {
1290                         cfg_handler[i].cfg_init(dpu_cfg);
1291                         dpu_cfg->hwversion = hw_rev;
1292                         return dpu_cfg;
1293                 }
1294         }
1295
1296         DPU_ERROR("unsupported chipset id:%X\n", hw_rev);
1297         dpu_hw_catalog_deinit(dpu_cfg);
1298         return ERR_PTR(-ENODEV);
1299 }
1300