drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   9 #include <linux/debugfs.h>
  10 #include <linux/kthread.h>
  11 #include <linux/seq_file.h>
  12
  13 #include <drm/drm_crtc.h>
  14 #include <drm/drm_file.h>
  15 #include <drm/drm_probe_helper.h>
  16
  17 #include "msm_drv.h"
  18 #include "dpu_kms.h"
  19 #include "dpu_hwio.h"
  20 #include "dpu_hw_catalog.h"
  21 #include "dpu_hw_intf.h"
  22 #include "dpu_hw_ctl.h"
  23 #include "dpu_hw_dspp.h"
  24 #include "dpu_formats.h"
  25 #include "dpu_encoder_phys.h"
  26 #include "dpu_crtc.h"
  27 #include "dpu_trace.h"
  28 #include "dpu_core_irq.h"
  29 #include "disp/msm_disp_snapshot.h"
  30
  31 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
  32                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  33
  34 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
  35                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  36
  37 #define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\
  38                 (p) ? (p)->parent->base.id : -1, \
  39                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  40                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  41                 ##__VA_ARGS__)
  42
  43 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
  44                 (p) ? (p)->parent->base.id : -1, \
  45                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  46                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  47                 ##__VA_ARGS__)
  48
  49 /*
  50  * Two to anticipate panels that can do cmd/vid dynamic switching
  51  * plan is to create all possible physical encoder types, and switch between
  52  * them at runtime
  53  */
  54 #define NUM_PHYS_ENCODER_TYPES 2
  55
  56 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
  57         (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
  58
  59 #define MAX_CHANNELS_PER_ENC 2
  60
  61 #define IDLE_SHORT_TIMEOUT      1
  62
  63 #define MAX_HDISPLAY_SPLIT 1080
  64
  65 /* timeout in frames waiting for frame done */
  66 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
  67
  68 /**
  69  * enum dpu_enc_rc_events - events for resource control state machine
  70  * @DPU_ENC_RC_EVENT_KICKOFF:
  71  *      This event happens at NORMAL priority.
  72  *      Event that signals the start of the transfer. When this event is
  73  *      received, enable MDP/DSI core clocks. Regardless of the previous
  74  *      state, the resource should be in ON state at the end of this event.
  75  * @DPU_ENC_RC_EVENT_FRAME_DONE:
  76  *      This event happens at INTERRUPT level.
  77  *      Event signals the end of the data transfer after the PP FRAME_DONE
  78  *      event. At the end of this event, a delayed work is scheduled to go to
  79  *      IDLE_PC state after IDLE_TIMEOUT time.
  80  * @DPU_ENC_RC_EVENT_PRE_STOP:
  81  *      This event happens at NORMAL priority.
  82  *      This event, when received during the ON state, leave the RC STATE
  83  *      in the PRE_OFF state. It should be followed by the STOP event as
  84  *      part of encoder disable.
  85  *      If received during IDLE or OFF states, it will do nothing.
  86  * @DPU_ENC_RC_EVENT_STOP:
  87  *      This event happens at NORMAL priority.
  88  *      When this event is received, disable all the MDP/DSI core clocks, and
  89  *      disable IRQs. It should be called from the PRE_OFF or IDLE states.
  90  *      IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  91  *      PRE_OFF is expected when PRE_STOP was executed during the ON state.
  92  *      Resource state should be in OFF at the end of the event.
  93  * @DPU_ENC_RC_EVENT_ENTER_IDLE:
  94  *      This event happens at NORMAL priority from a work item.
  95  *      Event signals that there were no frame updates for IDLE_TIMEOUT time.
  96  *      This would disable MDP/DSI core clocks and change the resource state
  97  *      to IDLE.
  98  */
  99 enum dpu_enc_rc_events {
 100         DPU_ENC_RC_EVENT_KICKOFF = 1,
 101         DPU_ENC_RC_EVENT_FRAME_DONE,
 102         DPU_ENC_RC_EVENT_PRE_STOP,
 103         DPU_ENC_RC_EVENT_STOP,
 104         DPU_ENC_RC_EVENT_ENTER_IDLE
 105 };
 106
 107 /*
 108  * enum dpu_enc_rc_states - states that the resource control maintains
 109  * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
 110  * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
 111  * @DPU_ENC_RC_STATE_ON: Resource is in ON state
 112  * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
 113  * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
 114  */
 115 enum dpu_enc_rc_states {
 116         DPU_ENC_RC_STATE_OFF,
 117         DPU_ENC_RC_STATE_PRE_OFF,
 118         DPU_ENC_RC_STATE_ON,
 119         DPU_ENC_RC_STATE_IDLE
 120 };
 121
 122 /**
 123  * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
 124  *      encoders. Virtual encoder manages one "logical" display. Physical
 125  *      encoders manage one intf block, tied to a specific panel/sub-panel.
 126  *      Virtual encoder defers as much as possible to the physical encoders.
 127  *      Virtual encoder registers itself with the DRM Framework as the encoder.
 128  * @base:               drm_encoder base class for registration with DRM
 129  * @enc_spinlock:       Virtual-Encoder-Wide Spin Lock for IRQ purposes
 130  * @bus_scaling_client: Client handle to the bus scaling interface
 131  * @enabled:            True if the encoder is active, protected by enc_lock
 132  * @num_phys_encs:      Actual number of physical encoders contained.
 133  * @phys_encs:          Container of physical encoders managed.
 134  * @cur_master:         Pointer to the current master in this mode. Optimization
 135  *                      Only valid after enable. Cleared as disable.
 136  * @cur_slave:          As above but for the slave encoder.
 137  * @hw_pp:              Handle to the pingpong blocks used for the display. No.
 138  *                      pingpong blocks can be different than num_phys_encs.
 139  * @intfs_swapped:      Whether or not the phys_enc interfaces have been swapped
 140  *                      for partial update right-only cases, such as pingpong
 141  *                      split where virtual pingpong does not generate IRQs
 142  * @crtc:               Pointer to the currently assigned crtc. Normally you
 143  *                      would use crtc->state->encoder_mask to determine the
 144  *                      link between encoder/crtc. However in this case we need
 145  *                      to track crtc in the disable() hook which is called
 146  *                      _after_ encoder_mask is cleared.
 147  * @crtc_kickoff_cb:            Callback into CRTC that will flush & start
 148  *                              all CTL paths
 149  * @crtc_kickoff_cb_data:       Opaque user data given to crtc_kickoff_cb
 150  * @debugfs_root:               Debug file system root file node
 151  * @enc_lock:                   Lock around physical encoder
 152  *                              create/destroy/enable/disable
 153  * @frame_busy_mask:            Bitmask tracking which phys_enc we are still
 154  *                              busy processing current command.
 155  *                              Bit0 = phys_encs[0] etc.
 156  * @crtc_frame_event_cb:        callback handler for frame event
 157  * @crtc_frame_event_cb_data:   callback handler private data
 158  * @frame_done_timeout_ms:      frame done timeout in ms
 159  * @frame_done_timer:           watchdog timer for frame done event
 160  * @vsync_event_timer:          vsync timer
 161  * @disp_info:                  local copy of msm_display_info struct
 162  * @idle_pc_supported:          indicate if idle power collaps is supported
 163  * @rc_lock:                    resource control mutex lock to protect
 164  *                              virt encoder over various state changes
 165  * @rc_state:                   resource controller state
 166  * @delayed_off_work:           delayed worker to schedule disabling of
 167  *                              clks and resources after IDLE_TIMEOUT time.
 168  * @vsync_event_work:           worker to handle vsync event for autorefresh
 169  * @topology:                   topology of the display
 170  * @idle_timeout:               idle timeout duration in milliseconds
 171  */
 172 struct dpu_encoder_virt {
 173         struct drm_encoder base;
 174         spinlock_t enc_spinlock;
 175         uint32_t bus_scaling_client;
 176
 177         bool enabled;
 178
 179         unsigned int num_phys_encs;
 180         struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
 181         struct dpu_encoder_phys *cur_master;
 182         struct dpu_encoder_phys *cur_slave;
 183         struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
 184
 185         bool intfs_swapped;
 186
 187         struct drm_crtc *crtc;
 188
 189         struct dentry *debugfs_root;
 190         struct mutex enc_lock;
 191         DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
 192         void (*crtc_frame_event_cb)(void *, u32 event);
 193         void *crtc_frame_event_cb_data;
 194
 195         atomic_t frame_done_timeout_ms;
 196         struct timer_list frame_done_timer;
 197         struct timer_list vsync_event_timer;
 198
 199         struct msm_display_info disp_info;
 200
 201         bool idle_pc_supported;
 202         struct mutex rc_lock;
 203         enum dpu_enc_rc_states rc_state;
 204         struct delayed_work delayed_off_work;
 205         struct kthread_work vsync_event_work;
 206         struct msm_display_topology topology;
 207
 208         u32 idle_timeout;
 209 };
 210
 211 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 212
 213 static u32 dither_matrix[DITHER_MATRIX_SZ] = {
 214         15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 215 };
 216
 217 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
 218 {
 219         struct dpu_hw_dither_cfg dither_cfg = { 0 };
 220
 221         if (!hw_pp->ops.setup_dither)
 222                 return;
 223
 224         switch (bpc) {
 225         case 6:
 226                 dither_cfg.c0_bitdepth = 6;
 227                 dither_cfg.c1_bitdepth = 6;
 228                 dither_cfg.c2_bitdepth = 6;
 229                 dither_cfg.c3_bitdepth = 6;
 230                 dither_cfg.temporal_en = 0;
 231                 break;
 232         default:
 233                 hw_pp->ops.setup_dither(hw_pp, NULL);
 234                 return;
 235         }
 236
 237         memcpy(&dither_cfg.matrix, dither_matrix,
 238                         sizeof(u32) * DITHER_MATRIX_SZ);
 239
 240         hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
 241 }
 242
 243 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
 244                 enum dpu_intr_idx intr_idx)
 245 {
 246         DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
 247                   DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
 248                   phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
 249
 250         if (phys_enc->parent_ops->handle_frame_done)
 251                 phys_enc->parent_ops->handle_frame_done(
 252                                 phys_enc->parent, phys_enc,
 253                                 DPU_ENCODER_FRAME_EVENT_ERROR);
 254 }
 255
 256 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
 257                 u32 irq_idx, struct dpu_encoder_wait_info *info);
 258
 259 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 260                 enum dpu_intr_idx intr_idx,
 261                 struct dpu_encoder_wait_info *wait_info)
 262 {
 263         struct dpu_encoder_irq *irq;
 264         u32 irq_status;
 265         int ret;
 266
 267         if (!wait_info || intr_idx >= INTR_IDX_MAX) {
 268                 DPU_ERROR("invalid params\n");
 269                 return -EINVAL;
 270         }
 271         irq = &phys_enc->irq[intr_idx];
 272
 273         /* note: do master / slave checking outside */
 274
 275         /* return EWOULDBLOCK since we know the wait isn't necessary */
 276         if (phys_enc->enable_state == DPU_ENC_DISABLED) {
 277                 DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d\n",
 278                           DRMID(phys_enc->parent), intr_idx,
 279                           irq->irq_idx);
 280                 return -EWOULDBLOCK;
 281         }
 282
 283         if (irq->irq_idx < 0) {
 284                 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s\n",
 285                               DRMID(phys_enc->parent), intr_idx,
 286                               irq->name);
 287                 return 0;
 288         }
 289
 290         DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d\n",
 291                       DRMID(phys_enc->parent), intr_idx,
 292                       irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
 293                       atomic_read(wait_info->atomic_cnt));
 294
 295         ret = dpu_encoder_helper_wait_event_timeout(
 296                         DRMID(phys_enc->parent),
 297                         irq->irq_idx,
 298                         wait_info);
 299
 300         if (ret <= 0) {
 301                 irq_status = dpu_core_irq_read(phys_enc->dpu_kms,
 302                                 irq->irq_idx, true);
 303                 if (irq_status) {
 304                         unsigned long flags;
 305
 306                         DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d\n",
 307                                       DRMID(phys_enc->parent), intr_idx,
 308                                       irq->irq_idx,
 309                                       phys_enc->hw_pp->idx - PINGPONG_0,
 310                                       atomic_read(wait_info->atomic_cnt));
 311                         local_irq_save(flags);
 312                         irq->cb.func(phys_enc, irq->irq_idx);
 313                         local_irq_restore(flags);
 314                         ret = 0;
 315                 } else {
 316                         ret = -ETIMEDOUT;
 317                         DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d\n",
 318                                       DRMID(phys_enc->parent), intr_idx,
 319                                       irq->irq_idx,
 320                                       phys_enc->hw_pp->idx - PINGPONG_0,
 321                                       atomic_read(wait_info->atomic_cnt));
 322                 }
 323         } else {
 324                 ret = 0;
 325                 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
 326                         intr_idx, irq->irq_idx,
 327                         phys_enc->hw_pp->idx - PINGPONG_0,
 328                         atomic_read(wait_info->atomic_cnt));
 329         }
 330
 331         return ret;
 332 }
 333
 334 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 335                 enum dpu_intr_idx intr_idx)
 336 {
 337         struct dpu_encoder_irq *irq;
 338         int ret = 0;
 339
 340         if (intr_idx >= INTR_IDX_MAX) {
 341                 DPU_ERROR("invalid params\n");
 342                 return -EINVAL;
 343         }
 344         irq = &phys_enc->irq[intr_idx];
 345
 346         if (irq->irq_idx < 0) {
 347                 DPU_ERROR_PHYS(phys_enc,
 348                         "invalid IRQ index:%d\n", irq->irq_idx);
 349                 return -EINVAL;
 350         }
 351
 352         ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx,
 353                         &irq->cb);
 354         if (ret) {
 355                 DPU_ERROR_PHYS(phys_enc,
 356                         "failed to register IRQ callback for %s\n",
 357                         irq->name);
 358                 irq->irq_idx = -EINVAL;
 359                 return ret;
 360         }
 361
 362         trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
 363                                 irq->irq_idx);
 364
 365         return ret;
 366 }
 367
 368 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
 369                 enum dpu_intr_idx intr_idx)
 370 {
 371         struct dpu_encoder_irq *irq;
 372         int ret;
 373
 374         irq = &phys_enc->irq[intr_idx];
 375
 376         /* silently skip irqs that weren't registered */
 377         if (irq->irq_idx < 0) {
 378                 DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d",
 379                           DRMID(phys_enc->parent), intr_idx,
 380                           irq->irq_idx);
 381                 return 0;
 382         }
 383
 384         ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
 385                         &irq->cb);
 386         if (ret) {
 387                 DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d",
 388                           DRMID(phys_enc->parent), intr_idx,
 389                           irq->irq_idx, ret);
 390         }
 391
 392         trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
 393                                              irq->irq_idx);
 394
 395         return 0;
 396 }
 397
 398 int dpu_encoder_get_frame_count(struct drm_encoder *drm_enc)
 399 {
 400         struct dpu_encoder_virt *dpu_enc;
 401         struct dpu_encoder_phys *phys;
 402         int framecount = 0;
 403
 404         dpu_enc = to_dpu_encoder_virt(drm_enc);
 405         phys = dpu_enc ? dpu_enc->cur_master : NULL;
 406
 407         if (phys && phys->ops.get_frame_count)
 408                 framecount = phys->ops.get_frame_count(phys);
 409
 410         return framecount;
 411 }
 412
 413 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
 414 {
 415         struct dpu_encoder_virt *dpu_enc;
 416         struct dpu_encoder_phys *phys;
 417         int linecount = 0;
 418
 419         dpu_enc = to_dpu_encoder_virt(drm_enc);
 420         phys = dpu_enc ? dpu_enc->cur_master : NULL;
 421
 422         if (phys && phys->ops.get_line_count)
 423                 linecount = phys->ops.get_line_count(phys);
 424
 425         return linecount;
 426 }
 427
 428 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 429                                   struct dpu_encoder_hw_resources *hw_res)
 430 {
 431         struct dpu_encoder_virt *dpu_enc = NULL;
 432         int i = 0;
 433
 434         dpu_enc = to_dpu_encoder_virt(drm_enc);
 435         DPU_DEBUG_ENC(dpu_enc, "\n");
 436
 437         /* Query resources used by phys encs, expected to be without overlap */
 438         memset(hw_res, 0, sizeof(*hw_res));
 439
 440         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 441                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 442
 443                 if (phys->ops.get_hw_resources)
 444                         phys->ops.get_hw_resources(phys, hw_res);
 445         }
 446 }
 447
 448 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
 449 {
 450         struct dpu_encoder_virt *dpu_enc = NULL;
 451         int i = 0;
 452
 453         if (!drm_enc) {
 454                 DPU_ERROR("invalid encoder\n");
 455                 return;
 456         }
 457
 458         dpu_enc = to_dpu_encoder_virt(drm_enc);
 459         DPU_DEBUG_ENC(dpu_enc, "\n");
 460
 461         mutex_lock(&dpu_enc->enc_lock);
 462
 463         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 464                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 465
 466                 if (phys->ops.destroy) {
 467                         phys->ops.destroy(phys);
 468                         --dpu_enc->num_phys_encs;
 469                         dpu_enc->phys_encs[i] = NULL;
 470                 }
 471         }
 472
 473         if (dpu_enc->num_phys_encs)
 474                 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
 475                                 dpu_enc->num_phys_encs);
 476         dpu_enc->num_phys_encs = 0;
 477         mutex_unlock(&dpu_enc->enc_lock);
 478
 479         drm_encoder_cleanup(drm_enc);
 480         mutex_destroy(&dpu_enc->enc_lock);
 481 }
 482
 483 void dpu_encoder_helper_split_config(
 484                 struct dpu_encoder_phys *phys_enc,
 485                 enum dpu_intf interface)
 486 {
 487         struct dpu_encoder_virt *dpu_enc;
 488         struct split_pipe_cfg cfg = { 0 };
 489         struct dpu_hw_mdp *hw_mdptop;
 490         struct msm_display_info *disp_info;
 491
 492         if (!phys_enc->hw_mdptop || !phys_enc->parent) {
 493                 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
 494                 return;
 495         }
 496
 497         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
 498         hw_mdptop = phys_enc->hw_mdptop;
 499         disp_info = &dpu_enc->disp_info;
 500
 501         if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
 502                 return;
 503
 504         /**
 505          * disable split modes since encoder will be operating in as the only
 506          * encoder, either for the entire use case in the case of, for example,
 507          * single DSI, or for this frame in the case of left/right only partial
 508          * update.
 509          */
 510         if (phys_enc->split_role == ENC_ROLE_SOLO) {
 511                 if (hw_mdptop->ops.setup_split_pipe)
 512                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 513                 return;
 514         }
 515
 516         cfg.en = true;
 517         cfg.mode = phys_enc->intf_mode;
 518         cfg.intf = interface;
 519
 520         if (cfg.en && phys_enc->ops.needs_single_flush &&
 521                         phys_enc->ops.needs_single_flush(phys_enc))
 522                 cfg.split_flush_en = true;
 523
 524         if (phys_enc->split_role == ENC_ROLE_MASTER) {
 525                 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
 526
 527                 if (hw_mdptop->ops.setup_split_pipe)
 528                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 529         }
 530 }
 531
 532 static struct msm_display_topology dpu_encoder_get_topology(
 533                         struct dpu_encoder_virt *dpu_enc,
 534                         struct dpu_kms *dpu_kms,
 535                         struct drm_display_mode *mode)
 536 {
 537         struct msm_display_topology topology = {0};
 538         int i, intf_count = 0;
 539
 540         for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
 541                 if (dpu_enc->phys_encs[i])
 542                         intf_count++;
 543
 544         /* Datapath topology selection
 545          *
 546          * Dual display
 547          * 2 LM, 2 INTF ( Split display using 2 interfaces)
 548          *
 549          * Single display
 550          * 1 LM, 1 INTF
 551          * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
 552          *
 553          * Adding color blocks only to primary interface if available in
 554          * sufficient number
 555          */
 556         if (intf_count == 2)
 557                 topology.num_lm = 2;
 558         else if (!dpu_kms->catalog->caps->has_3d_merge)
 559                 topology.num_lm = 1;
 560         else
 561                 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 562
 563         if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
 564                 if (dpu_kms->catalog->dspp &&
 565                         (dpu_kms->catalog->dspp_count >= topology.num_lm))
 566                         topology.num_dspp = topology.num_lm;
 567         }
 568
 569         topology.num_enc = 0;
 570         topology.num_intf = intf_count;
 571
 572         return topology;
 573 }
 574 static int dpu_encoder_virt_atomic_check(
 575                 struct drm_encoder *drm_enc,
 576                 struct drm_crtc_state *crtc_state,
 577                 struct drm_connector_state *conn_state)
 578 {
 579         struct dpu_encoder_virt *dpu_enc;
 580         struct msm_drm_private *priv;
 581         struct dpu_kms *dpu_kms;
 582         const struct drm_display_mode *mode;
 583         struct drm_display_mode *adj_mode;
 584         struct msm_display_topology topology;
 585         struct dpu_global_state *global_state;
 586         int i = 0;
 587         int ret = 0;
 588
 589         if (!drm_enc || !crtc_state || !conn_state) {
 590                 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
 591                                 drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
 592                 return -EINVAL;
 593         }
 594
 595         dpu_enc = to_dpu_encoder_virt(drm_enc);
 596         DPU_DEBUG_ENC(dpu_enc, "\n");
 597
 598         priv = drm_enc->dev->dev_private;
 599         dpu_kms = to_dpu_kms(priv->kms);
 600         mode = &crtc_state->mode;
 601         adj_mode = &crtc_state->adjusted_mode;
 602         global_state = dpu_kms_get_global_state(crtc_state->state);
 603         if (IS_ERR(global_state))
 604                 return PTR_ERR(global_state);
 605
 606         trace_dpu_enc_atomic_check(DRMID(drm_enc));
 607
 608         /* perform atomic check on the first physical encoder (master) */
 609         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 610                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 611
 612                 if (phys->ops.atomic_check)
 613                         ret = phys->ops.atomic_check(phys, crtc_state,
 614                                         conn_state);
 615                 else if (phys->ops.mode_fixup)
 616                         if (!phys->ops.mode_fixup(phys, mode, adj_mode))
 617                                 ret = -EINVAL;
 618
 619                 if (ret) {
 620                         DPU_ERROR_ENC(dpu_enc,
 621                                         "mode unsupported, phys idx %d\n", i);
 622                         break;
 623                 }
 624         }
 625
 626         topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 627
 628         /* Reserve dynamic resources now. */
 629         if (!ret) {
 630                 /*
 631                  * Release and Allocate resources on every modeset
 632                  * Dont allocate when active is false.
 633                  */
 634                 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
 635                         dpu_rm_release(global_state, drm_enc);
 636
 637                         if (!crtc_state->active_changed || crtc_state->active)
 638                                 ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
 639                                                 drm_enc, crtc_state, topology);
 640                 }
 641         }
 642
 643         trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
 644
 645         return ret;
 646 }
 647
 648 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
 649                         struct msm_display_info *disp_info)
 650 {
 651         struct dpu_vsync_source_cfg vsync_cfg = { 0 };
 652         struct msm_drm_private *priv;
 653         struct dpu_kms *dpu_kms;
 654         struct dpu_hw_mdp *hw_mdptop;
 655         struct drm_encoder *drm_enc;
 656         int i;
 657
 658         if (!dpu_enc || !disp_info) {
 659                 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
 660                                         dpu_enc != NULL, disp_info != NULL);
 661                 return;
 662         } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
 663                 DPU_ERROR("invalid num phys enc %d/%d\n",
 664                                 dpu_enc->num_phys_encs,
 665                                 (int) ARRAY_SIZE(dpu_enc->hw_pp));
 666                 return;
 667         }
 668
 669         drm_enc = &dpu_enc->base;
 670         /* this pointers are checked in virt_enable_helper */
 671         priv = drm_enc->dev->dev_private;
 672
 673         dpu_kms = to_dpu_kms(priv->kms);
 674         hw_mdptop = dpu_kms->hw_mdp;
 675         if (!hw_mdptop) {
 676                 DPU_ERROR("invalid mdptop\n");
 677                 return;
 678         }
 679
 680         if (hw_mdptop->ops.setup_vsync_source &&
 681                         disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
 682                 for (i = 0; i < dpu_enc->num_phys_encs; i++)
 683                         vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
 684
 685                 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
 686                 if (disp_info->is_te_using_watchdog_timer)
 687                         vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
 688                 else
 689                         vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
 690
 691                 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
 692         }
 693 }
 694
 695 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
 696 {
 697         struct dpu_encoder_virt *dpu_enc;
 698         int i;
 699
 700         if (!drm_enc) {
 701                 DPU_ERROR("invalid encoder\n");
 702                 return;
 703         }
 704
 705         dpu_enc = to_dpu_encoder_virt(drm_enc);
 706
 707         DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
 708         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 709                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 710
 711                 if (phys->ops.irq_control)
 712                         phys->ops.irq_control(phys, enable);
 713         }
 714
 715 }
 716
 717 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 718                 bool enable)
 719 {
 720         struct msm_drm_private *priv;
 721         struct dpu_kms *dpu_kms;
 722         struct dpu_encoder_virt *dpu_enc;
 723
 724         dpu_enc = to_dpu_encoder_virt(drm_enc);
 725         priv = drm_enc->dev->dev_private;
 726         dpu_kms = to_dpu_kms(priv->kms);
 727
 728         trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
 729
 730         if (!dpu_enc->cur_master) {
 731                 DPU_ERROR("encoder master not set\n");
 732                 return;
 733         }
 734
 735         if (enable) {
 736                 /* enable DPU core clks */
 737                 pm_runtime_get_sync(&dpu_kms->pdev->dev);
 738
 739                 /* enable all the irq */
 740                 _dpu_encoder_irq_control(drm_enc, true);
 741
 742         } else {
 743                 /* disable all the irq */
 744                 _dpu_encoder_irq_control(drm_enc, false);
 745
 746                 /* disable DPU core clks */
 747                 pm_runtime_put_sync(&dpu_kms->pdev->dev);
 748         }
 749
 750 }
 751
 752 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 753                 u32 sw_event)
 754 {
 755         struct dpu_encoder_virt *dpu_enc;
 756         struct msm_drm_private *priv;
 757         bool is_vid_mode = false;
 758
 759         if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
 760                 DPU_ERROR("invalid parameters\n");
 761                 return -EINVAL;
 762         }
 763         dpu_enc = to_dpu_encoder_virt(drm_enc);
 764         priv = drm_enc->dev->dev_private;
 765         is_vid_mode = dpu_enc->disp_info.capabilities &
 766                                                 MSM_DISPLAY_CAP_VID_MODE;
 767
 768         /*
 769          * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
 770          * events and return early for other events (ie wb display).
 771          */
 772         if (!dpu_enc->idle_pc_supported &&
 773                         (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
 774                         sw_event != DPU_ENC_RC_EVENT_STOP &&
 775                         sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
 776                 return 0;
 777
 778         trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
 779                          dpu_enc->rc_state, "begin");
 780
 781         switch (sw_event) {
 782         case DPU_ENC_RC_EVENT_KICKOFF:
 783                 /* cancel delayed off work, if any */
 784                 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 785                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 786                                         sw_event);
 787
 788                 mutex_lock(&dpu_enc->rc_lock);
 789
 790                 /* return if the resource control is already in ON state */
 791                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 792                         DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
 793                                       DRMID(drm_enc), sw_event);
 794                         mutex_unlock(&dpu_enc->rc_lock);
 795                         return 0;
 796                 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
 797                                 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
 798                         DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
 799                                       DRMID(drm_enc), sw_event,
 800                                       dpu_enc->rc_state);
 801                         mutex_unlock(&dpu_enc->rc_lock);
 802                         return -EINVAL;
 803                 }
 804
 805                 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
 806                         _dpu_encoder_irq_control(drm_enc, true);
 807                 else
 808                         _dpu_encoder_resource_control_helper(drm_enc, true);
 809
 810                 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
 811
 812                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 813                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 814                                  "kickoff");
 815
 816                 mutex_unlock(&dpu_enc->rc_lock);
 817                 break;
 818
 819         case DPU_ENC_RC_EVENT_FRAME_DONE:
 820                 /*
 821                  * mutex lock is not used as this event happens at interrupt
 822                  * context. And locking is not required as, the other events
 823                  * like KICKOFF and STOP does a wait-for-idle before executing
 824                  * the resource_control
 825                  */
 826                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 827                         DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
 828                                       DRMID(drm_enc), sw_event,
 829                                       dpu_enc->rc_state);
 830                         return -EINVAL;
 831                 }
 832
 833                 /*
 834                  * schedule off work item only when there are no
 835                  * frames pending
 836                  */
 837                 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
 838                         DRM_DEBUG_KMS("id:%d skip schedule work\n",
 839                                       DRMID(drm_enc));
 840                         return 0;
 841                 }
 842
 843                 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
 844                                    msecs_to_jiffies(dpu_enc->idle_timeout));
 845
 846                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 847                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 848                                  "frame done");
 849                 break;
 850
 851         case DPU_ENC_RC_EVENT_PRE_STOP:
 852                 /* cancel delayed off work, if any */
 853                 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 854                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 855                                         sw_event);
 856
 857                 mutex_lock(&dpu_enc->rc_lock);
 858
 859                 if (is_vid_mode &&
 860                           dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 861                         _dpu_encoder_irq_control(drm_enc, true);
 862                 }
 863                 /* skip if is already OFF or IDLE, resources are off already */
 864                 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
 865                                 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 866                         DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
 867                                       DRMID(drm_enc), sw_event,
 868                                       dpu_enc->rc_state);
 869                         mutex_unlock(&dpu_enc->rc_lock);
 870                         return 0;
 871                 }
 872
 873                 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
 874
 875                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 876                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 877                                  "pre stop");
 878
 879                 mutex_unlock(&dpu_enc->rc_lock);
 880                 break;
 881
 882         case DPU_ENC_RC_EVENT_STOP:
 883                 mutex_lock(&dpu_enc->rc_lock);
 884
 885                 /* return if the resource control is already in OFF state */
 886                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
 887                         DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
 888                                       DRMID(drm_enc), sw_event);
 889                         mutex_unlock(&dpu_enc->rc_lock);
 890                         return 0;
 891                 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 892                         DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
 893                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 894                         mutex_unlock(&dpu_enc->rc_lock);
 895                         return -EINVAL;
 896                 }
 897
 898                 /**
 899                  * expect to arrive here only if in either idle state or pre-off
 900                  * and in IDLE state the resources are already disabled
 901                  */
 902                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
 903                         _dpu_encoder_resource_control_helper(drm_enc, false);
 904
 905                 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
 906
 907                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 908                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 909                                  "stop");
 910
 911                 mutex_unlock(&dpu_enc->rc_lock);
 912                 break;
 913
 914         case DPU_ENC_RC_EVENT_ENTER_IDLE:
 915                 mutex_lock(&dpu_enc->rc_lock);
 916
 917                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 918                         DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
 919                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 920                         mutex_unlock(&dpu_enc->rc_lock);
 921                         return 0;
 922                 }
 923
 924                 /*
 925                  * if we are in ON but a frame was just kicked off,
 926                  * ignore the IDLE event, it's probably a stale timer event
 927                  */
 928                 if (dpu_enc->frame_busy_mask[0]) {
 929                         DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
 930                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 931                         mutex_unlock(&dpu_enc->rc_lock);
 932                         return 0;
 933                 }
 934
 935                 if (is_vid_mode)
 936                         _dpu_encoder_irq_control(drm_enc, false);
 937                 else
 938                         _dpu_encoder_resource_control_helper(drm_enc, false);
 939
 940                 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
 941
 942                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 943                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 944                                  "idle");
 945
 946                 mutex_unlock(&dpu_enc->rc_lock);
 947                 break;
 948
 949         default:
 950                 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
 951                           sw_event);
 952                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 953                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 954                                  "error");
 955                 break;
 956         }
 957
 958         trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 959                          dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 960                          "end");
 961         return 0;
 962 }
 963
 964 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 965                                       struct drm_display_mode *mode,
 966                                       struct drm_display_mode *adj_mode)
 967 {
 968         struct dpu_encoder_virt *dpu_enc;
 969         struct msm_drm_private *priv;
 970         struct dpu_kms *dpu_kms;
 971         struct list_head *connector_list;
 972         struct drm_connector *conn = NULL, *conn_iter;
 973         struct drm_crtc *drm_crtc;
 974         struct dpu_crtc_state *cstate;
 975         struct dpu_global_state *global_state;
 976         struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
 977         struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
 978         struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
 979         struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
 980         int num_lm, num_ctl, num_pp;
 981         int i, j;
 982
 983         if (!drm_enc) {
 984                 DPU_ERROR("invalid encoder\n");
 985                 return;
 986         }
 987
 988         dpu_enc = to_dpu_encoder_virt(drm_enc);
 989         DPU_DEBUG_ENC(dpu_enc, "\n");
 990
 991         priv = drm_enc->dev->dev_private;
 992         dpu_kms = to_dpu_kms(priv->kms);
 993         connector_list = &dpu_kms->dev->mode_config.connector_list;
 994
 995         global_state = dpu_kms_get_existing_global_state(dpu_kms);
 996         if (IS_ERR_OR_NULL(global_state)) {
 997                 DPU_ERROR("Failed to get global state");
 998                 return;
 999         }
1000
1001         trace_dpu_enc_mode_set(DRMID(drm_enc));
1002
1003         if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp)
1004                 msm_dp_display_mode_set(priv->dp, drm_enc, mode, adj_mode);
1005
1006         list_for_each_entry(conn_iter, connector_list, head)
1007                 if (conn_iter->encoder == drm_enc)
1008                         conn = conn_iter;
1009
1010         if (!conn) {
1011                 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n");
1012                 return;
1013         } else if (!conn->state) {
1014                 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n");
1015                 return;
1016         }
1017
1018         drm_for_each_crtc(drm_crtc, drm_enc->dev)
1019                 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
1020                         break;
1021
1022         /* Query resource that have been reserved in atomic check step. */
1023         num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1024                 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
1025                 ARRAY_SIZE(hw_pp));
1026         num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1027                 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1028         num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1029                 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
1030         dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1031                 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
1032                 ARRAY_SIZE(hw_dspp));
1033
1034         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1035                 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1036                                                 : NULL;
1037
1038         cstate = to_dpu_crtc_state(drm_crtc->state);
1039
1040         for (i = 0; i < num_lm; i++) {
1041                 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1042
1043                 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
1044                 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
1045                 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
1046         }
1047
1048         cstate->num_mixers = num_lm;
1049
1050         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1051                 int num_blk;
1052                 struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC];
1053                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1054
1055                 if (!dpu_enc->hw_pp[i]) {
1056                         DPU_ERROR_ENC(dpu_enc,
1057                                 "no pp block assigned at idx: %d\n", i);
1058                         return;
1059                 }
1060
1061                 if (!hw_ctl[i]) {
1062                         DPU_ERROR_ENC(dpu_enc,
1063                                 "no ctl block assigned at idx: %d\n", i);
1064                         return;
1065                 }
1066
1067                 phys->hw_pp = dpu_enc->hw_pp[i];
1068                 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
1069
1070                 num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm,
1071                         global_state, drm_enc->base.id, DPU_HW_BLK_INTF,
1072                         hw_blk, ARRAY_SIZE(hw_blk));
1073                 for (j = 0; j < num_blk; j++) {
1074                         struct dpu_hw_intf *hw_intf;
1075
1076                         hw_intf = to_dpu_hw_intf(hw_blk[i]);
1077                         if (hw_intf->idx == phys->intf_idx)
1078                                 phys->hw_intf = hw_intf;
1079                 }
1080
1081                 if (!phys->hw_intf) {
1082                         DPU_ERROR_ENC(dpu_enc,
1083                                       "no intf block assigned at idx: %d\n", i);
1084                         return;
1085                 }
1086
1087                 phys->connector = conn->state->connector;
1088                 if (phys->ops.mode_set)
1089                         phys->ops.mode_set(phys, mode, adj_mode);
1090         }
1091 }
1092
1093 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1094 {
1095         struct dpu_encoder_virt *dpu_enc = NULL;
1096         int i;
1097
1098         if (!drm_enc || !drm_enc->dev) {
1099                 DPU_ERROR("invalid parameters\n");
1100                 return;
1101         }
1102
1103         dpu_enc = to_dpu_encoder_virt(drm_enc);
1104         if (!dpu_enc || !dpu_enc->cur_master) {
1105                 DPU_ERROR("invalid dpu encoder/master\n");
1106                 return;
1107         }
1108
1109
1110         if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
1111                 dpu_enc->cur_master->hw_mdptop &&
1112                 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1113                 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1114                         dpu_enc->cur_master->hw_mdptop);
1115
1116         _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1117
1118         if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1119                         !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1120                 unsigned bpc = dpu_enc->phys_encs[0]->connector->display_info.bpc;
1121                 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1122                         if (!dpu_enc->hw_pp[i])
1123                                 continue;
1124                         _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1125                 }
1126         }
1127 }
1128
1129 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1130 {
1131         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1132
1133         mutex_lock(&dpu_enc->enc_lock);
1134
1135         if (!dpu_enc->enabled)
1136                 goto out;
1137
1138         if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1139                 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1140         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1141                 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1142
1143         _dpu_encoder_virt_enable_helper(drm_enc);
1144
1145 out:
1146         mutex_unlock(&dpu_enc->enc_lock);
1147 }
1148
1149 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1150 {
1151         struct dpu_encoder_virt *dpu_enc = NULL;
1152         int ret = 0;
1153         struct msm_drm_private *priv;
1154         struct drm_display_mode *cur_mode = NULL;
1155
1156         if (!drm_enc) {
1157                 DPU_ERROR("invalid encoder\n");
1158                 return;
1159         }
1160         dpu_enc = to_dpu_encoder_virt(drm_enc);
1161
1162         mutex_lock(&dpu_enc->enc_lock);
1163         cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1164         priv = drm_enc->dev->dev_private;
1165
1166         trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1167                              cur_mode->vdisplay);
1168
1169         /* always enable slave encoder before master */
1170         if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1171                 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1172
1173         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1174                 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1175
1176         ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1177         if (ret) {
1178                 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1179                                 ret);
1180                 goto out;
1181         }
1182
1183         _dpu_encoder_virt_enable_helper(drm_enc);
1184
1185         if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
1186                 ret = msm_dp_display_enable(priv->dp,
1187                                                 drm_enc);
1188                 if (ret) {
1189                         DPU_ERROR_ENC(dpu_enc, "dp display enable failed: %d\n",
1190                                 ret);
1191                         goto out;
1192                 }
1193         }
1194         dpu_enc->enabled = true;
1195
1196 out:
1197         mutex_unlock(&dpu_enc->enc_lock);
1198 }
1199
1200 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1201 {
1202         struct dpu_encoder_virt *dpu_enc = NULL;
1203         struct msm_drm_private *priv;
1204         int i = 0;
1205
1206         if (!drm_enc) {
1207                 DPU_ERROR("invalid encoder\n");
1208                 return;
1209         } else if (!drm_enc->dev) {
1210                 DPU_ERROR("invalid dev\n");
1211                 return;
1212         }
1213
1214         dpu_enc = to_dpu_encoder_virt(drm_enc);
1215         DPU_DEBUG_ENC(dpu_enc, "\n");
1216
1217         mutex_lock(&dpu_enc->enc_lock);
1218         dpu_enc->enabled = false;
1219
1220         priv = drm_enc->dev->dev_private;
1221
1222         trace_dpu_enc_disable(DRMID(drm_enc));
1223
1224         /* wait for idle */
1225         dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1226
1227         if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
1228                 if (msm_dp_display_pre_disable(priv->dp, drm_enc))
1229                         DPU_ERROR_ENC(dpu_enc, "dp display push idle failed\n");
1230         }
1231
1232         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1233
1234         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1235                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1236
1237                 if (phys->ops.disable)
1238                         phys->ops.disable(phys);
1239         }
1240
1241
1242         /* after phys waits for frame-done, should be no more frames pending */
1243         if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1244                 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1245                 del_timer_sync(&dpu_enc->frame_done_timer);
1246         }
1247
1248         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1249
1250         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1251                 dpu_enc->phys_encs[i]->connector = NULL;
1252         }
1253
1254         DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1255
1256         if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
1257                 if (msm_dp_display_disable(priv->dp, drm_enc))
1258                         DPU_ERROR_ENC(dpu_enc, "dp display disable failed\n");
1259         }
1260
1261         mutex_unlock(&dpu_enc->enc_lock);
1262 }
1263
1264 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
1265                 enum dpu_intf_type type, u32 controller_id)
1266 {
1267         int i = 0;
1268
1269         for (i = 0; i < catalog->intf_count; i++) {
1270                 if (catalog->intf[i].type == type
1271                     && catalog->intf[i].controller_id == controller_id) {
1272                         return catalog->intf[i].id;
1273                 }
1274         }
1275
1276         return INTF_MAX;
1277 }
1278
1279 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1280                 struct dpu_encoder_phys *phy_enc)
1281 {
1282         struct dpu_encoder_virt *dpu_enc = NULL;
1283         unsigned long lock_flags;
1284
1285         if (!drm_enc || !phy_enc)
1286                 return;
1287
1288         DPU_ATRACE_BEGIN("encoder_vblank_callback");
1289         dpu_enc = to_dpu_encoder_virt(drm_enc);
1290
1291         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1292         if (dpu_enc->crtc)
1293                 dpu_crtc_vblank_callback(dpu_enc->crtc);
1294         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1295
1296         atomic_inc(&phy_enc->vsync_cnt);
1297         DPU_ATRACE_END("encoder_vblank_callback");
1298 }
1299
1300 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1301                 struct dpu_encoder_phys *phy_enc)
1302 {
1303         if (!phy_enc)
1304                 return;
1305
1306         DPU_ATRACE_BEGIN("encoder_underrun_callback");
1307         atomic_inc(&phy_enc->underrun_cnt);
1308
1309         /* trigger dump only on the first underrun */
1310         if (atomic_read(&phy_enc->underrun_cnt) == 1)
1311                 msm_disp_snapshot_state(drm_enc->dev);
1312
1313         trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1314                                   atomic_read(&phy_enc->underrun_cnt));
1315         DPU_ATRACE_END("encoder_underrun_callback");
1316 }
1317
1318 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1319 {
1320         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1321         unsigned long lock_flags;
1322
1323         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1324         /* crtc should always be cleared before re-assigning */
1325         WARN_ON(crtc && dpu_enc->crtc);
1326         dpu_enc->crtc = crtc;
1327         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1328 }
1329
1330 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1331                                         struct drm_crtc *crtc, bool enable)
1332 {
1333         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1334         unsigned long lock_flags;
1335         int i;
1336
1337         trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1338
1339         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1340         if (dpu_enc->crtc != crtc) {
1341                 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1342                 return;
1343         }
1344         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1345
1346         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1347                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1348
1349                 if (phys->ops.control_vblank_irq)
1350                         phys->ops.control_vblank_irq(phys, enable);
1351         }
1352 }
1353
1354 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1355                 void (*frame_event_cb)(void *, u32 event),
1356                 void *frame_event_cb_data)
1357 {
1358         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1359         unsigned long lock_flags;
1360         bool enable;
1361
1362         enable = frame_event_cb ? true : false;
1363
1364         if (!drm_enc) {
1365                 DPU_ERROR("invalid encoder\n");
1366                 return;
1367         }
1368         trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1369
1370         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1371         dpu_enc->crtc_frame_event_cb = frame_event_cb;
1372         dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1373         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1374 }
1375
1376 static void dpu_encoder_frame_done_callback(
1377                 struct drm_encoder *drm_enc,
1378                 struct dpu_encoder_phys *ready_phys, u32 event)
1379 {
1380         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1381         unsigned int i;
1382
1383         if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1384                         | DPU_ENCODER_FRAME_EVENT_ERROR
1385                         | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1386
1387                 if (!dpu_enc->frame_busy_mask[0]) {
1388                         /**
1389                          * suppress frame_done without waiter,
1390                          * likely autorefresh
1391                          */
1392                         trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
1393                                         event, ready_phys->intf_idx);
1394                         return;
1395                 }
1396
1397                 /* One of the physical encoders has become idle */
1398                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1399                         if (dpu_enc->phys_encs[i] == ready_phys) {
1400                                 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1401                                                 dpu_enc->frame_busy_mask[0]);
1402                                 clear_bit(i, dpu_enc->frame_busy_mask);
1403                         }
1404                 }
1405
1406                 if (!dpu_enc->frame_busy_mask[0]) {
1407                         atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1408                         del_timer(&dpu_enc->frame_done_timer);
1409
1410                         dpu_encoder_resource_control(drm_enc,
1411                                         DPU_ENC_RC_EVENT_FRAME_DONE);
1412
1413                         if (dpu_enc->crtc_frame_event_cb)
1414                                 dpu_enc->crtc_frame_event_cb(
1415                                         dpu_enc->crtc_frame_event_cb_data,
1416                                         event);
1417                 }
1418         } else {
1419                 if (dpu_enc->crtc_frame_event_cb)
1420                         dpu_enc->crtc_frame_event_cb(
1421                                 dpu_enc->crtc_frame_event_cb_data, event);
1422         }
1423 }
1424
1425 static void dpu_encoder_off_work(struct work_struct *work)
1426 {
1427         struct dpu_encoder_virt *dpu_enc = container_of(work,
1428                         struct dpu_encoder_virt, delayed_off_work.work);
1429
1430         dpu_encoder_resource_control(&dpu_enc->base,
1431                                                 DPU_ENC_RC_EVENT_ENTER_IDLE);
1432
1433         dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1434                                 DPU_ENCODER_FRAME_EVENT_IDLE);
1435 }
1436
1437 /**
1438  * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1439  * @drm_enc: Pointer to drm encoder structure
1440  * @phys: Pointer to physical encoder structure
1441  * @extra_flush_bits: Additional bit mask to include in flush trigger
1442  */
1443 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1444                 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1445 {
1446         struct dpu_hw_ctl *ctl;
1447         int pending_kickoff_cnt;
1448         u32 ret = UINT_MAX;
1449
1450         if (!phys->hw_pp) {
1451                 DPU_ERROR("invalid pingpong hw\n");
1452                 return;
1453         }
1454
1455         ctl = phys->hw_ctl;
1456         if (!ctl->ops.trigger_flush) {
1457                 DPU_ERROR("missing trigger cb\n");
1458                 return;
1459         }
1460
1461         pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1462
1463         if (extra_flush_bits && ctl->ops.update_pending_flush)
1464                 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1465
1466         ctl->ops.trigger_flush(ctl);
1467
1468         if (ctl->ops.get_pending_flush)
1469                 ret = ctl->ops.get_pending_flush(ctl);
1470
1471         trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1472                                     pending_kickoff_cnt, ctl->idx,
1473                                     extra_flush_bits, ret);
1474 }
1475
1476 /**
1477  * _dpu_encoder_trigger_start - trigger start for a physical encoder
1478  * @phys: Pointer to physical encoder structure
1479  */
1480 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1481 {
1482         if (!phys) {
1483                 DPU_ERROR("invalid argument(s)\n");
1484                 return;
1485         }
1486
1487         if (!phys->hw_pp) {
1488                 DPU_ERROR("invalid pingpong hw\n");
1489                 return;
1490         }
1491
1492         if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1493                 phys->ops.trigger_start(phys);
1494 }
1495
1496 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1497 {
1498         struct dpu_hw_ctl *ctl;
1499
1500         ctl = phys_enc->hw_ctl;
1501         if (ctl->ops.trigger_start) {
1502                 ctl->ops.trigger_start(ctl);
1503                 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1504         }
1505 }
1506
1507 static int dpu_encoder_helper_wait_event_timeout(
1508                 int32_t drm_id,
1509                 u32 irq_idx,
1510                 struct dpu_encoder_wait_info *info)
1511 {
1512         int rc = 0;
1513         s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1514         s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1515         s64 time;
1516
1517         do {
1518                 rc = wait_event_timeout(*(info->wq),
1519                                 atomic_read(info->atomic_cnt) == 0, jiffies);
1520                 time = ktime_to_ms(ktime_get());
1521
1522                 trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
1523                                                  expected_time,
1524                                                  atomic_read(info->atomic_cnt));
1525         /* If we timed out, counter is valid and time is less, wait again */
1526         } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1527                         (time < expected_time));
1528
1529         return rc;
1530 }
1531
1532 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1533 {
1534         struct dpu_encoder_virt *dpu_enc;
1535         struct dpu_hw_ctl *ctl;
1536         int rc;
1537         struct drm_encoder *drm_enc;
1538
1539         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1540         ctl = phys_enc->hw_ctl;
1541         drm_enc = phys_enc->parent;
1542
1543         if (!ctl->ops.reset)
1544                 return;
1545
1546         DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1547                       ctl->idx);
1548
1549         rc = ctl->ops.reset(ctl);
1550         if (rc) {
1551                 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
1552                 msm_disp_snapshot_state(drm_enc->dev);
1553         }
1554
1555         phys_enc->enable_state = DPU_ENC_ENABLED;
1556 }
1557
1558 /**
1559  * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1560  *      Iterate through the physical encoders and perform consolidated flush
1561  *      and/or control start triggering as needed. This is done in the virtual
1562  *      encoder rather than the individual physical ones in order to handle
1563  *      use cases that require visibility into multiple physical encoders at
1564  *      a time.
1565  * @dpu_enc: Pointer to virtual encoder structure
1566  */
1567 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1568 {
1569         struct dpu_hw_ctl *ctl;
1570         uint32_t i, pending_flush;
1571         unsigned long lock_flags;
1572
1573         pending_flush = 0x0;
1574
1575         /* update pending counts and trigger kickoff ctl flush atomically */
1576         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1577
1578         /* don't perform flush/start operations for slave encoders */
1579         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1580                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1581
1582                 if (phys->enable_state == DPU_ENC_DISABLED)
1583                         continue;
1584
1585                 ctl = phys->hw_ctl;
1586
1587                 /*
1588                  * This is cleared in frame_done worker, which isn't invoked
1589                  * for async commits. So don't set this for async, since it'll
1590                  * roll over to the next commit.
1591                  */
1592                 if (phys->split_role != ENC_ROLE_SLAVE)
1593                         set_bit(i, dpu_enc->frame_busy_mask);
1594
1595                 if (!phys->ops.needs_single_flush ||
1596                                 !phys->ops.needs_single_flush(phys))
1597                         _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1598                 else if (ctl->ops.get_pending_flush)
1599                         pending_flush |= ctl->ops.get_pending_flush(ctl);
1600         }
1601
1602         /* for split flush, combine pending flush masks and send to master */
1603         if (pending_flush && dpu_enc->cur_master) {
1604                 _dpu_encoder_trigger_flush(
1605                                 &dpu_enc->base,
1606                                 dpu_enc->cur_master,
1607                                 pending_flush);
1608         }
1609
1610         _dpu_encoder_trigger_start(dpu_enc->cur_master);
1611
1612         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1613 }
1614
1615 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1616 {
1617         struct dpu_encoder_virt *dpu_enc;
1618         struct dpu_encoder_phys *phys;
1619         unsigned int i;
1620         struct dpu_hw_ctl *ctl;
1621         struct msm_display_info *disp_info;
1622
1623         if (!drm_enc) {
1624                 DPU_ERROR("invalid encoder\n");
1625                 return;
1626         }
1627         dpu_enc = to_dpu_encoder_virt(drm_enc);
1628         disp_info = &dpu_enc->disp_info;
1629
1630         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1631                 phys = dpu_enc->phys_encs[i];
1632
1633                 ctl = phys->hw_ctl;
1634                 if (ctl->ops.clear_pending_flush)
1635                         ctl->ops.clear_pending_flush(ctl);
1636
1637                 /* update only for command mode primary ctl */
1638                 if ((phys == dpu_enc->cur_master) &&
1639                    (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1640                     && ctl->ops.trigger_pending)
1641                         ctl->ops.trigger_pending(ctl);
1642         }
1643 }
1644
1645 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1646                 struct drm_display_mode *mode)
1647 {
1648         u64 pclk_rate;
1649         u32 pclk_period;
1650         u32 line_time;
1651
1652         /*
1653          * For linetime calculation, only operate on master encoder.
1654          */
1655         if (!dpu_enc->cur_master)
1656                 return 0;
1657
1658         if (!dpu_enc->cur_master->ops.get_line_count) {
1659                 DPU_ERROR("get_line_count function not defined\n");
1660                 return 0;
1661         }
1662
1663         pclk_rate = mode->clock; /* pixel clock in kHz */
1664         if (pclk_rate == 0) {
1665                 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1666                 return 0;
1667         }
1668
1669         pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1670         if (pclk_period == 0) {
1671                 DPU_ERROR("pclk period is 0\n");
1672                 return 0;
1673         }
1674
1675         /*
1676          * Line time calculation based on Pixel clock and HTOTAL.
1677          * Final unit is in ns.
1678          */
1679         line_time = (pclk_period * mode->htotal) / 1000;
1680         if (line_time == 0) {
1681                 DPU_ERROR("line time calculation is 0\n");
1682                 return 0;
1683         }
1684
1685         DPU_DEBUG_ENC(dpu_enc,
1686                         "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1687                         pclk_rate, pclk_period, line_time);
1688
1689         return line_time;
1690 }
1691
1692 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1693 {
1694         struct drm_display_mode *mode;
1695         struct dpu_encoder_virt *dpu_enc;
1696         u32 cur_line;
1697         u32 line_time;
1698         u32 vtotal, time_to_vsync;
1699         ktime_t cur_time;
1700
1701         dpu_enc = to_dpu_encoder_virt(drm_enc);
1702
1703         if (!drm_enc->crtc || !drm_enc->crtc->state) {
1704                 DPU_ERROR("crtc/crtc state object is NULL\n");
1705                 return -EINVAL;
1706         }
1707         mode = &drm_enc->crtc->state->adjusted_mode;
1708
1709         line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1710         if (!line_time)
1711                 return -EINVAL;
1712
1713         cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1714
1715         vtotal = mode->vtotal;
1716         if (cur_line >= vtotal)
1717                 time_to_vsync = line_time * vtotal;
1718         else
1719                 time_to_vsync = line_time * (vtotal - cur_line);
1720
1721         if (time_to_vsync == 0) {
1722                 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1723                                 vtotal);
1724                 return -EINVAL;
1725         }
1726
1727         cur_time = ktime_get();
1728         *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1729
1730         DPU_DEBUG_ENC(dpu_enc,
1731                         "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1732                         cur_line, vtotal, time_to_vsync,
1733                         ktime_to_ms(cur_time),
1734                         ktime_to_ms(*wakeup_time));
1735         return 0;
1736 }
1737
1738 static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1739 {
1740         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1741                         vsync_event_timer);
1742         struct drm_encoder *drm_enc = &dpu_enc->base;
1743         struct msm_drm_private *priv;
1744         struct msm_drm_thread *event_thread;
1745
1746         if (!drm_enc->dev || !drm_enc->crtc) {
1747                 DPU_ERROR("invalid parameters\n");
1748                 return;
1749         }
1750
1751         priv = drm_enc->dev->dev_private;
1752
1753         if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1754                 DPU_ERROR("invalid crtc index\n");
1755                 return;
1756         }
1757         event_thread = &priv->event_thread[drm_enc->crtc->index];
1758         if (!event_thread) {
1759                 DPU_ERROR("event_thread not found for crtc:%d\n",
1760                                 drm_enc->crtc->index);
1761                 return;
1762         }
1763
1764         del_timer(&dpu_enc->vsync_event_timer);
1765 }
1766
1767 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1768 {
1769         struct dpu_encoder_virt *dpu_enc = container_of(work,
1770                         struct dpu_encoder_virt, vsync_event_work);
1771         ktime_t wakeup_time;
1772
1773         if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1774                 return;
1775
1776         trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1777         mod_timer(&dpu_enc->vsync_event_timer,
1778                         nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1779 }
1780
1781 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1782 {
1783         struct dpu_encoder_virt *dpu_enc;
1784         struct dpu_encoder_phys *phys;
1785         bool needs_hw_reset = false;
1786         unsigned int i;
1787
1788         dpu_enc = to_dpu_encoder_virt(drm_enc);
1789
1790         trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1791
1792         /* prepare for next kickoff, may include waiting on previous kickoff */
1793         DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1794         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1795                 phys = dpu_enc->phys_encs[i];
1796                 if (phys->ops.prepare_for_kickoff)
1797                         phys->ops.prepare_for_kickoff(phys);
1798                 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1799                         needs_hw_reset = true;
1800         }
1801         DPU_ATRACE_END("enc_prepare_for_kickoff");
1802
1803         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1804
1805         /* if any phys needs reset, reset all phys, in-order */
1806         if (needs_hw_reset) {
1807                 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1808                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1809                         dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1810                 }
1811         }
1812 }
1813
1814 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1815 {
1816         struct dpu_encoder_virt *dpu_enc;
1817         struct dpu_encoder_phys *phys;
1818         ktime_t wakeup_time;
1819         unsigned long timeout_ms;
1820         unsigned int i;
1821
1822         DPU_ATRACE_BEGIN("encoder_kickoff");
1823         dpu_enc = to_dpu_encoder_virt(drm_enc);
1824
1825         trace_dpu_enc_kickoff(DRMID(drm_enc));
1826
1827         timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1828                         drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1829
1830         atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1831         mod_timer(&dpu_enc->frame_done_timer,
1832                         jiffies + msecs_to_jiffies(timeout_ms));
1833
1834         /* All phys encs are ready to go, trigger the kickoff */
1835         _dpu_encoder_kickoff_phys(dpu_enc);
1836
1837         /* allow phys encs to handle any post-kickoff business */
1838         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1839                 phys = dpu_enc->phys_encs[i];
1840                 if (phys->ops.handle_post_kickoff)
1841                         phys->ops.handle_post_kickoff(phys);
1842         }
1843
1844         if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1845                         !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
1846                 trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1847                                             ktime_to_ms(wakeup_time));
1848                 mod_timer(&dpu_enc->vsync_event_timer,
1849                                 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1850         }
1851
1852         DPU_ATRACE_END("encoder_kickoff");
1853 }
1854
1855 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
1856 {
1857         struct dpu_encoder_virt *dpu_enc;
1858         struct dpu_encoder_phys *phys;
1859         int i;
1860
1861         if (!drm_enc) {
1862                 DPU_ERROR("invalid encoder\n");
1863                 return;
1864         }
1865         dpu_enc = to_dpu_encoder_virt(drm_enc);
1866
1867         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1868                 phys = dpu_enc->phys_encs[i];
1869                 if (phys->ops.prepare_commit)
1870                         phys->ops.prepare_commit(phys);
1871         }
1872 }
1873
1874 #ifdef CONFIG_DEBUG_FS
1875 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
1876 {
1877         struct dpu_encoder_virt *dpu_enc = s->private;
1878         int i;
1879
1880         mutex_lock(&dpu_enc->enc_lock);
1881         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1882                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1883
1884                 seq_printf(s, "intf:%d    vsync:%8d     underrun:%8d    ",
1885                                 phys->intf_idx - INTF_0,
1886                                 atomic_read(&phys->vsync_cnt),
1887                                 atomic_read(&phys->underrun_cnt));
1888
1889                 switch (phys->intf_mode) {
1890                 case INTF_MODE_VIDEO:
1891                         seq_puts(s, "mode: video\n");
1892                         break;
1893                 case INTF_MODE_CMD:
1894                         seq_puts(s, "mode: command\n");
1895                         break;
1896                 default:
1897                         seq_puts(s, "mode: ???\n");
1898                         break;
1899                 }
1900         }
1901         mutex_unlock(&dpu_enc->enc_lock);
1902
1903         return 0;
1904 }
1905
1906 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
1907
1908 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1909 {
1910         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1911         int i;
1912
1913         char name[DPU_NAME_SIZE];
1914
1915         if (!drm_enc->dev) {
1916                 DPU_ERROR("invalid encoder or kms\n");
1917                 return -EINVAL;
1918         }
1919
1920         snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
1921
1922         /* create overall sub-directory for the encoder */
1923         dpu_enc->debugfs_root = debugfs_create_dir(name,
1924                         drm_enc->dev->primary->debugfs_root);
1925
1926         /* don't error check these */
1927         debugfs_create_file("status", 0600,
1928                 dpu_enc->debugfs_root, dpu_enc, &_dpu_encoder_status_fops);
1929
1930         for (i = 0; i < dpu_enc->num_phys_encs; i++)
1931                 if (dpu_enc->phys_encs[i]->ops.late_register)
1932                         dpu_enc->phys_encs[i]->ops.late_register(
1933                                         dpu_enc->phys_encs[i],
1934                                         dpu_enc->debugfs_root);
1935
1936         return 0;
1937 }
1938 #else
1939 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1940 {
1941         return 0;
1942 }
1943 #endif
1944
1945 static int dpu_encoder_late_register(struct drm_encoder *encoder)
1946 {
1947         return _dpu_encoder_init_debugfs(encoder);
1948 }
1949
1950 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
1951 {
1952         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
1953
1954         debugfs_remove_recursive(dpu_enc->debugfs_root);
1955 }
1956
1957 static int dpu_encoder_virt_add_phys_encs(
1958                 u32 display_caps,
1959                 struct dpu_encoder_virt *dpu_enc,
1960                 struct dpu_enc_phys_init_params *params)
1961 {
1962         struct dpu_encoder_phys *enc = NULL;
1963
1964         DPU_DEBUG_ENC(dpu_enc, "\n");
1965
1966         /*
1967          * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
1968          * in this function, check up-front.
1969          */
1970         if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
1971                         ARRAY_SIZE(dpu_enc->phys_encs)) {
1972                 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
1973                           dpu_enc->num_phys_encs);
1974                 return -EINVAL;
1975         }
1976
1977         if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
1978                 enc = dpu_encoder_phys_vid_init(params);
1979
1980                 if (IS_ERR_OR_NULL(enc)) {
1981                         DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
1982                                 PTR_ERR(enc));
1983                         return enc == NULL ? -EINVAL : PTR_ERR(enc);
1984                 }
1985
1986                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1987                 ++dpu_enc->num_phys_encs;
1988         }
1989
1990         if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
1991                 enc = dpu_encoder_phys_cmd_init(params);
1992
1993                 if (IS_ERR_OR_NULL(enc)) {
1994                         DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
1995                                 PTR_ERR(enc));
1996                         return enc == NULL ? -EINVAL : PTR_ERR(enc);
1997                 }
1998
1999                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2000                 ++dpu_enc->num_phys_encs;
2001         }
2002
2003         if (params->split_role == ENC_ROLE_SLAVE)
2004                 dpu_enc->cur_slave = enc;
2005         else
2006                 dpu_enc->cur_master = enc;
2007
2008         return 0;
2009 }
2010
2011 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
2012         .handle_vblank_virt = dpu_encoder_vblank_callback,
2013         .handle_underrun_virt = dpu_encoder_underrun_callback,
2014         .handle_frame_done = dpu_encoder_frame_done_callback,
2015 };
2016
2017 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2018                                  struct dpu_kms *dpu_kms,
2019                                  struct msm_display_info *disp_info)
2020 {
2021         int ret = 0;
2022         int i = 0;
2023         enum dpu_intf_type intf_type = INTF_NONE;
2024         struct dpu_enc_phys_init_params phys_params;
2025
2026         if (!dpu_enc) {
2027                 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2028                 return -EINVAL;
2029         }
2030
2031         dpu_enc->cur_master = NULL;
2032
2033         memset(&phys_params, 0, sizeof(phys_params));
2034         phys_params.dpu_kms = dpu_kms;
2035         phys_params.parent = &dpu_enc->base;
2036         phys_params.parent_ops = &dpu_encoder_parent_ops;
2037         phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2038
2039         switch (disp_info->intf_type) {
2040         case DRM_MODE_ENCODER_DSI:
2041                 intf_type = INTF_DSI;
2042                 break;
2043         case DRM_MODE_ENCODER_TMDS:
2044                 intf_type = INTF_DP;
2045                 break;
2046         }
2047
2048         WARN_ON(disp_info->num_of_h_tiles < 1);
2049
2050         DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2051
2052         if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
2053             (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
2054                 dpu_enc->idle_pc_supported =
2055                                 dpu_kms->catalog->caps->has_idle_pc;
2056
2057         mutex_lock(&dpu_enc->enc_lock);
2058         for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2059                 /*
2060                  * Left-most tile is at index 0, content is controller id
2061                  * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2062                  * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2063                  */
2064                 u32 controller_id = disp_info->h_tile_instance[i];
2065
2066                 if (disp_info->num_of_h_tiles > 1) {
2067                         if (i == 0)
2068                                 phys_params.split_role = ENC_ROLE_MASTER;
2069                         else
2070                                 phys_params.split_role = ENC_ROLE_SLAVE;
2071                 } else {
2072                         phys_params.split_role = ENC_ROLE_SOLO;
2073                 }
2074
2075                 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2076                                 i, controller_id, phys_params.split_role);
2077
2078                 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2079                                                                                                         intf_type,
2080                                                                                                         controller_id);
2081                 if (phys_params.intf_idx == INTF_MAX) {
2082                         DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n",
2083                                                   intf_type, controller_id);
2084                         ret = -EINVAL;
2085                 }
2086
2087                 if (!ret) {
2088                         ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
2089                                                                                                  dpu_enc,
2090                                                                                                  &phys_params);
2091                         if (ret)
2092                                 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2093                 }
2094         }
2095
2096         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2097                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2098                 atomic_set(&phys->vsync_cnt, 0);
2099                 atomic_set(&phys->underrun_cnt, 0);
2100         }
2101         mutex_unlock(&dpu_enc->enc_lock);
2102
2103         return ret;
2104 }
2105
2106 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2107 {
2108         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2109                         frame_done_timer);
2110         struct drm_encoder *drm_enc = &dpu_enc->base;
2111         u32 event;
2112
2113         if (!drm_enc->dev) {
2114                 DPU_ERROR("invalid parameters\n");
2115                 return;
2116         }
2117
2118         if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2119                 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2120                               DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2121                 return;
2122         } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2123                 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2124                 return;
2125         }
2126
2127         DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
2128
2129         event = DPU_ENCODER_FRAME_EVENT_ERROR;
2130         trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2131         dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2132 }
2133
2134 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2135         .mode_set = dpu_encoder_virt_mode_set,
2136         .disable = dpu_encoder_virt_disable,
2137         .enable = dpu_kms_encoder_enable,
2138         .atomic_check = dpu_encoder_virt_atomic_check,
2139
2140         /* This is called by dpu_kms_encoder_enable */
2141         .commit = dpu_encoder_virt_enable,
2142 };
2143
2144 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2145                 .destroy = dpu_encoder_destroy,
2146                 .late_register = dpu_encoder_late_register,
2147                 .early_unregister = dpu_encoder_early_unregister,
2148 };
2149
2150 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2151                 struct msm_display_info *disp_info)
2152 {
2153         struct msm_drm_private *priv = dev->dev_private;
2154         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2155         struct drm_encoder *drm_enc = NULL;
2156         struct dpu_encoder_virt *dpu_enc = NULL;
2157         int ret = 0;
2158
2159         dpu_enc = to_dpu_encoder_virt(enc);
2160
2161         ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2162         if (ret)
2163                 goto fail;
2164
2165         atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2166         timer_setup(&dpu_enc->frame_done_timer,
2167                         dpu_encoder_frame_done_timeout, 0);
2168
2169         if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2170                 timer_setup(&dpu_enc->vsync_event_timer,
2171                                 dpu_encoder_vsync_event_handler,
2172                                 0);
2173
2174
2175         INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2176                         dpu_encoder_off_work);
2177         dpu_enc->idle_timeout = IDLE_TIMEOUT;
2178
2179         kthread_init_work(&dpu_enc->vsync_event_work,
2180                         dpu_encoder_vsync_event_work_handler);
2181
2182         memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2183
2184         DPU_DEBUG_ENC(dpu_enc, "created\n");
2185
2186         return ret;
2187
2188 fail:
2189         DPU_ERROR("failed to create encoder\n");
2190         if (drm_enc)
2191                 dpu_encoder_destroy(drm_enc);
2192
2193         return ret;
2194
2195
2196 }
2197
2198 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2199                 int drm_enc_mode)
2200 {
2201         struct dpu_encoder_virt *dpu_enc = NULL;
2202         int rc = 0;
2203
2204         dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2205         if (!dpu_enc)
2206                 return ERR_PTR(-ENOMEM);
2207
2208         rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2209                         drm_enc_mode, NULL);
2210         if (rc) {
2211                 devm_kfree(dev->dev, dpu_enc);
2212                 return ERR_PTR(rc);
2213         }
2214
2215         drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2216
2217         spin_lock_init(&dpu_enc->enc_spinlock);
2218         dpu_enc->enabled = false;
2219         mutex_init(&dpu_enc->enc_lock);
2220         mutex_init(&dpu_enc->rc_lock);
2221
2222         return &dpu_enc->base;
2223 }
2224
2225 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2226         enum msm_event_wait event)
2227 {
2228         int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2229         struct dpu_encoder_virt *dpu_enc = NULL;
2230         int i, ret = 0;
2231
2232         if (!drm_enc) {
2233                 DPU_ERROR("invalid encoder\n");
2234                 return -EINVAL;
2235         }
2236         dpu_enc = to_dpu_encoder_virt(drm_enc);
2237         DPU_DEBUG_ENC(dpu_enc, "\n");
2238
2239         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2240                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2241
2242                 switch (event) {
2243                 case MSM_ENC_COMMIT_DONE:
2244                         fn_wait = phys->ops.wait_for_commit_done;
2245                         break;
2246                 case MSM_ENC_TX_COMPLETE:
2247                         fn_wait = phys->ops.wait_for_tx_complete;
2248                         break;
2249                 case MSM_ENC_VBLANK:
2250                         fn_wait = phys->ops.wait_for_vblank;
2251                         break;
2252                 default:
2253                         DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2254                                         event);
2255                         return -EINVAL;
2256                 }
2257
2258                 if (fn_wait) {
2259                         DPU_ATRACE_BEGIN("wait_for_completion_event");
2260                         ret = fn_wait(phys);
2261                         DPU_ATRACE_END("wait_for_completion_event");
2262                         if (ret)
2263                                 return ret;
2264                 }
2265         }
2266
2267         return ret;
2268 }
2269
2270 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2271 {
2272         struct dpu_encoder_virt *dpu_enc = NULL;
2273
2274         if (!encoder) {
2275                 DPU_ERROR("invalid encoder\n");
2276                 return INTF_MODE_NONE;
2277         }
2278         dpu_enc = to_dpu_encoder_virt(encoder);
2279
2280         if (dpu_enc->cur_master)
2281                 return dpu_enc->cur_master->intf_mode;
2282
2283         if (dpu_enc->num_phys_encs)
2284                 return dpu_enc->phys_encs[0]->intf_mode;
2285
2286         return INTF_MODE_NONE;
2287 }