1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
9 #include "adreno_gpu.h"
11 bool hang_debug = false;
12 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
13 module_param_named(hang_debug, hang_debug, bool, 0600);
15 bool snapshot_debugbus = false;
16 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
17 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
19 bool allow_vram_carveout = false;
20 MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
21 module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
23 static const struct adreno_info gpulist[] = {
25 .rev = ADRENO_REV(2, 0, 0, 0),
29 [ADRENO_FW_PM4] = "yamato_pm4.fw",
30 [ADRENO_FW_PFP] = "yamato_pfp.fw",
33 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
34 .init = a2xx_gpu_init,
35 }, { /* a200 on i.mx51 has only 128kib gmem */
36 .rev = ADRENO_REV(2, 0, 0, 1),
40 [ADRENO_FW_PM4] = "yamato_pm4.fw",
41 [ADRENO_FW_PFP] = "yamato_pfp.fw",
44 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
45 .init = a2xx_gpu_init,
47 .rev = ADRENO_REV(2, 2, 0, ANY_ID),
51 [ADRENO_FW_PM4] = "leia_pm4_470.fw",
52 [ADRENO_FW_PFP] = "leia_pfp_470.fw",
55 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
56 .init = a2xx_gpu_init,
58 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
62 [ADRENO_FW_PM4] = "a300_pm4.fw",
63 [ADRENO_FW_PFP] = "a300_pfp.fw",
66 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
67 .init = a3xx_gpu_init,
69 .rev = ADRENO_REV(3, 0, 6, 0),
70 .revn = 307, /* because a305c is revn==306 */
73 [ADRENO_FW_PM4] = "a300_pm4.fw",
74 [ADRENO_FW_PFP] = "a300_pfp.fw",
77 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
78 .init = a3xx_gpu_init,
80 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
84 [ADRENO_FW_PM4] = "a300_pm4.fw",
85 [ADRENO_FW_PFP] = "a300_pfp.fw",
88 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
89 .init = a3xx_gpu_init,
91 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
95 [ADRENO_FW_PM4] = "a330_pm4.fw",
96 [ADRENO_FW_PFP] = "a330_pfp.fw",
99 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
100 .init = a3xx_gpu_init,
102 .rev = ADRENO_REV(4, 0, 5, ANY_ID),
106 [ADRENO_FW_PM4] = "a420_pm4.fw",
107 [ADRENO_FW_PFP] = "a420_pfp.fw",
110 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
111 .init = a4xx_gpu_init,
113 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
117 [ADRENO_FW_PM4] = "a420_pm4.fw",
118 [ADRENO_FW_PFP] = "a420_pfp.fw",
120 .gmem = (SZ_1M + SZ_512K),
121 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
122 .init = a4xx_gpu_init,
124 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
128 [ADRENO_FW_PM4] = "a420_pm4.fw",
129 [ADRENO_FW_PFP] = "a420_pfp.fw",
131 .gmem = (SZ_1M + SZ_512K),
132 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
133 .init = a4xx_gpu_init,
135 .rev = ADRENO_REV(5, 0, 8, ANY_ID),
139 [ADRENO_FW_PM4] = "a530_pm4.fw",
140 [ADRENO_FW_PFP] = "a530_pfp.fw",
142 .gmem = (SZ_128K + SZ_8K),
144 * Increase inactive period to 250 to avoid bouncing
145 * the GDSC which appears to make it grumpy
147 .inactive_period = 250,
148 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
149 .init = a5xx_gpu_init,
150 .zapfw = "a508_zap.mdt",
152 .rev = ADRENO_REV(5, 0, 9, ANY_ID),
156 [ADRENO_FW_PM4] = "a530_pm4.fw",
157 [ADRENO_FW_PFP] = "a530_pfp.fw",
159 .gmem = (SZ_256K + SZ_16K),
161 * Increase inactive period to 250 to avoid bouncing
162 * the GDSC which appears to make it grumpy
164 .inactive_period = 250,
165 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
166 .init = a5xx_gpu_init,
167 /* Adreno 509 uses the same ZAP as 512 */
168 .zapfw = "a512_zap.mdt",
170 .rev = ADRENO_REV(5, 1, 0, ANY_ID),
174 [ADRENO_FW_PM4] = "a530_pm4.fw",
175 [ADRENO_FW_PFP] = "a530_pfp.fw",
179 * Increase inactive period to 250 to avoid bouncing
180 * the GDSC which appears to make it grumpy
182 .inactive_period = 250,
183 .init = a5xx_gpu_init,
185 .rev = ADRENO_REV(5, 1, 2, ANY_ID),
189 [ADRENO_FW_PM4] = "a530_pm4.fw",
190 [ADRENO_FW_PFP] = "a530_pfp.fw",
192 .gmem = (SZ_256K + SZ_16K),
194 * Increase inactive period to 250 to avoid bouncing
195 * the GDSC which appears to make it grumpy
197 .inactive_period = 250,
198 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
199 .init = a5xx_gpu_init,
200 .zapfw = "a512_zap.mdt",
202 .rev = ADRENO_REV(5, 3, 0, 2),
206 [ADRENO_FW_PM4] = "a530_pm4.fw",
207 [ADRENO_FW_PFP] = "a530_pfp.fw",
208 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
212 * Increase inactive period to 250 to avoid bouncing
213 * the GDSC which appears to make it grumpy
215 .inactive_period = 250,
216 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
217 ADRENO_QUIRK_FAULT_DETECT_MASK,
218 .init = a5xx_gpu_init,
219 .zapfw = "a530_zap.mdt",
221 .rev = ADRENO_REV(5, 4, 0, ANY_ID),
225 [ADRENO_FW_PM4] = "a530_pm4.fw",
226 [ADRENO_FW_PFP] = "a530_pfp.fw",
227 [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
231 * Increase inactive period to 250 to avoid bouncing
232 * the GDSC which appears to make it grumpy
234 .inactive_period = 250,
235 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
236 .init = a5xx_gpu_init,
237 .zapfw = "a540_zap.mdt",
239 .rev = ADRENO_REV(6, 1, 8, ANY_ID),
243 [ADRENO_FW_SQE] = "a630_sqe.fw",
244 [ADRENO_FW_GMU] = "a630_gmu.bin",
247 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
248 .init = a6xx_gpu_init,
250 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
254 [ADRENO_FW_SQE] = "a630_sqe.fw",
255 [ADRENO_FW_GMU] = "a630_gmu.bin",
258 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
259 .init = a6xx_gpu_init,
260 .zapfw = "a630_zap.mdt",
263 .rev = ADRENO_REV(6, 4, 0, ANY_ID),
267 [ADRENO_FW_SQE] = "a630_sqe.fw",
268 [ADRENO_FW_GMU] = "a640_gmu.bin",
271 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
272 .init = a6xx_gpu_init,
273 .zapfw = "a640_zap.mdt",
276 .rev = ADRENO_REV(6, 5, 0, ANY_ID),
280 [ADRENO_FW_SQE] = "a650_sqe.fw",
281 [ADRENO_FW_GMU] = "a650_gmu.bin",
283 .gmem = SZ_1M + SZ_128K,
284 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
285 .init = a6xx_gpu_init,
286 .zapfw = "a650_zap.mdt",
289 .rev = ADRENO_REV(6, 6, 0, ANY_ID),
293 [ADRENO_FW_SQE] = "a660_sqe.fw",
294 [ADRENO_FW_GMU] = "a660_gmu.bin",
296 .gmem = SZ_1M + SZ_512K,
297 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
298 .init = a6xx_gpu_init,
299 .zapfw = "a660_zap.mdt",
302 .rev = ADRENO_REV(6, 3, 5, ANY_ID),
303 .name = "Adreno 7c Gen 3",
305 [ADRENO_FW_SQE] = "a660_sqe.fw",
306 [ADRENO_FW_GMU] = "a660_gmu.bin",
309 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
310 .init = a6xx_gpu_init,
313 .rev = ADRENO_REV(6, 8, 0, ANY_ID),
317 [ADRENO_FW_SQE] = "a630_sqe.fw",
318 [ADRENO_FW_GMU] = "a640_gmu.bin",
321 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
322 .init = a6xx_gpu_init,
323 .zapfw = "a640_zap.mdt",
328 MODULE_FIRMWARE("qcom/a300_pm4.fw");
329 MODULE_FIRMWARE("qcom/a300_pfp.fw");
330 MODULE_FIRMWARE("qcom/a330_pm4.fw");
331 MODULE_FIRMWARE("qcom/a330_pfp.fw");
332 MODULE_FIRMWARE("qcom/a420_pm4.fw");
333 MODULE_FIRMWARE("qcom/a420_pfp.fw");
334 MODULE_FIRMWARE("qcom/a530_pm4.fw");
335 MODULE_FIRMWARE("qcom/a530_pfp.fw");
336 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
337 MODULE_FIRMWARE("qcom/a530_zap.mdt");
338 MODULE_FIRMWARE("qcom/a530_zap.b00");
339 MODULE_FIRMWARE("qcom/a530_zap.b01");
340 MODULE_FIRMWARE("qcom/a530_zap.b02");
341 MODULE_FIRMWARE("qcom/a630_sqe.fw");
342 MODULE_FIRMWARE("qcom/a630_gmu.bin");
343 MODULE_FIRMWARE("qcom/a630_zap.mbn");
345 static inline bool _rev_match(uint8_t entry, uint8_t id)
347 return (entry == ANY_ID) || (entry == id);
350 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
353 return _rev_match(rev1.core, rev2.core) &&
354 _rev_match(rev1.major, rev2.major) &&
355 _rev_match(rev1.minor, rev2.minor) &&
356 _rev_match(rev1.patchid, rev2.patchid);
359 const struct adreno_info *adreno_info(struct adreno_rev rev)
364 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
365 const struct adreno_info *info = &gpulist[i];
366 if (adreno_cmp_rev(info->rev, rev))
373 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
375 struct msm_drm_private *priv = dev->dev_private;
376 struct platform_device *pdev = priv->gpu_pdev;
377 struct msm_gpu *gpu = NULL;
378 struct adreno_gpu *adreno_gpu;
382 gpu = dev_to_gpu(&pdev->dev);
385 dev_err_once(dev->dev, "no GPU device was found\n");
389 adreno_gpu = to_adreno_gpu(gpu);
392 * The number one reason for HW init to fail is if the firmware isn't
393 * loaded yet. Try that first and don't bother continuing on
397 ret = adreno_load_fw(adreno_gpu);
401 /* Make sure pm runtime is active and reset any previous errors */
402 pm_runtime_set_active(&pdev->dev);
404 ret = pm_runtime_get_sync(&pdev->dev);
406 pm_runtime_put_sync(&pdev->dev);
407 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
411 mutex_lock(&dev->struct_mutex);
412 ret = msm_gpu_hw_init(gpu);
413 mutex_unlock(&dev->struct_mutex);
414 pm_runtime_put_autosuspend(&pdev->dev);
416 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
420 #ifdef CONFIG_DEBUG_FS
421 if (gpu->funcs->debugfs_init) {
422 gpu->funcs->debugfs_init(gpu, dev->primary);
423 gpu->funcs->debugfs_init(gpu, dev->render);
430 static void set_gpu_pdev(struct drm_device *dev,
431 struct platform_device *pdev)
433 struct msm_drm_private *priv = dev->dev_private;
434 priv->gpu_pdev = pdev;
437 static int find_chipid(struct device *dev, struct adreno_rev *rev)
439 struct device_node *node = dev->of_node;
444 /* first search the compat strings for qcom,adreno-XYZ.W: */
445 ret = of_property_read_string_index(node, "compatible", 0, &compat);
447 unsigned int r, patch;
449 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
450 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
456 rev->patchid = patch;
462 /* and if that fails, fall back to legacy "qcom,chipid" property: */
463 ret = of_property_read_u32(node, "qcom,chipid", &chipid);
465 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
469 rev->core = (chipid >> 24) & 0xff;
470 rev->major = (chipid >> 16) & 0xff;
471 rev->minor = (chipid >> 8) & 0xff;
472 rev->patchid = (chipid & 0xff);
474 dev_warn(dev, "Using legacy qcom,chipid binding!\n");
475 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
476 rev->core, rev->major, rev->minor, rev->patchid);
481 static int adreno_bind(struct device *dev, struct device *master, void *data)
483 static struct adreno_platform_config config = {};
484 const struct adreno_info *info;
485 struct drm_device *drm = dev_get_drvdata(master);
486 struct msm_drm_private *priv = drm->dev_private;
490 ret = find_chipid(dev, &config.rev);
494 dev->platform_data = &config;
495 set_gpu_pdev(drm, to_platform_device(dev));
497 info = adreno_info(config.rev);
500 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
501 config.rev.core, config.rev.major,
502 config.rev.minor, config.rev.patchid);
506 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
507 config.rev.minor, config.rev.patchid);
509 priv->is_a2xx = config.rev.core == 2;
510 priv->has_cached_coherent = config.rev.core >= 6;
512 gpu = info->init(drm);
514 dev_warn(drm->dev, "failed to load adreno gpu\n");
521 static void adreno_unbind(struct device *dev, struct device *master,
524 struct msm_gpu *gpu = dev_to_gpu(dev);
526 pm_runtime_force_suspend(dev);
527 gpu->funcs->destroy(gpu);
529 set_gpu_pdev(dev_get_drvdata(master), NULL);
532 static const struct component_ops a3xx_ops = {
534 .unbind = adreno_unbind,
537 static void adreno_device_register_headless(void)
539 /* on imx5, we don't have a top-level mdp/dpu node
540 * this creates a dummy node for the driver for that case
542 struct platform_device_info dummy_info = {
552 platform_device_register_full(&dummy_info);
555 static int adreno_probe(struct platform_device *pdev)
560 ret = component_add(&pdev->dev, &a3xx_ops);
564 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
565 adreno_device_register_headless();
570 static int adreno_remove(struct platform_device *pdev)
572 component_del(&pdev->dev, &a3xx_ops);
576 static void adreno_shutdown(struct platform_device *pdev)
578 pm_runtime_force_suspend(&pdev->dev);
581 static const struct of_device_id dt_match[] = {
582 { .compatible = "qcom,adreno" },
583 { .compatible = "qcom,adreno-3xx" },
584 /* for compatibility with imx5 gpu: */
585 { .compatible = "amd,imageon" },
586 /* for backwards compat w/ downstream kgsl DT files: */
587 { .compatible = "qcom,kgsl-3d0" },
592 static int adreno_resume(struct device *dev)
594 struct msm_gpu *gpu = dev_to_gpu(dev);
596 return gpu->funcs->pm_resume(gpu);
599 static int adreno_suspend(struct device *dev)
601 struct msm_gpu *gpu = dev_to_gpu(dev);
603 return gpu->funcs->pm_suspend(gpu);
607 static const struct dev_pm_ops adreno_pm_ops = {
608 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
609 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
612 static struct platform_driver adreno_driver = {
613 .probe = adreno_probe,
614 .remove = adreno_remove,
615 .shutdown = adreno_shutdown,
618 .of_match_table = dt_match,
619 .pm = &adreno_pm_ops,
623 void __init adreno_register(void)
625 platform_driver_register(&adreno_driver);
628 void __exit adreno_unregister(void)
630 platform_driver_unregister(&adreno_driver);