drivers/gpu/drm/msm/adreno/a6xx_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
   3
   4
   5 #include "msm_gem.h"
   6 #include "msm_mmu.h"
   7 #include "msm_gpu_trace.h"
   8 #include "a6xx_gpu.h"
   9 #include "a6xx_gmu.xml.h"
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/devfreq.h>
  13 #include <linux/nvmem-consumer.h>
  14 #include <linux/soc/qcom/llcc-qcom.h>
  15
  16 #define GPU_PAS_ID 13
  17
  18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
  19 {
  20         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
  21         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
  22
  23         /* Check that the GMU is idle */
  24         if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))
  25                 return false;
  26
  27         /* Check tha the CX master is idle */
  28         if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
  29                         ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
  30                 return false;
  31
  32         return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
  33                 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
  34 }
  35
  36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
  37 {
  38         /* wait for CP to drain ringbuffer: */
  39         if (!adreno_idle(gpu, ring))
  40                 return false;
  41
  42         if (spin_until(_a6xx_check_idle(gpu))) {
  43                 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
  44                         gpu->name, __builtin_return_address(0),
  45                         gpu_read(gpu, REG_A6XX_RBBM_STATUS),
  46                         gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
  47                         gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
  48                         gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
  49                 return false;
  50         }
  51
  52         return true;
  53 }
  54
  55 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
  56 {
  57         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
  58         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
  59         uint32_t wptr;
  60         unsigned long flags;
  61
  62         /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */
  63         if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) {
  64                 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
  65
  66                 OUT_PKT7(ring, CP_WHERE_AM_I, 2);
  67                 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));
  68                 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));
  69         }
  70
  71         spin_lock_irqsave(&ring->preempt_lock, flags);
  72
  73         /* Copy the shadow to the actual register */
  74         ring->cur = ring->next;
  75
  76         /* Make sure to wrap wptr if we need to */
  77         wptr = get_wptr(ring);
  78
  79         spin_unlock_irqrestore(&ring->preempt_lock, flags);
  80
  81         /* Make sure everything is posted before making a decision */
  82         mb();
  83
  84         gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
  85 }
  86
  87 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
  88                 u64 iova)
  89 {
  90         OUT_PKT7(ring, CP_REG_TO_MEM, 3);
  91         OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |
  92                 CP_REG_TO_MEM_0_CNT(2) |
  93                 CP_REG_TO_MEM_0_64B);
  94         OUT_RING(ring, lower_32_bits(iova));
  95         OUT_RING(ring, upper_32_bits(iova));
  96 }
  97
  98 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
  99                 struct msm_ringbuffer *ring, struct msm_file_private *ctx)
 100 {
 101         phys_addr_t ttbr;
 102         u32 asid;
 103         u64 memptr = rbmemptr(ring, ttbr0);
 104
 105         if (ctx == a6xx_gpu->cur_ctx)
 106                 return;
 107
 108         if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
 109                 return;
 110
 111         /* Execute the table update */
 112         OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
 113         OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
 114
 115         OUT_RING(ring,
 116                 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
 117                 CP_SMMU_TABLE_UPDATE_1_ASID(asid));
 118         OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
 119         OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
 120
 121         /*
 122          * Write the new TTBR0 to the memstore. This is good for debugging.
 123          */
 124         OUT_PKT7(ring, CP_MEM_WRITE, 4);
 125         OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
 126         OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
 127         OUT_RING(ring, lower_32_bits(ttbr));
 128         OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
 129
 130         /*
 131          * And finally, trigger a uche flush to be sure there isn't anything
 132          * lingering in that part of the GPU
 133          */
 134
 135         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 136         OUT_RING(ring, 0x31);
 137
 138         a6xx_gpu->cur_ctx = ctx;
 139 }
 140
 141 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 142 {
 143         unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
 144         struct msm_drm_private *priv = gpu->dev->dev_private;
 145         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 146         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 147         struct msm_ringbuffer *ring = submit->ring;
 148         unsigned int i;
 149
 150         a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
 151
 152         get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
 153                 rbmemptr_stats(ring, index, cpcycles_start));
 154
 155         /*
 156          * For PM4 the GMU register offsets are calculated from the base of the
 157          * GPU registers so we need to add 0x1a800 to the register value on A630
 158          * to get the right value from PM4.
 159          */
 160         get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
 161                 rbmemptr_stats(ring, index, alwayson_start));
 162
 163         /* Invalidate CCU depth and color */
 164         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 165         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));
 166
 167         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 168         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));
 169
 170         /* Submit the commands */
 171         for (i = 0; i < submit->nr_cmds; i++) {
 172                 switch (submit->cmd[i].type) {
 173                 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
 174                         break;
 175                 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
 176                         if (priv->lastctx == submit->queue->ctx)
 177                                 break;
 178                         fallthrough;
 179                 case MSM_SUBMIT_CMD_BUF:
 180                         OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
 181                         OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
 182                         OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
 183                         OUT_RING(ring, submit->cmd[i].size);
 184                         break;
 185                 }
 186         }
 187
 188         get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
 189                 rbmemptr_stats(ring, index, cpcycles_end));
 190         get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
 191                 rbmemptr_stats(ring, index, alwayson_end));
 192
 193         /* Write the fence to the scratch register */
 194         OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
 195         OUT_RING(ring, submit->seqno);
 196
 197         /*
 198          * Execute a CACHE_FLUSH_TS event. This will ensure that the
 199          * timestamp is written to the memory and then triggers the interrupt
 200          */
 201         OUT_PKT7(ring, CP_EVENT_WRITE, 4);
 202         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |
 203                 CP_EVENT_WRITE_0_IRQ);
 204         OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
 205         OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
 206         OUT_RING(ring, submit->seqno);
 207
 208         trace_msm_gpu_submit_flush(submit,
 209                 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
 210                         REG_A6XX_CP_ALWAYS_ON_COUNTER_HI));
 211
 212         a6xx_flush(gpu, ring);
 213 }
 214
 215 const struct adreno_reglist a630_hwcg[] = {
 216         {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
 217         {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
 218         {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
 219         {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
 220         {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
 221         {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
 222         {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
 223         {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
 224         {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
 225         {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
 226         {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
 227         {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
 228         {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
 229         {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
 230         {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
 231         {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
 232         {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
 233         {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
 234         {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
 235         {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
 236         {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
 237         {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
 238         {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
 239         {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
 240         {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
 241         {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
 242         {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
 243         {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
 244         {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
 245         {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
 246         {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
 247         {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
 248         {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
 249         {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
 250         {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
 251         {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
 252         {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
 253         {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
 254         {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
 255         {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
 256         {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
 257         {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
 258         {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
 259         {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
 260         {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
 261         {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
 262         {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
 263         {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
 264         {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
 265         {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
 266         {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
 267         {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
 268         {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
 269         {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
 270         {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
 271         {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
 272         {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
 273         {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
 274         {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
 275         {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
 276         {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
 277         {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
 278         {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
 279         {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
 280         {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
 281         {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
 282         {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
 283         {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
 284         {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
 285         {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
 286         {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
 287         {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
 288         {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
 289         {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
 290         {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
 291         {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
 292         {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
 293         {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
 294         {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
 295         {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
 296         {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
 297         {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
 298         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
 299         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
 300         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
 301         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
 302         {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
 303         {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
 304         {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
 305         {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
 306         {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
 307         {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
 308         {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
 309         {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
 310         {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
 311         {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
 312         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
 313         {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
 314         {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
 315         {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
 316         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
 317         {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
 318         {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
 319         {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
 320         {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
 321         {},
 322 };
 323
 324 const struct adreno_reglist a640_hwcg[] = {
 325         {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
 326         {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
 327         {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
 328         {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
 329         {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
 330         {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
 331         {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
 332         {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
 333         {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
 334         {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
 335         {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
 336         {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
 337         {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
 338         {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
 339         {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
 340         {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
 341         {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
 342         {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
 343         {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
 344         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
 345         {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
 346         {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
 347         {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
 348         {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
 349         {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
 350         {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
 351         {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
 352         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
 353         {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
 354         {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
 355         {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
 356         {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
 357         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
 358         {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
 359         {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
 360         {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
 361         {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
 362         {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
 363         {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
 364         {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
 365         {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
 366         {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
 367         {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
 368         {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
 369         {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
 370         {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
 371         {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
 372         {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
 373         {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
 374         {},
 375 };
 376
 377 const struct adreno_reglist a650_hwcg[] = {
 378         {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
 379         {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
 380         {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
 381         {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
 382         {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
 383         {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
 384         {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
 385         {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
 386         {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
 387         {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
 388         {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
 389         {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
 390         {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
 391         {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
 392         {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
 393         {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
 394         {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
 395         {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
 396         {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
 397         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
 398         {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
 399         {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
 400         {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
 401         {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
 402         {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
 403         {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
 404         {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
 405         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
 406         {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
 407         {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
 408         {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
 409         {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
 410         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
 411         {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
 412         {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
 413         {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
 414         {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
 415         {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
 416         {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
 417         {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
 418         {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
 419         {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
 420         {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
 421         {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
 422         {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
 423         {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
 424         {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
 425         {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
 426         {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
 427         {},
 428 };
 429
 430 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
 431 {
 432         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 433         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 434         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 435         const struct adreno_reglist *reg;
 436         unsigned int i;
 437         u32 val, clock_cntl_on;
 438
 439         if (!adreno_gpu->info->hwcg)
 440                 return;
 441
 442         if (adreno_is_a630(adreno_gpu))
 443                 clock_cntl_on = 0x8aa8aa02;
 444         else
 445                 clock_cntl_on = 0x8aa8aa82;
 446
 447         val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
 448
 449         /* Don't re-program the registers if they are already correct */
 450         if ((!state && !val) || (state && (val == clock_cntl_on)))
 451                 return;
 452
 453         /* Disable SP clock before programming HWCG registers */
 454         gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
 455
 456         for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
 457                 gpu_write(gpu, reg->offset, state ? reg->value : 0);
 458
 459         /* Enable SP clock */
 460         gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
 461
 462         gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
 463 }
 464
 465 /* For a615, a616, a618, A619, a630, a640 and a680 */
 466 static const u32 a6xx_protect[] = {
 467         A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
 468         A6XX_PROTECT_RDONLY(0x00501, 0x0005),
 469         A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
 470         A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
 471         A6XX_PROTECT_NORDWR(0x00510, 0x0000),
 472         A6XX_PROTECT_NORDWR(0x00534, 0x0000),
 473         A6XX_PROTECT_NORDWR(0x00800, 0x0082),
 474         A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
 475         A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
 476         A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
 477         A6XX_PROTECT_NORDWR(0x00900, 0x004d),
 478         A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
 479         A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
 480         A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
 481         A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
 482         A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
 483         A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
 484         A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
 485         A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
 486         A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
 487         A6XX_PROTECT_NORDWR(0x09624, 0x01db),
 488         A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
 489         A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
 490         A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
 491         A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
 492         A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
 493         A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
 494         A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
 495         A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
 496         A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
 497         A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
 498         A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
 499 };
 500
 501 /* These are for a620 and a650 */
 502 static const u32 a650_protect[] = {
 503         A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
 504         A6XX_PROTECT_RDONLY(0x00501, 0x0005),
 505         A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
 506         A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
 507         A6XX_PROTECT_NORDWR(0x00510, 0x0000),
 508         A6XX_PROTECT_NORDWR(0x00534, 0x0000),
 509         A6XX_PROTECT_NORDWR(0x00800, 0x0082),
 510         A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
 511         A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
 512         A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
 513         A6XX_PROTECT_NORDWR(0x00900, 0x004d),
 514         A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
 515         A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
 516         A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
 517         A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
 518         A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
 519         A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
 520         A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
 521         A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
 522         A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
 523         A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
 524         A6XX_PROTECT_NORDWR(0x09624, 0x01db),
 525         A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
 526         A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
 527         A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
 528         A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
 529         A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
 530         A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
 531         A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
 532         A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
 533         A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
 534         A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
 535         A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
 536         A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
 537         A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
 538         A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
 539         A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
 540         A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
 541         A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
 542 };
 543
 544 static void a6xx_set_cp_protect(struct msm_gpu *gpu)
 545 {
 546         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 547         const u32 *regs = a6xx_protect;
 548         unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32;
 549
 550         BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
 551         BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
 552
 553         if (adreno_is_a650(adreno_gpu)) {
 554                 regs = a650_protect;
 555                 count = ARRAY_SIZE(a650_protect);
 556                 count_max = 48;
 557         }
 558
 559         /*
 560          * Enable access protection to privileged registers, fault on an access
 561          * protect violation and select the last span to protect from the start
 562          * address all the way to the end of the register address space
 563          */
 564         gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
 565
 566         for (i = 0; i < count - 1; i++)
 567                 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
 568         /* last CP_PROTECT to have "infinite" length on the last entry */
 569         gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
 570 }
 571
 572 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 573 {
 574         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 575         u32 lower_bit = 2;
 576         u32 amsbc = 0;
 577         u32 rgb565_predicator = 0;
 578         u32 uavflagprd_inv = 0;
 579
 580         /* a618 is using the hw default values */
 581         if (adreno_is_a618(adreno_gpu))
 582                 return;
 583
 584         if (adreno_is_a640(adreno_gpu))
 585                 amsbc = 1;
 586
 587         if (adreno_is_a650(adreno_gpu)) {
 588                 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
 589                 lower_bit = 3;
 590                 amsbc = 1;
 591                 rgb565_predicator = 1;
 592                 uavflagprd_inv = 2;
 593         }
 594
 595         gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
 596                 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
 597         gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
 598         gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
 599                 uavflagprd_inv << 4 | lower_bit << 1);
 600         gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
 601 }
 602
 603 static int a6xx_cp_init(struct msm_gpu *gpu)
 604 {
 605         struct msm_ringbuffer *ring = gpu->rb[0];
 606
 607         OUT_PKT7(ring, CP_ME_INIT, 8);
 608
 609         OUT_RING(ring, 0x0000002f);
 610
 611         /* Enable multiple hardware contexts */
 612         OUT_RING(ring, 0x00000003);
 613
 614         /* Enable error detection */
 615         OUT_RING(ring, 0x20000000);
 616
 617         /* Don't enable header dump */
 618         OUT_RING(ring, 0x00000000);
 619         OUT_RING(ring, 0x00000000);
 620
 621         /* No workarounds enabled */
 622         OUT_RING(ring, 0x00000000);
 623
 624         /* Pad rest of the cmds with 0's */
 625         OUT_RING(ring, 0x00000000);
 626         OUT_RING(ring, 0x00000000);
 627
 628         a6xx_flush(gpu, ring);
 629         return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
 630 }
 631
 632 /*
 633  * Check that the microcode version is new enough to include several key
 634  * security fixes. Return true if the ucode is safe.
 635  */
 636 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
 637                 struct drm_gem_object *obj)
 638 {
 639         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 640         struct msm_gpu *gpu = &adreno_gpu->base;
 641         u32 *buf = msm_gem_get_vaddr(obj);
 642         bool ret = false;
 643
 644         if (IS_ERR(buf))
 645                 return false;
 646
 647         /*
 648          * Targets up to a640 (a618, a630 and a640) need to check for a
 649          * microcode version that is patched to support the whereami opcode or
 650          * one that is new enough to include it by default.
 651          */
 652         if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) ||
 653                 adreno_is_a640(adreno_gpu)) {
 654                 /*
 655                  * If the lowest nibble is 0xa that is an indication that this
 656                  * microcode has been patched. The actual version is in dword
 657                  * [3] but we only care about the patchlevel which is the lowest
 658                  * nibble of dword [3]
 659                  *
 660                  * Otherwise check that the firmware is greater than or equal
 661                  * to 1.90 which was the first version that had this fix built
 662                  * in
 663                  */
 664                 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) ||
 665                         (buf[0] & 0xfff) >= 0x190) {
 666                         a6xx_gpu->has_whereami = true;
 667                         ret = true;
 668                         goto out;
 669                 }
 670
 671                 DRM_DEV_ERROR(&gpu->pdev->dev,
 672                         "a630 SQE ucode is too old. Have version %x need at least %x\n",
 673                         buf[0] & 0xfff, 0x190);
 674         }  else {
 675                 /*
 676                  * a650 tier targets don't need whereami but still need to be
 677                  * equal to or newer than 0.95 for other security fixes
 678                  */
 679                 if (adreno_is_a650(adreno_gpu)) {
 680                         if ((buf[0] & 0xfff) >= 0x095) {
 681                                 ret = true;
 682                                 goto out;
 683                         }
 684
 685                         DRM_DEV_ERROR(&gpu->pdev->dev,
 686                                 "a650 SQE ucode is too old. Have version %x need at least %x\n",
 687                                 buf[0] & 0xfff, 0x095);
 688                 }
 689
 690                 /*
 691                  * When a660 is added those targets should return true here
 692                  * since those have all the critical security fixes built in
 693                  * from the start
 694                  */
 695         }
 696 out:
 697         msm_gem_put_vaddr(obj);
 698         return ret;
 699 }
 700
 701 static int a6xx_ucode_init(struct msm_gpu *gpu)
 702 {
 703         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 704         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 705
 706         if (!a6xx_gpu->sqe_bo) {
 707                 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
 708                         adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);
 709
 710                 if (IS_ERR(a6xx_gpu->sqe_bo)) {
 711                         int ret = PTR_ERR(a6xx_gpu->sqe_bo);
 712
 713                         a6xx_gpu->sqe_bo = NULL;
 714                         DRM_DEV_ERROR(&gpu->pdev->dev,
 715                                 "Could not allocate SQE ucode: %d\n", ret);
 716
 717                         return ret;
 718                 }
 719
 720                 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
 721                 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {
 722                         msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
 723                         drm_gem_object_put(a6xx_gpu->sqe_bo);
 724
 725                         a6xx_gpu->sqe_bo = NULL;
 726                         return -EPERM;
 727                 }
 728         }
 729
 730         gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
 731                 REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova);
 732
 733         return 0;
 734 }
 735
 736 static int a6xx_zap_shader_init(struct msm_gpu *gpu)
 737 {
 738         static bool loaded;
 739         int ret;
 740
 741         if (loaded)
 742                 return 0;
 743
 744         ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
 745
 746         loaded = !ret;
 747         return ret;
 748 }
 749
 750 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
 751           A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
 752           A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
 753           A6XX_RBBM_INT_0_MASK_CP_IB2 | \
 754           A6XX_RBBM_INT_0_MASK_CP_IB1 | \
 755           A6XX_RBBM_INT_0_MASK_CP_RB | \
 756           A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
 757           A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
 758           A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
 759           A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
 760           A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
 761
 762 static int a6xx_hw_init(struct msm_gpu *gpu)
 763 {
 764         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 765         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 766         int ret;
 767
 768         /* Make sure the GMU keeps the GPU on while we set it up */
 769         a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
 770
 771         gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
 772
 773         /*
 774          * Disable the trusted memory range - we don't actually supported secure
 775          * memory rendering at this point in time and we don't want to block off
 776          * part of the virtual memory space.
 777          */
 778         gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
 779                 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
 780         gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
 781
 782         /* Turn on 64 bit addressing for all blocks */
 783         gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
 784         gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
 785         gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
 786         gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
 787         gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
 788         gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
 789         gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
 790         gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
 791         gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
 792         gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
 793         gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
 794         gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
 795
 796         /* enable hardware clockgating */
 797         a6xx_set_hwcg(gpu, true);
 798
 799         /* VBIF/GBIF start*/
 800         if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
 801                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
 802                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
 803                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
 804                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
 805                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
 806                 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
 807         } else {
 808                 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
 809         }
 810
 811         if (adreno_is_a630(adreno_gpu))
 812                 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
 813
 814         /* Make all blocks contribute to the GPU BUSY perf counter */
 815         gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
 816
 817         /* Disable L2 bypass in the UCHE */
 818         gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
 819         gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
 820         gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
 821         gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
 822         gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
 823         gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
 824
 825         if (!adreno_is_a650(adreno_gpu)) {
 826                 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
 827                 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
 828                         REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
 829
 830                 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
 831                         REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
 832                         0x00100000 + adreno_gpu->gmem - 1);
 833         }
 834
 835         gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
 836         gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
 837
 838         if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
 839                 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
 840         else
 841                 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
 842         gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
 843
 844         /* Setting the mem pool size */
 845         gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
 846
 847         /* Setting the primFifo thresholds default values */
 848         if (adreno_is_a650(adreno_gpu))
 849                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
 850         else if (adreno_is_a640(adreno_gpu))
 851                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
 852         else
 853                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
 854
 855         /* Set the AHB default slave response to "ERROR" */
 856         gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
 857
 858         /* Turn on performance counters */
 859         gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
 860
 861         /* Select CP0 to always count cycles */
 862         gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
 863
 864         a6xx_set_ubwc_config(gpu);
 865
 866         /* Enable fault detection */
 867         gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
 868                 (1 << 30) | 0x1fffff);
 869
 870         gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
 871
 872         /* Set weights for bicubic filtering */
 873         if (adreno_is_a650(adreno_gpu)) {
 874                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
 875                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
 876                         0x3fe05ff4);
 877                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
 878                         0x3fa0ebee);
 879                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
 880                         0x3f5193ed);
 881                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
 882                         0x3f0243f0);
 883         }
 884
 885         /* Protect registers from the CP */
 886         a6xx_set_cp_protect(gpu);
 887
 888         /* Enable expanded apriv for targets that support it */
 889         if (gpu->hw_apriv) {
 890                 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
 891                         (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
 892         }
 893
 894         /* Enable interrupts */
 895         gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
 896
 897         ret = adreno_hw_init(gpu);
 898         if (ret)
 899                 goto out;
 900
 901         ret = a6xx_ucode_init(gpu);
 902         if (ret)
 903                 goto out;
 904
 905         /* Set the ringbuffer address */
 906         gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
 907                 gpu->rb[0]->iova);
 908
 909         /* Targets that support extended APRIV can use the RPTR shadow from
 910          * hardware but all the other ones need to disable the feature. Targets
 911          * that support the WHERE_AM_I opcode can use that instead
 912          */
 913         if (adreno_gpu->base.hw_apriv)
 914                 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
 915         else
 916                 gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
 917                         MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
 918
 919         /*
 920          * Expanded APRIV and targets that support WHERE_AM_I both need a
 921          * privileged buffer to store the RPTR shadow
 922          */
 923
 924         if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) {
 925                 if (!a6xx_gpu->shadow_bo) {
 926                         a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev,
 927                                 sizeof(u32) * gpu->nr_rings,
 928                                 MSM_BO_UNCACHED | MSM_BO_MAP_PRIV,
 929                                 gpu->aspace, &a6xx_gpu->shadow_bo,
 930                                 &a6xx_gpu->shadow_iova);
 931
 932                         if (IS_ERR(a6xx_gpu->shadow))
 933                                 return PTR_ERR(a6xx_gpu->shadow);
 934                 }
 935
 936                 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO,
 937                         REG_A6XX_CP_RB_RPTR_ADDR_HI,
 938                         shadowptr(a6xx_gpu, gpu->rb[0]));
 939         }
 940
 941         /* Always come up on rb 0 */
 942         a6xx_gpu->cur_ring = gpu->rb[0];
 943
 944         a6xx_gpu->cur_ctx = NULL;
 945
 946         /* Enable the SQE_to start the CP engine */
 947         gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
 948
 949         ret = a6xx_cp_init(gpu);
 950         if (ret)
 951                 goto out;
 952
 953         /*
 954          * Try to load a zap shader into the secure world. If successful
 955          * we can use the CP to switch out of secure mode. If not then we
 956          * have no resource but to try to switch ourselves out manually. If we
 957          * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
 958          * be blocked and a permissions violation will soon follow.
 959          */
 960         ret = a6xx_zap_shader_init(gpu);
 961         if (!ret) {
 962                 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
 963                 OUT_RING(gpu->rb[0], 0x00000000);
 964
 965                 a6xx_flush(gpu, gpu->rb[0]);
 966                 if (!a6xx_idle(gpu, gpu->rb[0]))
 967                         return -EINVAL;
 968         } else if (ret == -ENODEV) {
 969                 /*
 970                  * This device does not use zap shader (but print a warning
 971                  * just in case someone got their dt wrong.. hopefully they
 972                  * have a debug UART to realize the error of their ways...
 973                  * if you mess this up you are about to crash horribly)
 974                  */
 975                 dev_warn_once(gpu->dev->dev,
 976                         "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
 977                 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
 978                 ret = 0;
 979         } else {
 980                 return ret;
 981         }
 982
 983 out:
 984         /*
 985          * Tell the GMU that we are done touching the GPU and it can start power
 986          * management
 987          */
 988         a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
 989
 990         if (a6xx_gpu->gmu.legacy) {
 991                 /* Take the GMU out of its special boot mode */
 992                 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
 993         }
 994
 995         return ret;
 996 }
 997
 998 static void a6xx_dump(struct msm_gpu *gpu)
 999 {
1000         DRM_DEV_INFO(&gpu->pdev->dev, "status:   %08x\n",
1001                         gpu_read(gpu, REG_A6XX_RBBM_STATUS));
1002         adreno_dump(gpu);
1003 }
1004
1005 #define VBIF_RESET_ACK_TIMEOUT  100
1006 #define VBIF_RESET_ACK_MASK     0x00f0
1007
1008 static void a6xx_recover(struct msm_gpu *gpu)
1009 {
1010         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1011         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1012         int i;
1013
1014         adreno_dump_info(gpu);
1015
1016         for (i = 0; i < 8; i++)
1017                 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
1018                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
1019
1020         if (hang_debug)
1021                 a6xx_dump(gpu);
1022
1023         /*
1024          * Turn off keep alive that might have been enabled by the hang
1025          * interrupt
1026          */
1027         gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
1028
1029         gpu->funcs->pm_suspend(gpu);
1030         gpu->funcs->pm_resume(gpu);
1031
1032         msm_gpu_hw_init(gpu);
1033 }
1034
1035 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags)
1036 {
1037         struct msm_gpu *gpu = arg;
1038
1039         pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
1040                         iova, flags,
1041                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1042                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1043                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1044                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1045
1046         return -EFAULT;
1047 }
1048
1049 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
1050 {
1051         u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
1052
1053         if (status & A6XX_CP_INT_CP_OPCODE_ERROR) {
1054                 u32 val;
1055
1056                 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
1057                 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
1058                 dev_err_ratelimited(&gpu->pdev->dev,
1059                         "CP | opcode error | possible opcode=0x%8.8X\n",
1060                         val);
1061         }
1062
1063         if (status & A6XX_CP_INT_CP_UCODE_ERROR)
1064                 dev_err_ratelimited(&gpu->pdev->dev,
1065                         "CP ucode error interrupt\n");
1066
1067         if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR)
1068                 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
1069                         gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
1070
1071         if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) {
1072                 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
1073
1074                 dev_err_ratelimited(&gpu->pdev->dev,
1075                         "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n",
1076                         val & (1 << 20) ? "READ" : "WRITE",
1077                         (val & 0x3ffff), val);
1078         }
1079
1080         if (status & A6XX_CP_INT_CP_AHB_ERROR)
1081                 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
1082
1083         if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR)
1084                 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
1085
1086         if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR)
1087                 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
1088
1089 }
1090
1091 static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
1092 {
1093         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1094         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1095         struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1096
1097         /*
1098          * Force the GPU to stay on until after we finish
1099          * collecting information
1100          */
1101         gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
1102
1103         DRM_DEV_ERROR(&gpu->pdev->dev,
1104                 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
1105                 ring ? ring->id : -1, ring ? ring->seqno : 0,
1106                 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
1107                 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
1108                 gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1109                 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
1110                 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
1111                 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
1112                 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
1113
1114         /* Turn off the hangcheck timer to keep it from bothering us */
1115         del_timer(&gpu->hangcheck_timer);
1116
1117         kthread_queue_work(gpu->worker, &gpu->recover_work);
1118 }
1119
1120 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
1121 {
1122         u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
1123
1124         gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
1125
1126         if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
1127                 a6xx_fault_detect_irq(gpu);
1128
1129         if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
1130                 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
1131
1132         if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
1133                 a6xx_cp_hw_err_irq(gpu);
1134
1135         if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
1136                 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
1137
1138         if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
1139                 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
1140
1141         if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
1142                 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
1143
1144         if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
1145                 msm_gpu_retire(gpu);
1146
1147         return IRQ_HANDLED;
1148 }
1149
1150 static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
1151 {
1152         return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
1153 }
1154
1155 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
1156 {
1157         return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
1158 }
1159
1160 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
1161 {
1162         llcc_slice_deactivate(a6xx_gpu->llc_slice);
1163         llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
1164 }
1165
1166 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
1167 {
1168         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1169         struct msm_gpu *gpu = &adreno_gpu->base;
1170         u32 cntl1_regval = 0;
1171
1172         if (IS_ERR(a6xx_gpu->llc_mmio))
1173                 return;
1174
1175         if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
1176                 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
1177
1178                 gpu_scid &= 0x1f;
1179                 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) |
1180                                (gpu_scid << 15) | (gpu_scid << 20);
1181         }
1182
1183         /*
1184          * For targets with a MMU500, activate the slice but don't program the
1185          * register.  The XBL will take care of that.
1186          */
1187         if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
1188                 if (!a6xx_gpu->have_mmu500) {
1189                         u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
1190
1191                         gpuhtw_scid &= 0x1f;
1192                         cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
1193                 }
1194         }
1195
1196         if (cntl1_regval) {
1197                 /*
1198                  * Program the slice IDs for the various GPU blocks and GPU MMU
1199                  * pagetables
1200                  */
1201                 if (a6xx_gpu->have_mmu500)
1202                         gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0),
1203                                 cntl1_regval);
1204                 else {
1205                         a6xx_llc_write(a6xx_gpu,
1206                                 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
1207
1208                         /*
1209                          * Program cacheability overrides to not allocate cache
1210                          * lines on a write miss
1211                          */
1212                         a6xx_llc_rmw(a6xx_gpu,
1213                                 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
1214                 }
1215         }
1216 }
1217
1218 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
1219 {
1220         llcc_slice_putd(a6xx_gpu->llc_slice);
1221         llcc_slice_putd(a6xx_gpu->htw_llc_slice);
1222 }
1223
1224 static void a6xx_llc_slices_init(struct platform_device *pdev,
1225                 struct a6xx_gpu *a6xx_gpu)
1226 {
1227         struct device_node *phandle;
1228
1229         /*
1230          * There is a different programming path for targets with an mmu500
1231          * attached, so detect if that is the case
1232          */
1233         phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);
1234         a6xx_gpu->have_mmu500 = (phandle &&
1235                 of_device_is_compatible(phandle, "arm,mmu-500"));
1236         of_node_put(phandle);
1237
1238         if (a6xx_gpu->have_mmu500)
1239                 a6xx_gpu->llc_mmio = NULL;
1240         else
1241                 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
1242
1243         a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
1244         a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
1245
1246         if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1247                 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
1248 }
1249
1250 static int a6xx_pm_resume(struct msm_gpu *gpu)
1251 {
1252         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1253         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1254         int ret;
1255
1256         gpu->needs_hw_init = true;
1257
1258         trace_msm_gpu_resume(0);
1259
1260         ret = a6xx_gmu_resume(a6xx_gpu);
1261         if (ret)
1262                 return ret;
1263
1264         msm_gpu_resume_devfreq(gpu);
1265
1266         a6xx_llc_activate(a6xx_gpu);
1267
1268         return 0;
1269 }
1270
1271 static int a6xx_pm_suspend(struct msm_gpu *gpu)
1272 {
1273         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1274         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1275         int i, ret;
1276
1277         trace_msm_gpu_suspend(0);
1278
1279         a6xx_llc_deactivate(a6xx_gpu);
1280
1281         devfreq_suspend_device(gpu->devfreq.devfreq);
1282
1283         ret = a6xx_gmu_stop(a6xx_gpu);
1284         if (ret)
1285                 return ret;
1286
1287         if (a6xx_gpu->shadow_bo)
1288                 for (i = 0; i < gpu->nr_rings; i++)
1289                         a6xx_gpu->shadow[i] = 0;
1290
1291         return 0;
1292 }
1293
1294 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
1295 {
1296         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1297         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1298         static DEFINE_MUTEX(perfcounter_oob);
1299
1300         mutex_lock(&perfcounter_oob);
1301
1302         /* Force the GPU power on so we can read this register */
1303         a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1304
1305         *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
1306                 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);
1307
1308         a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1309         mutex_unlock(&perfcounter_oob);
1310         return 0;
1311 }
1312
1313 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
1314 {
1315         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1316         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1317
1318         return a6xx_gpu->cur_ring;
1319 }
1320
1321 static void a6xx_destroy(struct msm_gpu *gpu)
1322 {
1323         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1324         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1325
1326         if (a6xx_gpu->sqe_bo) {
1327                 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
1328                 drm_gem_object_put(a6xx_gpu->sqe_bo);
1329         }
1330
1331         if (a6xx_gpu->shadow_bo) {
1332                 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
1333                 drm_gem_object_put(a6xx_gpu->shadow_bo);
1334         }
1335
1336         a6xx_llc_slices_destroy(a6xx_gpu);
1337
1338         a6xx_gmu_remove(a6xx_gpu);
1339
1340         adreno_gpu_cleanup(adreno_gpu);
1341
1342         if (a6xx_gpu->opp_table)
1343                 dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table);
1344
1345         kfree(a6xx_gpu);
1346 }
1347
1348 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
1349 {
1350         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1351         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1352         u64 busy_cycles, busy_time;
1353
1354
1355         /* Only read the gpu busy if the hardware is already active */
1356         if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
1357                 return 0;
1358
1359         busy_cycles = gmu_read64(&a6xx_gpu->gmu,
1360                         REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
1361                         REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
1362
1363         busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
1364         do_div(busy_time, 192);
1365
1366         gpu->devfreq.busy_cycles = busy_cycles;
1367
1368         pm_runtime_put(a6xx_gpu->gmu.dev);
1369
1370         if (WARN_ON(busy_time > ~0LU))
1371                 return ~0LU;
1372
1373         return (unsigned long)busy_time;
1374 }
1375
1376 static struct msm_gem_address_space *
1377 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
1378 {
1379         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1380         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1381         struct iommu_domain *iommu;
1382         struct msm_mmu *mmu;
1383         struct msm_gem_address_space *aspace;
1384         u64 start, size;
1385
1386         iommu = iommu_domain_alloc(&platform_bus_type);
1387         if (!iommu)
1388                 return NULL;
1389
1390         /*
1391          * This allows GPU to set the bus attributes required to use system
1392          * cache on behalf of the iommu page table walker.
1393          */
1394         if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1395                 adreno_set_llc_attributes(iommu);
1396
1397         mmu = msm_iommu_new(&pdev->dev, iommu);
1398         if (IS_ERR(mmu)) {
1399                 iommu_domain_free(iommu);
1400                 return ERR_CAST(mmu);
1401         }
1402
1403         /*
1404          * Use the aperture start or SZ_16M, whichever is greater. This will
1405          * ensure that we align with the allocated pagetable range while still
1406          * allowing room in the lower 32 bits for GMEM and whatnot
1407          */
1408         start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
1409         size = iommu->geometry.aperture_end - start + 1;
1410
1411         aspace = msm_gem_address_space_create(mmu, "gpu",
1412                 start & GENMASK_ULL(48, 0), size);
1413
1414         if (IS_ERR(aspace) && !IS_ERR(mmu))
1415                 mmu->funcs->destroy(mmu);
1416
1417         return aspace;
1418 }
1419
1420 static struct msm_gem_address_space *
1421 a6xx_create_private_address_space(struct msm_gpu *gpu)
1422 {
1423         struct msm_mmu *mmu;
1424
1425         mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
1426
1427         if (IS_ERR(mmu))
1428                 return ERR_CAST(mmu);
1429
1430         return msm_gem_address_space_create(mmu,
1431                 "gpu", 0x100000000ULL, 0x1ffffffffULL);
1432 }
1433
1434 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
1435 {
1436         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1437         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1438
1439         if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
1440                 return a6xx_gpu->shadow[ring->id];
1441
1442         return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);
1443 }
1444
1445 static u32 a618_get_speed_bin(u32 fuse)
1446 {
1447         if (fuse == 0)
1448                 return 0;
1449         else if (fuse == 169)
1450                 return 1;
1451         else if (fuse == 174)
1452                 return 2;
1453
1454         return UINT_MAX;
1455 }
1456
1457 static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse)
1458 {
1459         u32 val = UINT_MAX;
1460
1461         if (revn == 618)
1462                 val = a618_get_speed_bin(fuse);
1463
1464         if (val == UINT_MAX) {
1465                 DRM_DEV_ERROR(dev,
1466                         "missing support for speed-bin: %u. Some OPPs may not be supported by hardware",
1467                         fuse);
1468                 return UINT_MAX;
1469         }
1470
1471         return (1 << val);
1472 }
1473
1474 static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
1475                 u32 revn)
1476 {
1477         struct opp_table *opp_table;
1478         u32 supp_hw = UINT_MAX;
1479         u16 speedbin;
1480         int ret;
1481
1482         ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin);
1483         /*
1484          * -ENOENT means that the platform doesn't support speedbin which is
1485          * fine
1486          */
1487         if (ret == -ENOENT) {
1488                 return 0;
1489         } else if (ret) {
1490                 DRM_DEV_ERROR(dev,
1491                               "failed to read speed-bin (%d). Some OPPs may not be supported by hardware",
1492                               ret);
1493                 goto done;
1494         }
1495         speedbin = le16_to_cpu(speedbin);
1496
1497         supp_hw = fuse_to_supp_hw(dev, revn, speedbin);
1498
1499 done:
1500         opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1501         if (IS_ERR(opp_table))
1502                 return PTR_ERR(opp_table);
1503
1504         a6xx_gpu->opp_table = opp_table;
1505         return 0;
1506 }
1507
1508 static const struct adreno_gpu_funcs funcs = {
1509         .base = {
1510                 .get_param = adreno_get_param,
1511                 .hw_init = a6xx_hw_init,
1512                 .pm_suspend = a6xx_pm_suspend,
1513                 .pm_resume = a6xx_pm_resume,
1514                 .recover = a6xx_recover,
1515                 .submit = a6xx_submit,
1516                 .active_ring = a6xx_active_ring,
1517                 .irq = a6xx_irq,
1518                 .destroy = a6xx_destroy,
1519 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1520                 .show = a6xx_show,
1521 #endif
1522                 .gpu_busy = a6xx_gpu_busy,
1523                 .gpu_get_freq = a6xx_gmu_get_freq,
1524                 .gpu_set_freq = a6xx_gmu_set_freq,
1525 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1526                 .gpu_state_get = a6xx_gpu_state_get,
1527                 .gpu_state_put = a6xx_gpu_state_put,
1528 #endif
1529                 .create_address_space = a6xx_create_address_space,
1530                 .create_private_address_space = a6xx_create_private_address_space,
1531                 .get_rptr = a6xx_get_rptr,
1532         },
1533         .get_timestamp = a6xx_get_timestamp,
1534 };
1535
1536 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
1537 {
1538         struct msm_drm_private *priv = dev->dev_private;
1539         struct platform_device *pdev = priv->gpu_pdev;
1540         struct adreno_platform_config *config = pdev->dev.platform_data;
1541         const struct adreno_info *info;
1542         struct device_node *node;
1543         struct a6xx_gpu *a6xx_gpu;
1544         struct adreno_gpu *adreno_gpu;
1545         struct msm_gpu *gpu;
1546         int ret;
1547
1548         a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
1549         if (!a6xx_gpu)
1550                 return ERR_PTR(-ENOMEM);
1551
1552         adreno_gpu = &a6xx_gpu->base;
1553         gpu = &adreno_gpu->base;
1554
1555         adreno_gpu->registers = NULL;
1556
1557         /*
1558          * We need to know the platform type before calling into adreno_gpu_init
1559          * so that the hw_apriv flag can be correctly set. Snoop into the info
1560          * and grab the revision number
1561          */
1562         info = adreno_info(config->rev);
1563
1564         if (info && info->revn == 650)
1565                 adreno_gpu->base.hw_apriv = true;
1566
1567         a6xx_llc_slices_init(pdev, a6xx_gpu);
1568
1569         ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn);
1570         if (ret) {
1571                 a6xx_destroy(&(a6xx_gpu->base.base));
1572                 return ERR_PTR(ret);
1573         }
1574
1575         ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
1576         if (ret) {
1577                 a6xx_destroy(&(a6xx_gpu->base.base));
1578                 return ERR_PTR(ret);
1579         }
1580
1581         /* Check if there is a GMU phandle and set it up */
1582         node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
1583
1584         /* FIXME: How do we gracefully handle this? */
1585         BUG_ON(!node);
1586
1587         ret = a6xx_gmu_init(a6xx_gpu, node);
1588         if (ret) {
1589                 a6xx_destroy(&(a6xx_gpu->base.base));
1590                 return ERR_PTR(ret);
1591         }
1592
1593         if (gpu->aspace)
1594                 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
1595                                 a6xx_fault_handler);
1596
1597         return gpu;
1598 }