drivers/gpu/drm/msm/adreno/a6xx_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
   3
   4
   5 #include "msm_gem.h"
   6 #include "msm_mmu.h"
   7 #include "msm_gpu_trace.h"
   8 #include "a6xx_gpu.h"
   9 #include "a6xx_gmu.xml.h"
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/devfreq.h>
  13 #include <linux/nvmem-consumer.h>
  14 #include <linux/soc/qcom/llcc-qcom.h>
  15
  16 #define GPU_PAS_ID 13
  17
  18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
  19 {
  20         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
  21         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
  22
  23         /* Check that the GMU is idle */
  24         if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))
  25                 return false;
  26
  27         /* Check tha the CX master is idle */
  28         if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
  29                         ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
  30                 return false;
  31
  32         return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
  33                 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
  34 }
  35
  36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
  37 {
  38         /* wait for CP to drain ringbuffer: */
  39         if (!adreno_idle(gpu, ring))
  40                 return false;
  41
  42         if (spin_until(_a6xx_check_idle(gpu))) {
  43                 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
  44                         gpu->name, __builtin_return_address(0),
  45                         gpu_read(gpu, REG_A6XX_RBBM_STATUS),
  46                         gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
  47                         gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
  48                         gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
  49                 return false;
  50         }
  51
  52         return true;
  53 }
  54
  55 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
  56 {
  57         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
  58         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
  59
  60         /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */
  61         if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) {
  62                 OUT_PKT7(ring, CP_WHERE_AM_I, 2);
  63                 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));
  64                 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));
  65         }
  66 }
  67
  68 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
  69 {
  70         uint32_t wptr;
  71         unsigned long flags;
  72
  73         update_shadow_rptr(gpu, ring);
  74
  75         spin_lock_irqsave(&ring->preempt_lock, flags);
  76
  77         /* Copy the shadow to the actual register */
  78         ring->cur = ring->next;
  79
  80         /* Make sure to wrap wptr if we need to */
  81         wptr = get_wptr(ring);
  82
  83         spin_unlock_irqrestore(&ring->preempt_lock, flags);
  84
  85         /* Make sure everything is posted before making a decision */
  86         mb();
  87
  88         gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
  89 }
  90
  91 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
  92                 u64 iova)
  93 {
  94         OUT_PKT7(ring, CP_REG_TO_MEM, 3);
  95         OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |
  96                 CP_REG_TO_MEM_0_CNT(2) |
  97                 CP_REG_TO_MEM_0_64B);
  98         OUT_RING(ring, lower_32_bits(iova));
  99         OUT_RING(ring, upper_32_bits(iova));
 100 }
 101
 102 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
 103                 struct msm_ringbuffer *ring, struct msm_file_private *ctx)
 104 {
 105         phys_addr_t ttbr;
 106         u32 asid;
 107         u64 memptr = rbmemptr(ring, ttbr0);
 108
 109         if (ctx == a6xx_gpu->cur_ctx)
 110                 return;
 111
 112         if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
 113                 return;
 114
 115         /* Execute the table update */
 116         OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
 117         OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
 118
 119         OUT_RING(ring,
 120                 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
 121                 CP_SMMU_TABLE_UPDATE_1_ASID(asid));
 122         OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
 123         OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
 124
 125         /*
 126          * Write the new TTBR0 to the memstore. This is good for debugging.
 127          */
 128         OUT_PKT7(ring, CP_MEM_WRITE, 4);
 129         OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
 130         OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
 131         OUT_RING(ring, lower_32_bits(ttbr));
 132         OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
 133
 134         /*
 135          * And finally, trigger a uche flush to be sure there isn't anything
 136          * lingering in that part of the GPU
 137          */
 138
 139         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 140         OUT_RING(ring, 0x31);
 141
 142         a6xx_gpu->cur_ctx = ctx;
 143 }
 144
 145 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 146 {
 147         unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
 148         struct msm_drm_private *priv = gpu->dev->dev_private;
 149         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 150         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 151         struct msm_ringbuffer *ring = submit->ring;
 152         unsigned int i, ibs = 0;
 153
 154         a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
 155
 156         get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
 157                 rbmemptr_stats(ring, index, cpcycles_start));
 158
 159         /*
 160          * For PM4 the GMU register offsets are calculated from the base of the
 161          * GPU registers so we need to add 0x1a800 to the register value on A630
 162          * to get the right value from PM4.
 163          */
 164         get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
 165                 rbmemptr_stats(ring, index, alwayson_start));
 166
 167         /* Invalidate CCU depth and color */
 168         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 169         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));
 170
 171         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 172         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));
 173
 174         /* Submit the commands */
 175         for (i = 0; i < submit->nr_cmds; i++) {
 176                 switch (submit->cmd[i].type) {
 177                 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
 178                         break;
 179                 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
 180                         if (priv->lastctx == submit->queue->ctx)
 181                                 break;
 182                         fallthrough;
 183                 case MSM_SUBMIT_CMD_BUF:
 184                         OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
 185                         OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
 186                         OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
 187                         OUT_RING(ring, submit->cmd[i].size);
 188                         ibs++;
 189                         break;
 190                 }
 191
 192                 /*
 193                  * Periodically update shadow-wptr if needed, so that we
 194                  * can see partial progress of submits with large # of
 195                  * cmds.. otherwise we could needlessly stall waiting for
 196                  * ringbuffer state, simply due to looking at a shadow
 197                  * rptr value that has not been updated
 198                  */
 199                 if ((ibs % 32) == 0)
 200                         update_shadow_rptr(gpu, ring);
 201         }
 202
 203         get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
 204                 rbmemptr_stats(ring, index, cpcycles_end));
 205         get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
 206                 rbmemptr_stats(ring, index, alwayson_end));
 207
 208         /* Write the fence to the scratch register */
 209         OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
 210         OUT_RING(ring, submit->seqno);
 211
 212         /*
 213          * Execute a CACHE_FLUSH_TS event. This will ensure that the
 214          * timestamp is written to the memory and then triggers the interrupt
 215          */
 216         OUT_PKT7(ring, CP_EVENT_WRITE, 4);
 217         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |
 218                 CP_EVENT_WRITE_0_IRQ);
 219         OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
 220         OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
 221         OUT_RING(ring, submit->seqno);
 222
 223         trace_msm_gpu_submit_flush(submit,
 224                 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
 225                         REG_A6XX_CP_ALWAYS_ON_COUNTER_HI));
 226
 227         a6xx_flush(gpu, ring);
 228 }
 229
 230 const struct adreno_reglist a630_hwcg[] = {
 231         {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
 232         {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
 233         {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
 234         {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
 235         {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
 236         {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
 237         {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
 238         {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
 239         {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
 240         {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
 241         {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
 242         {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
 243         {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
 244         {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
 245         {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
 246         {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
 247         {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
 248         {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
 249         {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
 250         {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
 251         {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
 252         {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
 253         {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
 254         {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
 255         {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
 256         {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
 257         {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
 258         {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
 259         {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
 260         {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
 261         {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
 262         {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
 263         {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
 264         {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
 265         {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
 266         {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
 267         {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
 268         {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
 269         {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
 270         {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
 271         {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
 272         {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
 273         {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
 274         {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
 275         {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
 276         {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
 277         {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
 278         {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
 279         {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
 280         {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
 281         {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
 282         {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
 283         {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
 284         {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
 285         {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
 286         {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
 287         {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
 288         {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
 289         {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
 290         {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
 291         {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
 292         {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
 293         {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
 294         {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
 295         {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
 296         {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
 297         {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
 298         {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
 299         {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
 300         {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
 301         {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
 302         {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
 303         {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
 304         {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
 305         {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
 306         {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
 307         {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
 308         {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
 309         {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
 310         {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
 311         {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
 312         {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
 313         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
 314         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
 315         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
 316         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
 317         {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
 318         {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
 319         {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
 320         {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
 321         {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
 322         {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
 323         {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
 324         {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
 325         {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
 326         {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
 327         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
 328         {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
 329         {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
 330         {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
 331         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
 332         {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
 333         {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
 334         {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
 335         {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
 336         {},
 337 };
 338
 339 const struct adreno_reglist a640_hwcg[] = {
 340         {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
 341         {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
 342         {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
 343         {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
 344         {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
 345         {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
 346         {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
 347         {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
 348         {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
 349         {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
 350         {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
 351         {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
 352         {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
 353         {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
 354         {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
 355         {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
 356         {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
 357         {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
 358         {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
 359         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
 360         {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
 361         {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
 362         {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
 363         {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
 364         {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
 365         {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
 366         {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
 367         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
 368         {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
 369         {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
 370         {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
 371         {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
 372         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
 373         {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
 374         {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
 375         {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
 376         {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
 377         {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
 378         {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
 379         {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
 380         {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
 381         {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
 382         {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
 383         {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
 384         {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
 385         {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
 386         {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
 387         {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
 388         {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
 389         {},
 390 };
 391
 392 const struct adreno_reglist a650_hwcg[] = {
 393         {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
 394         {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
 395         {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
 396         {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
 397         {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
 398         {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
 399         {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
 400         {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
 401         {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
 402         {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
 403         {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
 404         {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
 405         {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
 406         {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
 407         {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
 408         {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
 409         {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
 410         {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
 411         {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
 412         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
 413         {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
 414         {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
 415         {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
 416         {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
 417         {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
 418         {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
 419         {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
 420         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
 421         {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
 422         {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
 423         {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
 424         {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
 425         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
 426         {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
 427         {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
 428         {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
 429         {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
 430         {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
 431         {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
 432         {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
 433         {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
 434         {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
 435         {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
 436         {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
 437         {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
 438         {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
 439         {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
 440         {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
 441         {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
 442         {},
 443 };
 444
 445 const struct adreno_reglist a660_hwcg[] = {
 446         {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
 447         {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
 448         {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
 449         {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
 450         {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
 451         {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
 452         {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
 453         {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
 454         {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
 455         {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
 456         {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
 457         {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
 458         {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
 459         {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
 460         {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
 461         {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
 462         {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
 463         {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
 464         {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
 465         {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
 466         {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
 467         {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
 468         {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
 469         {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
 470         {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
 471         {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
 472         {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
 473         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
 474         {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
 475         {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
 476         {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
 477         {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
 478         {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
 479         {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
 480         {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
 481         {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
 482         {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
 483         {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
 484         {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
 485         {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
 486         {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
 487         {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
 488         {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
 489         {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
 490         {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
 491         {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
 492         {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
 493         {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
 494         {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
 495         {},
 496 };
 497
 498 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
 499 {
 500         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 501         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 502         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 503         const struct adreno_reglist *reg;
 504         unsigned int i;
 505         u32 val, clock_cntl_on;
 506
 507         if (!adreno_gpu->info->hwcg)
 508                 return;
 509
 510         if (adreno_is_a630(adreno_gpu))
 511                 clock_cntl_on = 0x8aa8aa02;
 512         else
 513                 clock_cntl_on = 0x8aa8aa82;
 514
 515         val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
 516
 517         /* Don't re-program the registers if they are already correct */
 518         if ((!state && !val) || (state && (val == clock_cntl_on)))
 519                 return;
 520
 521         /* Disable SP clock before programming HWCG registers */
 522         gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
 523
 524         for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
 525                 gpu_write(gpu, reg->offset, state ? reg->value : 0);
 526
 527         /* Enable SP clock */
 528         gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
 529
 530         gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
 531 }
 532
 533 /* For a615, a616, a618, A619, a630, a640 and a680 */
 534 static const u32 a6xx_protect[] = {
 535         A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
 536         A6XX_PROTECT_RDONLY(0x00501, 0x0005),
 537         A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
 538         A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
 539         A6XX_PROTECT_NORDWR(0x00510, 0x0000),
 540         A6XX_PROTECT_NORDWR(0x00534, 0x0000),
 541         A6XX_PROTECT_NORDWR(0x00800, 0x0082),
 542         A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
 543         A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
 544         A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
 545         A6XX_PROTECT_NORDWR(0x00900, 0x004d),
 546         A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
 547         A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
 548         A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
 549         A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
 550         A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
 551         A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
 552         A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
 553         A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
 554         A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
 555         A6XX_PROTECT_NORDWR(0x09624, 0x01db),
 556         A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
 557         A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
 558         A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
 559         A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
 560         A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
 561         A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
 562         A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
 563         A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
 564         A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
 565         A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
 566         A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
 567 };
 568
 569 /* These are for a620 and a650 */
 570 static const u32 a650_protect[] = {
 571         A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
 572         A6XX_PROTECT_RDONLY(0x00501, 0x0005),
 573         A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
 574         A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
 575         A6XX_PROTECT_NORDWR(0x00510, 0x0000),
 576         A6XX_PROTECT_NORDWR(0x00534, 0x0000),
 577         A6XX_PROTECT_NORDWR(0x00800, 0x0082),
 578         A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
 579         A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
 580         A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
 581         A6XX_PROTECT_NORDWR(0x00900, 0x004d),
 582         A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
 583         A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
 584         A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
 585         A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
 586         A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
 587         A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
 588         A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
 589         A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
 590         A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
 591         A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
 592         A6XX_PROTECT_NORDWR(0x09624, 0x01db),
 593         A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
 594         A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
 595         A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
 596         A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
 597         A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
 598         A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
 599         A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
 600         A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
 601         A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
 602         A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
 603         A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
 604         A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
 605         A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
 606         A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
 607         A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
 608         A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
 609         A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
 610 };
 611
 612 /* These are for a635 and a660 */
 613 static const u32 a660_protect[] = {
 614         A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
 615         A6XX_PROTECT_RDONLY(0x00501, 0x0005),
 616         A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
 617         A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
 618         A6XX_PROTECT_NORDWR(0x00510, 0x0000),
 619         A6XX_PROTECT_NORDWR(0x00534, 0x0000),
 620         A6XX_PROTECT_NORDWR(0x00800, 0x0082),
 621         A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
 622         A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
 623         A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
 624         A6XX_PROTECT_NORDWR(0x00900, 0x004d),
 625         A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
 626         A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
 627         A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
 628         A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
 629         A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
 630         A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
 631         A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
 632         A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
 633         A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
 634         A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
 635         A6XX_PROTECT_NORDWR(0x09624, 0x01db),
 636         A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
 637         A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
 638         A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
 639         A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
 640         A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
 641         A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
 642         A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
 643         A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
 644         A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
 645         A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
 646         A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
 647         A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
 648         A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
 649         A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
 650         A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
 651         A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
 652         A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
 653         A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
 654         A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
 655 };
 656
 657 static void a6xx_set_cp_protect(struct msm_gpu *gpu)
 658 {
 659         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 660         const u32 *regs = a6xx_protect;
 661         unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32;
 662
 663         BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
 664         BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
 665
 666         if (adreno_is_a650(adreno_gpu)) {
 667                 regs = a650_protect;
 668                 count = ARRAY_SIZE(a650_protect);
 669                 count_max = 48;
 670         } else if (adreno_is_a660_family(adreno_gpu)) {
 671                 regs = a660_protect;
 672                 count = ARRAY_SIZE(a660_protect);
 673                 count_max = 48;
 674         }
 675
 676         /*
 677          * Enable access protection to privileged registers, fault on an access
 678          * protect violation and select the last span to protect from the start
 679          * address all the way to the end of the register address space
 680          */
 681         gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
 682
 683         for (i = 0; i < count - 1; i++)
 684                 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
 685         /* last CP_PROTECT to have "infinite" length on the last entry */
 686         gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
 687 }
 688
 689 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 690 {
 691         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 692         u32 lower_bit = 2;
 693         u32 amsbc = 0;
 694         u32 rgb565_predicator = 0;
 695         u32 uavflagprd_inv = 0;
 696
 697         /* a618 is using the hw default values */
 698         if (adreno_is_a618(adreno_gpu))
 699                 return;
 700
 701         if (adreno_is_a640_family(adreno_gpu))
 702                 amsbc = 1;
 703
 704         if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
 705                 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
 706                 lower_bit = 3;
 707                 amsbc = 1;
 708                 rgb565_predicator = 1;
 709                 uavflagprd_inv = 2;
 710         }
 711
 712         if (adreno_is_7c3(adreno_gpu)) {
 713                 lower_bit = 1;
 714                 amsbc = 1;
 715                 rgb565_predicator = 1;
 716                 uavflagprd_inv = 2;
 717         }
 718
 719         gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
 720                 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
 721         gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
 722         gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
 723                 uavflagprd_inv << 4 | lower_bit << 1);
 724         gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
 725 }
 726
 727 static int a6xx_cp_init(struct msm_gpu *gpu)
 728 {
 729         struct msm_ringbuffer *ring = gpu->rb[0];
 730
 731         OUT_PKT7(ring, CP_ME_INIT, 8);
 732
 733         OUT_RING(ring, 0x0000002f);
 734
 735         /* Enable multiple hardware contexts */
 736         OUT_RING(ring, 0x00000003);
 737
 738         /* Enable error detection */
 739         OUT_RING(ring, 0x20000000);
 740
 741         /* Don't enable header dump */
 742         OUT_RING(ring, 0x00000000);
 743         OUT_RING(ring, 0x00000000);
 744
 745         /* No workarounds enabled */
 746         OUT_RING(ring, 0x00000000);
 747
 748         /* Pad rest of the cmds with 0's */
 749         OUT_RING(ring, 0x00000000);
 750         OUT_RING(ring, 0x00000000);
 751
 752         a6xx_flush(gpu, ring);
 753         return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
 754 }
 755
 756 /*
 757  * Check that the microcode version is new enough to include several key
 758  * security fixes. Return true if the ucode is safe.
 759  */
 760 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
 761                 struct drm_gem_object *obj)
 762 {
 763         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 764         struct msm_gpu *gpu = &adreno_gpu->base;
 765         const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE];
 766         u32 *buf = msm_gem_get_vaddr(obj);
 767         bool ret = false;
 768
 769         if (IS_ERR(buf))
 770                 return false;
 771
 772         /*
 773          * Targets up to a640 (a618, a630 and a640) need to check for a
 774          * microcode version that is patched to support the whereami opcode or
 775          * one that is new enough to include it by default.
 776          *
 777          * a650 tier targets don't need whereami but still need to be
 778          * equal to or newer than 0.95 for other security fixes
 779          *
 780          * a660 targets have all the critical security fixes from the start
 781          */
 782         if (!strcmp(sqe_name, "a630_sqe.fw")) {
 783                 /*
 784                  * If the lowest nibble is 0xa that is an indication that this
 785                  * microcode has been patched. The actual version is in dword
 786                  * [3] but we only care about the patchlevel which is the lowest
 787                  * nibble of dword [3]
 788                  *
 789                  * Otherwise check that the firmware is greater than or equal
 790                  * to 1.90 which was the first version that had this fix built
 791                  * in
 792                  */
 793                 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) ||
 794                         (buf[0] & 0xfff) >= 0x190) {
 795                         a6xx_gpu->has_whereami = true;
 796                         ret = true;
 797                         goto out;
 798                 }
 799
 800                 DRM_DEV_ERROR(&gpu->pdev->dev,
 801                         "a630 SQE ucode is too old. Have version %x need at least %x\n",
 802                         buf[0] & 0xfff, 0x190);
 803         } else if (!strcmp(sqe_name, "a650_sqe.fw")) {
 804                 if ((buf[0] & 0xfff) >= 0x095) {
 805                         ret = true;
 806                         goto out;
 807                 }
 808
 809                 DRM_DEV_ERROR(&gpu->pdev->dev,
 810                         "a650 SQE ucode is too old. Have version %x need at least %x\n",
 811                         buf[0] & 0xfff, 0x095);
 812         } else if (!strcmp(sqe_name, "a660_sqe.fw")) {
 813                 ret = true;
 814         } else {
 815                 DRM_DEV_ERROR(&gpu->pdev->dev,
 816                         "unknown GPU, add it to a6xx_ucode_check_version()!!\n");
 817         }
 818 out:
 819         msm_gem_put_vaddr(obj);
 820         return ret;
 821 }
 822
 823 static int a6xx_ucode_init(struct msm_gpu *gpu)
 824 {
 825         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 826         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 827
 828         if (!a6xx_gpu->sqe_bo) {
 829                 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
 830                         adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);
 831
 832                 if (IS_ERR(a6xx_gpu->sqe_bo)) {
 833                         int ret = PTR_ERR(a6xx_gpu->sqe_bo);
 834
 835                         a6xx_gpu->sqe_bo = NULL;
 836                         DRM_DEV_ERROR(&gpu->pdev->dev,
 837                                 "Could not allocate SQE ucode: %d\n", ret);
 838
 839                         return ret;
 840                 }
 841
 842                 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
 843                 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {
 844                         msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
 845                         drm_gem_object_put(a6xx_gpu->sqe_bo);
 846
 847                         a6xx_gpu->sqe_bo = NULL;
 848                         return -EPERM;
 849                 }
 850         }
 851
 852         gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE,
 853                 REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova);
 854
 855         return 0;
 856 }
 857
 858 static int a6xx_zap_shader_init(struct msm_gpu *gpu)
 859 {
 860         static bool loaded;
 861         int ret;
 862
 863         if (loaded)
 864                 return 0;
 865
 866         ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
 867
 868         loaded = !ret;
 869         return ret;
 870 }
 871
 872 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
 873           A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
 874           A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
 875           A6XX_RBBM_INT_0_MASK_CP_IB2 | \
 876           A6XX_RBBM_INT_0_MASK_CP_IB1 | \
 877           A6XX_RBBM_INT_0_MASK_CP_RB | \
 878           A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
 879           A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
 880           A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
 881           A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
 882           A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
 883
 884 static int a6xx_hw_init(struct msm_gpu *gpu)
 885 {
 886         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 887         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 888         int ret;
 889
 890         /* Make sure the GMU keeps the GPU on while we set it up */
 891         a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
 892
 893         gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
 894
 895         /*
 896          * Disable the trusted memory range - we don't actually supported secure
 897          * memory rendering at this point in time and we don't want to block off
 898          * part of the virtual memory space.
 899          */
 900         gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
 901                 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
 902         gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
 903
 904         /* Turn on 64 bit addressing for all blocks */
 905         gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
 906         gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
 907         gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
 908         gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
 909         gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
 910         gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
 911         gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
 912         gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
 913         gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
 914         gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
 915         gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
 916         gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
 917
 918         /* enable hardware clockgating */
 919         a6xx_set_hwcg(gpu, true);
 920
 921         /* VBIF/GBIF start*/
 922         if (adreno_is_a640_family(adreno_gpu) ||
 923             adreno_is_a650_family(adreno_gpu)) {
 924                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
 925                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
 926                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
 927                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
 928                 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
 929                 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
 930         } else {
 931                 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
 932         }
 933
 934         if (adreno_is_a630(adreno_gpu))
 935                 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
 936
 937         /* Make all blocks contribute to the GPU BUSY perf counter */
 938         gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
 939
 940         /* Disable L2 bypass in the UCHE */
 941         gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
 942         gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
 943         gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
 944         gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
 945         gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
 946         gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
 947
 948         if (!adreno_is_a650_family(adreno_gpu)) {
 949                 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
 950                 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
 951                         REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
 952
 953                 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
 954                         REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
 955                         0x00100000 + adreno_gpu->gmem - 1);
 956         }
 957
 958         gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
 959         gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
 960
 961         if (adreno_is_a640_family(adreno_gpu) ||
 962             adreno_is_a650_family(adreno_gpu))
 963                 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
 964         else
 965                 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
 966         gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
 967
 968         if (adreno_is_a660_family(adreno_gpu))
 969                 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
 970
 971         /* Setting the mem pool size */
 972         gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
 973
 974         /* Setting the primFifo thresholds default values,
 975          * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
 976         */
 977         if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
 978                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
 979         else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
 980                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
 981         else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
 982                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
 983         else
 984                 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
 985
 986         /* Set the AHB default slave response to "ERROR" */
 987         gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
 988
 989         /* Turn on performance counters */
 990         gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
 991
 992         /* Select CP0 to always count cycles */
 993         gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);
 994
 995         a6xx_set_ubwc_config(gpu);
 996
 997         /* Enable fault detection */
 998         gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
 999                 (1 << 30) | 0x1fffff);
1000
1001         gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
1002
1003         /* Set weights for bicubic filtering */
1004         if (adreno_is_a650_family(adreno_gpu)) {
1005                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
1006                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
1007                         0x3fe05ff4);
1008                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
1009                         0x3fa0ebee);
1010                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
1011                         0x3f5193ed);
1012                 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
1013                         0x3f0243f0);
1014         }
1015
1016         /* Protect registers from the CP */
1017         a6xx_set_cp_protect(gpu);
1018
1019         if (adreno_is_a660_family(adreno_gpu)) {
1020                 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
1021                 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
1022         }
1023
1024         /* Set dualQ + disable afull for A660 GPU */
1025         if (adreno_is_a660(adreno_gpu))
1026                 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
1027
1028         /* Enable expanded apriv for targets that support it */
1029         if (gpu->hw_apriv) {
1030                 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
1031                         (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
1032         }
1033
1034         /* Enable interrupts */
1035         gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
1036
1037         ret = adreno_hw_init(gpu);
1038         if (ret)
1039                 goto out;
1040
1041         ret = a6xx_ucode_init(gpu);
1042         if (ret)
1043                 goto out;
1044
1045         /* Set the ringbuffer address */
1046         gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
1047                 gpu->rb[0]->iova);
1048
1049         /* Targets that support extended APRIV can use the RPTR shadow from
1050          * hardware but all the other ones need to disable the feature. Targets
1051          * that support the WHERE_AM_I opcode can use that instead
1052          */
1053         if (adreno_gpu->base.hw_apriv)
1054                 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
1055         else
1056                 gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
1057                         MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
1058
1059         /*
1060          * Expanded APRIV and targets that support WHERE_AM_I both need a
1061          * privileged buffer to store the RPTR shadow
1062          */
1063
1064         if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) {
1065                 if (!a6xx_gpu->shadow_bo) {
1066                         a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
1067                                 sizeof(u32) * gpu->nr_rings,
1068                                 MSM_BO_WC | MSM_BO_MAP_PRIV,
1069                                 gpu->aspace, &a6xx_gpu->shadow_bo,
1070                                 &a6xx_gpu->shadow_iova);
1071
1072                         if (IS_ERR(a6xx_gpu->shadow))
1073                                 return PTR_ERR(a6xx_gpu->shadow);
1074                 }
1075
1076                 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO,
1077                         REG_A6XX_CP_RB_RPTR_ADDR_HI,
1078                         shadowptr(a6xx_gpu, gpu->rb[0]));
1079         }
1080
1081         /* Always come up on rb 0 */
1082         a6xx_gpu->cur_ring = gpu->rb[0];
1083
1084         a6xx_gpu->cur_ctx = NULL;
1085
1086         /* Enable the SQE_to start the CP engine */
1087         gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
1088
1089         ret = a6xx_cp_init(gpu);
1090         if (ret)
1091                 goto out;
1092
1093         /*
1094          * Try to load a zap shader into the secure world. If successful
1095          * we can use the CP to switch out of secure mode. If not then we
1096          * have no resource but to try to switch ourselves out manually. If we
1097          * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
1098          * be blocked and a permissions violation will soon follow.
1099          */
1100         ret = a6xx_zap_shader_init(gpu);
1101         if (!ret) {
1102                 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
1103                 OUT_RING(gpu->rb[0], 0x00000000);
1104
1105                 a6xx_flush(gpu, gpu->rb[0]);
1106                 if (!a6xx_idle(gpu, gpu->rb[0]))
1107                         return -EINVAL;
1108         } else if (ret == -ENODEV) {
1109                 /*
1110                  * This device does not use zap shader (but print a warning
1111                  * just in case someone got their dt wrong.. hopefully they
1112                  * have a debug UART to realize the error of their ways...
1113                  * if you mess this up you are about to crash horribly)
1114                  */
1115                 dev_warn_once(gpu->dev->dev,
1116                         "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
1117                 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
1118                 ret = 0;
1119         } else {
1120                 return ret;
1121         }
1122
1123 out:
1124         /*
1125          * Tell the GMU that we are done touching the GPU and it can start power
1126          * management
1127          */
1128         a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
1129
1130         if (a6xx_gpu->gmu.legacy) {
1131                 /* Take the GMU out of its special boot mode */
1132                 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
1133         }
1134
1135         return ret;
1136 }
1137
1138 static void a6xx_dump(struct msm_gpu *gpu)
1139 {
1140         DRM_DEV_INFO(&gpu->pdev->dev, "status:   %08x\n",
1141                         gpu_read(gpu, REG_A6XX_RBBM_STATUS));
1142         adreno_dump(gpu);
1143 }
1144
1145 #define VBIF_RESET_ACK_TIMEOUT  100
1146 #define VBIF_RESET_ACK_MASK     0x00f0
1147
1148 static void a6xx_recover(struct msm_gpu *gpu)
1149 {
1150         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1151         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1152         int i;
1153
1154         adreno_dump_info(gpu);
1155
1156         for (i = 0; i < 8; i++)
1157                 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
1158                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
1159
1160         if (hang_debug)
1161                 a6xx_dump(gpu);
1162
1163         /*
1164          * Turn off keep alive that might have been enabled by the hang
1165          * interrupt
1166          */
1167         gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
1168
1169         gpu->funcs->pm_suspend(gpu);
1170         gpu->funcs->pm_resume(gpu);
1171
1172         msm_gpu_hw_init(gpu);
1173 }
1174
1175 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)
1176 {
1177         static const char *uche_clients[7] = {
1178                 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ",
1179         };
1180         u32 val;
1181
1182         if (mid < 1 || mid > 3)
1183                 return "UNKNOWN";
1184
1185         /*
1186          * The source of the data depends on the mid ID read from FSYNR1.
1187          * and the client ID read from the UCHE block
1188          */
1189         val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);
1190
1191         /* mid = 3 is most precise and refers to only one block per client */
1192         if (mid == 3)
1193                 return uche_clients[val & 7];
1194
1195         /* For mid=2 the source is TP or VFD except when the client id is 0 */
1196         if (mid == 2)
1197                 return ((val & 7) == 0) ? "TP" : "TP|VFD";
1198
1199         /* For mid=1 just return "UCHE" as a catchall for everything else */
1200         return "UCHE";
1201 }
1202
1203 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id)
1204 {
1205         if (id == 0)
1206                 return "CP";
1207         else if (id == 4)
1208                 return "CCU";
1209         else if (id == 6)
1210                 return "CDP Prefetch";
1211
1212         return a6xx_uche_fault_block(gpu, id);
1213 }
1214
1215 #define ARM_SMMU_FSR_TF                 BIT(1)
1216 #define ARM_SMMU_FSR_PF                 BIT(3)
1217 #define ARM_SMMU_FSR_EF                 BIT(4)
1218
1219 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
1220 {
1221         struct msm_gpu *gpu = arg;
1222         struct adreno_smmu_fault_info *info = data;
1223         const char *type = "UNKNOWN";
1224         const char *block;
1225         bool do_devcoredump = info && !READ_ONCE(gpu->crashstate);
1226
1227         /*
1228          * If we aren't going to be resuming later from fault_worker, then do
1229          * it now.
1230          */
1231         if (!do_devcoredump) {
1232                 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
1233         }
1234
1235         /*
1236          * Print a default message if we couldn't get the data from the
1237          * adreno-smmu-priv
1238          */
1239         if (!info) {
1240                 pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n",
1241                         iova, flags,
1242                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1243                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1244                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1245                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1246
1247                 return 0;
1248         }
1249
1250         if (info->fsr & ARM_SMMU_FSR_TF)
1251                 type = "TRANSLATION";
1252         else if (info->fsr & ARM_SMMU_FSR_PF)
1253                 type = "PERMISSION";
1254         else if (info->fsr & ARM_SMMU_FSR_EF)
1255                 type = "EXTERNAL";
1256
1257         block = a6xx_fault_block(gpu, info->fsynr1 & 0xff);
1258
1259         pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n",
1260                         info->ttbr0, iova,
1261                         flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ",
1262                         type, block,
1263                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1264                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1265                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1266                         gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1267
1268         if (do_devcoredump) {
1269                 /* Turn off the hangcheck timer to keep it from bothering us */
1270                 del_timer(&gpu->hangcheck_timer);
1271
1272                 gpu->fault_info.ttbr0 = info->ttbr0;
1273                 gpu->fault_info.iova  = iova;
1274                 gpu->fault_info.flags = flags;
1275                 gpu->fault_info.type  = type;
1276                 gpu->fault_info.block = block;
1277
1278                 kthread_queue_work(gpu->worker, &gpu->fault_work);
1279         }
1280
1281         return 0;
1282 }
1283
1284 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
1285 {
1286         u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
1287
1288         if (status & A6XX_CP_INT_CP_OPCODE_ERROR) {
1289                 u32 val;
1290
1291                 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
1292                 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
1293                 dev_err_ratelimited(&gpu->pdev->dev,
1294                         "CP | opcode error | possible opcode=0x%8.8X\n",
1295                         val);
1296         }
1297
1298         if (status & A6XX_CP_INT_CP_UCODE_ERROR)
1299                 dev_err_ratelimited(&gpu->pdev->dev,
1300                         "CP ucode error interrupt\n");
1301
1302         if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR)
1303                 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
1304                         gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
1305
1306         if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) {
1307                 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
1308
1309                 dev_err_ratelimited(&gpu->pdev->dev,
1310                         "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n",
1311                         val & (1 << 20) ? "READ" : "WRITE",
1312                         (val & 0x3ffff), val);
1313         }
1314
1315         if (status & A6XX_CP_INT_CP_AHB_ERROR)
1316                 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
1317
1318         if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR)
1319                 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
1320
1321         if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR)
1322                 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
1323
1324 }
1325
1326 static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
1327 {
1328         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1329         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1330         struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1331
1332         /*
1333          * If stalled on SMMU fault, we could trip the GPU's hang detection,
1334          * but the fault handler will trigger the devcore dump, and we want
1335          * to otherwise resume normally rather than killing the submit, so
1336          * just bail.
1337          */
1338         if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)
1339                 return;
1340
1341         /*
1342          * Force the GPU to stay on until after we finish
1343          * collecting information
1344          */
1345         gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
1346
1347         DRM_DEV_ERROR(&gpu->pdev->dev,
1348                 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
1349                 ring ? ring->id : -1, ring ? ring->seqno : 0,
1350                 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
1351                 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
1352                 gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1353                 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
1354                 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
1355                 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
1356                 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
1357
1358         /* Turn off the hangcheck timer to keep it from bothering us */
1359         del_timer(&gpu->hangcheck_timer);
1360
1361         kthread_queue_work(gpu->worker, &gpu->recover_work);
1362 }
1363
1364 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
1365 {
1366         u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
1367
1368         gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
1369
1370         if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
1371                 a6xx_fault_detect_irq(gpu);
1372
1373         if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
1374                 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
1375
1376         if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
1377                 a6xx_cp_hw_err_irq(gpu);
1378
1379         if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
1380                 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
1381
1382         if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
1383                 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
1384
1385         if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
1386                 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
1387
1388         if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
1389                 msm_gpu_retire(gpu);
1390
1391         return IRQ_HANDLED;
1392 }
1393
1394 static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
1395 {
1396         return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
1397 }
1398
1399 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
1400 {
1401         return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
1402 }
1403
1404 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
1405 {
1406         llcc_slice_deactivate(a6xx_gpu->llc_slice);
1407         llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
1408 }
1409
1410 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
1411 {
1412         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1413         struct msm_gpu *gpu = &adreno_gpu->base;
1414         u32 gpu_scid, cntl1_regval = 0;
1415
1416         if (IS_ERR(a6xx_gpu->llc_mmio))
1417                 return;
1418
1419         if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
1420                 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
1421
1422                 gpu_scid &= 0x1f;
1423                 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) |
1424                                (gpu_scid << 15) | (gpu_scid << 20);
1425         }
1426
1427         /*
1428          * For targets with a MMU500, activate the slice but don't program the
1429          * register.  The XBL will take care of that.
1430          */
1431         if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
1432                 if (!a6xx_gpu->have_mmu500) {
1433                         u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
1434
1435                         gpuhtw_scid &= 0x1f;
1436                         cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
1437                 }
1438         }
1439
1440         if (!cntl1_regval)
1441                 return;
1442
1443         /*
1444          * Program the slice IDs for the various GPU blocks and GPU MMU
1445          * pagetables
1446          */
1447         if (!a6xx_gpu->have_mmu500) {
1448                 a6xx_llc_write(a6xx_gpu,
1449                         REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
1450
1451                 /*
1452                  * Program cacheability overrides to not allocate cache
1453                  * lines on a write miss
1454                  */
1455                 a6xx_llc_rmw(a6xx_gpu,
1456                         REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
1457                 return;
1458         }
1459
1460         gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval);
1461
1462         /* On A660, the SCID programming for UCHE traffic is done in
1463          * A6XX_GBIF_SCACHE_CNTL0[14:10]
1464          */
1465         if (adreno_is_a660_family(adreno_gpu))
1466                 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
1467                         (1 << 8), (gpu_scid << 10) | (1 << 8));
1468 }
1469
1470 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
1471 {
1472         llcc_slice_putd(a6xx_gpu->llc_slice);
1473         llcc_slice_putd(a6xx_gpu->htw_llc_slice);
1474 }
1475
1476 static void a6xx_llc_slices_init(struct platform_device *pdev,
1477                 struct a6xx_gpu *a6xx_gpu)
1478 {
1479         struct device_node *phandle;
1480
1481         /*
1482          * There is a different programming path for targets with an mmu500
1483          * attached, so detect if that is the case
1484          */
1485         phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);
1486         a6xx_gpu->have_mmu500 = (phandle &&
1487                 of_device_is_compatible(phandle, "arm,mmu-500"));
1488         of_node_put(phandle);
1489
1490         if (a6xx_gpu->have_mmu500)
1491                 a6xx_gpu->llc_mmio = NULL;
1492         else
1493                 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
1494
1495         a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
1496         a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
1497
1498         if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1499                 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
1500 }
1501
1502 static int a6xx_pm_resume(struct msm_gpu *gpu)
1503 {
1504         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1505         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1506         int ret;
1507
1508         gpu->needs_hw_init = true;
1509
1510         trace_msm_gpu_resume(0);
1511
1512         ret = a6xx_gmu_resume(a6xx_gpu);
1513         if (ret)
1514                 return ret;
1515
1516         msm_devfreq_resume(gpu);
1517
1518         a6xx_llc_activate(a6xx_gpu);
1519
1520         return 0;
1521 }
1522
1523 static int a6xx_pm_suspend(struct msm_gpu *gpu)
1524 {
1525         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1526         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1527         int i, ret;
1528
1529         trace_msm_gpu_suspend(0);
1530
1531         a6xx_llc_deactivate(a6xx_gpu);
1532
1533         msm_devfreq_suspend(gpu);
1534
1535         ret = a6xx_gmu_stop(a6xx_gpu);
1536         if (ret)
1537                 return ret;
1538
1539         if (a6xx_gpu->shadow_bo)
1540                 for (i = 0; i < gpu->nr_rings; i++)
1541                         a6xx_gpu->shadow[i] = 0;
1542
1543         return 0;
1544 }
1545
1546 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
1547 {
1548         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1549         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1550         static DEFINE_MUTEX(perfcounter_oob);
1551
1552         mutex_lock(&perfcounter_oob);
1553
1554         /* Force the GPU power on so we can read this register */
1555         a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1556
1557         *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
1558                 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);
1559
1560         a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1561         mutex_unlock(&perfcounter_oob);
1562         return 0;
1563 }
1564
1565 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
1566 {
1567         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1568         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1569
1570         return a6xx_gpu->cur_ring;
1571 }
1572
1573 static void a6xx_destroy(struct msm_gpu *gpu)
1574 {
1575         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1576         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1577
1578         if (a6xx_gpu->sqe_bo) {
1579                 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
1580                 drm_gem_object_put(a6xx_gpu->sqe_bo);
1581         }
1582
1583         if (a6xx_gpu->shadow_bo) {
1584                 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
1585                 drm_gem_object_put(a6xx_gpu->shadow_bo);
1586         }
1587
1588         a6xx_llc_slices_destroy(a6xx_gpu);
1589
1590         a6xx_gmu_remove(a6xx_gpu);
1591
1592         adreno_gpu_cleanup(adreno_gpu);
1593
1594         kfree(a6xx_gpu);
1595 }
1596
1597 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
1598 {
1599         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1600         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1601         u64 busy_cycles, busy_time;
1602
1603
1604         /* Only read the gpu busy if the hardware is already active */
1605         if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
1606                 return 0;
1607
1608         busy_cycles = gmu_read64(&a6xx_gpu->gmu,
1609                         REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
1610                         REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
1611
1612         busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
1613         do_div(busy_time, 192);
1614
1615         gpu->devfreq.busy_cycles = busy_cycles;
1616
1617         pm_runtime_put(a6xx_gpu->gmu.dev);
1618
1619         if (WARN_ON(busy_time > ~0LU))
1620                 return ~0LU;
1621
1622         return (unsigned long)busy_time;
1623 }
1624
1625 static struct msm_gem_address_space *
1626 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
1627 {
1628         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1629         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1630         struct iommu_domain *iommu;
1631         struct msm_mmu *mmu;
1632         struct msm_gem_address_space *aspace;
1633         u64 start, size;
1634
1635         iommu = iommu_domain_alloc(&platform_bus_type);
1636         if (!iommu)
1637                 return NULL;
1638
1639         /*
1640          * This allows GPU to set the bus attributes required to use system
1641          * cache on behalf of the iommu page table walker.
1642          */
1643         if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1644                 adreno_set_llc_attributes(iommu);
1645
1646         mmu = msm_iommu_new(&pdev->dev, iommu);
1647         if (IS_ERR(mmu)) {
1648                 iommu_domain_free(iommu);
1649                 return ERR_CAST(mmu);
1650         }
1651
1652         /*
1653          * Use the aperture start or SZ_16M, whichever is greater. This will
1654          * ensure that we align with the allocated pagetable range while still
1655          * allowing room in the lower 32 bits for GMEM and whatnot
1656          */
1657         start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
1658         size = iommu->geometry.aperture_end - start + 1;
1659
1660         aspace = msm_gem_address_space_create(mmu, "gpu",
1661                 start & GENMASK_ULL(48, 0), size);
1662
1663         if (IS_ERR(aspace) && !IS_ERR(mmu))
1664                 mmu->funcs->destroy(mmu);
1665
1666         return aspace;
1667 }
1668
1669 static struct msm_gem_address_space *
1670 a6xx_create_private_address_space(struct msm_gpu *gpu)
1671 {
1672         struct msm_mmu *mmu;
1673
1674         mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
1675
1676         if (IS_ERR(mmu))
1677                 return ERR_CAST(mmu);
1678
1679         return msm_gem_address_space_create(mmu,
1680                 "gpu", 0x100000000ULL, 0x1ffffffffULL);
1681 }
1682
1683 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
1684 {
1685         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1686         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1687
1688         if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
1689                 return a6xx_gpu->shadow[ring->id];
1690
1691         return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);
1692 }
1693
1694 static u32 a618_get_speed_bin(u32 fuse)
1695 {
1696         if (fuse == 0)
1697                 return 0;
1698         else if (fuse == 169)
1699                 return 1;
1700         else if (fuse == 174)
1701                 return 2;
1702
1703         return UINT_MAX;
1704 }
1705
1706 static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
1707 {
1708         u32 val = UINT_MAX;
1709
1710         if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
1711                 val = a618_get_speed_bin(fuse);
1712
1713         if (val == UINT_MAX) {
1714                 DRM_DEV_ERROR(dev,
1715                         "missing support for speed-bin: %u. Some OPPs may not be supported by hardware",
1716                         fuse);
1717                 return UINT_MAX;
1718         }
1719
1720         return (1 << val);
1721 }
1722
1723 static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
1724 {
1725         u32 supp_hw = UINT_MAX;
1726         u32 speedbin;
1727         int ret;
1728
1729         ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", &speedbin);
1730         /*
1731          * -ENOENT means that the platform doesn't support speedbin which is
1732          * fine
1733          */
1734         if (ret == -ENOENT) {
1735                 return 0;
1736         } else if (ret) {
1737                 DRM_DEV_ERROR(dev,
1738                               "failed to read speed-bin (%d). Some OPPs may not be supported by hardware",
1739                               ret);
1740                 goto done;
1741         }
1742
1743         supp_hw = fuse_to_supp_hw(dev, rev, speedbin);
1744
1745 done:
1746         ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1747         if (ret)
1748                 return ret;
1749
1750         return 0;
1751 }
1752
1753 static const struct adreno_gpu_funcs funcs = {
1754         .base = {
1755                 .get_param = adreno_get_param,
1756                 .hw_init = a6xx_hw_init,
1757                 .pm_suspend = a6xx_pm_suspend,
1758                 .pm_resume = a6xx_pm_resume,
1759                 .recover = a6xx_recover,
1760                 .submit = a6xx_submit,
1761                 .active_ring = a6xx_active_ring,
1762                 .irq = a6xx_irq,
1763                 .destroy = a6xx_destroy,
1764 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1765                 .show = a6xx_show,
1766 #endif
1767                 .gpu_busy = a6xx_gpu_busy,
1768                 .gpu_get_freq = a6xx_gmu_get_freq,
1769                 .gpu_set_freq = a6xx_gmu_set_freq,
1770 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1771                 .gpu_state_get = a6xx_gpu_state_get,
1772                 .gpu_state_put = a6xx_gpu_state_put,
1773 #endif
1774                 .create_address_space = a6xx_create_address_space,
1775                 .create_private_address_space = a6xx_create_private_address_space,
1776                 .get_rptr = a6xx_get_rptr,
1777         },
1778         .get_timestamp = a6xx_get_timestamp,
1779 };
1780
1781 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
1782 {
1783         struct msm_drm_private *priv = dev->dev_private;
1784         struct platform_device *pdev = priv->gpu_pdev;
1785         struct adreno_platform_config *config = pdev->dev.platform_data;
1786         const struct adreno_info *info;
1787         struct device_node *node;
1788         struct a6xx_gpu *a6xx_gpu;
1789         struct adreno_gpu *adreno_gpu;
1790         struct msm_gpu *gpu;
1791         int ret;
1792
1793         a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
1794         if (!a6xx_gpu)
1795                 return ERR_PTR(-ENOMEM);
1796
1797         adreno_gpu = &a6xx_gpu->base;
1798         gpu = &adreno_gpu->base;
1799
1800         adreno_gpu->registers = NULL;
1801
1802         /*
1803          * We need to know the platform type before calling into adreno_gpu_init
1804          * so that the hw_apriv flag can be correctly set. Snoop into the info
1805          * and grab the revision number
1806          */
1807         info = adreno_info(config->rev);
1808
1809         if (info && (info->revn == 650 || info->revn == 660 ||
1810                         adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
1811                 adreno_gpu->base.hw_apriv = true;
1812
1813         a6xx_llc_slices_init(pdev, a6xx_gpu);
1814
1815         ret = a6xx_set_supported_hw(&pdev->dev, config->rev);
1816         if (ret) {
1817                 a6xx_destroy(&(a6xx_gpu->base.base));
1818                 return ERR_PTR(ret);
1819         }
1820
1821         ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
1822         if (ret) {
1823                 a6xx_destroy(&(a6xx_gpu->base.base));
1824                 return ERR_PTR(ret);
1825         }
1826
1827         /* Check if there is a GMU phandle and set it up */
1828         node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
1829
1830         /* FIXME: How do we gracefully handle this? */
1831         BUG_ON(!node);
1832
1833         ret = a6xx_gmu_init(a6xx_gpu, node);
1834         if (ret) {
1835                 a6xx_destroy(&(a6xx_gpu->base.base));
1836                 return ERR_PTR(ret);
1837         }
1838
1839         if (gpu->aspace)
1840                 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
1841                                 a6xx_fault_handler);
1842
1843         return gpu;
1844 }