drivers/gpu/drm/mediatek/mtk_drm_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/mailbox_controller.h>
   9 #include <linux/pm_runtime.h>
  10 #include <linux/soc/mediatek/mtk-cmdq.h>
  11 #include <linux/soc/mediatek/mtk-mmsys.h>
  12 #include <linux/soc/mediatek/mtk-mutex.h>
  13
  14 #include <asm/barrier.h>
  15 #include <soc/mediatek/smi.h>
  16
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20 #include <drm/drm_probe_helper.h>
  21 #include <drm/drm_vblank.h>
  22
  23 #include "mtk_drm_drv.h"
  24 #include "mtk_drm_crtc.h"
  25 #include "mtk_drm_ddp_comp.h"
  26 #include "mtk_drm_gem.h"
  27 #include "mtk_drm_plane.h"
  28
  29 /*
  30  * struct mtk_drm_crtc - MediaTek specific crtc structure.
  31  * @base: crtc object.
  32  * @enabled: records whether crtc_enable succeeded
  33  * @planes: array of 4 drm_plane structures, one for each overlay plane
  34  * @pending_planes: whether any plane has pending changes to be applied
  35  * @mmsys_dev: pointer to the mmsys device for configuration registers
  36  * @mutex: handle to one of the ten disp_mutex streams
  37  * @ddp_comp_nr: number of components in ddp_comp
  38  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
  39  *
  40  * TODO: Needs update: this header is missing a bunch of member descriptions.
  41  */
  42 struct mtk_drm_crtc {
  43         struct drm_crtc                 base;
  44         bool                            enabled;
  45
  46         bool                            pending_needs_vblank;
  47         struct drm_pending_vblank_event *event;
  48
  49         struct drm_plane                *planes;
  50         unsigned int                    layer_nr;
  51         bool                            pending_planes;
  52         bool                            pending_async_planes;
  53
  54 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  55         struct mbox_client              cmdq_cl;
  56         struct mbox_chan                *cmdq_chan;
  57         struct cmdq_pkt                 cmdq_handle;
  58         u32                             cmdq_event;
  59         u32                             cmdq_vblank_cnt;
  60 #endif
  61
  62         struct device                   *mmsys_dev;
  63         struct mtk_mutex                *mutex;
  64         unsigned int                    ddp_comp_nr;
  65         struct mtk_ddp_comp             **ddp_comp;
  66
  67         /* lock for display hardware access */
  68         struct mutex                    hw_lock;
  69         bool                            config_updating;
  70 };
  71
  72 struct mtk_crtc_state {
  73         struct drm_crtc_state           base;
  74
  75         bool                            pending_config;
  76         unsigned int                    pending_width;
  77         unsigned int                    pending_height;
  78         unsigned int                    pending_vrefresh;
  79 };
  80
  81 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
  82 {
  83         return container_of(c, struct mtk_drm_crtc, base);
  84 }
  85
  86 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
  87 {
  88         return container_of(s, struct mtk_crtc_state, base);
  89 }
  90
  91 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
  92 {
  93         struct drm_crtc *crtc = &mtk_crtc->base;
  94         unsigned long flags;
  95
  96         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  97         drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
  98         drm_crtc_vblank_put(crtc);
  99         mtk_crtc->event = NULL;
 100         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 101 }
 102
 103 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
 104 {
 105         drm_crtc_handle_vblank(&mtk_crtc->base);
 106         if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
 107                 mtk_drm_crtc_finish_page_flip(mtk_crtc);
 108                 mtk_crtc->pending_needs_vblank = false;
 109         }
 110 }
 111
 112 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
 113 {
 114         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 115
 116         mtk_mutex_put(mtk_crtc->mutex);
 117
 118         drm_crtc_cleanup(crtc);
 119 }
 120
 121 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
 122 {
 123         struct mtk_crtc_state *state;
 124
 125         if (crtc->state)
 126                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 127
 128         kfree(to_mtk_crtc_state(crtc->state));
 129         crtc->state = NULL;
 130
 131         state = kzalloc(sizeof(*state), GFP_KERNEL);
 132         if (state)
 133                 __drm_atomic_helper_crtc_reset(crtc, &state->base);
 134 }
 135
 136 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
 137 {
 138         struct mtk_crtc_state *state;
 139
 140         state = kzalloc(sizeof(*state), GFP_KERNEL);
 141         if (!state)
 142                 return NULL;
 143
 144         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 145
 146         WARN_ON(state->base.crtc != crtc);
 147         state->base.crtc = crtc;
 148
 149         return &state->base;
 150 }
 151
 152 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
 153                                        struct drm_crtc_state *state)
 154 {
 155         __drm_atomic_helper_crtc_destroy_state(state);
 156         kfree(to_mtk_crtc_state(state));
 157 }
 158
 159 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 160                                     const struct drm_display_mode *mode,
 161                                     struct drm_display_mode *adjusted_mode)
 162 {
 163         /* Nothing to do here, but this callback is mandatory. */
 164         return true;
 165 }
 166
 167 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 168 {
 169         struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
 170
 171         state->pending_width = crtc->mode.hdisplay;
 172         state->pending_height = crtc->mode.vdisplay;
 173         state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
 174         wmb();  /* Make sure the above parameters are set before update */
 175         state->pending_config = true;
 176 }
 177
 178 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
 179 {
 180         int ret;
 181         int i;
 182
 183         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 184                 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
 185                 if (ret) {
 186                         DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
 187                         goto err;
 188                 }
 189         }
 190
 191         return 0;
 192 err:
 193         while (--i >= 0)
 194                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 195         return ret;
 196 }
 197
 198 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
 199 {
 200         int i;
 201
 202         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 203                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 204 }
 205
 206 static
 207 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
 208                                                 struct drm_plane *plane,
 209                                                 unsigned int *local_layer)
 210 {
 211         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 212         struct mtk_ddp_comp *comp;
 213         int i, count = 0;
 214         unsigned int local_index = plane - mtk_crtc->planes;
 215
 216         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 217                 comp = mtk_crtc->ddp_comp[i];
 218                 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
 219                         *local_layer = local_index - count;
 220                         return comp;
 221                 }
 222                 count += mtk_ddp_comp_layer_nr(comp);
 223         }
 224
 225         WARN(1, "Failed to find component for plane %d\n", plane->index);
 226         return NULL;
 227 }
 228
 229 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 230 static int mtk_drm_cmdq_pkt_create(struct mbox_chan *chan, struct cmdq_pkt *pkt,
 231                                     size_t size)
 232 {
 233         struct device *dev;
 234         dma_addr_t dma_addr;
 235
 236         pkt->va_base = kzalloc(size, GFP_KERNEL);
 237         if (!pkt->va_base) {
 238                 kfree(pkt);
 239                 return -ENOMEM;
 240         }
 241         pkt->buf_size = size;
 242
 243         dev = chan->mbox->dev;
 244         dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
 245                                   DMA_TO_DEVICE);
 246         if (dma_mapping_error(dev, dma_addr)) {
 247                 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
 248                 kfree(pkt->va_base);
 249                 kfree(pkt);
 250                 return -ENOMEM;
 251         }
 252
 253         pkt->pa_base = dma_addr;
 254
 255         return 0;
 256 }
 257
 258 static void mtk_drm_cmdq_pkt_destroy(struct mbox_chan *chan, struct cmdq_pkt *pkt)
 259 {
 260         dma_unmap_single(chan->mbox->dev, pkt->pa_base, pkt->buf_size,
 261                          DMA_TO_DEVICE);
 262         kfree(pkt->va_base);
 263         kfree(pkt);
 264 }
 265
 266 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
 267 {
 268         struct mtk_drm_crtc *mtk_crtc = container_of(cl, struct mtk_drm_crtc, cmdq_cl);
 269         struct cmdq_cb_data *data = mssg;
 270         struct mtk_crtc_state *state;
 271         unsigned int i;
 272
 273         state = to_mtk_crtc_state(mtk_crtc->base.state);
 274
 275         state->pending_config = false;
 276
 277         if (mtk_crtc->pending_planes) {
 278                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 279                         struct drm_plane *plane = &mtk_crtc->planes[i];
 280                         struct mtk_plane_state *plane_state;
 281
 282                         plane_state = to_mtk_plane_state(plane->state);
 283
 284                         plane_state->pending.config = false;
 285                 }
 286                 mtk_crtc->pending_planes = false;
 287         }
 288
 289         if (mtk_crtc->pending_async_planes) {
 290                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 291                         struct drm_plane *plane = &mtk_crtc->planes[i];
 292                         struct mtk_plane_state *plane_state;
 293
 294                         plane_state = to_mtk_plane_state(plane->state);
 295
 296                         plane_state->pending.async_config = false;
 297                 }
 298                 mtk_crtc->pending_async_planes = false;
 299         }
 300
 301         mtk_crtc->cmdq_vblank_cnt = 0;
 302         mtk_drm_cmdq_pkt_destroy(mtk_crtc->cmdq_chan, data->pkt);
 303 }
 304 #endif
 305
 306 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
 307 {
 308         struct drm_crtc *crtc = &mtk_crtc->base;
 309         struct drm_connector *connector;
 310         struct drm_encoder *encoder;
 311         struct drm_connector_list_iter conn_iter;
 312         unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
 313         int ret;
 314         int i;
 315
 316         if (WARN_ON(!crtc->state))
 317                 return -EINVAL;
 318
 319         width = crtc->state->adjusted_mode.hdisplay;
 320         height = crtc->state->adjusted_mode.vdisplay;
 321         vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
 322
 323         drm_for_each_encoder(encoder, crtc->dev) {
 324                 if (encoder->crtc != crtc)
 325                         continue;
 326
 327                 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 328                 drm_for_each_connector_iter(connector, &conn_iter) {
 329                         if (connector->encoder != encoder)
 330                                 continue;
 331                         if (connector->display_info.bpc != 0 &&
 332                             bpc > connector->display_info.bpc)
 333                                 bpc = connector->display_info.bpc;
 334                 }
 335                 drm_connector_list_iter_end(&conn_iter);
 336         }
 337
 338         ret = pm_runtime_resume_and_get(crtc->dev->dev);
 339         if (ret < 0) {
 340                 DRM_ERROR("Failed to enable power domain: %d\n", ret);
 341                 return ret;
 342         }
 343
 344         ret = mtk_mutex_prepare(mtk_crtc->mutex);
 345         if (ret < 0) {
 346                 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
 347                 goto err_pm_runtime_put;
 348         }
 349
 350         ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
 351         if (ret < 0) {
 352                 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
 353                 goto err_mutex_unprepare;
 354         }
 355
 356         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 357                 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
 358                                       mtk_crtc->ddp_comp[i]->id,
 359                                       mtk_crtc->ddp_comp[i + 1]->id);
 360                 mtk_mutex_add_comp(mtk_crtc->mutex,
 361                                         mtk_crtc->ddp_comp[i]->id);
 362         }
 363         mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 364         mtk_mutex_enable(mtk_crtc->mutex);
 365
 366         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 367                 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
 368
 369                 if (i == 1)
 370                         mtk_ddp_comp_bgclr_in_on(comp);
 371
 372                 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
 373                 mtk_ddp_comp_start(comp);
 374         }
 375
 376         /* Initially configure all planes */
 377         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 378                 struct drm_plane *plane = &mtk_crtc->planes[i];
 379                 struct mtk_plane_state *plane_state;
 380                 struct mtk_ddp_comp *comp;
 381                 unsigned int local_layer;
 382
 383                 plane_state = to_mtk_plane_state(plane->state);
 384                 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
 385                 if (comp)
 386                         mtk_ddp_comp_layer_config(comp, local_layer,
 387                                                   plane_state, NULL);
 388         }
 389
 390         return 0;
 391
 392 err_mutex_unprepare:
 393         mtk_mutex_unprepare(mtk_crtc->mutex);
 394 err_pm_runtime_put:
 395         pm_runtime_put(crtc->dev->dev);
 396         return ret;
 397 }
 398
 399 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
 400 {
 401         struct drm_device *drm = mtk_crtc->base.dev;
 402         struct drm_crtc *crtc = &mtk_crtc->base;
 403         int i;
 404
 405         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 406                 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
 407                 if (i == 1)
 408                         mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
 409         }
 410
 411         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 412                 mtk_mutex_remove_comp(mtk_crtc->mutex,
 413                                            mtk_crtc->ddp_comp[i]->id);
 414         mtk_mutex_disable(mtk_crtc->mutex);
 415         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 416                 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
 417                                          mtk_crtc->ddp_comp[i]->id,
 418                                          mtk_crtc->ddp_comp[i + 1]->id);
 419                 mtk_mutex_remove_comp(mtk_crtc->mutex,
 420                                            mtk_crtc->ddp_comp[i]->id);
 421         }
 422         mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 423         mtk_crtc_ddp_clk_disable(mtk_crtc);
 424         mtk_mutex_unprepare(mtk_crtc->mutex);
 425
 426         pm_runtime_put(drm->dev);
 427
 428         if (crtc->state->event && !crtc->state->active) {
 429                 spin_lock_irq(&crtc->dev->event_lock);
 430                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 431                 crtc->state->event = NULL;
 432                 spin_unlock_irq(&crtc->dev->event_lock);
 433         }
 434 }
 435
 436 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
 437                                 struct cmdq_pkt *cmdq_handle)
 438 {
 439         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 440         struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
 441         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 442         unsigned int i;
 443         unsigned int local_layer;
 444
 445         /*
 446          * TODO: instead of updating the registers here, we should prepare
 447          * working registers in atomic_commit and let the hardware command
 448          * queue update module registers on vblank.
 449          */
 450         if (state->pending_config) {
 451                 mtk_ddp_comp_config(comp, state->pending_width,
 452                                     state->pending_height,
 453                                     state->pending_vrefresh, 0,
 454                                     cmdq_handle);
 455
 456                 if (!cmdq_handle)
 457                         state->pending_config = false;
 458         }
 459
 460         if (mtk_crtc->pending_planes) {
 461                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 462                         struct drm_plane *plane = &mtk_crtc->planes[i];
 463                         struct mtk_plane_state *plane_state;
 464
 465                         plane_state = to_mtk_plane_state(plane->state);
 466
 467                         if (!plane_state->pending.config)
 468                                 continue;
 469
 470                         comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
 471                                                           &local_layer);
 472
 473                         if (comp)
 474                                 mtk_ddp_comp_layer_config(comp, local_layer,
 475                                                           plane_state,
 476                                                           cmdq_handle);
 477                         if (!cmdq_handle)
 478                                 plane_state->pending.config = false;
 479                 }
 480
 481                 if (!cmdq_handle)
 482                         mtk_crtc->pending_planes = false;
 483         }
 484
 485         if (mtk_crtc->pending_async_planes) {
 486                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 487                         struct drm_plane *plane = &mtk_crtc->planes[i];
 488                         struct mtk_plane_state *plane_state;
 489
 490                         plane_state = to_mtk_plane_state(plane->state);
 491
 492                         if (!plane_state->pending.async_config)
 493                                 continue;
 494
 495                         comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
 496                                                           &local_layer);
 497
 498                         if (comp)
 499                                 mtk_ddp_comp_layer_config(comp, local_layer,
 500                                                           plane_state,
 501                                                           cmdq_handle);
 502                         if (!cmdq_handle)
 503                                 plane_state->pending.async_config = false;
 504                 }
 505
 506                 if (!cmdq_handle)
 507                         mtk_crtc->pending_async_planes = false;
 508         }
 509 }
 510
 511 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
 512                                        bool needs_vblank)
 513 {
 514 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 515         struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
 516 #endif
 517         struct drm_crtc *crtc = &mtk_crtc->base;
 518         struct mtk_drm_private *priv = crtc->dev->dev_private;
 519         unsigned int pending_planes = 0, pending_async_planes = 0;
 520         int i;
 521
 522         mutex_lock(&mtk_crtc->hw_lock);
 523         mtk_crtc->config_updating = true;
 524         if (needs_vblank)
 525                 mtk_crtc->pending_needs_vblank = true;
 526
 527         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 528                 struct drm_plane *plane = &mtk_crtc->planes[i];
 529                 struct mtk_plane_state *plane_state;
 530
 531                 plane_state = to_mtk_plane_state(plane->state);
 532                 if (plane_state->pending.dirty) {
 533                         plane_state->pending.config = true;
 534                         plane_state->pending.dirty = false;
 535                         pending_planes |= BIT(i);
 536                 } else if (plane_state->pending.async_dirty) {
 537                         plane_state->pending.async_config = true;
 538                         plane_state->pending.async_dirty = false;
 539                         pending_async_planes |= BIT(i);
 540                 }
 541         }
 542         if (pending_planes)
 543                 mtk_crtc->pending_planes = true;
 544         if (pending_async_planes)
 545                 mtk_crtc->pending_async_planes = true;
 546
 547         if (priv->data->shadow_register) {
 548                 mtk_mutex_acquire(mtk_crtc->mutex);
 549                 mtk_crtc_ddp_config(crtc, NULL);
 550                 mtk_mutex_release(mtk_crtc->mutex);
 551         }
 552 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 553         if (mtk_crtc->cmdq_chan) {
 554                 mbox_flush(mtk_crtc->cmdq_chan, 2000);
 555                 cmdq_handle->cmd_buf_size = 0;
 556                 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 557                 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
 558                 mtk_crtc_ddp_config(crtc, cmdq_handle);
 559                 cmdq_pkt_finalize(cmdq_handle);
 560                 dma_sync_single_for_device(mtk_crtc->cmdq_chan->mbox->dev,
 561                                             cmdq_handle->pa_base,
 562                                             cmdq_handle->cmd_buf_size,
 563                                             DMA_TO_DEVICE);
 564                 /*
 565                  * CMDQ command should execute in next vblank,
 566                  * If it fail to execute in next 2 vblank, timeout happen.
 567                  */
 568                 mtk_crtc->cmdq_vblank_cnt = 2;
 569                 mbox_send_message(mtk_crtc->cmdq_chan, cmdq_handle);
 570                 mbox_client_txdone(mtk_crtc->cmdq_chan, 0);
 571         }
 572 #endif
 573         mtk_crtc->config_updating = false;
 574         mutex_unlock(&mtk_crtc->hw_lock);
 575 }
 576
 577 static void mtk_crtc_ddp_irq(void *data)
 578 {
 579         struct drm_crtc *crtc = data;
 580         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 581         struct mtk_drm_private *priv = crtc->dev->dev_private;
 582
 583 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 584         if (!priv->data->shadow_register && !mtk_crtc->cmdq_chan)
 585                 mtk_crtc_ddp_config(crtc, NULL);
 586         else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
 587                 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
 588                           drm_crtc_index(&mtk_crtc->base));
 589 #else
 590         if (!priv->data->shadow_register)
 591                 mtk_crtc_ddp_config(crtc, NULL);
 592 #endif
 593         mtk_drm_finish_page_flip(mtk_crtc);
 594 }
 595
 596 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
 597 {
 598         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 599         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 600
 601         mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
 602
 603         return 0;
 604 }
 605
 606 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
 607 {
 608         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 609         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 610
 611         mtk_ddp_comp_disable_vblank(comp);
 612 }
 613
 614 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
 615                              struct mtk_plane_state *state)
 616 {
 617         unsigned int local_layer;
 618         struct mtk_ddp_comp *comp;
 619
 620         comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
 621         if (comp)
 622                 return mtk_ddp_comp_layer_check(comp, local_layer, state);
 623         return 0;
 624 }
 625
 626 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
 627                                struct drm_atomic_state *state)
 628 {
 629         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 630         const struct drm_plane_helper_funcs *plane_helper_funcs =
 631                         plane->helper_private;
 632
 633         if (!mtk_crtc->enabled)
 634                 return;
 635
 636         plane_helper_funcs->atomic_update(plane, state);
 637         mtk_drm_crtc_update_config(mtk_crtc, false);
 638 }
 639
 640 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 641                                        struct drm_atomic_state *state)
 642 {
 643         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 644         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 645         int ret;
 646
 647         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 648
 649         ret = mtk_smi_larb_get(comp->larb_dev);
 650         if (ret) {
 651                 DRM_ERROR("Failed to get larb: %d\n", ret);
 652                 return;
 653         }
 654
 655         ret = mtk_crtc_ddp_hw_init(mtk_crtc);
 656         if (ret) {
 657                 mtk_smi_larb_put(comp->larb_dev);
 658                 return;
 659         }
 660
 661         drm_crtc_vblank_on(crtc);
 662         mtk_crtc->enabled = true;
 663 }
 664
 665 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 666                                         struct drm_atomic_state *state)
 667 {
 668         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 669         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 670         int i;
 671
 672         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 673         if (!mtk_crtc->enabled)
 674                 return;
 675
 676         /* Set all pending plane state to disabled */
 677         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 678                 struct drm_plane *plane = &mtk_crtc->planes[i];
 679                 struct mtk_plane_state *plane_state;
 680
 681                 plane_state = to_mtk_plane_state(plane->state);
 682                 plane_state->pending.enable = false;
 683                 plane_state->pending.config = true;
 684         }
 685         mtk_crtc->pending_planes = true;
 686
 687         mtk_drm_crtc_update_config(mtk_crtc, false);
 688         /* Wait for planes to be disabled */
 689         drm_crtc_wait_one_vblank(crtc);
 690
 691         drm_crtc_vblank_off(crtc);
 692         mtk_crtc_ddp_hw_fini(mtk_crtc);
 693         mtk_smi_larb_put(comp->larb_dev);
 694
 695         mtk_crtc->enabled = false;
 696 }
 697
 698 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 699                                       struct drm_atomic_state *state)
 700 {
 701         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 702                                                                           crtc);
 703         struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
 704         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 705
 706         if (mtk_crtc->event && mtk_crtc_state->base.event)
 707                 DRM_ERROR("new event while there is still a pending event\n");
 708
 709         if (mtk_crtc_state->base.event) {
 710                 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
 711                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 712                 mtk_crtc->event = mtk_crtc_state->base.event;
 713                 mtk_crtc_state->base.event = NULL;
 714         }
 715 }
 716
 717 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 718                                       struct drm_atomic_state *state)
 719 {
 720         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 721         int i;
 722
 723         if (crtc->state->color_mgmt_changed)
 724                 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 725                         mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
 726                         mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
 727                 }
 728         mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
 729 }
 730
 731 static const struct drm_crtc_funcs mtk_crtc_funcs = {
 732         .set_config             = drm_atomic_helper_set_config,
 733         .page_flip              = drm_atomic_helper_page_flip,
 734         .destroy                = mtk_drm_crtc_destroy,
 735         .reset                  = mtk_drm_crtc_reset,
 736         .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
 737         .atomic_destroy_state   = mtk_drm_crtc_destroy_state,
 738         .enable_vblank          = mtk_drm_crtc_enable_vblank,
 739         .disable_vblank         = mtk_drm_crtc_disable_vblank,
 740 };
 741
 742 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
 743         .mode_fixup     = mtk_drm_crtc_mode_fixup,
 744         .mode_set_nofb  = mtk_drm_crtc_mode_set_nofb,
 745         .atomic_begin   = mtk_drm_crtc_atomic_begin,
 746         .atomic_flush   = mtk_drm_crtc_atomic_flush,
 747         .atomic_enable  = mtk_drm_crtc_atomic_enable,
 748         .atomic_disable = mtk_drm_crtc_atomic_disable,
 749 };
 750
 751 static int mtk_drm_crtc_init(struct drm_device *drm,
 752                              struct mtk_drm_crtc *mtk_crtc,
 753                              unsigned int pipe)
 754 {
 755         struct drm_plane *primary = NULL;
 756         struct drm_plane *cursor = NULL;
 757         int i, ret;
 758
 759         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 760                 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
 761                         primary = &mtk_crtc->planes[i];
 762                 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
 763                         cursor = &mtk_crtc->planes[i];
 764         }
 765
 766         ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
 767                                         &mtk_crtc_funcs, NULL);
 768         if (ret)
 769                 goto err_cleanup_crtc;
 770
 771         drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
 772
 773         return 0;
 774
 775 err_cleanup_crtc:
 776         drm_crtc_cleanup(&mtk_crtc->base);
 777         return ret;
 778 }
 779
 780 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
 781                                         int comp_idx)
 782 {
 783         struct mtk_ddp_comp *comp;
 784
 785         if (comp_idx > 1)
 786                 return 0;
 787
 788         comp = mtk_crtc->ddp_comp[comp_idx];
 789         if (!comp->funcs)
 790                 return 0;
 791
 792         if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
 793                 return 0;
 794
 795         return mtk_ddp_comp_layer_nr(comp);
 796 }
 797
 798 static inline
 799 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
 800                                             unsigned int num_planes)
 801 {
 802         if (plane_idx == 0)
 803                 return DRM_PLANE_TYPE_PRIMARY;
 804         else if (plane_idx == (num_planes - 1))
 805                 return DRM_PLANE_TYPE_CURSOR;
 806         else
 807                 return DRM_PLANE_TYPE_OVERLAY;
 808
 809 }
 810
 811 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
 812                                          struct mtk_drm_crtc *mtk_crtc,
 813                                          int comp_idx, int pipe)
 814 {
 815         int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
 816         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
 817         int i, ret;
 818
 819         for (i = 0; i < num_planes; i++) {
 820                 ret = mtk_plane_init(drm_dev,
 821                                 &mtk_crtc->planes[mtk_crtc->layer_nr],
 822                                 BIT(pipe),
 823                                 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
 824                                                         num_planes),
 825                                 mtk_ddp_comp_supported_rotations(comp));
 826                 if (ret)
 827                         return ret;
 828
 829                 mtk_crtc->layer_nr++;
 830         }
 831         return 0;
 832 }
 833
 834 int mtk_drm_crtc_create(struct drm_device *drm_dev,
 835                         const enum mtk_ddp_comp_id *path, unsigned int path_len)
 836 {
 837         struct mtk_drm_private *priv = drm_dev->dev_private;
 838         struct device *dev = drm_dev->dev;
 839         struct mtk_drm_crtc *mtk_crtc;
 840         unsigned int num_comp_planes = 0;
 841         int pipe = priv->num_pipes;
 842         int ret;
 843         int i;
 844         bool has_ctm = false;
 845         uint gamma_lut_size = 0;
 846
 847         if (!path)
 848                 return 0;
 849
 850         for (i = 0; i < path_len; i++) {
 851                 enum mtk_ddp_comp_id comp_id = path[i];
 852                 struct device_node *node;
 853                 struct mtk_ddp_comp *comp;
 854
 855                 node = priv->comp_node[comp_id];
 856                 comp = &priv->ddp_comp[comp_id];
 857
 858                 if (!node) {
 859                         dev_info(dev,
 860                                  "Not creating crtc %d because component %d is disabled or missing\n",
 861                                  pipe, comp_id);
 862                         return 0;
 863                 }
 864
 865                 if (!comp->dev) {
 866                         dev_err(dev, "Component %pOF not initialized\n", node);
 867                         return -ENODEV;
 868                 }
 869         }
 870
 871         mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
 872         if (!mtk_crtc)
 873                 return -ENOMEM;
 874
 875         mtk_crtc->mmsys_dev = priv->mmsys_dev;
 876         mtk_crtc->ddp_comp_nr = path_len;
 877         mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
 878                                                 sizeof(*mtk_crtc->ddp_comp),
 879                                                 GFP_KERNEL);
 880         if (!mtk_crtc->ddp_comp)
 881                 return -ENOMEM;
 882
 883         mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
 884         if (IS_ERR(mtk_crtc->mutex)) {
 885                 ret = PTR_ERR(mtk_crtc->mutex);
 886                 dev_err(dev, "Failed to get mutex: %d\n", ret);
 887                 return ret;
 888         }
 889
 890         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 891                 enum mtk_ddp_comp_id comp_id = path[i];
 892                 struct mtk_ddp_comp *comp;
 893
 894                 comp = &priv->ddp_comp[comp_id];
 895                 mtk_crtc->ddp_comp[i] = comp;
 896
 897                 if (comp->funcs) {
 898                         if (comp->funcs->gamma_set)
 899                                 gamma_lut_size = MTK_LUT_SIZE;
 900
 901                         if (comp->funcs->ctm_set)
 902                                 has_ctm = true;
 903                 }
 904         }
 905
 906         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 907                 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
 908
 909         mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
 910                                         sizeof(struct drm_plane), GFP_KERNEL);
 911
 912         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 913                 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
 914                                                     pipe);
 915                 if (ret)
 916                         return ret;
 917         }
 918
 919         ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
 920         if (ret < 0)
 921                 return ret;
 922
 923         if (gamma_lut_size)
 924                 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
 925         drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
 926         priv->num_pipes++;
 927         mutex_init(&mtk_crtc->hw_lock);
 928
 929 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 930         mtk_crtc->cmdq_cl.dev = mtk_crtc->mmsys_dev;
 931         mtk_crtc->cmdq_cl.tx_block = false;
 932         mtk_crtc->cmdq_cl.knows_txdone = true;
 933         mtk_crtc->cmdq_cl.rx_callback = ddp_cmdq_cb;
 934         mtk_crtc->cmdq_chan =
 935                         mbox_request_channel(&mtk_crtc->cmdq_cl,
 936                                               drm_crtc_index(&mtk_crtc->base));
 937         if (IS_ERR(mtk_crtc->cmdq_chan)) {
 938                 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
 939                         drm_crtc_index(&mtk_crtc->base));
 940                 mtk_crtc->cmdq_chan = NULL;
 941         }
 942
 943         if (mtk_crtc->cmdq_chan) {
 944                 ret = of_property_read_u32_index(priv->mutex_node,
 945                                                  "mediatek,gce-events",
 946                                                  drm_crtc_index(&mtk_crtc->base),
 947                                                  &mtk_crtc->cmdq_event);
 948                 if (ret) {
 949                         dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
 950                                 drm_crtc_index(&mtk_crtc->base));
 951                         mbox_free_channel(mtk_crtc->cmdq_chan);
 952                         mtk_crtc->cmdq_chan = NULL;
 953                 } else {
 954                         ret = mtk_drm_cmdq_pkt_create(mtk_crtc->cmdq_chan,
 955                                                        &mtk_crtc->cmdq_handle,
 956                                                        PAGE_SIZE);
 957                         if (ret) {
 958                                 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
 959                                         drm_crtc_index(&mtk_crtc->base));
 960                                 mbox_free_channel(mtk_crtc->cmdq_chan);
 961                                 mtk_crtc->cmdq_chan = NULL;
 962                         }
 963                 }
 964         }
 965 #endif
 966         return 0;
 967 }