1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/circ_buf.h>
32 #include <linux/slab.h>
33 #include <linux/sysrq.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_irq.h>
38 #include "display/intel_display_types.h"
39 #include "display/intel_fifo_underrun.h"
40 #include "display/intel_hotplug.h"
41 #include "display/intel_lpe_audio.h"
42 #include "display/intel_psr.h"
44 #include "gt/intel_breadcrumbs.h"
45 #include "gt/intel_gt.h"
46 #include "gt/intel_gt_irq.h"
47 #include "gt/intel_gt_pm_irq.h"
48 #include "gt/intel_rps.h"
52 #include "i915_trace.h"
56 * DOC: interrupt handling
58 * These functions provide the basic support for enabling and disabling the
59 * interrupt handling support. There's a lot more functionality in i915_irq.c
60 * and related files, but that will be described in separate chapters.
64 * Interrupt statistic for PMU. Increments the counter only if the
65 * interrupt originated from the the GPU so interrupts from a device which
66 * shares the interrupt line are not accounted.
68 static inline void pmu_irq_stats(struct drm_i915_private *i915,
71 if (unlikely(res != IRQ_HANDLED))
75 * A clever compiler translates that into INC. A not so clever one
76 * should at least prevent store tearing.
78 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1);
81 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
83 static const u32 hpd_ilk[HPD_NUM_PINS] = {
84 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
87 static const u32 hpd_ivb[HPD_NUM_PINS] = {
88 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
91 static const u32 hpd_bdw[HPD_NUM_PINS] = {
92 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
95 static const u32 hpd_ibx[HPD_NUM_PINS] = {
96 [HPD_CRT] = SDE_CRT_HOTPLUG,
97 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
98 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
99 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
100 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
103 static const u32 hpd_cpt[HPD_NUM_PINS] = {
104 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
105 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
106 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
107 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
108 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
111 static const u32 hpd_spt[HPD_NUM_PINS] = {
112 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
113 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
114 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
115 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
116 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
119 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
120 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
121 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
122 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
123 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
124 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
125 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
128 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
129 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
130 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
131 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
132 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
133 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
134 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
137 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
138 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
139 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
140 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
141 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
142 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
143 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
146 static const u32 hpd_bxt[HPD_NUM_PINS] = {
147 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
148 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
149 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
152 static const u32 hpd_gen11[HPD_NUM_PINS] = {
153 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1),
154 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2),
155 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3),
156 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4),
157 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5),
158 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6),
161 static const u32 hpd_icp[HPD_NUM_PINS] = {
162 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
163 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
164 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
165 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
166 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
167 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
168 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
169 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
170 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
173 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
175 struct i915_hotplug *hpd = &dev_priv->hotplug;
177 if (HAS_GMCH(dev_priv)) {
178 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
179 IS_CHERRYVIEW(dev_priv))
180 hpd->hpd = hpd_status_g4x;
182 hpd->hpd = hpd_status_i915;
186 if (INTEL_GEN(dev_priv) >= 11)
187 hpd->hpd = hpd_gen11;
188 else if (IS_GEN9_LP(dev_priv))
190 else if (INTEL_GEN(dev_priv) >= 8)
192 else if (INTEL_GEN(dev_priv) >= 7)
197 if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
200 if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
201 HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
202 hpd->pch_hpd = hpd_icp;
203 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
204 hpd->pch_hpd = hpd_spt;
205 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
206 hpd->pch_hpd = hpd_cpt;
207 else if (HAS_PCH_IBX(dev_priv))
208 hpd->pch_hpd = hpd_ibx;
210 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
214 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
216 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
218 drm_crtc_handle_vblank(&crtc->base);
221 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
222 i915_reg_t iir, i915_reg_t ier)
224 intel_uncore_write(uncore, imr, 0xffffffff);
225 intel_uncore_posting_read(uncore, imr);
227 intel_uncore_write(uncore, ier, 0);
229 /* IIR can theoretically queue up two events. Be paranoid. */
230 intel_uncore_write(uncore, iir, 0xffffffff);
231 intel_uncore_posting_read(uncore, iir);
232 intel_uncore_write(uncore, iir, 0xffffffff);
233 intel_uncore_posting_read(uncore, iir);
236 void gen2_irq_reset(struct intel_uncore *uncore)
238 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
239 intel_uncore_posting_read16(uncore, GEN2_IMR);
241 intel_uncore_write16(uncore, GEN2_IER, 0);
243 /* IIR can theoretically queue up two events. Be paranoid. */
244 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
245 intel_uncore_posting_read16(uncore, GEN2_IIR);
246 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
247 intel_uncore_posting_read16(uncore, GEN2_IIR);
251 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
253 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
255 u32 val = intel_uncore_read(uncore, reg);
260 drm_WARN(&uncore->i915->drm, 1,
261 "Interrupt register 0x%x is not zero: 0x%08x\n",
262 i915_mmio_reg_offset(reg), val);
263 intel_uncore_write(uncore, reg, 0xffffffff);
264 intel_uncore_posting_read(uncore, reg);
265 intel_uncore_write(uncore, reg, 0xffffffff);
266 intel_uncore_posting_read(uncore, reg);
269 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
271 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
276 drm_WARN(&uncore->i915->drm, 1,
277 "Interrupt register 0x%x is not zero: 0x%08x\n",
278 i915_mmio_reg_offset(GEN2_IIR), val);
279 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
280 intel_uncore_posting_read16(uncore, GEN2_IIR);
281 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
282 intel_uncore_posting_read16(uncore, GEN2_IIR);
285 void gen3_irq_init(struct intel_uncore *uncore,
286 i915_reg_t imr, u32 imr_val,
287 i915_reg_t ier, u32 ier_val,
290 gen3_assert_iir_is_zero(uncore, iir);
292 intel_uncore_write(uncore, ier, ier_val);
293 intel_uncore_write(uncore, imr, imr_val);
294 intel_uncore_posting_read(uncore, imr);
297 void gen2_irq_init(struct intel_uncore *uncore,
298 u32 imr_val, u32 ier_val)
300 gen2_assert_iir_is_zero(uncore);
302 intel_uncore_write16(uncore, GEN2_IER, ier_val);
303 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
304 intel_uncore_posting_read16(uncore, GEN2_IMR);
307 /* For display hotplug interrupt */
309 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
315 lockdep_assert_held(&dev_priv->irq_lock);
316 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
318 val = I915_READ(PORT_HOTPLUG_EN);
321 I915_WRITE(PORT_HOTPLUG_EN, val);
325 * i915_hotplug_interrupt_update - update hotplug interrupt enable
326 * @dev_priv: driver private
327 * @mask: bits to update
328 * @bits: bits to enable
329 * NOTE: the HPD enable bits are modified both inside and outside
330 * of an interrupt context. To avoid that read-modify-write cycles
331 * interfer, these bits are protected by a spinlock. Since this
332 * function is usually not called from a context where the lock is
333 * held already, this function acquires the lock itself. A non-locking
334 * version is also available.
336 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
340 spin_lock_irq(&dev_priv->irq_lock);
341 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
342 spin_unlock_irq(&dev_priv->irq_lock);
346 * ilk_update_display_irq - update DEIMR
347 * @dev_priv: driver private
348 * @interrupt_mask: mask of interrupt bits to update
349 * @enabled_irq_mask: mask of interrupt bits to enable
351 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
353 u32 enabled_irq_mask)
357 lockdep_assert_held(&dev_priv->irq_lock);
359 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
361 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
364 new_val = dev_priv->irq_mask;
365 new_val &= ~interrupt_mask;
366 new_val |= (~enabled_irq_mask & interrupt_mask);
368 if (new_val != dev_priv->irq_mask) {
369 dev_priv->irq_mask = new_val;
370 I915_WRITE(DEIMR, dev_priv->irq_mask);
376 * bdw_update_port_irq - update DE port interrupt
377 * @dev_priv: driver private
378 * @interrupt_mask: mask of interrupt bits to update
379 * @enabled_irq_mask: mask of interrupt bits to enable
381 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
383 u32 enabled_irq_mask)
388 lockdep_assert_held(&dev_priv->irq_lock);
390 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
392 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
395 old_val = I915_READ(GEN8_DE_PORT_IMR);
398 new_val &= ~interrupt_mask;
399 new_val |= (~enabled_irq_mask & interrupt_mask);
401 if (new_val != old_val) {
402 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
403 POSTING_READ(GEN8_DE_PORT_IMR);
408 * bdw_update_pipe_irq - update DE pipe interrupt
409 * @dev_priv: driver private
410 * @pipe: pipe whose interrupt to update
411 * @interrupt_mask: mask of interrupt bits to update
412 * @enabled_irq_mask: mask of interrupt bits to enable
414 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
417 u32 enabled_irq_mask)
421 lockdep_assert_held(&dev_priv->irq_lock);
423 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
425 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
428 new_val = dev_priv->de_irq_mask[pipe];
429 new_val &= ~interrupt_mask;
430 new_val |= (~enabled_irq_mask & interrupt_mask);
432 if (new_val != dev_priv->de_irq_mask[pipe]) {
433 dev_priv->de_irq_mask[pipe] = new_val;
434 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
435 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
440 * ibx_display_interrupt_update - update SDEIMR
441 * @dev_priv: driver private
442 * @interrupt_mask: mask of interrupt bits to update
443 * @enabled_irq_mask: mask of interrupt bits to enable
445 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
447 u32 enabled_irq_mask)
449 u32 sdeimr = I915_READ(SDEIMR);
450 sdeimr &= ~interrupt_mask;
451 sdeimr |= (~enabled_irq_mask & interrupt_mask);
453 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
455 lockdep_assert_held(&dev_priv->irq_lock);
457 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
460 I915_WRITE(SDEIMR, sdeimr);
461 POSTING_READ(SDEIMR);
464 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
467 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
468 u32 enable_mask = status_mask << 16;
470 lockdep_assert_held(&dev_priv->irq_lock);
472 if (INTEL_GEN(dev_priv) < 5)
476 * On pipe A we don't support the PSR interrupt yet,
477 * on pipe B and C the same bit MBZ.
479 if (drm_WARN_ON_ONCE(&dev_priv->drm,
480 status_mask & PIPE_A_PSR_STATUS_VLV))
483 * On pipe B and C we don't support the PSR interrupt yet, on pipe
484 * A the same bit is for perf counters which we don't use either.
486 if (drm_WARN_ON_ONCE(&dev_priv->drm,
487 status_mask & PIPE_B_PSR_STATUS_VLV))
490 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
491 SPRITE0_FLIP_DONE_INT_EN_VLV |
492 SPRITE1_FLIP_DONE_INT_EN_VLV);
493 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
494 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
495 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
496 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
499 drm_WARN_ONCE(&dev_priv->drm,
500 enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
501 status_mask & ~PIPESTAT_INT_STATUS_MASK,
502 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
503 pipe_name(pipe), enable_mask, status_mask);
508 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
509 enum pipe pipe, u32 status_mask)
511 i915_reg_t reg = PIPESTAT(pipe);
514 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
515 "pipe %c: status_mask=0x%x\n",
516 pipe_name(pipe), status_mask);
518 lockdep_assert_held(&dev_priv->irq_lock);
519 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
521 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
524 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
525 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
527 I915_WRITE(reg, enable_mask | status_mask);
531 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
532 enum pipe pipe, u32 status_mask)
534 i915_reg_t reg = PIPESTAT(pipe);
537 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
538 "pipe %c: status_mask=0x%x\n",
539 pipe_name(pipe), status_mask);
541 lockdep_assert_held(&dev_priv->irq_lock);
542 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
544 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
547 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
548 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
550 I915_WRITE(reg, enable_mask | status_mask);
554 static bool i915_has_asle(struct drm_i915_private *dev_priv)
556 if (!dev_priv->opregion.asle)
559 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
563 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
564 * @dev_priv: i915 device private
566 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
568 if (!i915_has_asle(dev_priv))
571 spin_lock_irq(&dev_priv->irq_lock);
573 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
574 if (INTEL_GEN(dev_priv) >= 4)
575 i915_enable_pipestat(dev_priv, PIPE_A,
576 PIPE_LEGACY_BLC_EVENT_STATUS);
578 spin_unlock_irq(&dev_priv->irq_lock);
582 * This timing diagram depicts the video signal in and
583 * around the vertical blanking period.
585 * Assumptions about the fictitious mode used in this example:
587 * vsync_start = vblank_start + 1
588 * vsync_end = vblank_start + 2
589 * vtotal = vblank_start + 3
592 * latch double buffered registers
593 * increment frame counter (ctg+)
594 * generate start of vblank interrupt (gen4+)
597 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
598 * | may be shifted forward 1-3 extra lines via PIPECONF
600 * | | start of vsync:
601 * | | generate vsync interrupt
603 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
604 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
605 * ----va---> <-----------------vb--------------------> <--------va-------------
606 * | | <----vs-----> |
607 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
608 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
609 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
611 * last visible pixel first visible pixel
612 * | increment frame counter (gen3/4)
613 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
615 * x = horizontal active
616 * _ = horizontal blanking
617 * hs = horizontal sync
618 * va = vertical active
619 * vb = vertical blanking
621 * vbs = vblank_start (number)
624 * - most events happen at the start of horizontal sync
625 * - frame start happens at the start of horizontal blank, 1-4 lines
626 * (depending on PIPECONF settings) after the start of vblank
627 * - gen3/4 pixel and frame counter are synchronized with the start
628 * of horizontal active on the first line of vertical active
631 /* Called from drm generic code, passed a 'crtc', which
632 * we use as a pipe index
634 u32 i915_get_vblank_counter(struct drm_crtc *crtc)
636 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
637 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
638 const struct drm_display_mode *mode = &vblank->hwmode;
639 enum pipe pipe = to_intel_crtc(crtc)->pipe;
640 i915_reg_t high_frame, low_frame;
641 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
642 unsigned long irqflags;
645 * On i965gm TV output the frame counter only works up to
646 * the point when we enable the TV encoder. After that the
647 * frame counter ceases to work and reads zero. We need a
648 * vblank wait before enabling the TV encoder and so we
649 * have to enable vblank interrupts while the frame counter
650 * is still in a working state. However the core vblank code
651 * does not like us returning non-zero frame counter values
652 * when we've told it that we don't have a working frame
653 * counter. Thus we must stop non-zero values leaking out.
655 if (!vblank->max_vblank_count)
658 htotal = mode->crtc_htotal;
659 hsync_start = mode->crtc_hsync_start;
660 vbl_start = mode->crtc_vblank_start;
661 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
662 vbl_start = DIV_ROUND_UP(vbl_start, 2);
664 /* Convert to pixel count */
667 /* Start of vblank event occurs at start of hsync */
668 vbl_start -= htotal - hsync_start;
670 high_frame = PIPEFRAME(pipe);
671 low_frame = PIPEFRAMEPIXEL(pipe);
673 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
676 * High & low register fields aren't synchronized, so make sure
677 * we get a low value that's stable across two reads of the high
681 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
682 low = intel_de_read_fw(dev_priv, low_frame);
683 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
684 } while (high1 != high2);
686 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
688 high1 >>= PIPE_FRAME_HIGH_SHIFT;
689 pixel = low & PIPE_PIXEL_MASK;
690 low >>= PIPE_FRAME_LOW_SHIFT;
693 * The frame counter increments at beginning of active.
694 * Cook up a vblank counter by also checking the pixel
695 * counter against vblank start.
697 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
700 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
702 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
703 enum pipe pipe = to_intel_crtc(crtc)->pipe;
705 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
709 * On certain encoders on certain platforms, pipe
710 * scanline register will not work to get the scanline,
711 * since the timings are driven from the PORT or issues
712 * with scanline register updates.
713 * This function will use Framestamp and current
714 * timestamp registers to calculate the scanline.
716 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
718 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
719 struct drm_vblank_crtc *vblank =
720 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
721 const struct drm_display_mode *mode = &vblank->hwmode;
722 u32 vblank_start = mode->crtc_vblank_start;
723 u32 vtotal = mode->crtc_vtotal;
724 u32 htotal = mode->crtc_htotal;
725 u32 clock = mode->crtc_clock;
726 u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
729 * To avoid the race condition where we might cross into the
730 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
731 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
732 * during the same frame.
736 * This field provides read back of the display
737 * pipe frame time stamp. The time stamp value
738 * is sampled at every start of vertical blank.
740 scan_prev_time = intel_de_read_fw(dev_priv,
741 PIPE_FRMTMSTMP(crtc->pipe));
744 * The TIMESTAMP_CTR register has the current
747 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
749 scan_post_time = intel_de_read_fw(dev_priv,
750 PIPE_FRMTMSTMP(crtc->pipe));
751 } while (scan_post_time != scan_prev_time);
753 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
754 clock), 1000 * htotal);
755 scanline = min(scanline, vtotal - 1);
756 scanline = (scanline + vblank_start) % vtotal;
762 * intel_de_read_fw(), only for fast reads of display block, no need for
765 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
767 struct drm_device *dev = crtc->base.dev;
768 struct drm_i915_private *dev_priv = to_i915(dev);
769 const struct drm_display_mode *mode;
770 struct drm_vblank_crtc *vblank;
771 enum pipe pipe = crtc->pipe;
772 int position, vtotal;
777 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
778 mode = &vblank->hwmode;
780 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
781 return __intel_get_crtc_scanline_from_timestamp(crtc);
783 vtotal = mode->crtc_vtotal;
784 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
787 if (IS_GEN(dev_priv, 2))
788 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
790 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
793 * On HSW, the DSL reg (0x70000) appears to return 0 if we
794 * read it just before the start of vblank. So try it again
795 * so we don't accidentally end up spanning a vblank frame
796 * increment, causing the pipe_update_end() code to squak at us.
798 * The nature of this problem means we can't simply check the ISR
799 * bit and return the vblank start value; nor can we use the scanline
800 * debug register in the transcoder as it appears to have the same
801 * problem. We may need to extend this to include other platforms,
802 * but so far testing only shows the problem on HSW.
804 if (HAS_DDI(dev_priv) && !position) {
807 for (i = 0; i < 100; i++) {
809 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
810 if (temp != position) {
818 * See update_scanline_offset() for the details on the
819 * scanline_offset adjustment.
821 return (position + crtc->scanline_offset) % vtotal;
824 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
826 int *vpos, int *hpos,
827 ktime_t *stime, ktime_t *etime,
828 const struct drm_display_mode *mode)
830 struct drm_device *dev = _crtc->dev;
831 struct drm_i915_private *dev_priv = to_i915(dev);
832 struct intel_crtc *crtc = to_intel_crtc(_crtc);
833 enum pipe pipe = crtc->pipe;
835 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
836 unsigned long irqflags;
837 bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
838 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
839 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
841 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
842 drm_dbg(&dev_priv->drm,
843 "trying to get scanoutpos for disabled "
844 "pipe %c\n", pipe_name(pipe));
848 htotal = mode->crtc_htotal;
849 hsync_start = mode->crtc_hsync_start;
850 vtotal = mode->crtc_vtotal;
851 vbl_start = mode->crtc_vblank_start;
852 vbl_end = mode->crtc_vblank_end;
854 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
855 vbl_start = DIV_ROUND_UP(vbl_start, 2);
861 * Lock uncore.lock, as we will do multiple timing critical raw
862 * register reads, potentially with preemption disabled, so the
863 * following code must not block on uncore.lock.
865 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
867 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
869 /* Get optional system timestamp before query. */
871 *stime = ktime_get();
873 if (use_scanline_counter) {
874 /* No obvious pixelcount register. Only query vertical
875 * scanout position from Display scan line register.
877 position = __intel_get_crtc_scanline(crtc);
879 /* Have access to pixelcount since start of frame.
880 * We can split this into vertical and horizontal
883 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
885 /* convert to pixel counts */
891 * In interlaced modes, the pixel counter counts all pixels,
892 * so one field will have htotal more pixels. In order to avoid
893 * the reported position from jumping backwards when the pixel
894 * counter is beyond the length of the shorter field, just
895 * clamp the position the length of the shorter field. This
896 * matches how the scanline counter based position works since
897 * the scanline counter doesn't count the two half lines.
899 if (position >= vtotal)
900 position = vtotal - 1;
903 * Start of vblank interrupt is triggered at start of hsync,
904 * just prior to the first active line of vblank. However we
905 * consider lines to start at the leading edge of horizontal
906 * active. So, should we get here before we've crossed into
907 * the horizontal active of the first line in vblank, we would
908 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
909 * always add htotal-hsync_start to the current pixel position.
911 position = (position + htotal - hsync_start) % vtotal;
914 /* Get optional system timestamp after query. */
916 *etime = ktime_get();
918 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
920 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
923 * While in vblank, position will be negative
924 * counting up towards 0 at vbl_end. And outside
925 * vblank, position will be positive counting
928 if (position >= vbl_start)
931 position += vtotal - vbl_end;
933 if (use_scanline_counter) {
937 *vpos = position / htotal;
938 *hpos = position - (*vpos * htotal);
944 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
945 ktime_t *vblank_time, bool in_vblank_irq)
947 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
948 crtc, max_error, vblank_time, in_vblank_irq,
949 i915_get_crtc_scanoutpos);
952 int intel_get_crtc_scanline(struct intel_crtc *crtc)
954 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
955 unsigned long irqflags;
958 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
959 position = __intel_get_crtc_scanline(crtc);
960 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
966 * ivb_parity_work - Workqueue called when a parity error interrupt
968 * @work: workqueue struct
970 * Doesn't actually do anything except notify userspace. As a consequence of
971 * this event, userspace should try to remap the bad rows since statistically
972 * it is likely the same row is more likely to go bad again.
974 static void ivb_parity_work(struct work_struct *work)
976 struct drm_i915_private *dev_priv =
977 container_of(work, typeof(*dev_priv), l3_parity.error_work);
978 struct intel_gt *gt = &dev_priv->gt;
979 u32 error_status, row, bank, subbank;
980 char *parity_event[6];
984 /* We must turn off DOP level clock gating to access the L3 registers.
985 * In order to prevent a get/put style interface, acquire struct mutex
986 * any time we access those registers.
988 mutex_lock(&dev_priv->drm.struct_mutex);
990 /* If we've screwed up tracking, just let the interrupt fire again */
991 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
994 misccpctl = I915_READ(GEN7_MISCCPCTL);
995 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
996 POSTING_READ(GEN7_MISCCPCTL);
998 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1002 if (drm_WARN_ON_ONCE(&dev_priv->drm,
1003 slice >= NUM_L3_SLICES(dev_priv)))
1006 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1008 reg = GEN7_L3CDERRST1(slice);
1010 error_status = I915_READ(reg);
1011 row = GEN7_PARITY_ERROR_ROW(error_status);
1012 bank = GEN7_PARITY_ERROR_BANK(error_status);
1013 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1015 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1018 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1019 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1020 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1021 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1022 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1023 parity_event[5] = NULL;
1025 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1026 KOBJ_CHANGE, parity_event);
1028 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1029 slice, row, bank, subbank);
1031 kfree(parity_event[4]);
1032 kfree(parity_event[3]);
1033 kfree(parity_event[2]);
1034 kfree(parity_event[1]);
1037 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1040 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
1041 spin_lock_irq(>->irq_lock);
1042 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1043 spin_unlock_irq(>->irq_lock);
1045 mutex_unlock(&dev_priv->drm.struct_mutex);
1048 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1052 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1054 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1056 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1058 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1060 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
1062 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
1068 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1072 return val & PORTA_HOTPLUG_LONG_DETECT;
1074 return val & PORTB_HOTPLUG_LONG_DETECT;
1076 return val & PORTC_HOTPLUG_LONG_DETECT;
1082 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1086 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
1088 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
1090 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
1096 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1100 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1102 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1104 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1106 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1108 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
1110 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
1116 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1120 return val & PORTE_HOTPLUG_LONG_DETECT;
1126 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1130 return val & PORTA_HOTPLUG_LONG_DETECT;
1132 return val & PORTB_HOTPLUG_LONG_DETECT;
1134 return val & PORTC_HOTPLUG_LONG_DETECT;
1136 return val & PORTD_HOTPLUG_LONG_DETECT;
1142 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1146 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1152 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1156 return val & PORTB_HOTPLUG_LONG_DETECT;
1158 return val & PORTC_HOTPLUG_LONG_DETECT;
1160 return val & PORTD_HOTPLUG_LONG_DETECT;
1166 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1170 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1172 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1174 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1181 * Get a bit mask of pins that have triggered, and which ones may be long.
1182 * This can be called multiple times with the same masks to accumulate
1183 * hotplug detection results from several registers.
1185 * Note that the caller is expected to zero out the masks initially.
1187 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1188 u32 *pin_mask, u32 *long_mask,
1189 u32 hotplug_trigger, u32 dig_hotplug_reg,
1190 const u32 hpd[HPD_NUM_PINS],
1191 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1195 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1197 for_each_hpd_pin(pin) {
1198 if ((hpd[pin] & hotplug_trigger) == 0)
1201 *pin_mask |= BIT(pin);
1203 if (long_pulse_detect(pin, dig_hotplug_reg))
1204 *long_mask |= BIT(pin);
1207 drm_dbg(&dev_priv->drm,
1208 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1209 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1213 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1215 wake_up_all(&dev_priv->gmbus_wait_queue);
1218 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1220 wake_up_all(&dev_priv->gmbus_wait_queue);
1223 #if defined(CONFIG_DEBUG_FS)
1224 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1230 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1231 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1232 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1234 trace_intel_pipe_crc(crtc, crcs);
1236 spin_lock(&pipe_crc->lock);
1238 * For some not yet identified reason, the first CRC is
1239 * bonkers. So let's just wait for the next vblank and read
1240 * out the buggy result.
1242 * On GEN8+ sometimes the second CRC is bonkers as well, so
1243 * don't trust that one either.
1245 if (pipe_crc->skipped <= 0 ||
1246 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1247 pipe_crc->skipped++;
1248 spin_unlock(&pipe_crc->lock);
1251 spin_unlock(&pipe_crc->lock);
1253 drm_crtc_add_crc_entry(&crtc->base, true,
1254 drm_crtc_accurate_vblank_count(&crtc->base),
1259 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1267 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1270 display_pipe_crc_irq_handler(dev_priv, pipe,
1271 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1275 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1278 display_pipe_crc_irq_handler(dev_priv, pipe,
1279 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1280 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1281 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1282 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1283 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1286 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1291 if (INTEL_GEN(dev_priv) >= 3)
1292 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1296 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1297 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1301 display_pipe_crc_irq_handler(dev_priv, pipe,
1302 I915_READ(PIPE_CRC_RES_RED(pipe)),
1303 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1304 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1308 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1312 for_each_pipe(dev_priv, pipe) {
1313 I915_WRITE(PIPESTAT(pipe),
1314 PIPESTAT_INT_STATUS_MASK |
1315 PIPE_FIFO_UNDERRUN_STATUS);
1317 dev_priv->pipestat_irq_mask[pipe] = 0;
1321 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1322 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1326 spin_lock(&dev_priv->irq_lock);
1328 if (!dev_priv->display_irqs_enabled) {
1329 spin_unlock(&dev_priv->irq_lock);
1333 for_each_pipe(dev_priv, pipe) {
1335 u32 status_mask, enable_mask, iir_bit = 0;
1338 * PIPESTAT bits get signalled even when the interrupt is
1339 * disabled with the mask bits, and some of the status bits do
1340 * not generate interrupts at all (like the underrun bit). Hence
1341 * we need to be careful that we only handle what we want to
1345 /* fifo underruns are filterered in the underrun handler. */
1346 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1351 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1354 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1357 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1361 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1366 reg = PIPESTAT(pipe);
1367 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1368 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1371 * Clear the PIPE*STAT regs before the IIR
1373 * Toggle the enable bits to make sure we get an
1374 * edge in the ISR pipe event bit if we don't clear
1375 * all the enabled status bits. Otherwise the edge
1376 * triggered IIR on i965/g4x wouldn't notice that
1377 * an interrupt is still pending.
1379 if (pipe_stats[pipe]) {
1380 I915_WRITE(reg, pipe_stats[pipe]);
1381 I915_WRITE(reg, enable_mask);
1384 spin_unlock(&dev_priv->irq_lock);
1387 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1388 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1392 for_each_pipe(dev_priv, pipe) {
1393 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1394 intel_handle_vblank(dev_priv, pipe);
1396 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1397 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1399 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1400 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1404 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1405 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1407 bool blc_event = false;
1410 for_each_pipe(dev_priv, pipe) {
1411 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1412 intel_handle_vblank(dev_priv, pipe);
1414 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1417 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1418 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1420 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1421 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1424 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1425 intel_opregion_asle_intr(dev_priv);
1428 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1429 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1431 bool blc_event = false;
1434 for_each_pipe(dev_priv, pipe) {
1435 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1436 intel_handle_vblank(dev_priv, pipe);
1438 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1441 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1442 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1444 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1445 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1448 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1449 intel_opregion_asle_intr(dev_priv);
1451 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1452 gmbus_irq_handler(dev_priv);
1455 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1456 u32 pipe_stats[I915_MAX_PIPES])
1460 for_each_pipe(dev_priv, pipe) {
1461 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1462 intel_handle_vblank(dev_priv, pipe);
1464 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1465 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1467 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1468 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1471 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1472 gmbus_irq_handler(dev_priv);
1475 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1477 u32 hotplug_status = 0, hotplug_status_mask;
1480 if (IS_G4X(dev_priv) ||
1481 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1482 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1483 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1485 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1488 * We absolutely have to clear all the pending interrupt
1489 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1490 * interrupt bit won't have an edge, and the i965/g4x
1491 * edge triggered IIR will not notice that an interrupt
1492 * is still pending. We can't use PORT_HOTPLUG_EN to
1493 * guarantee the edge as the act of toggling the enable
1494 * bits can itself generate a new hotplug interrupt :(
1496 for (i = 0; i < 10; i++) {
1497 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1500 return hotplug_status;
1502 hotplug_status |= tmp;
1503 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1506 drm_WARN_ONCE(&dev_priv->drm, 1,
1507 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1508 I915_READ(PORT_HOTPLUG_STAT));
1510 return hotplug_status;
1513 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1516 u32 pin_mask = 0, long_mask = 0;
1517 u32 hotplug_trigger;
1519 if (IS_G4X(dev_priv) ||
1520 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1521 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1523 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1525 if (hotplug_trigger) {
1526 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1527 hotplug_trigger, hotplug_trigger,
1528 dev_priv->hotplug.hpd,
1529 i9xx_port_hotplug_long_detect);
1531 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1534 if ((IS_G4X(dev_priv) ||
1535 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1536 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1537 dp_aux_irq_handler(dev_priv);
1540 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1542 struct drm_i915_private *dev_priv = arg;
1543 irqreturn_t ret = IRQ_NONE;
1545 if (!intel_irqs_enabled(dev_priv))
1548 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1549 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1552 u32 iir, gt_iir, pm_iir;
1553 u32 pipe_stats[I915_MAX_PIPES] = {};
1554 u32 hotplug_status = 0;
1557 gt_iir = I915_READ(GTIIR);
1558 pm_iir = I915_READ(GEN6_PMIIR);
1559 iir = I915_READ(VLV_IIR);
1561 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1567 * Theory on interrupt generation, based on empirical evidence:
1569 * x = ((VLV_IIR & VLV_IER) ||
1570 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1571 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1573 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1574 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1575 * guarantee the CPU interrupt will be raised again even if we
1576 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1577 * bits this time around.
1579 I915_WRITE(VLV_MASTER_IER, 0);
1580 ier = I915_READ(VLV_IER);
1581 I915_WRITE(VLV_IER, 0);
1584 I915_WRITE(GTIIR, gt_iir);
1586 I915_WRITE(GEN6_PMIIR, pm_iir);
1588 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1589 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1591 /* Call regardless, as some status bits might not be
1592 * signalled in iir */
1593 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1595 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1596 I915_LPE_PIPE_B_INTERRUPT))
1597 intel_lpe_audio_irq_handler(dev_priv);
1600 * VLV_IIR is single buffered, and reflects the level
1601 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1604 I915_WRITE(VLV_IIR, iir);
1606 I915_WRITE(VLV_IER, ier);
1607 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1610 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1612 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1615 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1617 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1620 pmu_irq_stats(dev_priv, ret);
1622 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1627 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1629 struct drm_i915_private *dev_priv = arg;
1630 irqreturn_t ret = IRQ_NONE;
1632 if (!intel_irqs_enabled(dev_priv))
1635 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1636 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1639 u32 master_ctl, iir;
1640 u32 pipe_stats[I915_MAX_PIPES] = {};
1641 u32 hotplug_status = 0;
1644 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1645 iir = I915_READ(VLV_IIR);
1647 if (master_ctl == 0 && iir == 0)
1653 * Theory on interrupt generation, based on empirical evidence:
1655 * x = ((VLV_IIR & VLV_IER) ||
1656 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1657 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1659 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1660 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1661 * guarantee the CPU interrupt will be raised again even if we
1662 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1663 * bits this time around.
1665 I915_WRITE(GEN8_MASTER_IRQ, 0);
1666 ier = I915_READ(VLV_IER);
1667 I915_WRITE(VLV_IER, 0);
1669 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1671 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1672 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1674 /* Call regardless, as some status bits might not be
1675 * signalled in iir */
1676 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1678 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1679 I915_LPE_PIPE_B_INTERRUPT |
1680 I915_LPE_PIPE_C_INTERRUPT))
1681 intel_lpe_audio_irq_handler(dev_priv);
1684 * VLV_IIR is single buffered, and reflects the level
1685 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1688 I915_WRITE(VLV_IIR, iir);
1690 I915_WRITE(VLV_IER, ier);
1691 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1694 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1696 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1699 pmu_irq_stats(dev_priv, ret);
1701 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1706 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1707 u32 hotplug_trigger)
1709 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1712 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1713 * unless we touch the hotplug register, even if hotplug_trigger is
1714 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1717 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1718 if (!hotplug_trigger) {
1719 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1720 PORTD_HOTPLUG_STATUS_MASK |
1721 PORTC_HOTPLUG_STATUS_MASK |
1722 PORTB_HOTPLUG_STATUS_MASK;
1723 dig_hotplug_reg &= ~mask;
1726 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1727 if (!hotplug_trigger)
1730 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1731 hotplug_trigger, dig_hotplug_reg,
1732 dev_priv->hotplug.pch_hpd,
1733 pch_port_hotplug_long_detect);
1735 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1738 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1741 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1743 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1745 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1746 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1747 SDE_AUDIO_POWER_SHIFT);
1748 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1752 if (pch_iir & SDE_AUX_MASK)
1753 dp_aux_irq_handler(dev_priv);
1755 if (pch_iir & SDE_GMBUS)
1756 gmbus_irq_handler(dev_priv);
1758 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1759 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1761 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1762 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1764 if (pch_iir & SDE_POISON)
1765 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1767 if (pch_iir & SDE_FDI_MASK) {
1768 for_each_pipe(dev_priv, pipe)
1769 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1771 I915_READ(FDI_RX_IIR(pipe)));
1774 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1775 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1777 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1778 drm_dbg(&dev_priv->drm,
1779 "PCH transcoder CRC error interrupt\n");
1781 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1782 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1784 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1785 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1788 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1790 u32 err_int = I915_READ(GEN7_ERR_INT);
1793 if (err_int & ERR_INT_POISON)
1794 drm_err(&dev_priv->drm, "Poison interrupt\n");
1796 for_each_pipe(dev_priv, pipe) {
1797 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1798 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1800 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1801 if (IS_IVYBRIDGE(dev_priv))
1802 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1804 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1808 I915_WRITE(GEN7_ERR_INT, err_int);
1811 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1813 u32 serr_int = I915_READ(SERR_INT);
1816 if (serr_int & SERR_INT_POISON)
1817 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1819 for_each_pipe(dev_priv, pipe)
1820 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1821 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1823 I915_WRITE(SERR_INT, serr_int);
1826 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1829 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1831 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1833 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1834 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1835 SDE_AUDIO_POWER_SHIFT_CPT);
1836 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1840 if (pch_iir & SDE_AUX_MASK_CPT)
1841 dp_aux_irq_handler(dev_priv);
1843 if (pch_iir & SDE_GMBUS_CPT)
1844 gmbus_irq_handler(dev_priv);
1846 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1847 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1849 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1850 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1852 if (pch_iir & SDE_FDI_MASK_CPT) {
1853 for_each_pipe(dev_priv, pipe)
1854 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1856 I915_READ(FDI_RX_IIR(pipe)));
1859 if (pch_iir & SDE_ERROR_CPT)
1860 cpt_serr_int_handler(dev_priv);
1863 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1865 u32 ddi_hotplug_trigger, tc_hotplug_trigger;
1866 u32 pin_mask = 0, long_mask = 0;
1868 if (HAS_PCH_TGP(dev_priv)) {
1869 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1870 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
1871 } else if (HAS_PCH_JSP(dev_priv)) {
1872 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1873 tc_hotplug_trigger = 0;
1874 } else if (HAS_PCH_MCC(dev_priv)) {
1875 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1876 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
1878 drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
1879 "Unrecognized PCH type 0x%x\n",
1880 INTEL_PCH_TYPE(dev_priv));
1882 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1883 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
1886 if (ddi_hotplug_trigger) {
1887 u32 dig_hotplug_reg;
1889 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
1890 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1892 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1893 ddi_hotplug_trigger, dig_hotplug_reg,
1894 dev_priv->hotplug.pch_hpd,
1895 icp_ddi_port_hotplug_long_detect);
1898 if (tc_hotplug_trigger) {
1899 u32 dig_hotplug_reg;
1901 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
1902 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
1904 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1905 tc_hotplug_trigger, dig_hotplug_reg,
1906 dev_priv->hotplug.pch_hpd,
1907 icp_tc_port_hotplug_long_detect);
1911 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1913 if (pch_iir & SDE_GMBUS_ICP)
1914 gmbus_irq_handler(dev_priv);
1917 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1919 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1920 ~SDE_PORTE_HOTPLUG_SPT;
1921 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1922 u32 pin_mask = 0, long_mask = 0;
1924 if (hotplug_trigger) {
1925 u32 dig_hotplug_reg;
1927 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1928 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1930 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1931 hotplug_trigger, dig_hotplug_reg,
1932 dev_priv->hotplug.pch_hpd,
1933 spt_port_hotplug_long_detect);
1936 if (hotplug2_trigger) {
1937 u32 dig_hotplug_reg;
1939 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1940 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1942 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1943 hotplug2_trigger, dig_hotplug_reg,
1944 dev_priv->hotplug.pch_hpd,
1945 spt_port_hotplug2_long_detect);
1949 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1951 if (pch_iir & SDE_GMBUS_CPT)
1952 gmbus_irq_handler(dev_priv);
1955 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
1956 u32 hotplug_trigger)
1958 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1960 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
1961 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
1963 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1964 hotplug_trigger, dig_hotplug_reg,
1965 dev_priv->hotplug.hpd,
1966 ilk_port_hotplug_long_detect);
1968 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1971 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
1975 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
1977 if (hotplug_trigger)
1978 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
1980 if (de_iir & DE_AUX_CHANNEL_A)
1981 dp_aux_irq_handler(dev_priv);
1983 if (de_iir & DE_GSE)
1984 intel_opregion_asle_intr(dev_priv);
1986 if (de_iir & DE_POISON)
1987 drm_err(&dev_priv->drm, "Poison interrupt\n");
1989 for_each_pipe(dev_priv, pipe) {
1990 if (de_iir & DE_PIPE_VBLANK(pipe))
1991 intel_handle_vblank(dev_priv, pipe);
1993 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1994 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1996 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1997 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2000 /* check event from PCH */
2001 if (de_iir & DE_PCH_EVENT) {
2002 u32 pch_iir = I915_READ(SDEIIR);
2004 if (HAS_PCH_CPT(dev_priv))
2005 cpt_irq_handler(dev_priv, pch_iir);
2007 ibx_irq_handler(dev_priv, pch_iir);
2009 /* should clear PCH hotplug event before clear CPU irq */
2010 I915_WRITE(SDEIIR, pch_iir);
2013 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2014 gen5_rps_irq_handler(&dev_priv->gt.rps);
2017 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2021 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2023 if (hotplug_trigger)
2024 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2026 if (de_iir & DE_ERR_INT_IVB)
2027 ivb_err_int_handler(dev_priv);
2029 if (de_iir & DE_EDP_PSR_INT_HSW) {
2030 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2032 intel_psr_irq_handler(dev_priv, psr_iir);
2033 I915_WRITE(EDP_PSR_IIR, psr_iir);
2036 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2037 dp_aux_irq_handler(dev_priv);
2039 if (de_iir & DE_GSE_IVB)
2040 intel_opregion_asle_intr(dev_priv);
2042 for_each_pipe(dev_priv, pipe) {
2043 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2044 intel_handle_vblank(dev_priv, pipe);
2047 /* check event from PCH */
2048 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2049 u32 pch_iir = I915_READ(SDEIIR);
2051 cpt_irq_handler(dev_priv, pch_iir);
2053 /* clear PCH hotplug event before clear CPU irq */
2054 I915_WRITE(SDEIIR, pch_iir);
2059 * To handle irqs with the minimum potential races with fresh interrupts, we:
2060 * 1 - Disable Master Interrupt Control.
2061 * 2 - Find the source(s) of the interrupt.
2062 * 3 - Clear the Interrupt Identity bits (IIR).
2063 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2064 * 5 - Re-enable Master Interrupt Control.
2066 static irqreturn_t ilk_irq_handler(int irq, void *arg)
2068 struct drm_i915_private *i915 = arg;
2069 void __iomem * const regs = i915->uncore.regs;
2070 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2071 irqreturn_t ret = IRQ_NONE;
2073 if (unlikely(!intel_irqs_enabled(i915)))
2076 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2077 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2079 /* disable master interrupt before clearing iir */
2080 de_ier = raw_reg_read(regs, DEIER);
2081 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2083 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2084 * interrupts will will be stored on its back queue, and then we'll be
2085 * able to process them after we restore SDEIER (as soon as we restore
2086 * it, we'll get an interrupt if SDEIIR still has something to process
2087 * due to its back queue). */
2088 if (!HAS_PCH_NOP(i915)) {
2089 sde_ier = raw_reg_read(regs, SDEIER);
2090 raw_reg_write(regs, SDEIER, 0);
2093 /* Find, clear, then process each source of interrupt */
2095 gt_iir = raw_reg_read(regs, GTIIR);
2097 raw_reg_write(regs, GTIIR, gt_iir);
2098 if (INTEL_GEN(i915) >= 6)
2099 gen6_gt_irq_handler(&i915->gt, gt_iir);
2101 gen5_gt_irq_handler(&i915->gt, gt_iir);
2105 de_iir = raw_reg_read(regs, DEIIR);
2107 raw_reg_write(regs, DEIIR, de_iir);
2108 if (INTEL_GEN(i915) >= 7)
2109 ivb_display_irq_handler(i915, de_iir);
2111 ilk_display_irq_handler(i915, de_iir);
2115 if (INTEL_GEN(i915) >= 6) {
2116 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2118 raw_reg_write(regs, GEN6_PMIIR, pm_iir);
2119 gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2124 raw_reg_write(regs, DEIER, de_ier);
2126 raw_reg_write(regs, SDEIER, sde_ier);
2128 pmu_irq_stats(i915, ret);
2130 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2131 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2136 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2137 u32 hotplug_trigger)
2139 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2141 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2142 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2144 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2145 hotplug_trigger, dig_hotplug_reg,
2146 dev_priv->hotplug.hpd,
2147 bxt_port_hotplug_long_detect);
2149 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2152 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2154 u32 pin_mask = 0, long_mask = 0;
2155 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2156 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2159 u32 dig_hotplug_reg;
2161 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2162 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2164 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2165 trigger_tc, dig_hotplug_reg,
2166 dev_priv->hotplug.hpd,
2167 gen11_port_hotplug_long_detect);
2171 u32 dig_hotplug_reg;
2173 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2174 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2176 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2177 trigger_tbt, dig_hotplug_reg,
2178 dev_priv->hotplug.hpd,
2179 gen11_port_hotplug_long_detect);
2183 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2185 drm_err(&dev_priv->drm,
2186 "Unexpected DE HPD interrupt 0x%08x\n", iir);
2189 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2193 if (INTEL_GEN(dev_priv) >= 12)
2194 return TGL_DE_PORT_AUX_DDIA |
2195 TGL_DE_PORT_AUX_DDIB |
2196 TGL_DE_PORT_AUX_DDIC |
2197 TGL_DE_PORT_AUX_USBC1 |
2198 TGL_DE_PORT_AUX_USBC2 |
2199 TGL_DE_PORT_AUX_USBC3 |
2200 TGL_DE_PORT_AUX_USBC4 |
2201 TGL_DE_PORT_AUX_USBC5 |
2202 TGL_DE_PORT_AUX_USBC6;
2205 mask = GEN8_AUX_CHANNEL_A;
2206 if (INTEL_GEN(dev_priv) >= 9)
2207 mask |= GEN9_AUX_CHANNEL_B |
2208 GEN9_AUX_CHANNEL_C |
2211 if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
2212 mask |= CNL_AUX_CHANNEL_F;
2214 if (IS_GEN(dev_priv, 11))
2215 mask |= ICL_AUX_CHANNEL_E;
2220 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2222 if (IS_ROCKETLAKE(dev_priv))
2223 return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
2224 else if (INTEL_GEN(dev_priv) >= 11)
2225 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2226 else if (INTEL_GEN(dev_priv) >= 9)
2227 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2229 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2233 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2237 if (iir & GEN8_DE_MISC_GSE) {
2238 intel_opregion_asle_intr(dev_priv);
2242 if (iir & GEN8_DE_EDP_PSR) {
2246 if (INTEL_GEN(dev_priv) >= 12)
2247 iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
2249 iir_reg = EDP_PSR_IIR;
2251 psr_iir = I915_READ(iir_reg);
2252 I915_WRITE(iir_reg, psr_iir);
2257 intel_psr_irq_handler(dev_priv, psr_iir);
2261 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2265 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2267 irqreturn_t ret = IRQ_NONE;
2271 if (master_ctl & GEN8_DE_MISC_IRQ) {
2272 iir = I915_READ(GEN8_DE_MISC_IIR);
2274 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2276 gen8_de_misc_irq_handler(dev_priv, iir);
2278 drm_err(&dev_priv->drm,
2279 "The master control interrupt lied (DE MISC)!\n");
2283 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2284 iir = I915_READ(GEN11_DE_HPD_IIR);
2286 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2288 gen11_hpd_irq_handler(dev_priv, iir);
2290 drm_err(&dev_priv->drm,
2291 "The master control interrupt lied, (DE HPD)!\n");
2295 if (master_ctl & GEN8_DE_PORT_IRQ) {
2296 iir = I915_READ(GEN8_DE_PORT_IIR);
2301 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2304 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2305 dp_aux_irq_handler(dev_priv);
2309 if (IS_GEN9_LP(dev_priv)) {
2310 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2312 bxt_hpd_irq_handler(dev_priv, tmp_mask);
2315 } else if (IS_BROADWELL(dev_priv)) {
2316 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2318 ilk_hpd_irq_handler(dev_priv, tmp_mask);
2323 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2324 gmbus_irq_handler(dev_priv);
2329 drm_err(&dev_priv->drm,
2330 "Unexpected DE Port interrupt\n");
2333 drm_err(&dev_priv->drm,
2334 "The master control interrupt lied (DE PORT)!\n");
2337 for_each_pipe(dev_priv, pipe) {
2340 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2343 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2345 drm_err(&dev_priv->drm,
2346 "The master control interrupt lied (DE PIPE)!\n");
2351 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2353 if (iir & GEN8_PIPE_VBLANK)
2354 intel_handle_vblank(dev_priv, pipe);
2356 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2357 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2359 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2360 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2362 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2364 drm_err(&dev_priv->drm,
2365 "Fault errors on pipe %c: 0x%08x\n",
2370 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2371 master_ctl & GEN8_DE_PCH_IRQ) {
2373 * FIXME(BDW): Assume for now that the new interrupt handling
2374 * scheme also closed the SDE interrupt handling race we've seen
2375 * on older pch-split platforms. But this needs testing.
2377 iir = I915_READ(SDEIIR);
2379 I915_WRITE(SDEIIR, iir);
2382 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2383 icp_irq_handler(dev_priv, iir);
2384 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2385 spt_irq_handler(dev_priv, iir);
2387 cpt_irq_handler(dev_priv, iir);
2390 * Like on previous PCH there seems to be something
2391 * fishy going on with forwarding PCH interrupts.
2393 drm_dbg(&dev_priv->drm,
2394 "The master control interrupt lied (SDE)!\n");
2401 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2403 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2406 * Now with master disabled, get a sample of level indications
2407 * for this interrupt. Indications will be cleared on related acks.
2408 * New indications can and will light up during processing,
2409 * and will generate new interrupt after enabling master.
2411 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2414 static inline void gen8_master_intr_enable(void __iomem * const regs)
2416 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2419 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2421 struct drm_i915_private *dev_priv = arg;
2422 void __iomem * const regs = dev_priv->uncore.regs;
2425 if (!intel_irqs_enabled(dev_priv))
2428 master_ctl = gen8_master_intr_disable(regs);
2430 gen8_master_intr_enable(regs);
2434 /* Find, queue (onto bottom-halves), then clear each source */
2435 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2437 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2438 if (master_ctl & ~GEN8_GT_IRQS) {
2439 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2440 gen8_de_irq_handler(dev_priv, master_ctl);
2441 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2444 gen8_master_intr_enable(regs);
2446 pmu_irq_stats(dev_priv, IRQ_HANDLED);
2452 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2454 void __iomem * const regs = gt->uncore->regs;
2457 if (!(master_ctl & GEN11_GU_MISC_IRQ))
2460 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2462 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2468 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2470 if (iir & GEN11_GU_MISC_GSE)
2471 intel_opregion_asle_intr(gt->i915);
2474 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2476 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2479 * Now with master disabled, get a sample of level indications
2480 * for this interrupt. Indications will be cleared on related acks.
2481 * New indications can and will light up during processing,
2482 * and will generate new interrupt after enabling master.
2484 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2487 static inline void gen11_master_intr_enable(void __iomem * const regs)
2489 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2493 gen11_display_irq_handler(struct drm_i915_private *i915)
2495 void __iomem * const regs = i915->uncore.regs;
2496 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2498 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2500 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2501 * for the display related bits.
2503 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2504 gen8_de_irq_handler(i915, disp_ctl);
2505 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2506 GEN11_DISPLAY_IRQ_ENABLE);
2508 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2511 static __always_inline irqreturn_t
2512 __gen11_irq_handler(struct drm_i915_private * const i915,
2513 u32 (*intr_disable)(void __iomem * const regs),
2514 void (*intr_enable)(void __iomem * const regs))
2516 void __iomem * const regs = i915->uncore.regs;
2517 struct intel_gt *gt = &i915->gt;
2521 if (!intel_irqs_enabled(i915))
2524 master_ctl = intr_disable(regs);
2530 /* Find, queue (onto bottom-halves), then clear each source */
2531 gen11_gt_irq_handler(gt, master_ctl);
2533 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2534 if (master_ctl & GEN11_DISPLAY_IRQ)
2535 gen11_display_irq_handler(i915);
2537 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2541 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2543 pmu_irq_stats(i915, IRQ_HANDLED);
2548 static irqreturn_t gen11_irq_handler(int irq, void *arg)
2550 return __gen11_irq_handler(arg,
2551 gen11_master_intr_disable,
2552 gen11_master_intr_enable);
2555 static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
2559 /* First disable interrupts */
2560 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
2562 /* Get the indication levels and ack the master unit */
2563 val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
2567 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
2570 * Now with master disabled, get a sample of level indications
2571 * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
2572 * out as this bit doesn't exist anymore for DG1
2574 val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
2578 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
2583 static inline void dg1_master_intr_enable(void __iomem * const regs)
2585 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
2588 static irqreturn_t dg1_irq_handler(int irq, void *arg)
2590 return __gen11_irq_handler(arg,
2591 dg1_master_intr_disable_and_ack,
2592 dg1_master_intr_enable);
2595 /* Called from drm generic code, passed 'crtc' which
2596 * we use as a pipe index
2598 int i8xx_enable_vblank(struct drm_crtc *crtc)
2600 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2601 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2602 unsigned long irqflags;
2604 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2605 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2606 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2611 int i915gm_enable_vblank(struct drm_crtc *crtc)
2613 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2616 * Vblank interrupts fail to wake the device up from C2+.
2617 * Disabling render clock gating during C-states avoids
2618 * the problem. There is a small power cost so we do this
2619 * only when vblank interrupts are actually enabled.
2621 if (dev_priv->vblank_enabled++ == 0)
2622 I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2624 return i8xx_enable_vblank(crtc);
2627 int i965_enable_vblank(struct drm_crtc *crtc)
2629 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2630 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2631 unsigned long irqflags;
2633 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2634 i915_enable_pipestat(dev_priv, pipe,
2635 PIPE_START_VBLANK_INTERRUPT_STATUS);
2636 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2641 int ilk_enable_vblank(struct drm_crtc *crtc)
2643 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2644 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2645 unsigned long irqflags;
2646 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2647 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2649 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2650 ilk_enable_display_irq(dev_priv, bit);
2651 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2653 /* Even though there is no DMC, frame counter can get stuck when
2654 * PSR is active as no frames are generated.
2656 if (HAS_PSR(dev_priv))
2657 drm_crtc_vblank_restore(crtc);
2662 int bdw_enable_vblank(struct drm_crtc *crtc)
2664 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2665 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2666 unsigned long irqflags;
2668 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2669 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2670 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2672 /* Even if there is no DMC, frame counter can get stuck when
2673 * PSR is active as no frames are generated, so check only for PSR.
2675 if (HAS_PSR(dev_priv))
2676 drm_crtc_vblank_restore(crtc);
2681 /* Called from drm generic code, passed 'crtc' which
2682 * we use as a pipe index
2684 void i8xx_disable_vblank(struct drm_crtc *crtc)
2686 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2687 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2688 unsigned long irqflags;
2690 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2691 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2692 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2695 void i915gm_disable_vblank(struct drm_crtc *crtc)
2697 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2699 i8xx_disable_vblank(crtc);
2701 if (--dev_priv->vblank_enabled == 0)
2702 I915_WRITE(SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2705 void i965_disable_vblank(struct drm_crtc *crtc)
2707 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2708 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2709 unsigned long irqflags;
2711 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2712 i915_disable_pipestat(dev_priv, pipe,
2713 PIPE_START_VBLANK_INTERRUPT_STATUS);
2714 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2717 void ilk_disable_vblank(struct drm_crtc *crtc)
2719 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2720 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2721 unsigned long irqflags;
2722 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2723 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2725 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2726 ilk_disable_display_irq(dev_priv, bit);
2727 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2730 void bdw_disable_vblank(struct drm_crtc *crtc)
2732 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2733 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2734 unsigned long irqflags;
2736 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2737 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2738 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2741 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2743 struct intel_uncore *uncore = &dev_priv->uncore;
2745 if (HAS_PCH_NOP(dev_priv))
2748 GEN3_IRQ_RESET(uncore, SDE);
2750 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2751 I915_WRITE(SERR_INT, 0xffffffff);
2755 * SDEIER is also touched by the interrupt handler to work around missed PCH
2756 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2757 * instead we unconditionally enable all PCH interrupt sources here, but then
2758 * only unmask them as needed with SDEIMR.
2760 * This function needs to be called before interrupts are enabled.
2762 static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
2764 if (HAS_PCH_NOP(dev_priv))
2767 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
2768 I915_WRITE(SDEIER, 0xffffffff);
2769 POSTING_READ(SDEIER);
2772 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2774 struct intel_uncore *uncore = &dev_priv->uncore;
2776 if (IS_CHERRYVIEW(dev_priv))
2777 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2779 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
2781 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2782 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2784 i9xx_pipestat_irq_reset(dev_priv);
2786 GEN3_IRQ_RESET(uncore, VLV_);
2787 dev_priv->irq_mask = ~0u;
2790 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2792 struct intel_uncore *uncore = &dev_priv->uncore;
2798 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
2800 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2801 for_each_pipe(dev_priv, pipe)
2802 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2804 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2805 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2806 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2807 I915_LPE_PIPE_A_INTERRUPT |
2808 I915_LPE_PIPE_B_INTERRUPT;
2810 if (IS_CHERRYVIEW(dev_priv))
2811 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
2812 I915_LPE_PIPE_C_INTERRUPT;
2814 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
2816 dev_priv->irq_mask = ~enable_mask;
2818 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
2823 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
2825 struct intel_uncore *uncore = &dev_priv->uncore;
2827 GEN3_IRQ_RESET(uncore, DE);
2828 if (IS_GEN(dev_priv, 7))
2829 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
2831 if (IS_HASWELL(dev_priv)) {
2832 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2833 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2836 gen5_gt_irq_reset(&dev_priv->gt);
2838 ibx_irq_reset(dev_priv);
2841 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
2843 I915_WRITE(VLV_MASTER_IER, 0);
2844 POSTING_READ(VLV_MASTER_IER);
2846 gen5_gt_irq_reset(&dev_priv->gt);
2848 spin_lock_irq(&dev_priv->irq_lock);
2849 if (dev_priv->display_irqs_enabled)
2850 vlv_display_irq_reset(dev_priv);
2851 spin_unlock_irq(&dev_priv->irq_lock);
2854 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
2856 struct intel_uncore *uncore = &dev_priv->uncore;
2859 gen8_master_intr_disable(dev_priv->uncore.regs);
2861 gen8_gt_irq_reset(&dev_priv->gt);
2863 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2864 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2866 for_each_pipe(dev_priv, pipe)
2867 if (intel_display_power_is_enabled(dev_priv,
2868 POWER_DOMAIN_PIPE(pipe)))
2869 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2871 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
2872 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
2873 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2875 if (HAS_PCH_SPLIT(dev_priv))
2876 ibx_irq_reset(dev_priv);
2879 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
2881 struct intel_uncore *uncore = &dev_priv->uncore;
2883 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
2884 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
2886 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
2888 if (INTEL_GEN(dev_priv) >= 12) {
2889 enum transcoder trans;
2891 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
2892 enum intel_display_power_domain domain;
2894 domain = POWER_DOMAIN_TRANSCODER(trans);
2895 if (!intel_display_power_is_enabled(dev_priv, domain))
2898 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
2899 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
2902 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2903 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2906 for_each_pipe(dev_priv, pipe)
2907 if (intel_display_power_is_enabled(dev_priv,
2908 POWER_DOMAIN_PIPE(pipe)))
2909 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2911 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
2912 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
2913 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
2915 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2916 GEN3_IRQ_RESET(uncore, SDE);
2918 /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
2919 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
2920 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
2921 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
2922 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
2923 SBCLK_RUN_REFCLK_DIS, 0);
2927 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
2929 struct intel_uncore *uncore = &dev_priv->uncore;
2931 if (HAS_MASTER_UNIT_IRQ(dev_priv))
2932 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
2934 gen11_master_intr_disable(dev_priv->uncore.regs);
2936 gen11_gt_irq_reset(&dev_priv->gt);
2937 gen11_display_irq_reset(dev_priv);
2939 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
2940 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2943 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
2946 struct intel_uncore *uncore = &dev_priv->uncore;
2948 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
2951 spin_lock_irq(&dev_priv->irq_lock);
2953 if (!intel_irqs_enabled(dev_priv)) {
2954 spin_unlock_irq(&dev_priv->irq_lock);
2958 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
2959 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
2960 dev_priv->de_irq_mask[pipe],
2961 ~dev_priv->de_irq_mask[pipe] | extra_ier);
2963 spin_unlock_irq(&dev_priv->irq_lock);
2966 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
2969 struct intel_uncore *uncore = &dev_priv->uncore;
2972 spin_lock_irq(&dev_priv->irq_lock);
2974 if (!intel_irqs_enabled(dev_priv)) {
2975 spin_unlock_irq(&dev_priv->irq_lock);
2979 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
2980 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2982 spin_unlock_irq(&dev_priv->irq_lock);
2984 /* make sure we're done processing display irqs */
2985 intel_synchronize_irq(dev_priv);
2988 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
2990 struct intel_uncore *uncore = &dev_priv->uncore;
2992 I915_WRITE(GEN8_MASTER_IRQ, 0);
2993 POSTING_READ(GEN8_MASTER_IRQ);
2995 gen8_gt_irq_reset(&dev_priv->gt);
2997 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2999 spin_lock_irq(&dev_priv->irq_lock);
3000 if (dev_priv->display_irqs_enabled)
3001 vlv_display_irq_reset(dev_priv);
3002 spin_unlock_irq(&dev_priv->irq_lock);
3005 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3006 const u32 hpd[HPD_NUM_PINS])
3008 struct intel_encoder *encoder;
3009 u32 enabled_irqs = 0;
3011 for_each_intel_encoder(&dev_priv->drm, encoder)
3012 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3013 enabled_irqs |= hpd[encoder->hpd_pin];
3015 return enabled_irqs;
3018 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
3019 const u32 hpd[HPD_NUM_PINS])
3021 struct intel_encoder *encoder;
3022 u32 hotplug_irqs = 0;
3024 for_each_intel_encoder(&dev_priv->drm, encoder)
3025 hotplug_irqs |= hpd[encoder->hpd_pin];
3027 return hotplug_irqs;
3030 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3035 * Enable digital hotplug on the PCH, and configure the DP short pulse
3036 * duration to 2ms (which is the minimum in the Display Port spec).
3037 * The pulse duration bits are reserved on LPT+.
3039 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3040 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3041 PORTC_PULSE_DURATION_MASK |
3042 PORTD_PULSE_DURATION_MASK);
3043 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3044 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3045 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3047 * When CPU and PCH are on the same package, port A
3048 * HPD must be enabled in both north and south.
3050 if (HAS_PCH_LPT_LP(dev_priv))
3051 hotplug |= PORTA_HOTPLUG_ENABLE;
3052 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3055 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3057 u32 hotplug_irqs, enabled_irqs;
3059 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3060 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3062 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3064 ibx_hpd_detection_setup(dev_priv);
3067 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
3072 hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3073 hotplug |= enable_mask;
3074 I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3077 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
3082 hotplug = I915_READ(SHOTPLUG_CTL_TC);
3083 hotplug |= enable_mask;
3084 I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3087 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
3088 u32 ddi_enable_mask, u32 tc_enable_mask)
3090 u32 hotplug_irqs, enabled_irqs;
3092 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3093 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3095 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
3096 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3098 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3100 icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
3102 icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
3106 * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
3107 * equivalent of SDE.
3109 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
3111 icp_hpd_irq_setup(dev_priv,
3112 ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
3116 * JSP behaves exactly the same as MCC above except that port C is mapped to
3117 * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
3118 * masks & tables rather than ICP's masks & tables.
3120 static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3122 icp_hpd_irq_setup(dev_priv,
3123 TGP_DDI_HPD_ENABLE_MASK, 0);
3126 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
3130 hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3131 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3132 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3133 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3134 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
3135 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
3136 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
3137 I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3139 hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3140 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3141 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3142 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3143 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
3144 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
3145 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
3146 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3149 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3151 u32 hotplug_irqs, enabled_irqs;
3154 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3155 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3157 val = I915_READ(GEN11_DE_HPD_IMR);
3158 val &= ~hotplug_irqs;
3159 val |= ~enabled_irqs & hotplug_irqs;
3160 I915_WRITE(GEN11_DE_HPD_IMR, val);
3161 POSTING_READ(GEN11_DE_HPD_IMR);
3163 gen11_hpd_detection_setup(dev_priv);
3165 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
3166 icp_hpd_irq_setup(dev_priv,
3167 TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
3168 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3169 icp_hpd_irq_setup(dev_priv,
3170 ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
3173 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3177 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3178 if (HAS_PCH_CNP(dev_priv)) {
3179 val = I915_READ(SOUTH_CHICKEN1);
3180 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3181 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3182 I915_WRITE(SOUTH_CHICKEN1, val);
3185 /* Enable digital hotplug on the PCH */
3186 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3187 hotplug |= PORTA_HOTPLUG_ENABLE |
3188 PORTB_HOTPLUG_ENABLE |
3189 PORTC_HOTPLUG_ENABLE |
3190 PORTD_HOTPLUG_ENABLE;
3191 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3193 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3194 hotplug |= PORTE_HOTPLUG_ENABLE;
3195 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3198 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3200 u32 hotplug_irqs, enabled_irqs;
3202 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3203 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3205 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3206 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3208 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3210 spt_hpd_detection_setup(dev_priv);
3213 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3218 * Enable digital hotplug on the CPU, and configure the DP short pulse
3219 * duration to 2ms (which is the minimum in the Display Port spec)
3220 * The pulse duration bits are reserved on HSW+.
3222 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3223 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3224 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3225 DIGITAL_PORTA_PULSE_DURATION_2ms;
3226 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3229 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3231 u32 hotplug_irqs, enabled_irqs;
3233 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3234 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3236 if (INTEL_GEN(dev_priv) >= 8)
3237 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3239 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3241 ilk_hpd_detection_setup(dev_priv);
3243 ibx_hpd_irq_setup(dev_priv);
3246 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3251 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3252 hotplug |= PORTA_HOTPLUG_ENABLE |
3253 PORTB_HOTPLUG_ENABLE |
3254 PORTC_HOTPLUG_ENABLE;
3256 drm_dbg_kms(&dev_priv->drm,
3257 "Invert bit setting: hp_ctl:%x hp_port:%x\n",
3258 hotplug, enabled_irqs);
3259 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3262 * For BXT invert bit has to be set based on AOB design
3263 * for HPD detection logic, update it based on VBT fields.
3265 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3266 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3267 hotplug |= BXT_DDIA_HPD_INVERT;
3268 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3269 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3270 hotplug |= BXT_DDIB_HPD_INVERT;
3271 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3272 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3273 hotplug |= BXT_DDIC_HPD_INVERT;
3275 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3278 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3280 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3283 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3285 u32 hotplug_irqs, enabled_irqs;
3287 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3288 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3290 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3292 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3295 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3299 if (HAS_PCH_NOP(dev_priv))
3302 if (HAS_PCH_IBX(dev_priv))
3303 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3304 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3305 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3307 mask = SDE_GMBUS_CPT;
3309 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3310 I915_WRITE(SDEIMR, ~mask);
3312 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3313 HAS_PCH_LPT(dev_priv))
3314 ibx_hpd_detection_setup(dev_priv);
3316 spt_hpd_detection_setup(dev_priv);
3319 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3321 struct intel_uncore *uncore = &dev_priv->uncore;
3322 u32 display_mask, extra_mask;
3324 if (INTEL_GEN(dev_priv) >= 7) {
3325 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3326 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3327 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3328 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3329 DE_DP_A_HOTPLUG_IVB);
3331 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3332 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3333 DE_PIPEA_CRC_DONE | DE_POISON);
3334 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3335 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3339 if (IS_HASWELL(dev_priv)) {
3340 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3341 display_mask |= DE_EDP_PSR_INT_HSW;
3344 dev_priv->irq_mask = ~display_mask;
3346 ibx_irq_pre_postinstall(dev_priv);
3348 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3349 display_mask | extra_mask);
3351 gen5_gt_irq_postinstall(&dev_priv->gt);
3353 ilk_hpd_detection_setup(dev_priv);
3355 ibx_irq_postinstall(dev_priv);
3357 if (IS_IRONLAKE_M(dev_priv)) {
3358 /* Enable PCU event interrupts
3360 * spinlocking not required here for correctness since interrupt
3361 * setup is guaranteed to run in single-threaded context. But we
3362 * need it to make the assert_spin_locked happy. */
3363 spin_lock_irq(&dev_priv->irq_lock);
3364 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3365 spin_unlock_irq(&dev_priv->irq_lock);
3369 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3371 lockdep_assert_held(&dev_priv->irq_lock);
3373 if (dev_priv->display_irqs_enabled)
3376 dev_priv->display_irqs_enabled = true;
3378 if (intel_irqs_enabled(dev_priv)) {
3379 vlv_display_irq_reset(dev_priv);
3380 vlv_display_irq_postinstall(dev_priv);
3384 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3386 lockdep_assert_held(&dev_priv->irq_lock);
3388 if (!dev_priv->display_irqs_enabled)
3391 dev_priv->display_irqs_enabled = false;
3393 if (intel_irqs_enabled(dev_priv))
3394 vlv_display_irq_reset(dev_priv);
3398 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3400 gen5_gt_irq_postinstall(&dev_priv->gt);
3402 spin_lock_irq(&dev_priv->irq_lock);
3403 if (dev_priv->display_irqs_enabled)
3404 vlv_display_irq_postinstall(dev_priv);
3405 spin_unlock_irq(&dev_priv->irq_lock);
3407 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3408 POSTING_READ(VLV_MASTER_IER);
3411 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3413 struct intel_uncore *uncore = &dev_priv->uncore;
3415 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3416 GEN8_PIPE_CDCLK_CRC_DONE;
3417 u32 de_pipe_enables;
3418 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3419 u32 de_port_enables;
3420 u32 de_misc_masked = GEN8_DE_EDP_PSR;
3421 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3422 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3425 if (INTEL_GEN(dev_priv) <= 10)
3426 de_misc_masked |= GEN8_DE_MISC_GSE;
3428 if (IS_GEN9_LP(dev_priv))
3429 de_port_masked |= BXT_DE_PORT_GMBUS;
3431 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3432 GEN8_PIPE_FIFO_UNDERRUN;
3434 de_port_enables = de_port_masked;
3435 if (IS_GEN9_LP(dev_priv))
3436 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3437 else if (IS_BROADWELL(dev_priv))
3438 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3440 if (INTEL_GEN(dev_priv) >= 12) {
3441 enum transcoder trans;
3443 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3444 enum intel_display_power_domain domain;
3446 domain = POWER_DOMAIN_TRANSCODER(trans);
3447 if (!intel_display_power_is_enabled(dev_priv, domain))
3450 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3453 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3456 for_each_pipe(dev_priv, pipe) {
3457 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3459 if (intel_display_power_is_enabled(dev_priv,
3460 POWER_DOMAIN_PIPE(pipe)))
3461 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3462 dev_priv->de_irq_mask[pipe],
3466 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3467 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3469 if (INTEL_GEN(dev_priv) >= 11) {
3470 u32 de_hpd_masked = 0;
3471 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3472 GEN11_DE_TBT_HOTPLUG_MASK;
3474 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3476 gen11_hpd_detection_setup(dev_priv);
3477 } else if (IS_GEN9_LP(dev_priv)) {
3478 bxt_hpd_detection_setup(dev_priv);
3479 } else if (IS_BROADWELL(dev_priv)) {
3480 ilk_hpd_detection_setup(dev_priv);
3484 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3486 if (HAS_PCH_SPLIT(dev_priv))
3487 ibx_irq_pre_postinstall(dev_priv);
3489 gen8_gt_irq_postinstall(&dev_priv->gt);
3490 gen8_de_irq_postinstall(dev_priv);
3492 if (HAS_PCH_SPLIT(dev_priv))
3493 ibx_irq_postinstall(dev_priv);
3495 gen8_master_intr_enable(dev_priv->uncore.regs);
3498 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3500 u32 mask = SDE_GMBUS_ICP;
3502 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
3503 I915_WRITE(SDEIER, 0xffffffff);
3504 POSTING_READ(SDEIER);
3506 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3507 I915_WRITE(SDEIMR, ~mask);
3509 if (HAS_PCH_TGP(dev_priv)) {
3510 icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
3511 icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
3512 } else if (HAS_PCH_JSP(dev_priv)) {
3513 icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
3514 } else if (HAS_PCH_MCC(dev_priv)) {
3515 icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
3516 icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
3518 icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
3519 icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
3523 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3525 struct intel_uncore *uncore = &dev_priv->uncore;
3526 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3528 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3529 icp_irq_postinstall(dev_priv);
3531 gen11_gt_irq_postinstall(&dev_priv->gt);
3532 gen8_de_irq_postinstall(dev_priv);
3534 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3536 I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
3538 if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
3539 dg1_master_intr_enable(uncore->regs);
3540 POSTING_READ(DG1_MSTR_UNIT_INTR);
3542 gen11_master_intr_enable(uncore->regs);
3543 POSTING_READ(GEN11_GFX_MSTR_IRQ);
3547 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3549 gen8_gt_irq_postinstall(&dev_priv->gt);
3551 spin_lock_irq(&dev_priv->irq_lock);
3552 if (dev_priv->display_irqs_enabled)
3553 vlv_display_irq_postinstall(dev_priv);
3554 spin_unlock_irq(&dev_priv->irq_lock);
3556 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3557 POSTING_READ(GEN8_MASTER_IRQ);
3560 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3562 struct intel_uncore *uncore = &dev_priv->uncore;
3564 i9xx_pipestat_irq_reset(dev_priv);
3566 GEN2_IRQ_RESET(uncore);
3569 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3571 struct intel_uncore *uncore = &dev_priv->uncore;
3574 intel_uncore_write16(uncore,
3576 ~(I915_ERROR_PAGE_TABLE |
3577 I915_ERROR_MEMORY_REFRESH));
3579 /* Unmask the interrupts that we always want on. */
3580 dev_priv->irq_mask =
3581 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3582 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3583 I915_MASTER_ERROR_INTERRUPT);
3586 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3587 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3588 I915_MASTER_ERROR_INTERRUPT |
3589 I915_USER_INTERRUPT;
3591 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3593 /* Interrupt setup is already guaranteed to be single-threaded, this is
3594 * just to make the assert_spin_locked check happy. */
3595 spin_lock_irq(&dev_priv->irq_lock);
3596 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3597 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3598 spin_unlock_irq(&dev_priv->irq_lock);
3601 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3602 u16 *eir, u16 *eir_stuck)
3604 struct intel_uncore *uncore = &i915->uncore;
3607 *eir = intel_uncore_read16(uncore, EIR);
3610 intel_uncore_write16(uncore, EIR, *eir);
3612 *eir_stuck = intel_uncore_read16(uncore, EIR);
3613 if (*eir_stuck == 0)
3617 * Toggle all EMR bits to make sure we get an edge
3618 * in the ISR master error bit if we don't clear
3619 * all the EIR bits. Otherwise the edge triggered
3620 * IIR on i965/g4x wouldn't notice that an interrupt
3621 * is still pending. Also some EIR bits can't be
3622 * cleared except by handling the underlying error
3623 * (or by a GPU reset) so we mask any bit that
3626 emr = intel_uncore_read16(uncore, EMR);
3627 intel_uncore_write16(uncore, EMR, 0xffff);
3628 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3631 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3632 u16 eir, u16 eir_stuck)
3634 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3637 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3641 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3642 u32 *eir, u32 *eir_stuck)
3646 *eir = I915_READ(EIR);
3648 I915_WRITE(EIR, *eir);
3650 *eir_stuck = I915_READ(EIR);
3651 if (*eir_stuck == 0)
3655 * Toggle all EMR bits to make sure we get an edge
3656 * in the ISR master error bit if we don't clear
3657 * all the EIR bits. Otherwise the edge triggered
3658 * IIR on i965/g4x wouldn't notice that an interrupt
3659 * is still pending. Also some EIR bits can't be
3660 * cleared except by handling the underlying error
3661 * (or by a GPU reset) so we mask any bit that
3664 emr = I915_READ(EMR);
3665 I915_WRITE(EMR, 0xffffffff);
3666 I915_WRITE(EMR, emr | *eir_stuck);
3669 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
3670 u32 eir, u32 eir_stuck)
3672 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
3675 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
3679 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3681 struct drm_i915_private *dev_priv = arg;
3682 irqreturn_t ret = IRQ_NONE;
3684 if (!intel_irqs_enabled(dev_priv))
3687 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3688 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3691 u32 pipe_stats[I915_MAX_PIPES] = {};
3692 u16 eir = 0, eir_stuck = 0;
3695 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
3701 /* Call regardless, as some status bits might not be
3702 * signalled in iir */
3703 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3705 if (iir & I915_MASTER_ERROR_INTERRUPT)
3706 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3708 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
3710 if (iir & I915_USER_INTERRUPT)
3711 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3713 if (iir & I915_MASTER_ERROR_INTERRUPT)
3714 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
3716 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3719 pmu_irq_stats(dev_priv, ret);
3721 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3726 static void i915_irq_reset(struct drm_i915_private *dev_priv)
3728 struct intel_uncore *uncore = &dev_priv->uncore;
3730 if (I915_HAS_HOTPLUG(dev_priv)) {
3731 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3732 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3735 i9xx_pipestat_irq_reset(dev_priv);
3737 GEN3_IRQ_RESET(uncore, GEN2_);
3740 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
3742 struct intel_uncore *uncore = &dev_priv->uncore;
3745 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
3746 I915_ERROR_MEMORY_REFRESH));
3748 /* Unmask the interrupts that we always want on. */
3749 dev_priv->irq_mask =
3750 ~(I915_ASLE_INTERRUPT |
3751 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3752 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3753 I915_MASTER_ERROR_INTERRUPT);
3756 I915_ASLE_INTERRUPT |
3757 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3758 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3759 I915_MASTER_ERROR_INTERRUPT |
3760 I915_USER_INTERRUPT;
3762 if (I915_HAS_HOTPLUG(dev_priv)) {
3763 /* Enable in IER... */
3764 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3765 /* and unmask in IMR */
3766 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3769 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3771 /* Interrupt setup is already guaranteed to be single-threaded, this is
3772 * just to make the assert_spin_locked check happy. */
3773 spin_lock_irq(&dev_priv->irq_lock);
3774 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3775 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3776 spin_unlock_irq(&dev_priv->irq_lock);
3778 i915_enable_asle_pipestat(dev_priv);
3781 static irqreturn_t i915_irq_handler(int irq, void *arg)
3783 struct drm_i915_private *dev_priv = arg;
3784 irqreturn_t ret = IRQ_NONE;
3786 if (!intel_irqs_enabled(dev_priv))
3789 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3790 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3793 u32 pipe_stats[I915_MAX_PIPES] = {};
3794 u32 eir = 0, eir_stuck = 0;
3795 u32 hotplug_status = 0;
3798 iir = I915_READ(GEN2_IIR);
3804 if (I915_HAS_HOTPLUG(dev_priv) &&
3805 iir & I915_DISPLAY_PORT_INTERRUPT)
3806 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3808 /* Call regardless, as some status bits might not be
3809 * signalled in iir */
3810 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3812 if (iir & I915_MASTER_ERROR_INTERRUPT)
3813 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3815 I915_WRITE(GEN2_IIR, iir);
3817 if (iir & I915_USER_INTERRUPT)
3818 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3820 if (iir & I915_MASTER_ERROR_INTERRUPT)
3821 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3824 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3826 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3829 pmu_irq_stats(dev_priv, ret);
3831 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3836 static void i965_irq_reset(struct drm_i915_private *dev_priv)
3838 struct intel_uncore *uncore = &dev_priv->uncore;
3840 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3841 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3843 i9xx_pipestat_irq_reset(dev_priv);
3845 GEN3_IRQ_RESET(uncore, GEN2_);
3848 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
3850 struct intel_uncore *uncore = &dev_priv->uncore;
3855 * Enable some error detection, note the instruction error mask
3856 * bit is reserved, so we leave it masked.
3858 if (IS_G4X(dev_priv)) {
3859 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3860 GM45_ERROR_MEM_PRIV |
3861 GM45_ERROR_CP_PRIV |
3862 I915_ERROR_MEMORY_REFRESH);
3864 error_mask = ~(I915_ERROR_PAGE_TABLE |
3865 I915_ERROR_MEMORY_REFRESH);
3867 I915_WRITE(EMR, error_mask);
3869 /* Unmask the interrupts that we always want on. */
3870 dev_priv->irq_mask =
3871 ~(I915_ASLE_INTERRUPT |
3872 I915_DISPLAY_PORT_INTERRUPT |
3873 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3874 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3875 I915_MASTER_ERROR_INTERRUPT);
3878 I915_ASLE_INTERRUPT |
3879 I915_DISPLAY_PORT_INTERRUPT |
3880 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3881 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3882 I915_MASTER_ERROR_INTERRUPT |
3883 I915_USER_INTERRUPT;
3885 if (IS_G4X(dev_priv))
3886 enable_mask |= I915_BSD_USER_INTERRUPT;
3888 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3890 /* Interrupt setup is already guaranteed to be single-threaded, this is
3891 * just to make the assert_spin_locked check happy. */
3892 spin_lock_irq(&dev_priv->irq_lock);
3893 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3894 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3895 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3896 spin_unlock_irq(&dev_priv->irq_lock);
3898 i915_enable_asle_pipestat(dev_priv);
3901 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
3905 lockdep_assert_held(&dev_priv->irq_lock);
3907 /* Note HDMI and DP share hotplug bits */
3908 /* enable bits are the same for all generations */
3909 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
3910 /* Programming the CRT detection parameters tends
3911 to generate a spurious hotplug event about three
3912 seconds later. So just do it once.
3914 if (IS_G4X(dev_priv))
3915 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3916 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3918 /* Ignore TV since it's buggy */
3919 i915_hotplug_interrupt_update_locked(dev_priv,
3920 HOTPLUG_INT_EN_MASK |
3921 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
3922 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
3926 static irqreturn_t i965_irq_handler(int irq, void *arg)
3928 struct drm_i915_private *dev_priv = arg;
3929 irqreturn_t ret = IRQ_NONE;
3931 if (!intel_irqs_enabled(dev_priv))
3934 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3935 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3938 u32 pipe_stats[I915_MAX_PIPES] = {};
3939 u32 eir = 0, eir_stuck = 0;
3940 u32 hotplug_status = 0;
3943 iir = I915_READ(GEN2_IIR);
3949 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3950 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3952 /* Call regardless, as some status bits might not be
3953 * signalled in iir */
3954 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3956 if (iir & I915_MASTER_ERROR_INTERRUPT)
3957 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3959 I915_WRITE(GEN2_IIR, iir);
3961 if (iir & I915_USER_INTERRUPT)
3962 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3964 if (iir & I915_BSD_USER_INTERRUPT)
3965 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
3967 if (iir & I915_MASTER_ERROR_INTERRUPT)
3968 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3971 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3973 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3976 pmu_irq_stats(dev_priv, IRQ_HANDLED);
3978 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3984 * intel_irq_init - initializes irq support
3985 * @dev_priv: i915 device instance
3987 * This function initializes all the irq support including work items, timers
3988 * and all the vtables. It does not setup the interrupt itself though.
3990 void intel_irq_init(struct drm_i915_private *dev_priv)
3992 struct drm_device *dev = &dev_priv->drm;
3995 intel_hpd_init_pins(dev_priv);
3997 intel_hpd_init_work(dev_priv);
3999 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4000 for (i = 0; i < MAX_L3_SLICES; ++i)
4001 dev_priv->l3_parity.remap_info[i] = NULL;
4003 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4004 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
4005 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4007 dev->vblank_disable_immediate = true;
4009 /* Most platforms treat the display irq block as an always-on
4010 * power domain. vlv/chv can disable it at runtime and need
4011 * special care to avoid writing any of the display block registers
4012 * outside of the power domain. We defer setting up the display irqs
4013 * in this case to the runtime pm.
4015 dev_priv->display_irqs_enabled = true;
4016 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4017 dev_priv->display_irqs_enabled = false;
4019 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4020 /* If we have MST support, we want to avoid doing short HPD IRQ storm
4021 * detection, as short HPD storms will occur as a natural part of
4022 * sideband messaging with MST.
4023 * On older platforms however, IRQ storms can occur with both long and
4024 * short pulses, as seen on some G4x systems.
4026 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4028 if (HAS_GMCH(dev_priv)) {
4029 if (I915_HAS_HOTPLUG(dev_priv))
4030 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4032 if (HAS_PCH_JSP(dev_priv))
4033 dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
4034 else if (HAS_PCH_MCC(dev_priv))
4035 dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
4036 else if (INTEL_GEN(dev_priv) >= 11)
4037 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4038 else if (IS_GEN9_LP(dev_priv))
4039 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4040 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4041 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4043 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4048 * intel_irq_fini - deinitializes IRQ support
4049 * @i915: i915 device instance
4051 * This function deinitializes all the IRQ support.
4053 void intel_irq_fini(struct drm_i915_private *i915)
4057 for (i = 0; i < MAX_L3_SLICES; ++i)
4058 kfree(i915->l3_parity.remap_info[i]);
4061 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4063 if (HAS_GMCH(dev_priv)) {
4064 if (IS_CHERRYVIEW(dev_priv))
4065 return cherryview_irq_handler;
4066 else if (IS_VALLEYVIEW(dev_priv))
4067 return valleyview_irq_handler;
4068 else if (IS_GEN(dev_priv, 4))
4069 return i965_irq_handler;
4070 else if (IS_GEN(dev_priv, 3))
4071 return i915_irq_handler;
4073 return i8xx_irq_handler;
4075 if (HAS_MASTER_UNIT_IRQ(dev_priv))
4076 return dg1_irq_handler;
4077 if (INTEL_GEN(dev_priv) >= 11)
4078 return gen11_irq_handler;
4079 else if (INTEL_GEN(dev_priv) >= 8)
4080 return gen8_irq_handler;
4082 return ilk_irq_handler;
4086 static void intel_irq_reset(struct drm_i915_private *dev_priv)
4088 if (HAS_GMCH(dev_priv)) {
4089 if (IS_CHERRYVIEW(dev_priv))
4090 cherryview_irq_reset(dev_priv);
4091 else if (IS_VALLEYVIEW(dev_priv))
4092 valleyview_irq_reset(dev_priv);
4093 else if (IS_GEN(dev_priv, 4))
4094 i965_irq_reset(dev_priv);
4095 else if (IS_GEN(dev_priv, 3))
4096 i915_irq_reset(dev_priv);
4098 i8xx_irq_reset(dev_priv);
4100 if (INTEL_GEN(dev_priv) >= 11)
4101 gen11_irq_reset(dev_priv);
4102 else if (INTEL_GEN(dev_priv) >= 8)
4103 gen8_irq_reset(dev_priv);
4105 ilk_irq_reset(dev_priv);
4109 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4111 if (HAS_GMCH(dev_priv)) {
4112 if (IS_CHERRYVIEW(dev_priv))
4113 cherryview_irq_postinstall(dev_priv);
4114 else if (IS_VALLEYVIEW(dev_priv))
4115 valleyview_irq_postinstall(dev_priv);
4116 else if (IS_GEN(dev_priv, 4))
4117 i965_irq_postinstall(dev_priv);
4118 else if (IS_GEN(dev_priv, 3))
4119 i915_irq_postinstall(dev_priv);
4121 i8xx_irq_postinstall(dev_priv);
4123 if (INTEL_GEN(dev_priv) >= 11)
4124 gen11_irq_postinstall(dev_priv);
4125 else if (INTEL_GEN(dev_priv) >= 8)
4126 gen8_irq_postinstall(dev_priv);
4128 ilk_irq_postinstall(dev_priv);
4133 * intel_irq_install - enables the hardware interrupt
4134 * @dev_priv: i915 device instance
4136 * This function enables the hardware interrupt handling, but leaves the hotplug
4137 * handling still disabled. It is called after intel_irq_init().
4139 * In the driver load and resume code we need working interrupts in a few places
4140 * but don't want to deal with the hassle of concurrent probe and hotplug
4141 * workers. Hence the split into this two-stage approach.
4143 int intel_irq_install(struct drm_i915_private *dev_priv)
4145 int irq = dev_priv->drm.pdev->irq;
4149 * We enable some interrupt sources in our postinstall hooks, so mark
4150 * interrupts as enabled _before_ actually enabling them to avoid
4151 * special cases in our ordering checks.
4153 dev_priv->runtime_pm.irqs_enabled = true;
4155 dev_priv->drm.irq_enabled = true;
4157 intel_irq_reset(dev_priv);
4159 ret = request_irq(irq, intel_irq_handler(dev_priv),
4160 IRQF_SHARED, DRIVER_NAME, dev_priv);
4162 dev_priv->drm.irq_enabled = false;
4166 intel_irq_postinstall(dev_priv);
4172 * intel_irq_uninstall - finilizes all irq handling
4173 * @dev_priv: i915 device instance
4175 * This stops interrupt and hotplug handling and unregisters and frees all
4176 * resources acquired in the init functions.
4178 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4180 int irq = dev_priv->drm.pdev->irq;
4183 * FIXME we can get called twice during driver probe
4184 * error handling as well as during driver remove due to
4185 * intel_modeset_driver_remove() calling us out of sequence.
4186 * Would be nice if it didn't do that...
4188 if (!dev_priv->drm.irq_enabled)
4191 dev_priv->drm.irq_enabled = false;
4193 intel_irq_reset(dev_priv);
4195 free_irq(irq, dev_priv);
4197 intel_hpd_cancel_work(dev_priv);
4198 dev_priv->runtime_pm.irqs_enabled = false;
4202 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4203 * @dev_priv: i915 device instance
4205 * This function is used to disable interrupts at runtime, both in the runtime
4206 * pm and the system suspend/resume code.
4208 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4210 intel_irq_reset(dev_priv);
4211 dev_priv->runtime_pm.irqs_enabled = false;
4212 intel_synchronize_irq(dev_priv);
4216 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4217 * @dev_priv: i915 device instance
4219 * This function is used to enable interrupts at runtime, both in the runtime
4220 * pm and the system suspend/resume code.
4222 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4224 dev_priv->runtime_pm.irqs_enabled = true;
4225 intel_irq_reset(dev_priv);
4226 intel_irq_postinstall(dev_priv);
4229 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4232 * We only use drm_irq_uninstall() at unload and VT switch, so
4233 * this is the only thing we need to check.
4235 return dev_priv->runtime_pm.irqs_enabled;
4238 void intel_synchronize_irq(struct drm_i915_private *i915)
4240 synchronize_irq(i915->drm.pdev->irq);