2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <acpi/video.h>
28 #include <linux/i2c.h>
29 #include <linux/input.h>
30 #include <linux/intel-iommu.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/dma-resv.h>
34 #include <linux/slab.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_damage_helper.h>
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_edid.h>
42 #include <drm/drm_fourcc.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/drm_rect.h>
47 #include "display/intel_audio.h"
48 #include "display/intel_crt.h"
49 #include "display/intel_ddi.h"
50 #include "display/intel_display_debugfs.h"
51 #include "display/intel_dp.h"
52 #include "display/intel_dp_mst.h"
53 #include "display/intel_dpll.h"
54 #include "display/intel_dpll_mgr.h"
55 #include "display/intel_dsi.h"
56 #include "display/intel_dvo.h"
57 #include "display/intel_fb.h"
58 #include "display/intel_gmbus.h"
59 #include "display/intel_hdmi.h"
60 #include "display/intel_lvds.h"
61 #include "display/intel_sdvo.h"
62 #include "display/intel_tv.h"
63 #include "display/intel_vdsc.h"
64 #include "display/intel_vrr.h"
66 #include "gem/i915_gem_lmem.h"
67 #include "gem/i915_gem_object.h"
69 #include "gt/intel_rps.h"
70 #include "gt/gen8_ppgtt.h"
75 #include "intel_acpi.h"
76 #include "intel_atomic.h"
77 #include "intel_atomic_plane.h"
79 #include "intel_cdclk.h"
80 #include "intel_color.h"
81 #include "intel_crtc.h"
83 #include "intel_display_types.h"
84 #include "intel_dmc.h"
85 #include "intel_dp_link_training.h"
86 #include "intel_fbc.h"
87 #include "intel_fdi.h"
88 #include "intel_fbdev.h"
89 #include "intel_fifo_underrun.h"
90 #include "intel_frontbuffer.h"
91 #include "intel_hdcp.h"
92 #include "intel_hotplug.h"
93 #include "intel_overlay.h"
94 #include "intel_pipe_crc.h"
96 #include "intel_pps.h"
97 #include "intel_psr.h"
98 #include "intel_quirks.h"
99 #include "intel_sideband.h"
100 #include "intel_sprite.h"
101 #include "intel_tc.h"
102 #include "intel_vga.h"
103 #include "i9xx_plane.h"
104 #include "skl_scaler.h"
105 #include "skl_universal_plane.h"
107 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
108 struct intel_crtc_state *pipe_config);
109 static void ilk_pch_clock_get(struct intel_crtc *crtc,
110 struct intel_crtc_state *pipe_config);
112 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
113 struct drm_i915_gem_object *obj,
114 struct drm_mode_fb_cmd2 *mode_cmd);
115 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
116 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
117 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
118 const struct intel_link_m_n *m_n,
119 const struct intel_link_m_n *m2_n2);
120 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
121 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
122 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
123 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
124 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
125 static void intel_modeset_setup_hw_state(struct drm_device *dev,
126 struct drm_modeset_acquire_ctx *ctx);
129 struct i915_address_space vm;
131 struct drm_i915_gem_object *obj;
132 struct i915_vma *vma;
136 #define i915_is_dpt(vm) ((vm)->is_dpt)
138 static inline struct i915_dpt *
139 i915_vm_to_dpt(struct i915_address_space *vm)
141 BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
142 GEM_BUG_ON(!i915_is_dpt(vm));
143 return container_of(vm, struct i915_dpt, vm);
146 #define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
148 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
153 static void dpt_insert_page(struct i915_address_space *vm,
156 enum i915_cache_level level,
159 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
160 gen8_pte_t __iomem *base = dpt->iomem;
162 gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
163 vm->pte_encode(addr, level, flags));
166 static void dpt_insert_entries(struct i915_address_space *vm,
167 struct i915_vma *vma,
168 enum i915_cache_level level,
171 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
172 gen8_pte_t __iomem *base = dpt->iomem;
173 const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
174 struct sgt_iter sgt_iter;
179 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
180 * not to allow the user to override access to a read only page.
183 i = vma->node.start / I915_GTT_PAGE_SIZE;
184 for_each_sgt_daddr(addr, sgt_iter, vma->pages)
185 gen8_set_pte(&base[i++], pte_encode | addr);
188 static void dpt_clear_range(struct i915_address_space *vm,
189 u64 start, u64 length)
193 static void dpt_bind_vma(struct i915_address_space *vm,
194 struct i915_vm_pt_stash *stash,
195 struct i915_vma *vma,
196 enum i915_cache_level cache_level,
199 struct drm_i915_gem_object *obj = vma->obj;
202 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
204 if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
205 pte_flags |= PTE_READ_ONLY;
206 if (i915_gem_object_is_lmem(obj))
209 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
211 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
214 * Without aliasing PPGTT there's no difference between
215 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
216 * upgrade to both bound if we bind either to avoid double-binding.
218 atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
221 static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
223 vm->clear_range(vm, vma->node.start, vma->size);
226 static void dpt_cleanup(struct i915_address_space *vm)
228 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
230 i915_gem_object_put(dpt->obj);
233 static struct i915_address_space *
234 intel_dpt_create(struct intel_framebuffer *fb)
236 struct drm_gem_object *obj = &intel_fb_obj(&fb->base)->base;
237 struct drm_i915_private *i915 = to_i915(obj->dev);
238 struct drm_i915_gem_object *dpt_obj;
239 struct i915_address_space *vm;
240 struct i915_dpt *dpt;
244 if (intel_fb_needs_pot_stride_remap(fb))
245 size = intel_remapped_info_size(&fb->remapped_view.gtt.remapped);
247 size = DIV_ROUND_UP_ULL(obj->size, I915_GTT_PAGE_SIZE);
249 size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE);
252 dpt_obj = i915_gem_object_create_lmem(i915, size, 0);
254 dpt_obj = i915_gem_object_create_stolen(i915, size);
256 return ERR_CAST(dpt_obj);
258 ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
260 i915_gem_object_put(dpt_obj);
264 dpt = kzalloc(sizeof(*dpt), GFP_KERNEL);
266 i915_gem_object_put(dpt_obj);
267 return ERR_PTR(-ENOMEM);
274 vm->dma = i915->drm.dev;
275 vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
278 i915_address_space_init(vm, VM_CLASS_DPT);
280 vm->insert_page = dpt_insert_page;
281 vm->clear_range = dpt_clear_range;
282 vm->insert_entries = dpt_insert_entries;
283 vm->cleanup = dpt_cleanup;
285 vm->vma_ops.bind_vma = dpt_bind_vma;
286 vm->vma_ops.unbind_vma = dpt_unbind_vma;
287 vm->vma_ops.set_pages = ggtt_set_pages;
288 vm->vma_ops.clear_pages = clear_pages;
290 vm->pte_encode = gen8_ggtt_pte_encode;
297 static void intel_dpt_destroy(struct i915_address_space *vm)
299 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
301 i915_vm_close(&dpt->vm);
304 /* returns HPLL frequency in kHz */
305 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
307 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
309 /* Obtain SKU information */
310 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
311 CCK_FUSE_HPLL_FREQ_MASK;
313 return vco_freq[hpll_freq] * 1000;
316 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
317 const char *name, u32 reg, int ref_freq)
322 val = vlv_cck_read(dev_priv, reg);
323 divider = val & CCK_FREQUENCY_VALUES;
325 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
326 (divider << CCK_FREQUENCY_STATUS_SHIFT),
327 "%s change in progress\n", name);
329 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
332 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
333 const char *name, u32 reg)
337 vlv_cck_get(dev_priv);
339 if (dev_priv->hpll_freq == 0)
340 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
342 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
344 vlv_cck_put(dev_priv);
349 static void intel_update_czclk(struct drm_i915_private *dev_priv)
351 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
354 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
355 CCK_CZ_CLOCK_CONTROL);
357 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
358 dev_priv->czclk_freq);
361 /* WA Display #0827: Gen9:all */
363 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
366 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
367 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
369 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
370 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
373 /* Wa_2006604312:icl,ehl */
375 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
379 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
380 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
382 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
383 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
387 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
389 return crtc_state->master_transcoder != INVALID_TRANSCODER;
393 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
395 return crtc_state->sync_mode_slaves_mask != 0;
399 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
401 return is_trans_port_sync_master(crtc_state) ||
402 is_trans_port_sync_slave(crtc_state);
405 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
408 i915_reg_t reg = PIPEDSL(pipe);
412 if (DISPLAY_VER(dev_priv) == 2)
413 line_mask = DSL_LINEMASK_GEN2;
415 line_mask = DSL_LINEMASK_GEN3;
417 line1 = intel_de_read(dev_priv, reg) & line_mask;
419 line2 = intel_de_read(dev_priv, reg) & line_mask;
421 return line1 != line2;
424 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
426 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
427 enum pipe pipe = crtc->pipe;
429 /* Wait for the display line to settle/start moving */
430 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
431 drm_err(&dev_priv->drm,
432 "pipe %c scanline %s wait timed out\n",
433 pipe_name(pipe), onoff(state));
436 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
438 wait_for_pipe_scanline_moving(crtc, false);
441 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
443 wait_for_pipe_scanline_moving(crtc, true);
447 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
449 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
450 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
452 if (DISPLAY_VER(dev_priv) >= 4) {
453 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
454 i915_reg_t reg = PIPECONF(cpu_transcoder);
456 /* Wait for the Pipe State to go off */
457 if (intel_de_wait_for_clear(dev_priv, reg,
458 I965_PIPECONF_ACTIVE, 100))
459 drm_WARN(&dev_priv->drm, 1,
460 "pipe_off wait timed out\n");
462 intel_wait_for_pipe_scanline_stopped(crtc);
466 /* Only for pre-ILK configs */
467 void assert_pll(struct drm_i915_private *dev_priv,
468 enum pipe pipe, bool state)
473 val = intel_de_read(dev_priv, DPLL(pipe));
474 cur_state = !!(val & DPLL_VCO_ENABLE);
475 I915_STATE_WARN(cur_state != state,
476 "PLL state assertion failure (expected %s, current %s)\n",
477 onoff(state), onoff(cur_state));
480 /* XXX: the dsi pll is shared between MIPI DSI ports */
481 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
486 vlv_cck_get(dev_priv);
487 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
488 vlv_cck_put(dev_priv);
490 cur_state = val & DSI_PLL_VCO_EN;
491 I915_STATE_WARN(cur_state != state,
492 "DSI PLL state assertion failure (expected %s, current %s)\n",
493 onoff(state), onoff(cur_state));
496 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
497 enum pipe pipe, bool state)
501 if (HAS_DDI(dev_priv)) {
503 * DDI does not have a specific FDI_TX register.
505 * FDI is never fed from EDP transcoder
506 * so pipe->transcoder cast is fine here.
508 enum transcoder cpu_transcoder = (enum transcoder)pipe;
509 u32 val = intel_de_read(dev_priv,
510 TRANS_DDI_FUNC_CTL(cpu_transcoder));
511 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
513 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
514 cur_state = !!(val & FDI_TX_ENABLE);
516 I915_STATE_WARN(cur_state != state,
517 "FDI TX state assertion failure (expected %s, current %s)\n",
518 onoff(state), onoff(cur_state));
520 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
521 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
523 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
524 enum pipe pipe, bool state)
529 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
530 cur_state = !!(val & FDI_RX_ENABLE);
531 I915_STATE_WARN(cur_state != state,
532 "FDI RX state assertion failure (expected %s, current %s)\n",
533 onoff(state), onoff(cur_state));
535 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
536 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
538 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
543 /* ILK FDI PLL is always enabled */
544 if (IS_IRONLAKE(dev_priv))
547 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
548 if (HAS_DDI(dev_priv))
551 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
552 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
555 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
556 enum pipe pipe, bool state)
561 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
562 cur_state = !!(val & FDI_RX_PLL_ENABLE);
563 I915_STATE_WARN(cur_state != state,
564 "FDI RX PLL assertion failure (expected %s, current %s)\n",
565 onoff(state), onoff(cur_state));
568 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
572 enum pipe panel_pipe = INVALID_PIPE;
575 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
578 if (HAS_PCH_SPLIT(dev_priv)) {
581 pp_reg = PP_CONTROL(0);
582 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
585 case PANEL_PORT_SELECT_LVDS:
586 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
588 case PANEL_PORT_SELECT_DPA:
589 g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
591 case PANEL_PORT_SELECT_DPC:
592 g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
594 case PANEL_PORT_SELECT_DPD:
595 g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
598 MISSING_CASE(port_sel);
601 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
602 /* presumably write lock depends on pipe, not port select */
603 pp_reg = PP_CONTROL(pipe);
608 pp_reg = PP_CONTROL(0);
609 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
611 drm_WARN_ON(&dev_priv->drm,
612 port_sel != PANEL_PORT_SELECT_LVDS);
613 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
616 val = intel_de_read(dev_priv, pp_reg);
617 if (!(val & PANEL_POWER_ON) ||
618 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
621 I915_STATE_WARN(panel_pipe == pipe && locked,
622 "panel assertion failure, pipe %c regs locked\n",
626 void assert_pipe(struct drm_i915_private *dev_priv,
627 enum transcoder cpu_transcoder, bool state)
630 enum intel_display_power_domain power_domain;
631 intel_wakeref_t wakeref;
633 /* we keep both pipes enabled on 830 */
634 if (IS_I830(dev_priv))
637 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
638 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
640 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
641 cur_state = !!(val & PIPECONF_ENABLE);
643 intel_display_power_put(dev_priv, power_domain, wakeref);
648 I915_STATE_WARN(cur_state != state,
649 "transcoder %s assertion failure (expected %s, current %s)\n",
650 transcoder_name(cpu_transcoder),
651 onoff(state), onoff(cur_state));
654 static void assert_plane(struct intel_plane *plane, bool state)
659 cur_state = plane->get_hw_state(plane, &pipe);
661 I915_STATE_WARN(cur_state != state,
662 "%s assertion failure (expected %s, current %s)\n",
663 plane->base.name, onoff(state), onoff(cur_state));
666 #define assert_plane_enabled(p) assert_plane(p, true)
667 #define assert_plane_disabled(p) assert_plane(p, false)
669 static void assert_planes_disabled(struct intel_crtc *crtc)
671 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
672 struct intel_plane *plane;
674 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
675 assert_plane_disabled(plane);
678 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
684 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
685 enabled = !!(val & TRANS_ENABLE);
686 I915_STATE_WARN(enabled,
687 "transcoder assertion failed, should be off on pipe %c but is still active\n",
691 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
692 enum pipe pipe, enum port port,
698 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
700 I915_STATE_WARN(state && port_pipe == pipe,
701 "PCH DP %c enabled on transcoder %c, should be disabled\n",
702 port_name(port), pipe_name(pipe));
704 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
705 "IBX PCH DP %c still using transcoder B\n",
709 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
710 enum pipe pipe, enum port port,
716 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
718 I915_STATE_WARN(state && port_pipe == pipe,
719 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
720 port_name(port), pipe_name(pipe));
722 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
723 "IBX PCH HDMI %c still using transcoder B\n",
727 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
732 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
733 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
734 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
736 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
738 "PCH VGA enabled on transcoder %c, should be disabled\n",
741 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
743 "PCH LVDS enabled on transcoder %c, should be disabled\n",
746 /* PCH SDVOB multiplex with HDMIB */
747 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
748 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
749 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
752 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
753 struct intel_digital_port *dig_port,
754 unsigned int expected_mask)
759 switch (dig_port->base.port) {
761 port_mask = DPLL_PORTB_READY_MASK;
765 port_mask = DPLL_PORTC_READY_MASK;
770 port_mask = DPLL_PORTD_READY_MASK;
771 dpll_reg = DPIO_PHY_STATUS;
777 if (intel_de_wait_for_register(dev_priv, dpll_reg,
778 port_mask, expected_mask, 1000))
779 drm_WARN(&dev_priv->drm, 1,
780 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
781 dig_port->base.base.base.id, dig_port->base.base.name,
782 intel_de_read(dev_priv, dpll_reg) & port_mask,
786 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
788 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
789 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
790 enum pipe pipe = crtc->pipe;
792 u32 val, pipeconf_val;
794 /* Make sure PCH DPLL is enabled */
795 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
797 /* FDI must be feeding us bits for PCH ports */
798 assert_fdi_tx_enabled(dev_priv, pipe);
799 assert_fdi_rx_enabled(dev_priv, pipe);
801 if (HAS_PCH_CPT(dev_priv)) {
802 reg = TRANS_CHICKEN2(pipe);
803 val = intel_de_read(dev_priv, reg);
805 * Workaround: Set the timing override bit
806 * before enabling the pch transcoder.
808 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
809 /* Configure frame start delay to match the CPU */
810 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
811 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
812 intel_de_write(dev_priv, reg, val);
815 reg = PCH_TRANSCONF(pipe);
816 val = intel_de_read(dev_priv, reg);
817 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
819 if (HAS_PCH_IBX(dev_priv)) {
820 /* Configure frame start delay to match the CPU */
821 val &= ~TRANS_FRAME_START_DELAY_MASK;
822 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
825 * Make the BPC in transcoder be consistent with
826 * that in pipeconf reg. For HDMI we must use 8bpc
827 * here for both 8bpc and 12bpc.
829 val &= ~PIPECONF_BPC_MASK;
830 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
831 val |= PIPECONF_8BPC;
833 val |= pipeconf_val & PIPECONF_BPC_MASK;
836 val &= ~TRANS_INTERLACE_MASK;
837 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
838 if (HAS_PCH_IBX(dev_priv) &&
839 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
840 val |= TRANS_LEGACY_INTERLACED_ILK;
842 val |= TRANS_INTERLACED;
844 val |= TRANS_PROGRESSIVE;
847 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
848 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
849 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
853 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
854 enum transcoder cpu_transcoder)
856 u32 val, pipeconf_val;
858 /* FDI must be feeding us bits for PCH ports */
859 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
860 assert_fdi_rx_enabled(dev_priv, PIPE_A);
862 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
863 /* Workaround: set timing override bit. */
864 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
865 /* Configure frame start delay to match the CPU */
866 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
867 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
868 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
871 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
873 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
874 PIPECONF_INTERLACED_ILK)
875 val |= TRANS_INTERLACED;
877 val |= TRANS_PROGRESSIVE;
879 intel_de_write(dev_priv, LPT_TRANSCONF, val);
880 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
881 TRANS_STATE_ENABLE, 100))
882 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
885 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
891 /* FDI relies on the transcoder */
892 assert_fdi_tx_disabled(dev_priv, pipe);
893 assert_fdi_rx_disabled(dev_priv, pipe);
895 /* Ports must be off as well */
896 assert_pch_ports_disabled(dev_priv, pipe);
898 reg = PCH_TRANSCONF(pipe);
899 val = intel_de_read(dev_priv, reg);
900 val &= ~TRANS_ENABLE;
901 intel_de_write(dev_priv, reg, val);
902 /* wait for PCH transcoder off, transcoder state */
903 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
904 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
907 if (HAS_PCH_CPT(dev_priv)) {
908 /* Workaround: Clear the timing override chicken bit again. */
909 reg = TRANS_CHICKEN2(pipe);
910 val = intel_de_read(dev_priv, reg);
911 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
912 intel_de_write(dev_priv, reg, val);
916 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
920 val = intel_de_read(dev_priv, LPT_TRANSCONF);
921 val &= ~TRANS_ENABLE;
922 intel_de_write(dev_priv, LPT_TRANSCONF, val);
923 /* wait for PCH transcoder off, transcoder state */
924 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
925 TRANS_STATE_ENABLE, 50))
926 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
928 /* Workaround: clear timing override bit. */
929 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
930 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
931 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
934 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
936 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
938 if (HAS_PCH_LPT(dev_priv))
944 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
946 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
947 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
948 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
949 enum pipe pipe = crtc->pipe;
953 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
955 assert_planes_disabled(crtc);
958 * A pipe without a PLL won't actually be able to drive bits from
959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
962 if (HAS_GMCH(dev_priv)) {
963 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
964 assert_dsi_pll_enabled(dev_priv);
966 assert_pll_enabled(dev_priv, pipe);
968 if (new_crtc_state->has_pch_encoder) {
969 /* if driving the PCH, we need FDI enabled */
970 assert_fdi_rx_pll_enabled(dev_priv,
971 intel_crtc_pch_transcoder(crtc));
972 assert_fdi_tx_pll_enabled(dev_priv,
973 (enum pipe) cpu_transcoder);
975 /* FIXME: assert CPU port conditions for SNB+ */
978 /* Wa_22012358565:adlp */
979 if (DISPLAY_VER(dev_priv) == 13)
980 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
981 0, PIPE_ARB_USE_PROG_SLOTS);
983 reg = PIPECONF(cpu_transcoder);
984 val = intel_de_read(dev_priv, reg);
985 if (val & PIPECONF_ENABLE) {
986 /* we keep both pipes enabled on 830 */
987 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
991 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
992 intel_de_posting_read(dev_priv, reg);
995 * Until the pipe starts PIPEDSL reads will return a stale value,
996 * which causes an apparent vblank timestamp jump when PIPEDSL
997 * resets to its proper value. That also messes up the frame count
998 * when it's derived from the timestamps. So let's wait for the
999 * pipe to start properly before we call drm_crtc_vblank_on()
1001 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1002 intel_wait_for_pipe_scanline_moving(crtc);
1005 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1007 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1008 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1009 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1010 enum pipe pipe = crtc->pipe;
1014 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1017 * Make sure planes won't keep trying to pump pixels to us,
1018 * or we might hang the display.
1020 assert_planes_disabled(crtc);
1022 reg = PIPECONF(cpu_transcoder);
1023 val = intel_de_read(dev_priv, reg);
1024 if ((val & PIPECONF_ENABLE) == 0)
1028 * Double wide has implications for planes
1029 * so best keep it disabled when not needed.
1031 if (old_crtc_state->double_wide)
1032 val &= ~PIPECONF_DOUBLE_WIDE;
1034 /* Don't disable pipe or pipe PLLs if needed */
1035 if (!IS_I830(dev_priv))
1036 val &= ~PIPECONF_ENABLE;
1038 intel_de_write(dev_priv, reg, val);
1039 if ((val & PIPECONF_ENABLE) == 0)
1040 intel_wait_for_pipe_off(old_crtc_state);
1044 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
1047 return info->is_yuv &&
1048 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
1052 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1054 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1055 unsigned int cpp = fb->format->cpp[color_plane];
1057 switch (fb->modifier) {
1058 case DRM_FORMAT_MOD_LINEAR:
1059 return intel_tile_size(dev_priv);
1060 case I915_FORMAT_MOD_X_TILED:
1061 if (DISPLAY_VER(dev_priv) == 2)
1065 case I915_FORMAT_MOD_Y_TILED_CCS:
1066 if (is_ccs_plane(fb, color_plane))
1069 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1070 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1071 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1072 if (is_ccs_plane(fb, color_plane))
1075 case I915_FORMAT_MOD_Y_TILED:
1076 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
1080 case I915_FORMAT_MOD_Yf_TILED_CCS:
1081 if (is_ccs_plane(fb, color_plane))
1084 case I915_FORMAT_MOD_Yf_TILED:
1100 MISSING_CASE(fb->modifier);
1106 intel_fb_align_height(const struct drm_framebuffer *fb,
1107 int color_plane, unsigned int height)
1109 unsigned int tile_height = intel_tile_height(fb, color_plane);
1111 return ALIGN(height, tile_height);
1114 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1116 unsigned int size = 0;
1119 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1120 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
1125 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
1127 unsigned int size = 0;
1130 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
1131 size += rem_info->plane[i].dst_stride * rem_info->plane[i].height;
1136 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
1138 if (DISPLAY_VER(dev_priv) >= 9)
1140 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
1141 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1143 else if (DISPLAY_VER(dev_priv) >= 4)
1149 static bool has_async_flips(struct drm_i915_private *i915)
1151 return DISPLAY_VER(i915) >= 5;
1154 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
1157 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1159 if (intel_fb_uses_dpt(fb))
1162 /* AUX_DIST needs only 4K alignment */
1163 if (is_ccs_plane(fb, color_plane))
1166 if (is_semiplanar_uv_plane(fb, color_plane)) {
1168 * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
1169 * alignment for linear UV planes on all platforms.
1171 if (DISPLAY_VER(dev_priv) >= 12) {
1172 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1173 return intel_linear_alignment(dev_priv);
1175 return intel_tile_row_size(fb, color_plane);
1181 drm_WARN_ON(&dev_priv->drm, color_plane != 0);
1183 switch (fb->modifier) {
1184 case DRM_FORMAT_MOD_LINEAR:
1185 return intel_linear_alignment(dev_priv);
1186 case I915_FORMAT_MOD_X_TILED:
1187 if (has_async_flips(dev_priv))
1190 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1191 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1192 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1194 case I915_FORMAT_MOD_Y_TILED_CCS:
1195 case I915_FORMAT_MOD_Yf_TILED_CCS:
1196 case I915_FORMAT_MOD_Y_TILED:
1197 case I915_FORMAT_MOD_Yf_TILED:
1198 return 1 * 1024 * 1024;
1200 MISSING_CASE(fb->modifier);
1205 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
1207 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1208 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1210 return DISPLAY_VER(dev_priv) < 4 ||
1212 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
1215 static struct i915_vma *
1216 intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
1217 const struct i915_ggtt_view *view,
1219 unsigned long *out_flags,
1220 struct i915_address_space *vm)
1222 struct drm_device *dev = fb->dev;
1223 struct drm_i915_private *dev_priv = to_i915(dev);
1224 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1225 struct i915_vma *vma;
1229 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
1230 return ERR_PTR(-EINVAL);
1232 alignment = 4096 * 512;
1234 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1236 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1242 vma = i915_vma_instance(obj, vm, view);
1246 if (i915_vma_misplaced(vma, 0, alignment, 0)) {
1247 ret = i915_vma_unbind(vma);
1254 ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
1260 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
1262 i915_gem_object_flush_if_display(obj);
1266 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1272 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1274 const struct i915_ggtt_view *view,
1276 unsigned long *out_flags)
1278 struct drm_device *dev = fb->dev;
1279 struct drm_i915_private *dev_priv = to_i915(dev);
1280 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1281 intel_wakeref_t wakeref;
1282 struct i915_gem_ww_ctx ww;
1283 struct i915_vma *vma;
1284 unsigned int pinctl;
1288 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
1289 return ERR_PTR(-EINVAL);
1292 alignment = intel_cursor_alignment(dev_priv);
1294 alignment = intel_surf_alignment(fb, 0);
1295 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
1296 return ERR_PTR(-EINVAL);
1298 /* Note that the w/a also requires 64 PTE of padding following the
1299 * bo. We currently fill all unused PTE with the shadow page and so
1300 * we should always have valid PTE following the scanout preventing
1303 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
1304 alignment = 256 * 1024;
1307 * Global gtt pte registers are special registers which actually forward
1308 * writes to a chunk of system memory. Which means that there is no risk
1309 * that the register values disappear as soon as we call
1310 * intel_runtime_pm_put(), so it is correct to wrap only the
1311 * pin/unpin/fence and not more.
1313 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1315 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1318 * Valleyview is definitely limited to scanning out the first
1319 * 512MiB. Lets presume this behaviour was inherited from the
1320 * g4x display engine and that all earlier gen are similarly
1321 * limited. Testing suggests that it is a little more
1322 * complicated than this. For example, Cherryview appears quite
1323 * happy to scanout from anywhere within its global aperture.
1326 if (HAS_GMCH(dev_priv))
1327 pinctl |= PIN_MAPPABLE;
1329 i915_gem_ww_ctx_init(&ww, true);
1331 ret = i915_gem_object_lock(obj, &ww);
1332 if (!ret && phys_cursor)
1333 ret = i915_gem_object_attach_phys(obj, alignment);
1335 ret = i915_gem_object_pin_pages(obj);
1340 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
1348 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
1350 * Install a fence for tiled scan-out. Pre-i965 always needs a
1351 * fence, whereas 965+ only requires a fence if using
1352 * framebuffer compression. For simplicity, we always, when
1353 * possible, install a fence as the cost is not that onerous.
1355 * If we fail to fence the tiled scanout, then either the
1356 * modeset will reject the change (which is highly unlikely as
1357 * the affected systems, all but one, do not have unmappable
1358 * space) or we will not be able to enable full powersaving
1359 * techniques (also likely not to apply due to various limits
1360 * FBC and the like impose on the size of the buffer, which
1361 * presumably we violated anyway with this unmappable buffer).
1362 * Anyway, it is presumably better to stumble onwards with
1363 * something and try to run the system in a "less than optimal"
1364 * mode that matches the user configuration.
1366 ret = i915_vma_pin_fence(vma);
1367 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
1368 i915_vma_unpin(vma);
1374 *out_flags |= PLANE_HAS_FENCE;
1380 i915_gem_object_unpin_pages(obj);
1382 if (ret == -EDEADLK) {
1383 ret = i915_gem_ww_ctx_backoff(&ww);
1387 i915_gem_ww_ctx_fini(&ww);
1391 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1392 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1396 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
1398 if (flags & PLANE_HAS_FENCE)
1399 i915_vma_unpin_fence(vma);
1400 i915_vma_unpin(vma);
1405 * Convert the x/y offsets into a linear offset.
1406 * Only valid with 0/180 degree rotation, which is fine since linear
1407 * offset is only used with linear buffers on pre-hsw and tiled buffers
1408 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
1410 u32 intel_fb_xy_to_linear(int x, int y,
1411 const struct intel_plane_state *state,
1414 const struct drm_framebuffer *fb = state->hw.fb;
1415 unsigned int cpp = fb->format->cpp[color_plane];
1416 unsigned int pitch = state->view.color_plane[color_plane].stride;
1418 return y * pitch + x * cpp;
1422 * Add the x/y offsets derived from fb->offsets[] to the user
1423 * specified plane src x/y offsets. The resulting x/y offsets
1424 * specify the start of scanout from the beginning of the gtt mapping.
1426 void intel_add_fb_offsets(int *x, int *y,
1427 const struct intel_plane_state *state,
1431 *x += state->view.color_plane[color_plane].x;
1432 *y += state->view.color_plane[color_plane].y;
1435 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
1437 switch (fb_modifier) {
1438 case I915_FORMAT_MOD_X_TILED:
1439 return I915_TILING_X;
1440 case I915_FORMAT_MOD_Y_TILED:
1441 case I915_FORMAT_MOD_Y_TILED_CCS:
1442 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1443 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1444 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1445 return I915_TILING_Y;
1447 return I915_TILING_NONE;
1452 * From the Sky Lake PRM:
1453 * "The Color Control Surface (CCS) contains the compression status of
1454 * the cache-line pairs. The compression state of the cache-line pair
1455 * is specified by 2 bits in the CCS. Each CCS cache-line represents
1456 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
1457 * cache-line-pairs. CCS is always Y tiled."
1459 * Since cache line pairs refers to horizontally adjacent cache lines,
1460 * each cache line in the CCS corresponds to an area of 32x16 cache
1461 * lines on the main surface. Since each pixel is 4 bytes, this gives
1462 * us a ratio of one byte in the CCS for each 8x16 pixels in the
1465 static const struct drm_format_info skl_ccs_formats[] = {
1466 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1467 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1468 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1469 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1470 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1471 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1472 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1473 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1477 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
1478 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
1479 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
1480 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
1483 static const struct drm_format_info gen12_ccs_formats[] = {
1484 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1485 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1486 .hsub = 1, .vsub = 1, },
1487 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1488 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1489 .hsub = 1, .vsub = 1, },
1490 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1491 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1492 .hsub = 1, .vsub = 1, .has_alpha = true },
1493 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1494 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1495 .hsub = 1, .vsub = 1, .has_alpha = true },
1496 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
1497 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1498 .hsub = 2, .vsub = 1, .is_yuv = true },
1499 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
1500 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1501 .hsub = 2, .vsub = 1, .is_yuv = true },
1502 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
1503 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1504 .hsub = 2, .vsub = 1, .is_yuv = true },
1505 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
1506 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1507 .hsub = 2, .vsub = 1, .is_yuv = true },
1508 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
1509 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1510 .hsub = 1, .vsub = 1, .is_yuv = true },
1511 { .format = DRM_FORMAT_NV12, .num_planes = 4,
1512 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
1513 .hsub = 2, .vsub = 2, .is_yuv = true },
1514 { .format = DRM_FORMAT_P010, .num_planes = 4,
1515 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1516 .hsub = 2, .vsub = 2, .is_yuv = true },
1517 { .format = DRM_FORMAT_P012, .num_planes = 4,
1518 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1519 .hsub = 2, .vsub = 2, .is_yuv = true },
1520 { .format = DRM_FORMAT_P016, .num_planes = 4,
1521 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1522 .hsub = 2, .vsub = 2, .is_yuv = true },
1526 * Same as gen12_ccs_formats[] above, but with additional surface used
1527 * to pass Clear Color information in plane 2 with 64 bits of data.
1529 static const struct drm_format_info gen12_ccs_cc_formats[] = {
1530 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
1531 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1532 .hsub = 1, .vsub = 1, },
1533 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
1534 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1535 .hsub = 1, .vsub = 1, },
1536 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
1537 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1538 .hsub = 1, .vsub = 1, .has_alpha = true },
1539 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
1540 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1541 .hsub = 1, .vsub = 1, .has_alpha = true },
1544 static const struct drm_format_info *
1545 lookup_format_info(const struct drm_format_info formats[],
1546 int num_formats, u32 format)
1550 for (i = 0; i < num_formats; i++) {
1551 if (formats[i].format == format)
1558 static const struct drm_format_info *
1559 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
1561 switch (cmd->modifier[0]) {
1562 case I915_FORMAT_MOD_Y_TILED_CCS:
1563 case I915_FORMAT_MOD_Yf_TILED_CCS:
1564 return lookup_format_info(skl_ccs_formats,
1565 ARRAY_SIZE(skl_ccs_formats),
1567 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1568 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1569 return lookup_format_info(gen12_ccs_formats,
1570 ARRAY_SIZE(gen12_ccs_formats),
1572 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1573 return lookup_format_info(gen12_ccs_cc_formats,
1574 ARRAY_SIZE(gen12_ccs_cc_formats),
1581 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
1583 return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
1587 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
1588 u32 pixel_format, u64 modifier)
1590 struct intel_crtc *crtc;
1591 struct intel_plane *plane;
1593 if (!HAS_DISPLAY(dev_priv))
1597 * We assume the primary plane for pipe A has
1598 * the highest stride limits of them all,
1599 * if in case pipe A is disabled, use the first pipe from pipe_mask.
1601 crtc = intel_get_first_crtc(dev_priv);
1605 plane = to_intel_plane(crtc->base.primary);
1607 return plane->max_stride(plane, pixel_format, modifier,
1612 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1613 u32 pixel_format, u64 modifier)
1616 * Arbitrary limit for gen4+ chosen to match the
1617 * render engine max stride.
1619 * The new CCS hash mode makes remapping impossible
1621 if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
1622 intel_modifier_uses_dpt(dev_priv, modifier))
1623 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1624 else if (DISPLAY_VER(dev_priv) >= 7)
1631 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1633 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1636 if (is_surface_linear(fb, color_plane)) {
1637 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
1642 * To make remapping with linear generally feasible
1643 * we need the stride to be page aligned.
1645 if (fb->pitches[color_plane] > max_stride &&
1646 !is_ccs_modifier(fb->modifier))
1647 return intel_tile_size(dev_priv);
1652 tile_width = intel_tile_width_bytes(fb, color_plane);
1653 if (is_ccs_modifier(fb->modifier)) {
1655 * Display WA #0531: skl,bxt,kbl,glk
1657 * Render decompression and plane width > 3840
1658 * combined with horizontal panning requires the
1659 * plane stride to be a multiple of 4. We'll just
1660 * require the entire fb to accommodate that to avoid
1661 * potential runtime errors at plane configuration time.
1663 if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
1664 color_plane == 0 && fb->width > 3840)
1667 * The main surface pitch must be padded to a multiple of four
1670 else if (DISPLAY_VER(dev_priv) >= 12)
1676 static struct i915_vma *
1677 initial_plane_vma(struct drm_i915_private *i915,
1678 struct intel_initial_plane_config *plane_config)
1680 struct drm_i915_gem_object *obj;
1681 struct i915_vma *vma;
1684 if (plane_config->size == 0)
1687 base = round_down(plane_config->base,
1688 I915_GTT_MIN_ALIGNMENT);
1689 size = round_up(plane_config->base + plane_config->size,
1690 I915_GTT_MIN_ALIGNMENT);
1694 * If the FB is too big, just don't use it since fbdev is not very
1695 * important and we should probably use that space with FBC or other
1698 if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
1699 size * 2 > i915->stolen_usable_size)
1702 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
1707 * Mark it WT ahead of time to avoid changing the
1708 * cache_level during fbdev initialization. The
1709 * unbind there would get stuck waiting for rcu.
1711 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
1712 I915_CACHE_WT : I915_CACHE_NONE);
1714 switch (plane_config->tiling) {
1715 case I915_TILING_NONE:
1719 obj->tiling_and_stride =
1720 plane_config->fb->base.pitches[0] |
1721 plane_config->tiling;
1724 MISSING_CASE(plane_config->tiling);
1728 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1732 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
1735 if (i915_gem_object_is_tiled(obj) &&
1736 !i915_vma_is_map_and_fenceable(vma))
1742 i915_gem_object_put(obj);
1747 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
1748 struct intel_initial_plane_config *plane_config)
1750 struct drm_device *dev = crtc->base.dev;
1751 struct drm_i915_private *dev_priv = to_i915(dev);
1752 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
1753 struct drm_framebuffer *fb = &plane_config->fb->base;
1754 struct i915_vma *vma;
1756 switch (fb->modifier) {
1757 case DRM_FORMAT_MOD_LINEAR:
1758 case I915_FORMAT_MOD_X_TILED:
1759 case I915_FORMAT_MOD_Y_TILED:
1762 drm_dbg(&dev_priv->drm,
1763 "Unsupported modifier for initial FB: 0x%llx\n",
1768 vma = initial_plane_vma(dev_priv, plane_config);
1772 mode_cmd.pixel_format = fb->format->format;
1773 mode_cmd.width = fb->width;
1774 mode_cmd.height = fb->height;
1775 mode_cmd.pitches[0] = fb->pitches[0];
1776 mode_cmd.modifier[0] = fb->modifier;
1777 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
1779 if (intel_framebuffer_init(to_intel_framebuffer(fb),
1780 vma->obj, &mode_cmd)) {
1781 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
1785 plane_config->vma = vma;
1794 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
1795 struct intel_plane_state *plane_state,
1798 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1800 plane_state->uapi.visible = visible;
1803 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
1805 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
1808 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811 struct drm_plane *plane;
1814 * Active_planes aliases if multiple "primary" or cursor planes
1815 * have been used on the same (or wrong) pipe. plane_mask uses
1816 * unique ids, hence we can use that to reconstruct active_planes.
1818 crtc_state->enabled_planes = 0;
1819 crtc_state->active_planes = 0;
1821 drm_for_each_plane_mask(plane, &dev_priv->drm,
1822 crtc_state->uapi.plane_mask) {
1823 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
1824 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
1828 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
1829 struct intel_plane *plane)
1831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1832 struct intel_crtc_state *crtc_state =
1833 to_intel_crtc_state(crtc->base.state);
1834 struct intel_plane_state *plane_state =
1835 to_intel_plane_state(plane->base.state);
1837 drm_dbg_kms(&dev_priv->drm,
1838 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
1839 plane->base.base.id, plane->base.name,
1840 crtc->base.base.id, crtc->base.name);
1842 intel_set_plane_visible(crtc_state, plane_state, false);
1843 fixup_plane_bitmasks(crtc_state);
1844 crtc_state->data_rate[plane->id] = 0;
1845 crtc_state->min_cdclk[plane->id] = 0;
1847 if (plane->id == PLANE_PRIMARY)
1848 hsw_disable_ips(crtc_state);
1851 * Vblank time updates from the shadow to live plane control register
1852 * are blocked if the memory self-refresh mode is active at that
1853 * moment. So to make sure the plane gets truly disabled, disable
1854 * first the self-refresh mode. The self-refresh enable bit in turn
1855 * will be checked/applied by the HW only at the next frame start
1856 * event which is after the vblank start event, so we need to have a
1857 * wait-for-vblank between disabling the plane and the pipe.
1859 if (HAS_GMCH(dev_priv) &&
1860 intel_set_memory_cxsr(dev_priv, false))
1861 intel_wait_for_vblank(dev_priv, crtc->pipe);
1864 * Gen2 reports pipe underruns whenever all planes are disabled.
1865 * So disable underrun reporting before all the planes get disabled.
1867 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
1868 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
1870 intel_disable_plane(plane, crtc_state);
1871 intel_wait_for_vblank(dev_priv, crtc->pipe);
1874 static struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
1876 struct drm_i915_private *i915 = vm->i915;
1877 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
1878 intel_wakeref_t wakeref;
1879 struct i915_vma *vma;
1880 void __iomem *iomem;
1882 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1883 atomic_inc(&i915->gpu_error.pending_fb_pin);
1885 vma = i915_gem_object_ggtt_pin(dpt->obj, NULL, 0, 4096,
1886 HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);
1890 iomem = i915_vma_pin_iomap(vma);
1891 i915_vma_unpin(vma);
1892 if (IS_ERR(iomem)) {
1903 atomic_dec(&i915->gpu_error.pending_fb_pin);
1904 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1909 static void intel_dpt_unpin(struct i915_address_space *vm)
1911 struct i915_dpt *dpt = i915_vm_to_dpt(vm);
1913 i915_vma_unpin_iomap(dpt->vma);
1914 i915_vma_put(dpt->vma);
1918 intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
1919 const struct intel_initial_plane_config *plane_config,
1920 struct drm_framebuffer **fb,
1921 struct i915_vma **vma)
1923 struct intel_crtc *crtc;
1925 for_each_intel_crtc(&i915->drm, crtc) {
1926 struct intel_crtc_state *crtc_state =
1927 to_intel_crtc_state(crtc->base.state);
1928 struct intel_plane *plane =
1929 to_intel_plane(crtc->base.primary);
1930 struct intel_plane_state *plane_state =
1931 to_intel_plane_state(plane->base.state);
1933 if (!crtc_state->uapi.active)
1936 if (!plane_state->ggtt_vma)
1939 if (intel_plane_ggtt_offset(plane_state) == plane_config->base) {
1940 *fb = plane_state->hw.fb;
1941 *vma = plane_state->ggtt_vma;
1950 intel_find_initial_plane_obj(struct intel_crtc *crtc,
1951 struct intel_initial_plane_config *plane_config)
1953 struct drm_device *dev = crtc->base.dev;
1954 struct drm_i915_private *dev_priv = to_i915(dev);
1955 struct intel_crtc_state *crtc_state =
1956 to_intel_crtc_state(crtc->base.state);
1957 struct intel_plane *plane =
1958 to_intel_plane(crtc->base.primary);
1959 struct intel_plane_state *plane_state =
1960 to_intel_plane_state(plane->base.state);
1961 struct drm_framebuffer *fb;
1962 struct i915_vma *vma;
1966 * Disable planes if get_initial_plane_config() failed.
1967 * Make sure things work if the surface base is not page aligned.
1969 if (!plane_config->fb)
1972 if (intel_alloc_initial_plane_obj(crtc, plane_config)) {
1973 fb = &plane_config->fb->base;
1974 vma = plane_config->vma;
1979 * Failed to alloc the obj, check to see if we should share
1980 * an fb with another CRTC instead
1982 if (intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb, &vma))
1986 * We've failed to reconstruct the BIOS FB. Current display state
1987 * indicates that the primary plane is visible, but has a NULL FB,
1988 * which will lead to problems later if we don't fix it up. The
1989 * simplest solution is to just disable the primary plane now and
1990 * pretend the BIOS never had it enabled.
1992 intel_plane_disable_noatomic(crtc, plane);
1993 if (crtc_state->bigjoiner) {
1994 struct intel_crtc *slave =
1995 crtc_state->bigjoiner_linked_crtc;
1996 intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
2002 plane_state->uapi.rotation = plane_config->rotation;
2003 intel_fb_fill_view(to_intel_framebuffer(fb),
2004 plane_state->uapi.rotation, &plane_state->view);
2006 __i915_vma_pin(vma);
2007 plane_state->ggtt_vma = i915_vma_get(vma);
2008 if (intel_plane_uses_fence(plane_state) &&
2009 i915_vma_pin_fence(vma) == 0 && vma->fence)
2010 plane_state->flags |= PLANE_HAS_FENCE;
2012 plane_state->uapi.src_x = 0;
2013 plane_state->uapi.src_y = 0;
2014 plane_state->uapi.src_w = fb->width << 16;
2015 plane_state->uapi.src_h = fb->height << 16;
2017 plane_state->uapi.crtc_x = 0;
2018 plane_state->uapi.crtc_y = 0;
2019 plane_state->uapi.crtc_w = fb->width;
2020 plane_state->uapi.crtc_h = fb->height;
2022 if (plane_config->tiling)
2023 dev_priv->preserve_bios_swizzle = true;
2025 plane_state->uapi.fb = fb;
2026 drm_framebuffer_get(fb);
2028 plane_state->uapi.crtc = &crtc->base;
2029 intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc);
2031 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
2033 atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits);
2037 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
2041 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
2042 plane_state->view.color_plane[0].offset, 0);
2048 __intel_display_resume(struct drm_device *dev,
2049 struct drm_atomic_state *state,
2050 struct drm_modeset_acquire_ctx *ctx)
2052 struct drm_crtc_state *crtc_state;
2053 struct drm_crtc *crtc;
2056 intel_modeset_setup_hw_state(dev, ctx);
2057 intel_vga_redisable(to_i915(dev));
2063 * We've duplicated the state, pointers to the old state are invalid.
2065 * Don't attempt to use the old state until we commit the duplicated state.
2067 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
2069 * Force recalculation even if we restore
2070 * current state. With fast modeset this may not result
2071 * in a modeset when the state is compatible.
2073 crtc_state->mode_changed = true;
2076 /* ignore any reset values/BIOS leftovers in the WM registers */
2077 if (!HAS_GMCH(to_i915(dev)))
2078 to_intel_atomic_state(state)->skip_intermediate_wm = true;
2080 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
2082 drm_WARN_ON(dev, ret == -EDEADLK);
2086 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
2088 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
2089 intel_has_gpu_reset(&dev_priv->gt));
2092 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
2094 struct drm_device *dev = &dev_priv->drm;
2095 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
2096 struct drm_atomic_state *state;
2099 if (!HAS_DISPLAY(dev_priv))
2102 /* reset doesn't touch the display */
2103 if (!dev_priv->params.force_reset_modeset_test &&
2104 !gpu_reset_clobbers_display(dev_priv))
2107 /* We have a modeset vs reset deadlock, defensively unbreak it. */
2108 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
2109 smp_mb__after_atomic();
2110 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
2112 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
2113 drm_dbg_kms(&dev_priv->drm,
2114 "Modeset potentially stuck, unbreaking through wedging\n");
2115 intel_gt_set_wedged(&dev_priv->gt);
2119 * Need mode_config.mutex so that we don't
2120 * trample ongoing ->detect() and whatnot.
2122 mutex_lock(&dev->mode_config.mutex);
2123 drm_modeset_acquire_init(ctx, 0);
2125 ret = drm_modeset_lock_all_ctx(dev, ctx);
2126 if (ret != -EDEADLK)
2129 drm_modeset_backoff(ctx);
2132 * Disabling the crtcs gracefully seems nicer. Also the
2133 * g33 docs say we should at least disable all the planes.
2135 state = drm_atomic_helper_duplicate_state(dev, ctx);
2136 if (IS_ERR(state)) {
2137 ret = PTR_ERR(state);
2138 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
2143 ret = drm_atomic_helper_disable_all(dev, ctx);
2145 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2147 drm_atomic_state_put(state);
2151 dev_priv->modeset_restore_state = state;
2152 state->acquire_ctx = ctx;
2155 void intel_display_finish_reset(struct drm_i915_private *dev_priv)
2157 struct drm_device *dev = &dev_priv->drm;
2158 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
2159 struct drm_atomic_state *state;
2162 if (!HAS_DISPLAY(dev_priv))
2165 /* reset doesn't touch the display */
2166 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
2169 state = fetch_and_zero(&dev_priv->modeset_restore_state);
2173 /* reset doesn't touch the display */
2174 if (!gpu_reset_clobbers_display(dev_priv)) {
2175 /* for testing only restore the display */
2176 ret = __intel_display_resume(dev, state, ctx);
2178 drm_err(&dev_priv->drm,
2179 "Restoring old state failed with %i\n", ret);
2182 * The display has been reset as well,
2183 * so need a full re-initialization.
2185 intel_pps_unlock_regs_wa(dev_priv);
2186 intel_modeset_init_hw(dev_priv);
2187 intel_init_clock_gating(dev_priv);
2188 intel_hpd_init(dev_priv);
2190 ret = __intel_display_resume(dev, state, ctx);
2192 drm_err(&dev_priv->drm,
2193 "Restoring old state failed with %i\n", ret);
2195 intel_hpd_poll_disable(dev_priv);
2198 drm_atomic_state_put(state);
2200 drm_modeset_drop_locks(ctx);
2201 drm_modeset_acquire_fini(ctx);
2202 mutex_unlock(&dev->mode_config.mutex);
2204 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
2207 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
2209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2210 enum pipe pipe = crtc->pipe;
2213 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
2216 * Display WA #1153: icl
2217 * enable hardware to bypass the alpha math
2218 * and rounding for per-pixel values 00 and 0xff
2220 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
2222 * Display WA # 1605353570: icl
2223 * Set the pixel rounding bit to 1 for allowing
2224 * passthrough of Frame buffer pixels unmodified
2227 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
2230 * "The underrun recovery mechanism should be disabled
2231 * when the following is enabled for this pipe:
2233 * Downscaling (this includes YUV420 fullblend)
2238 * FIXME: enable whenever possible...
2240 if (IS_ALDERLAKE_P(dev_priv))
2241 tmp |= UNDERRUN_RECOVERY_DISABLE;
2243 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
2246 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
2248 struct drm_crtc *crtc;
2251 drm_for_each_crtc(crtc, &dev_priv->drm) {
2252 struct drm_crtc_commit *commit;
2253 spin_lock(&crtc->commit_lock);
2254 commit = list_first_entry_or_null(&crtc->commit_list,
2255 struct drm_crtc_commit, commit_entry);
2256 cleanup_done = commit ?
2257 try_wait_for_completion(&commit->cleanup_done) : true;
2258 spin_unlock(&crtc->commit_lock);
2263 drm_crtc_wait_one_vblank(crtc);
2271 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
2275 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
2277 mutex_lock(&dev_priv->sb_lock);
2279 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2280 temp |= SBI_SSCCTL_DISABLE;
2281 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2283 mutex_unlock(&dev_priv->sb_lock);
2286 /* Program iCLKIP clock to the desired frequency */
2287 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
2289 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2290 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2291 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
2292 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2295 lpt_disable_iclkip(dev_priv);
2297 /* The iCLK virtual clock root frequency is in MHz,
2298 * but the adjusted_mode->crtc_clock in in KHz. To get the
2299 * divisors, it is necessary to divide one by another, so we
2300 * convert the virtual clock precision to KHz here for higher
2303 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
2304 u32 iclk_virtual_root_freq = 172800 * 1000;
2305 u32 iclk_pi_range = 64;
2306 u32 desired_divisor;
2308 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2310 divsel = (desired_divisor / iclk_pi_range) - 2;
2311 phaseinc = desired_divisor % iclk_pi_range;
2314 * Near 20MHz is a corner case which is
2315 * out of range for the 7-bit divisor
2321 /* This should not happen with any sane values */
2322 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2323 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2324 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
2325 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2327 drm_dbg_kms(&dev_priv->drm,
2328 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2329 clock, auxdiv, divsel, phasedir, phaseinc);
2331 mutex_lock(&dev_priv->sb_lock);
2333 /* Program SSCDIVINTPHASE6 */
2334 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2335 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2336 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2337 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2338 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2339 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2340 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2341 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2343 /* Program SSCAUXDIV */
2344 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2345 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2346 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2347 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2349 /* Enable modulator and associated divider */
2350 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2351 temp &= ~SBI_SSCCTL_DISABLE;
2352 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2354 mutex_unlock(&dev_priv->sb_lock);
2356 /* Wait for initialization time */
2359 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2362 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
2364 u32 divsel, phaseinc, auxdiv;
2365 u32 iclk_virtual_root_freq = 172800 * 1000;
2366 u32 iclk_pi_range = 64;
2367 u32 desired_divisor;
2370 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
2373 mutex_lock(&dev_priv->sb_lock);
2375 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2376 if (temp & SBI_SSCCTL_DISABLE) {
2377 mutex_unlock(&dev_priv->sb_lock);
2381 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2382 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
2383 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
2384 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
2385 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
2387 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2388 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
2389 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
2391 mutex_unlock(&dev_priv->sb_lock);
2393 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
2395 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2396 desired_divisor << auxdiv);
2399 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
2400 enum pipe pch_transcoder)
2402 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2404 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2406 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
2407 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
2408 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
2409 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
2410 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
2411 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
2413 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
2414 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
2415 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
2416 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
2417 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
2418 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
2419 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2420 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
2423 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
2427 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
2428 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
2431 drm_WARN_ON(&dev_priv->drm,
2432 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
2434 drm_WARN_ON(&dev_priv->drm,
2435 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
2438 temp &= ~FDI_BC_BIFURCATION_SELECT;
2440 temp |= FDI_BC_BIFURCATION_SELECT;
2442 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
2443 enable ? "en" : "dis");
2444 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
2445 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
2448 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
2450 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2451 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2453 switch (crtc->pipe) {
2457 if (crtc_state->fdi_lanes > 2)
2458 cpt_set_fdi_bc_bifurcation(dev_priv, false);
2460 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2464 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2473 * Finds the encoder associated with the given CRTC. This can only be
2474 * used when we know that the CRTC isn't feeding multiple encoders!
2476 struct intel_encoder *
2477 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
2478 const struct intel_crtc_state *crtc_state)
2480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2481 const struct drm_connector_state *connector_state;
2482 const struct drm_connector *connector;
2483 struct intel_encoder *encoder = NULL;
2484 int num_encoders = 0;
2487 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
2488 if (connector_state->crtc != &crtc->base)
2491 encoder = to_intel_encoder(connector_state->best_encoder);
2495 drm_WARN(encoder->base.dev, num_encoders != 1,
2496 "%d encoders for pipe %c\n",
2497 num_encoders, pipe_name(crtc->pipe));
2503 * Enable PCH resources required for PCH ports:
2505 * - FDI training & RX/TX
2506 * - update transcoder timings
2507 * - DP transcoding bits
2510 static void ilk_pch_enable(const struct intel_atomic_state *state,
2511 const struct intel_crtc_state *crtc_state)
2513 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2514 struct drm_device *dev = crtc->base.dev;
2515 struct drm_i915_private *dev_priv = to_i915(dev);
2516 enum pipe pipe = crtc->pipe;
2519 assert_pch_transcoder_disabled(dev_priv, pipe);
2521 if (IS_IVYBRIDGE(dev_priv))
2522 ivb_update_fdi_bc_bifurcation(crtc_state);
2524 /* Write the TU size bits before fdi link training, so that error
2525 * detection works. */
2526 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
2527 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2529 /* For PCH output, training FDI link */
2530 dev_priv->display.fdi_link_train(crtc, crtc_state);
2532 /* We need to program the right clock selection before writing the pixel
2533 * mutliplier into the DPLL. */
2534 if (HAS_PCH_CPT(dev_priv)) {
2537 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
2538 temp |= TRANS_DPLL_ENABLE(pipe);
2539 sel = TRANS_DPLLB_SEL(pipe);
2540 if (crtc_state->shared_dpll ==
2541 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
2545 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
2548 /* XXX: pch pll's can be enabled any time before we enable the PCH
2549 * transcoder, and we actually should do this to not upset any PCH
2550 * transcoder that already use the clock when we share it.
2552 * Note that enable_shared_dpll tries to do the right thing, but
2553 * get_shared_dpll unconditionally resets the pll - we need that to have
2554 * the right LVDS enable sequence. */
2555 intel_enable_shared_dpll(crtc_state);
2557 /* set transcoder timing, panel must allow it */
2558 assert_panel_unlocked(dev_priv, pipe);
2559 ilk_pch_transcoder_set_timings(crtc_state, pipe);
2561 intel_fdi_normal_train(crtc);
2563 /* For PCH DP, enable TRANS_DP_CTL */
2564 if (HAS_PCH_CPT(dev_priv) &&
2565 intel_crtc_has_dp_encoder(crtc_state)) {
2566 const struct drm_display_mode *adjusted_mode =
2567 &crtc_state->hw.adjusted_mode;
2568 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2569 i915_reg_t reg = TRANS_DP_CTL(pipe);
2572 temp = intel_de_read(dev_priv, reg);
2573 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2574 TRANS_DP_SYNC_MASK |
2576 temp |= TRANS_DP_OUTPUT_ENABLE;
2577 temp |= bpc << 9; /* same format but at 11:9 */
2579 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2580 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2581 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2582 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2584 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
2585 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
2586 temp |= TRANS_DP_PORT_SEL(port);
2588 intel_de_write(dev_priv, reg, temp);
2591 ilk_enable_pch_transcoder(crtc_state);
2594 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
2596 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2597 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2598 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2600 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
2602 lpt_program_iclkip(crtc_state);
2604 /* Set transcoder timing. */
2605 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
2607 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
2610 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
2613 i915_reg_t dslreg = PIPEDSL(pipe);
2616 temp = intel_de_read(dev_priv, dslreg);
2618 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
2619 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
2620 drm_err(&dev_priv->drm,
2621 "mode set failed: pipe %c stuck\n",
2626 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
2628 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2629 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2630 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
2631 enum pipe pipe = crtc->pipe;
2632 int width = drm_rect_width(dst);
2633 int height = drm_rect_height(dst);
2637 if (!crtc_state->pch_pfit.enabled)
2640 /* Force use of hard-coded filter coefficients
2641 * as some pre-programmed values are broken,
2644 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
2645 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
2646 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
2648 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
2650 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
2651 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
2654 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
2656 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2657 struct drm_device *dev = crtc->base.dev;
2658 struct drm_i915_private *dev_priv = to_i915(dev);
2660 if (!crtc_state->ips_enabled)
2664 * We can only enable IPS after we enable a plane and wait for a vblank
2665 * This function is called from post_plane_update, which is run after
2668 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
2670 if (IS_BROADWELL(dev_priv)) {
2671 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
2672 IPS_ENABLE | IPS_PCODE_CONTROL));
2673 /* Quoting Art Runyan: "its not safe to expect any particular
2674 * value in IPS_CTL bit 31 after enabling IPS through the
2675 * mailbox." Moreover, the mailbox may return a bogus state,
2676 * so we need to just enable it and continue on.
2679 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
2680 /* The bit only becomes 1 in the next vblank, so this wait here
2681 * is essentially intel_wait_for_vblank. If we don't have this
2682 * and don't wait for vblanks until the end of crtc_enable, then
2683 * the HW state readout code will complain that the expected
2684 * IPS_CTL value is not the one we read. */
2685 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
2686 drm_err(&dev_priv->drm,
2687 "Timed out waiting for IPS enable\n");
2691 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
2693 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2694 struct drm_device *dev = crtc->base.dev;
2695 struct drm_i915_private *dev_priv = to_i915(dev);
2697 if (!crtc_state->ips_enabled)
2700 if (IS_BROADWELL(dev_priv)) {
2702 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
2704 * Wait for PCODE to finish disabling IPS. The BSpec specified
2705 * 42ms timeout value leads to occasional timeouts so use 100ms
2708 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
2709 drm_err(&dev_priv->drm,
2710 "Timed out waiting for IPS disable\n");
2712 intel_de_write(dev_priv, IPS_CTL, 0);
2713 intel_de_posting_read(dev_priv, IPS_CTL);
2716 /* We need to wait for a vblank before we can disable the plane. */
2717 intel_wait_for_vblank(dev_priv, crtc->pipe);
2720 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
2723 (void) intel_overlay_switch_off(crtc->overlay);
2725 /* Let userspace switch the overlay on again. In most cases userspace
2726 * has to recompute where to put it anyway.
2730 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
2731 const struct intel_crtc_state *new_crtc_state)
2733 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2734 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2736 if (!old_crtc_state->ips_enabled)
2739 if (intel_crtc_needs_modeset(new_crtc_state))
2743 * Workaround : Do not read or write the pipe palette/gamma data while
2744 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
2746 * Disable IPS before we program the LUT.
2748 if (IS_HASWELL(dev_priv) &&
2749 (new_crtc_state->uapi.color_mgmt_changed ||
2750 new_crtc_state->update_pipe) &&
2751 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2754 return !new_crtc_state->ips_enabled;
2757 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
2758 const struct intel_crtc_state *new_crtc_state)
2760 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2761 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2763 if (!new_crtc_state->ips_enabled)
2766 if (intel_crtc_needs_modeset(new_crtc_state))
2770 * Workaround : Do not read or write the pipe palette/gamma data while
2771 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
2773 * Re-enable IPS after the LUT has been programmed.
2775 if (IS_HASWELL(dev_priv) &&
2776 (new_crtc_state->uapi.color_mgmt_changed ||
2777 new_crtc_state->update_pipe) &&
2778 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2782 * We can't read out IPS on broadwell, assume the worst and
2783 * forcibly enable IPS on the first fastset.
2785 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
2788 return !old_crtc_state->ips_enabled;
2791 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
2793 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2795 if (!crtc_state->nv12_planes)
2798 /* WA Display #0827: Gen9:all */
2799 if (DISPLAY_VER(dev_priv) == 9)
2805 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
2807 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2809 /* Wa_2006604312:icl,ehl */
2810 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
2816 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
2817 const struct intel_crtc_state *new_crtc_state)
2819 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
2820 new_crtc_state->active_planes;
2823 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
2824 const struct intel_crtc_state *new_crtc_state)
2826 return old_crtc_state->active_planes &&
2827 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
2830 static void intel_post_plane_update(struct intel_atomic_state *state,
2831 struct intel_crtc *crtc)
2833 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2834 const struct intel_crtc_state *old_crtc_state =
2835 intel_atomic_get_old_crtc_state(state, crtc);
2836 const struct intel_crtc_state *new_crtc_state =
2837 intel_atomic_get_new_crtc_state(state, crtc);
2838 enum pipe pipe = crtc->pipe;
2840 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
2842 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
2843 intel_update_watermarks(crtc);
2845 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
2846 hsw_enable_ips(new_crtc_state);
2848 intel_fbc_post_update(state, crtc);
2850 if (needs_nv12_wa(old_crtc_state) &&
2851 !needs_nv12_wa(new_crtc_state))
2852 skl_wa_827(dev_priv, pipe, false);
2854 if (needs_scalerclk_wa(old_crtc_state) &&
2855 !needs_scalerclk_wa(new_crtc_state))
2856 icl_wa_scalerclkgating(dev_priv, pipe, false);
2859 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
2860 struct intel_crtc *crtc)
2862 const struct intel_crtc_state *crtc_state =
2863 intel_atomic_get_new_crtc_state(state, crtc);
2864 u8 update_planes = crtc_state->update_planes;
2865 const struct intel_plane_state *plane_state;
2866 struct intel_plane *plane;
2869 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
2870 if (plane->enable_flip_done &&
2871 plane->pipe == crtc->pipe &&
2872 update_planes & BIT(plane->id))
2873 plane->enable_flip_done(plane);
2877 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
2878 struct intel_crtc *crtc)
2880 const struct intel_crtc_state *crtc_state =
2881 intel_atomic_get_new_crtc_state(state, crtc);
2882 u8 update_planes = crtc_state->update_planes;
2883 const struct intel_plane_state *plane_state;
2884 struct intel_plane *plane;
2887 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
2888 if (plane->disable_flip_done &&
2889 plane->pipe == crtc->pipe &&
2890 update_planes & BIT(plane->id))
2891 plane->disable_flip_done(plane);
2895 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
2896 struct intel_crtc *crtc)
2898 struct drm_i915_private *i915 = to_i915(state->base.dev);
2899 const struct intel_crtc_state *old_crtc_state =
2900 intel_atomic_get_old_crtc_state(state, crtc);
2901 const struct intel_crtc_state *new_crtc_state =
2902 intel_atomic_get_new_crtc_state(state, crtc);
2903 u8 update_planes = new_crtc_state->update_planes;
2904 const struct intel_plane_state *old_plane_state;
2905 struct intel_plane *plane;
2906 bool need_vbl_wait = false;
2909 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
2910 if (plane->need_async_flip_disable_wa &&
2911 plane->pipe == crtc->pipe &&
2912 update_planes & BIT(plane->id)) {
2914 * Apart from the async flip bit we want to
2915 * preserve the old state for the plane.
2917 plane->async_flip(plane, old_crtc_state,
2918 old_plane_state, false);
2919 need_vbl_wait = true;
2924 intel_wait_for_vblank(i915, crtc->pipe);
2927 static void intel_pre_plane_update(struct intel_atomic_state *state,
2928 struct intel_crtc *crtc)
2930 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2931 const struct intel_crtc_state *old_crtc_state =
2932 intel_atomic_get_old_crtc_state(state, crtc);
2933 const struct intel_crtc_state *new_crtc_state =
2934 intel_atomic_get_new_crtc_state(state, crtc);
2935 enum pipe pipe = crtc->pipe;
2937 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
2938 hsw_disable_ips(old_crtc_state);
2940 if (intel_fbc_pre_update(state, crtc))
2941 intel_wait_for_vblank(dev_priv, pipe);
2943 /* Display WA 827 */
2944 if (!needs_nv12_wa(old_crtc_state) &&
2945 needs_nv12_wa(new_crtc_state))
2946 skl_wa_827(dev_priv, pipe, true);
2948 /* Wa_2006604312:icl,ehl */
2949 if (!needs_scalerclk_wa(old_crtc_state) &&
2950 needs_scalerclk_wa(new_crtc_state))
2951 icl_wa_scalerclkgating(dev_priv, pipe, true);
2954 * Vblank time updates from the shadow to live plane control register
2955 * are blocked if the memory self-refresh mode is active at that
2956 * moment. So to make sure the plane gets truly disabled, disable
2957 * first the self-refresh mode. The self-refresh enable bit in turn
2958 * will be checked/applied by the HW only at the next frame start
2959 * event which is after the vblank start event, so we need to have a
2960 * wait-for-vblank between disabling the plane and the pipe.
2962 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
2963 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
2964 intel_wait_for_vblank(dev_priv, pipe);
2967 * IVB workaround: must disable low power watermarks for at least
2968 * one frame before enabling scaling. LP watermarks can be re-enabled
2969 * when scaling is disabled.
2971 * WaCxSRDisabledForSpriteScaling:ivb
2973 if (old_crtc_state->hw.active &&
2974 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
2975 intel_wait_for_vblank(dev_priv, pipe);
2978 * If we're doing a modeset we don't need to do any
2979 * pre-vblank watermark programming here.
2981 if (!intel_crtc_needs_modeset(new_crtc_state)) {
2983 * For platforms that support atomic watermarks, program the
2984 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
2985 * will be the intermediate values that are safe for both pre- and
2986 * post- vblank; when vblank happens, the 'active' values will be set
2987 * to the final 'target' values and we'll do this again to get the
2988 * optimal watermarks. For gen9+ platforms, the values we program here
2989 * will be the final target values which will get automatically latched
2990 * at vblank time; no further programming will be necessary.
2992 * If a platform hasn't been transitioned to atomic watermarks yet,
2993 * we'll continue to update watermarks the old way, if flags tell
2996 if (dev_priv->display.initial_watermarks)
2997 dev_priv->display.initial_watermarks(state, crtc);
2998 else if (new_crtc_state->update_wm_pre)
2999 intel_update_watermarks(crtc);
3003 * Gen2 reports pipe underruns whenever all planes are disabled.
3004 * So disable underrun reporting before all the planes get disabled.
3006 * We do this after .initial_watermarks() so that we have a
3007 * chance of catching underruns with the intermediate watermarks
3008 * vs. the old plane configuration.
3010 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
3011 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3014 * WA for platforms where async address update enable bit
3015 * is double buffered and only latched at start of vblank.
3017 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
3018 intel_crtc_async_flip_disable_wa(state, crtc);
3021 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
3022 struct intel_crtc *crtc)
3024 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3025 const struct intel_crtc_state *new_crtc_state =
3026 intel_atomic_get_new_crtc_state(state, crtc);
3027 unsigned int update_mask = new_crtc_state->update_planes;
3028 const struct intel_plane_state *old_plane_state;
3029 struct intel_plane *plane;
3030 unsigned fb_bits = 0;
3033 intel_crtc_dpms_overlay_disable(crtc);
3035 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
3036 if (crtc->pipe != plane->pipe ||
3037 !(update_mask & BIT(plane->id)))
3040 intel_disable_plane(plane, new_crtc_state);
3042 if (old_plane_state->uapi.visible)
3043 fb_bits |= plane->frontbuffer_bit;
3046 intel_frontbuffer_flip(dev_priv, fb_bits);
3050 * intel_connector_primary_encoder - get the primary encoder for a connector
3051 * @connector: connector for which to return the encoder
3053 * Returns the primary encoder for a connector. There is a 1:1 mapping from
3054 * all connectors to their encoder, except for DP-MST connectors which have
3055 * both a virtual and a primary encoder. These DP-MST primary encoders can be
3056 * pointed to by as many DP-MST connectors as there are pipes.
3058 static struct intel_encoder *
3059 intel_connector_primary_encoder(struct intel_connector *connector)
3061 struct intel_encoder *encoder;
3063 if (connector->mst_port)
3064 return &dp_to_dig_port(connector->mst_port)->base;
3066 encoder = intel_attached_encoder(connector);
3067 drm_WARN_ON(connector->base.dev, !encoder);
3072 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
3074 struct drm_connector_state *new_conn_state;
3075 struct drm_connector *connector;
3078 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
3080 struct intel_connector *intel_connector;
3081 struct intel_encoder *encoder;
3082 struct intel_crtc *crtc;
3084 if (!intel_connector_needs_modeset(state, connector))
3087 intel_connector = to_intel_connector(connector);
3088 encoder = intel_connector_primary_encoder(intel_connector);
3089 if (!encoder->update_prepare)
3092 crtc = new_conn_state->crtc ?
3093 to_intel_crtc(new_conn_state->crtc) : NULL;
3094 encoder->update_prepare(state, encoder, crtc);
3098 static void intel_encoders_update_complete(struct intel_atomic_state *state)
3100 struct drm_connector_state *new_conn_state;
3101 struct drm_connector *connector;
3104 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
3106 struct intel_connector *intel_connector;
3107 struct intel_encoder *encoder;
3108 struct intel_crtc *crtc;
3110 if (!intel_connector_needs_modeset(state, connector))
3113 intel_connector = to_intel_connector(connector);
3114 encoder = intel_connector_primary_encoder(intel_connector);
3115 if (!encoder->update_complete)
3118 crtc = new_conn_state->crtc ?
3119 to_intel_crtc(new_conn_state->crtc) : NULL;
3120 encoder->update_complete(state, encoder, crtc);
3124 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
3125 struct intel_crtc *crtc)
3127 const struct intel_crtc_state *crtc_state =
3128 intel_atomic_get_new_crtc_state(state, crtc);
3129 const struct drm_connector_state *conn_state;
3130 struct drm_connector *conn;
3133 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3134 struct intel_encoder *encoder =
3135 to_intel_encoder(conn_state->best_encoder);
3137 if (conn_state->crtc != &crtc->base)
3140 if (encoder->pre_pll_enable)
3141 encoder->pre_pll_enable(state, encoder,
3142 crtc_state, conn_state);
3146 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
3147 struct intel_crtc *crtc)
3149 const struct intel_crtc_state *crtc_state =
3150 intel_atomic_get_new_crtc_state(state, crtc);
3151 const struct drm_connector_state *conn_state;
3152 struct drm_connector *conn;
3155 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3156 struct intel_encoder *encoder =
3157 to_intel_encoder(conn_state->best_encoder);
3159 if (conn_state->crtc != &crtc->base)
3162 if (encoder->pre_enable)
3163 encoder->pre_enable(state, encoder,
3164 crtc_state, conn_state);
3168 static void intel_encoders_enable(struct intel_atomic_state *state,
3169 struct intel_crtc *crtc)
3171 const struct intel_crtc_state *crtc_state =
3172 intel_atomic_get_new_crtc_state(state, crtc);
3173 const struct drm_connector_state *conn_state;
3174 struct drm_connector *conn;
3177 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3178 struct intel_encoder *encoder =
3179 to_intel_encoder(conn_state->best_encoder);
3181 if (conn_state->crtc != &crtc->base)
3184 if (encoder->enable)
3185 encoder->enable(state, encoder,
3186 crtc_state, conn_state);
3187 intel_opregion_notify_encoder(encoder, true);
3191 static void intel_encoders_disable(struct intel_atomic_state *state,
3192 struct intel_crtc *crtc)
3194 const struct intel_crtc_state *old_crtc_state =
3195 intel_atomic_get_old_crtc_state(state, crtc);
3196 const struct drm_connector_state *old_conn_state;
3197 struct drm_connector *conn;
3200 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3201 struct intel_encoder *encoder =
3202 to_intel_encoder(old_conn_state->best_encoder);
3204 if (old_conn_state->crtc != &crtc->base)
3207 intel_opregion_notify_encoder(encoder, false);
3208 if (encoder->disable)
3209 encoder->disable(state, encoder,
3210 old_crtc_state, old_conn_state);
3214 static void intel_encoders_post_disable(struct intel_atomic_state *state,
3215 struct intel_crtc *crtc)
3217 const struct intel_crtc_state *old_crtc_state =
3218 intel_atomic_get_old_crtc_state(state, crtc);
3219 const struct drm_connector_state *old_conn_state;
3220 struct drm_connector *conn;
3223 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3224 struct intel_encoder *encoder =
3225 to_intel_encoder(old_conn_state->best_encoder);
3227 if (old_conn_state->crtc != &crtc->base)
3230 if (encoder->post_disable)
3231 encoder->post_disable(state, encoder,
3232 old_crtc_state, old_conn_state);
3236 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
3237 struct intel_crtc *crtc)
3239 const struct intel_crtc_state *old_crtc_state =
3240 intel_atomic_get_old_crtc_state(state, crtc);
3241 const struct drm_connector_state *old_conn_state;
3242 struct drm_connector *conn;
3245 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3246 struct intel_encoder *encoder =
3247 to_intel_encoder(old_conn_state->best_encoder);
3249 if (old_conn_state->crtc != &crtc->base)
3252 if (encoder->post_pll_disable)
3253 encoder->post_pll_disable(state, encoder,
3254 old_crtc_state, old_conn_state);
3258 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
3259 struct intel_crtc *crtc)
3261 const struct intel_crtc_state *crtc_state =
3262 intel_atomic_get_new_crtc_state(state, crtc);
3263 const struct drm_connector_state *conn_state;
3264 struct drm_connector *conn;
3267 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3268 struct intel_encoder *encoder =
3269 to_intel_encoder(conn_state->best_encoder);
3271 if (conn_state->crtc != &crtc->base)
3274 if (encoder->update_pipe)
3275 encoder->update_pipe(state, encoder,
3276 crtc_state, conn_state);
3280 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
3282 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3283 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3285 plane->disable_plane(plane, crtc_state);
3288 static void ilk_crtc_enable(struct intel_atomic_state *state,
3289 struct intel_crtc *crtc)
3291 const struct intel_crtc_state *new_crtc_state =
3292 intel_atomic_get_new_crtc_state(state, crtc);
3293 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3294 enum pipe pipe = crtc->pipe;
3296 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3300 * Sometimes spurious CPU pipe underruns happen during FDI
3301 * training, at least with VGA+HDMI cloning. Suppress them.
3303 * On ILK we get an occasional spurious CPU pipe underruns
3304 * between eDP port A enable and vdd enable. Also PCH port
3305 * enable seems to result in the occasional CPU pipe underrun.
3307 * Spurious PCH underruns also occur during PCH enabling.
3309 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3310 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
3312 if (new_crtc_state->has_pch_encoder)
3313 intel_prepare_shared_dpll(new_crtc_state);
3315 if (intel_crtc_has_dp_encoder(new_crtc_state))
3316 intel_dp_set_m_n(new_crtc_state, M1_N1);
3318 intel_set_transcoder_timings(new_crtc_state);
3319 intel_set_pipe_src_size(new_crtc_state);
3321 if (new_crtc_state->has_pch_encoder)
3322 intel_cpu_transcoder_set_m_n(new_crtc_state,
3323 &new_crtc_state->fdi_m_n, NULL);
3325 ilk_set_pipeconf(new_crtc_state);
3327 crtc->active = true;
3329 intel_encoders_pre_enable(state, crtc);
3331 if (new_crtc_state->has_pch_encoder) {
3332 /* Note: FDI PLL enabling _must_ be done before we enable the
3333 * cpu pipes, hence this is separate from all the other fdi/pch
3335 ilk_fdi_pll_enable(new_crtc_state);
3337 assert_fdi_tx_disabled(dev_priv, pipe);
3338 assert_fdi_rx_disabled(dev_priv, pipe);
3341 ilk_pfit_enable(new_crtc_state);
3344 * On ILK+ LUT must be loaded before the pipe is running but with
3347 intel_color_load_luts(new_crtc_state);
3348 intel_color_commit(new_crtc_state);
3349 /* update DSPCNTR to configure gamma for pipe bottom color */
3350 intel_disable_primary_plane(new_crtc_state);
3352 if (dev_priv->display.initial_watermarks)
3353 dev_priv->display.initial_watermarks(state, crtc);
3354 intel_enable_pipe(new_crtc_state);
3356 if (new_crtc_state->has_pch_encoder)
3357 ilk_pch_enable(state, new_crtc_state);
3359 intel_crtc_vblank_on(new_crtc_state);
3361 intel_encoders_enable(state, crtc);
3363 if (HAS_PCH_CPT(dev_priv))
3364 cpt_verify_modeset(dev_priv, pipe);
3367 * Must wait for vblank to avoid spurious PCH FIFO underruns.
3368 * And a second vblank wait is needed at least on ILK with
3369 * some interlaced HDMI modes. Let's do the double wait always
3370 * in case there are more corner cases we don't know about.
3372 if (new_crtc_state->has_pch_encoder) {
3373 intel_wait_for_vblank(dev_priv, pipe);
3374 intel_wait_for_vblank(dev_priv, pipe);
3376 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3377 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
3380 /* IPS only exists on ULT machines and is tied to pipe A. */
3381 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3383 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
3386 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
3387 enum pipe pipe, bool apply)
3389 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
3390 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
3397 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
3400 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
3402 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3403 enum pipe pipe = crtc->pipe;
3406 val = MBUS_DBOX_A_CREDIT(2);
3408 if (DISPLAY_VER(dev_priv) >= 12) {
3409 val |= MBUS_DBOX_BW_CREDIT(2);
3410 val |= MBUS_DBOX_B_CREDIT(12);
3412 val |= MBUS_DBOX_BW_CREDIT(1);
3413 val |= MBUS_DBOX_B_CREDIT(8);
3416 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
3419 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
3421 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3424 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
3425 HSW_LINETIME(crtc_state->linetime) |
3426 HSW_IPS_LINETIME(crtc_state->ips_linetime));
3429 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
3431 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3432 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3433 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
3436 val = intel_de_read(dev_priv, reg);
3437 val &= ~HSW_FRAME_START_DELAY_MASK;
3438 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
3439 intel_de_write(dev_priv, reg, val);
3442 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
3443 const struct intel_crtc_state *crtc_state)
3445 struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
3446 struct drm_i915_private *dev_priv = to_i915(master->base.dev);
3447 struct intel_crtc_state *master_crtc_state;
3448 struct drm_connector_state *conn_state;
3449 struct drm_connector *conn;
3450 struct intel_encoder *encoder = NULL;
3453 if (crtc_state->bigjoiner_slave)
3454 master = crtc_state->bigjoiner_linked_crtc;
3456 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
3458 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3459 if (conn_state->crtc != &master->base)
3462 encoder = to_intel_encoder(conn_state->best_encoder);
3466 if (!crtc_state->bigjoiner_slave) {
3467 /* need to enable VDSC, which we skipped in pre-enable */
3468 intel_dsc_enable(encoder, crtc_state);
3471 * Enable sequence steps 1-7 on bigjoiner master
3473 intel_encoders_pre_pll_enable(state, master);
3474 intel_enable_shared_dpll(master_crtc_state);
3475 intel_encoders_pre_enable(state, master);
3477 /* and DSC on slave */
3478 intel_dsc_enable(NULL, crtc_state);
3481 if (DISPLAY_VER(dev_priv) >= 13)
3482 intel_uncompressed_joiner_enable(crtc_state);
3485 static void hsw_crtc_enable(struct intel_atomic_state *state,
3486 struct intel_crtc *crtc)
3488 const struct intel_crtc_state *new_crtc_state =
3489 intel_atomic_get_new_crtc_state(state, crtc);
3490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3491 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
3492 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
3493 bool psl_clkgate_wa;
3495 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3498 if (!new_crtc_state->bigjoiner) {
3499 intel_encoders_pre_pll_enable(state, crtc);
3501 if (new_crtc_state->shared_dpll)
3502 intel_enable_shared_dpll(new_crtc_state);
3504 intel_encoders_pre_enable(state, crtc);
3506 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
3509 intel_set_pipe_src_size(new_crtc_state);
3510 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
3511 bdw_set_pipemisc(new_crtc_state);
3513 if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
3514 intel_set_transcoder_timings(new_crtc_state);
3516 if (cpu_transcoder != TRANSCODER_EDP)
3517 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
3518 new_crtc_state->pixel_multiplier - 1);
3520 if (new_crtc_state->has_pch_encoder)
3521 intel_cpu_transcoder_set_m_n(new_crtc_state,
3522 &new_crtc_state->fdi_m_n, NULL);
3524 hsw_set_frame_start_delay(new_crtc_state);
3527 if (!transcoder_is_dsi(cpu_transcoder))
3528 hsw_set_pipeconf(new_crtc_state);
3530 crtc->active = true;
3532 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
3533 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
3534 new_crtc_state->pch_pfit.enabled;
3536 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
3538 if (DISPLAY_VER(dev_priv) >= 9)
3539 skl_pfit_enable(new_crtc_state);
3541 ilk_pfit_enable(new_crtc_state);
3544 * On ILK+ LUT must be loaded before the pipe is running but with
3547 intel_color_load_luts(new_crtc_state);
3548 intel_color_commit(new_crtc_state);
3549 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
3550 if (DISPLAY_VER(dev_priv) < 9)
3551 intel_disable_primary_plane(new_crtc_state);
3553 hsw_set_linetime_wm(new_crtc_state);
3555 if (DISPLAY_VER(dev_priv) >= 11)
3556 icl_set_pipe_chicken(crtc);
3558 if (dev_priv->display.initial_watermarks)
3559 dev_priv->display.initial_watermarks(state, crtc);
3561 if (DISPLAY_VER(dev_priv) >= 11)
3562 icl_pipe_mbus_enable(crtc);
3564 if (new_crtc_state->bigjoiner_slave)
3565 intel_crtc_vblank_on(new_crtc_state);
3567 intel_encoders_enable(state, crtc);
3569 if (psl_clkgate_wa) {
3570 intel_wait_for_vblank(dev_priv, pipe);
3571 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
3574 /* If we change the relative order between pipe/planes enabling, we need
3575 * to change the workaround. */
3576 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
3577 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
3578 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
3579 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
3583 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
3585 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3586 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3587 enum pipe pipe = crtc->pipe;
3589 /* To avoid upsetting the power well on haswell only disable the pfit if
3590 * it's in use. The hw state code will make sure we get this right. */
3591 if (!old_crtc_state->pch_pfit.enabled)
3594 intel_de_write(dev_priv, PF_CTL(pipe), 0);
3595 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
3596 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
3599 static void ilk_crtc_disable(struct intel_atomic_state *state,
3600 struct intel_crtc *crtc)
3602 const struct intel_crtc_state *old_crtc_state =
3603 intel_atomic_get_old_crtc_state(state, crtc);
3604 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3605 enum pipe pipe = crtc->pipe;
3608 * Sometimes spurious CPU pipe underruns happen when the
3609 * pipe is already disabled, but FDI RX/TX is still enabled.
3610 * Happens at least with VGA+HDMI cloning. Suppress them.
3612 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3613 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
3615 intel_encoders_disable(state, crtc);
3617 intel_crtc_vblank_off(old_crtc_state);
3619 intel_disable_pipe(old_crtc_state);
3621 ilk_pfit_disable(old_crtc_state);
3623 if (old_crtc_state->has_pch_encoder)
3624 ilk_fdi_disable(crtc);
3626 intel_encoders_post_disable(state, crtc);
3628 if (old_crtc_state->has_pch_encoder) {
3629 ilk_disable_pch_transcoder(dev_priv, pipe);
3631 if (HAS_PCH_CPT(dev_priv)) {
3635 /* disable TRANS_DP_CTL */
3636 reg = TRANS_DP_CTL(pipe);
3637 temp = intel_de_read(dev_priv, reg);
3638 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3639 TRANS_DP_PORT_SEL_MASK);
3640 temp |= TRANS_DP_PORT_SEL_NONE;
3641 intel_de_write(dev_priv, reg, temp);
3643 /* disable DPLL_SEL */
3644 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
3645 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3646 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
3649 ilk_fdi_pll_disable(crtc);
3652 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3653 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
3656 static void hsw_crtc_disable(struct intel_atomic_state *state,
3657 struct intel_crtc *crtc)
3660 * FIXME collapse everything to one hook.
3661 * Need care with mst->ddi interactions.
3663 intel_encoders_disable(state, crtc);
3664 intel_encoders_post_disable(state, crtc);
3667 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
3669 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3670 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3672 if (!crtc_state->gmch_pfit.control)
3676 * The panel fitter should only be adjusted whilst the pipe is disabled,
3677 * according to register description and PRM.
3679 drm_WARN_ON(&dev_priv->drm,
3680 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
3681 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
3683 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
3684 crtc_state->gmch_pfit.pgm_ratios);
3685 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
3687 /* Border color in case we don't scale up to the full screen. Black by
3688 * default, change to something else for debugging. */
3689 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
3692 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
3694 if (phy == PHY_NONE)
3696 else if (IS_ALDERLAKE_S(dev_priv))
3697 return phy <= PHY_E;
3698 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
3699 return phy <= PHY_D;
3700 else if (IS_JSL_EHL(dev_priv))
3701 return phy <= PHY_C;
3702 else if (DISPLAY_VER(dev_priv) >= 11)
3703 return phy <= PHY_B;
3708 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
3710 if (IS_ALDERLAKE_P(dev_priv))
3711 return phy >= PHY_F && phy <= PHY_I;
3712 else if (IS_TIGERLAKE(dev_priv))
3713 return phy >= PHY_D && phy <= PHY_I;
3714 else if (IS_ICELAKE(dev_priv))
3715 return phy >= PHY_C && phy <= PHY_F;
3720 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
3722 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
3723 return PHY_D + port - PORT_D_XELPD;
3724 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
3725 return PHY_F + port - PORT_TC1;
3726 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
3727 return PHY_B + port - PORT_TC1;
3728 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
3729 return PHY_C + port - PORT_TC1;
3730 else if (IS_JSL_EHL(i915) && port == PORT_D)
3733 return PHY_A + port - PORT_A;
3736 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
3738 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
3739 return TC_PORT_NONE;
3741 if (DISPLAY_VER(dev_priv) >= 12)
3742 return TC_PORT_1 + port - PORT_TC1;
3744 return TC_PORT_1 + port - PORT_C;
3747 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
3751 return POWER_DOMAIN_PORT_DDI_A_LANES;
3753 return POWER_DOMAIN_PORT_DDI_B_LANES;
3755 return POWER_DOMAIN_PORT_DDI_C_LANES;
3757 return POWER_DOMAIN_PORT_DDI_D_LANES;
3759 return POWER_DOMAIN_PORT_DDI_E_LANES;
3761 return POWER_DOMAIN_PORT_DDI_F_LANES;
3763 return POWER_DOMAIN_PORT_DDI_G_LANES;
3765 return POWER_DOMAIN_PORT_DDI_H_LANES;
3767 return POWER_DOMAIN_PORT_DDI_I_LANES;
3770 return POWER_DOMAIN_PORT_OTHER;
3774 enum intel_display_power_domain
3775 intel_aux_power_domain(struct intel_digital_port *dig_port)
3777 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3778 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
3780 if (intel_phy_is_tc(dev_priv, phy) &&
3781 dig_port->tc_mode == TC_PORT_TBT_ALT) {
3782 switch (dig_port->aux_ch) {
3784 return POWER_DOMAIN_AUX_C_TBT;
3786 return POWER_DOMAIN_AUX_D_TBT;
3788 return POWER_DOMAIN_AUX_E_TBT;
3790 return POWER_DOMAIN_AUX_F_TBT;
3792 return POWER_DOMAIN_AUX_G_TBT;
3794 return POWER_DOMAIN_AUX_H_TBT;
3796 return POWER_DOMAIN_AUX_I_TBT;
3798 MISSING_CASE(dig_port->aux_ch);
3799 return POWER_DOMAIN_AUX_C_TBT;
3803 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
3807 * Converts aux_ch to power_domain without caring about TBT ports for that use
3808 * intel_aux_power_domain()
3810 enum intel_display_power_domain
3811 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
3815 return POWER_DOMAIN_AUX_A;
3817 return POWER_DOMAIN_AUX_B;
3819 return POWER_DOMAIN_AUX_C;
3821 return POWER_DOMAIN_AUX_D;
3823 return POWER_DOMAIN_AUX_E;
3825 return POWER_DOMAIN_AUX_F;
3827 return POWER_DOMAIN_AUX_G;
3829 return POWER_DOMAIN_AUX_H;
3831 return POWER_DOMAIN_AUX_I;
3833 MISSING_CASE(aux_ch);
3834 return POWER_DOMAIN_AUX_A;
3838 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
3840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3842 struct drm_encoder *encoder;
3843 enum pipe pipe = crtc->pipe;
3845 enum transcoder transcoder = crtc_state->cpu_transcoder;
3847 if (!crtc_state->hw.active)
3850 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
3851 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
3852 if (crtc_state->pch_pfit.enabled ||
3853 crtc_state->pch_pfit.force_thru)
3854 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
3856 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
3857 crtc_state->uapi.encoder_mask) {
3858 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3860 mask |= BIT_ULL(intel_encoder->power_domain);
3863 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
3864 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
3866 if (crtc_state->shared_dpll)
3867 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
3869 if (crtc_state->dsc.compression_enable)
3870 mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
3876 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
3878 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3879 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3880 enum intel_display_power_domain domain;
3881 u64 domains, new_domains, old_domains;
3883 domains = get_crtc_power_domains(crtc_state);
3885 new_domains = domains & ~crtc->enabled_power_domains.mask;
3886 old_domains = crtc->enabled_power_domains.mask & ~domains;
3888 for_each_power_domain(domain, new_domains)
3889 intel_display_power_get_in_set(dev_priv,
3890 &crtc->enabled_power_domains,
3896 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
3899 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
3900 &crtc->enabled_power_domains,
3904 static void valleyview_crtc_enable(struct intel_atomic_state *state,
3905 struct intel_crtc *crtc)
3907 const struct intel_crtc_state *new_crtc_state =
3908 intel_atomic_get_new_crtc_state(state, crtc);
3909 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3910 enum pipe pipe = crtc->pipe;
3912 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3915 if (intel_crtc_has_dp_encoder(new_crtc_state))
3916 intel_dp_set_m_n(new_crtc_state, M1_N1);
3918 intel_set_transcoder_timings(new_crtc_state);
3919 intel_set_pipe_src_size(new_crtc_state);
3921 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
3922 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
3923 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
3926 i9xx_set_pipeconf(new_crtc_state);
3928 crtc->active = true;
3930 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3932 intel_encoders_pre_pll_enable(state, crtc);
3934 if (IS_CHERRYVIEW(dev_priv)) {
3935 chv_prepare_pll(crtc, new_crtc_state);
3936 chv_enable_pll(crtc, new_crtc_state);
3938 vlv_prepare_pll(crtc, new_crtc_state);
3939 vlv_enable_pll(crtc, new_crtc_state);
3942 intel_encoders_pre_enable(state, crtc);
3944 i9xx_pfit_enable(new_crtc_state);
3946 intel_color_load_luts(new_crtc_state);
3947 intel_color_commit(new_crtc_state);
3948 /* update DSPCNTR to configure gamma for pipe bottom color */
3949 intel_disable_primary_plane(new_crtc_state);
3951 dev_priv->display.initial_watermarks(state, crtc);
3952 intel_enable_pipe(new_crtc_state);
3954 intel_crtc_vblank_on(new_crtc_state);
3956 intel_encoders_enable(state, crtc);
3959 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
3961 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3964 intel_de_write(dev_priv, FP0(crtc->pipe),
3965 crtc_state->dpll_hw_state.fp0);
3966 intel_de_write(dev_priv, FP1(crtc->pipe),
3967 crtc_state->dpll_hw_state.fp1);
3970 static void i9xx_crtc_enable(struct intel_atomic_state *state,
3971 struct intel_crtc *crtc)
3973 const struct intel_crtc_state *new_crtc_state =
3974 intel_atomic_get_new_crtc_state(state, crtc);
3975 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3976 enum pipe pipe = crtc->pipe;
3978 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3981 i9xx_set_pll_dividers(new_crtc_state);
3983 if (intel_crtc_has_dp_encoder(new_crtc_state))
3984 intel_dp_set_m_n(new_crtc_state, M1_N1);
3986 intel_set_transcoder_timings(new_crtc_state);
3987 intel_set_pipe_src_size(new_crtc_state);
3989 i9xx_set_pipeconf(new_crtc_state);
3991 crtc->active = true;
3993 if (DISPLAY_VER(dev_priv) != 2)
3994 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3996 intel_encoders_pre_enable(state, crtc);
3998 i9xx_enable_pll(crtc, new_crtc_state);
4000 i9xx_pfit_enable(new_crtc_state);
4002 intel_color_load_luts(new_crtc_state);
4003 intel_color_commit(new_crtc_state);
4004 /* update DSPCNTR to configure gamma for pipe bottom color */
4005 intel_disable_primary_plane(new_crtc_state);
4007 if (dev_priv->display.initial_watermarks)
4008 dev_priv->display.initial_watermarks(state, crtc);
4010 intel_update_watermarks(crtc);
4011 intel_enable_pipe(new_crtc_state);
4013 intel_crtc_vblank_on(new_crtc_state);
4015 intel_encoders_enable(state, crtc);
4017 /* prevents spurious underruns */
4018 if (DISPLAY_VER(dev_priv) == 2)
4019 intel_wait_for_vblank(dev_priv, pipe);
4022 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
4024 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4025 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4027 if (!old_crtc_state->gmch_pfit.control)
4030 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
4032 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
4033 intel_de_read(dev_priv, PFIT_CONTROL));
4034 intel_de_write(dev_priv, PFIT_CONTROL, 0);
4037 static void i9xx_crtc_disable(struct intel_atomic_state *state,
4038 struct intel_crtc *crtc)
4040 struct intel_crtc_state *old_crtc_state =
4041 intel_atomic_get_old_crtc_state(state, crtc);
4042 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4043 enum pipe pipe = crtc->pipe;
4046 * On gen2 planes are double buffered but the pipe isn't, so we must
4047 * wait for planes to fully turn off before disabling the pipe.
4049 if (DISPLAY_VER(dev_priv) == 2)
4050 intel_wait_for_vblank(dev_priv, pipe);
4052 intel_encoders_disable(state, crtc);
4054 intel_crtc_vblank_off(old_crtc_state);
4056 intel_disable_pipe(old_crtc_state);
4058 i9xx_pfit_disable(old_crtc_state);
4060 intel_encoders_post_disable(state, crtc);
4062 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
4063 if (IS_CHERRYVIEW(dev_priv))
4064 chv_disable_pll(dev_priv, pipe);
4065 else if (IS_VALLEYVIEW(dev_priv))
4066 vlv_disable_pll(dev_priv, pipe);
4068 i9xx_disable_pll(old_crtc_state);
4071 intel_encoders_post_pll_disable(state, crtc);
4073 if (DISPLAY_VER(dev_priv) != 2)
4074 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4076 if (!dev_priv->display.initial_watermarks)
4077 intel_update_watermarks(crtc);
4079 /* clock the pipe down to 640x480@60 to potentially save power */
4080 if (IS_I830(dev_priv))
4081 i830_enable_pipe(dev_priv, pipe);
4084 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
4085 struct drm_modeset_acquire_ctx *ctx)
4087 struct intel_encoder *encoder;
4088 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4089 struct intel_bw_state *bw_state =
4090 to_intel_bw_state(dev_priv->bw_obj.state);
4091 struct intel_cdclk_state *cdclk_state =
4092 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
4093 struct intel_dbuf_state *dbuf_state =
4094 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
4095 struct intel_crtc_state *crtc_state =
4096 to_intel_crtc_state(crtc->base.state);
4097 struct intel_plane *plane;
4098 struct drm_atomic_state *state;
4099 struct intel_crtc_state *temp_crtc_state;
4100 enum pipe pipe = crtc->pipe;
4103 if (!crtc_state->hw.active)
4106 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
4107 const struct intel_plane_state *plane_state =
4108 to_intel_plane_state(plane->base.state);
4110 if (plane_state->uapi.visible)
4111 intel_plane_disable_noatomic(crtc, plane);
4114 state = drm_atomic_state_alloc(&dev_priv->drm);
4116 drm_dbg_kms(&dev_priv->drm,
4117 "failed to disable [CRTC:%d:%s], out of memory",
4118 crtc->base.base.id, crtc->base.name);
4122 state->acquire_ctx = ctx;
4124 /* Everything's already locked, -EDEADLK can't happen. */
4125 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
4126 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
4128 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
4130 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
4132 drm_atomic_state_put(state);
4134 drm_dbg_kms(&dev_priv->drm,
4135 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
4136 crtc->base.base.id, crtc->base.name);
4138 crtc->active = false;
4139 crtc->base.enabled = false;
4141 drm_WARN_ON(&dev_priv->drm,
4142 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
4143 crtc_state->uapi.active = false;
4144 crtc_state->uapi.connector_mask = 0;
4145 crtc_state->uapi.encoder_mask = 0;
4146 intel_crtc_free_hw_state(crtc_state);
4147 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
4149 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
4150 encoder->base.crtc = NULL;
4152 intel_fbc_disable(crtc);
4153 intel_update_watermarks(crtc);
4154 intel_disable_shared_dpll(crtc_state);
4156 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
4158 dev_priv->active_pipes &= ~BIT(pipe);
4159 cdclk_state->min_cdclk[pipe] = 0;
4160 cdclk_state->min_voltage_level[pipe] = 0;
4161 cdclk_state->active_pipes &= ~BIT(pipe);
4163 dbuf_state->active_pipes &= ~BIT(pipe);
4165 bw_state->data_rate[pipe] = 0;
4166 bw_state->num_active_planes[pipe] = 0;
4170 * turn all crtc's off, but do not adjust state
4171 * This has to be paired with a call to intel_modeset_setup_hw_state.
4173 int intel_display_suspend(struct drm_device *dev)
4175 struct drm_i915_private *dev_priv = to_i915(dev);
4176 struct drm_atomic_state *state;
4179 if (!HAS_DISPLAY(dev_priv))
4182 state = drm_atomic_helper_suspend(dev);
4183 ret = PTR_ERR_OR_ZERO(state);
4185 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4188 dev_priv->modeset_restore_state = state;
4192 void intel_encoder_destroy(struct drm_encoder *encoder)
4194 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4196 drm_encoder_cleanup(encoder);
4197 kfree(intel_encoder);
4200 /* Cross check the actual hw state with our own modeset state tracking (and it's
4201 * internal consistency). */
4202 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
4203 struct drm_connector_state *conn_state)
4205 struct intel_connector *connector = to_intel_connector(conn_state->connector);
4206 struct drm_i915_private *i915 = to_i915(connector->base.dev);
4208 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
4209 connector->base.base.id, connector->base.name);
4211 if (connector->get_hw_state(connector)) {
4212 struct intel_encoder *encoder = intel_attached_encoder(connector);
4214 I915_STATE_WARN(!crtc_state,
4215 "connector enabled without attached crtc\n");
4220 I915_STATE_WARN(!crtc_state->hw.active,
4221 "connector is active, but attached crtc isn't\n");
4223 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
4226 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
4227 "atomic encoder doesn't match attached encoder\n");
4229 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
4230 "attached encoder crtc differs from connector crtc\n");
4232 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
4233 "attached crtc is active, but connector isn't\n");
4234 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
4235 "best encoder set without crtc!\n");
4239 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
4241 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4244 /* IPS only exists on ULT machines and is tied to pipe A. */
4245 if (!hsw_crtc_supports_ips(crtc))
4248 if (!dev_priv->params.enable_ips)
4251 if (crtc_state->pipe_bpp > 24)
4255 * We compare against max which means we must take
4256 * the increased cdclk requirement into account when
4257 * calculating the new cdclk.
4259 * Should measure whether using a lower cdclk w/o IPS
4261 if (IS_BROADWELL(dev_priv) &&
4262 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
4268 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
4270 struct drm_i915_private *dev_priv =
4271 to_i915(crtc_state->uapi.crtc->dev);
4272 struct intel_atomic_state *state =
4273 to_intel_atomic_state(crtc_state->uapi.state);
4275 crtc_state->ips_enabled = false;
4277 if (!hsw_crtc_state_ips_capable(crtc_state))
4281 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4282 * enabled and disabled dynamically based on package C states,
4283 * user space can't make reliable use of the CRCs, so let's just
4284 * completely disable it.
4286 if (crtc_state->crc_enabled)
4289 /* IPS should be fine as long as at least one plane is enabled. */
4290 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
4293 if (IS_BROADWELL(dev_priv)) {
4294 const struct intel_cdclk_state *cdclk_state;
4296 cdclk_state = intel_atomic_get_cdclk_state(state);
4297 if (IS_ERR(cdclk_state))
4298 return PTR_ERR(cdclk_state);
4300 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
4301 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
4305 crtc_state->ips_enabled = true;
4310 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
4312 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4314 /* GDG double wide on either pipe, otherwise pipe A only */
4315 return DISPLAY_VER(dev_priv) < 4 &&
4316 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
4319 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
4321 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
4322 struct drm_rect src;
4325 * We only use IF-ID interlacing. If we ever use
4326 * PF-ID we'll need to adjust the pixel_rate here.
4329 if (!crtc_state->pch_pfit.enabled)
4332 drm_rect_init(&src, 0, 0,
4333 crtc_state->pipe_src_w << 16,
4334 crtc_state->pipe_src_h << 16);
4336 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
4340 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
4341 const struct drm_display_mode *timings)
4343 mode->hdisplay = timings->crtc_hdisplay;
4344 mode->htotal = timings->crtc_htotal;
4345 mode->hsync_start = timings->crtc_hsync_start;
4346 mode->hsync_end = timings->crtc_hsync_end;
4348 mode->vdisplay = timings->crtc_vdisplay;
4349 mode->vtotal = timings->crtc_vtotal;
4350 mode->vsync_start = timings->crtc_vsync_start;
4351 mode->vsync_end = timings->crtc_vsync_end;
4353 mode->flags = timings->flags;
4354 mode->type = DRM_MODE_TYPE_DRIVER;
4356 mode->clock = timings->crtc_clock;
4358 drm_mode_set_name(mode);
4361 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
4363 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4365 if (HAS_GMCH(dev_priv))
4366 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
4367 crtc_state->pixel_rate =
4368 crtc_state->hw.pipe_mode.crtc_clock;
4370 crtc_state->pixel_rate =
4371 ilk_pipe_pixel_rate(crtc_state);
4374 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
4376 struct drm_display_mode *mode = &crtc_state->hw.mode;
4377 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4378 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
4380 drm_mode_copy(pipe_mode, adjusted_mode);
4382 if (crtc_state->bigjoiner) {
4384 * transcoder is programmed to the full mode,
4385 * but pipe timings are half of the transcoder mode
4387 pipe_mode->crtc_hdisplay /= 2;
4388 pipe_mode->crtc_hblank_start /= 2;
4389 pipe_mode->crtc_hblank_end /= 2;
4390 pipe_mode->crtc_hsync_start /= 2;
4391 pipe_mode->crtc_hsync_end /= 2;
4392 pipe_mode->crtc_htotal /= 2;
4393 pipe_mode->crtc_clock /= 2;
4396 if (crtc_state->splitter.enable) {
4397 int n = crtc_state->splitter.link_count;
4398 int overlap = crtc_state->splitter.pixel_overlap;
4401 * eDP MSO uses segment timings from EDID for transcoder
4402 * timings, but full mode for everything else.
4404 * h_full = (h_segment - pixel_overlap) * link_count
4406 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4407 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4408 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4409 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4410 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4411 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4412 pipe_mode->crtc_clock *= n;
4414 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4415 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
4417 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4418 intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
4421 intel_crtc_compute_pixel_rate(crtc_state);
4423 drm_mode_copy(mode, adjusted_mode);
4424 mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner;
4425 mode->vdisplay = crtc_state->pipe_src_h;
4428 static void intel_encoder_get_config(struct intel_encoder *encoder,
4429 struct intel_crtc_state *crtc_state)
4431 encoder->get_config(encoder, crtc_state);
4433 intel_crtc_readout_derived_state(crtc_state);
4436 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4437 struct intel_crtc_state *pipe_config)
4439 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4440 struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
4441 int clock_limit = dev_priv->max_dotclk_freq;
4443 drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
4445 /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
4446 if (pipe_config->bigjoiner) {
4447 pipe_mode->crtc_clock /= 2;
4448 pipe_mode->crtc_hdisplay /= 2;
4449 pipe_mode->crtc_hblank_start /= 2;
4450 pipe_mode->crtc_hblank_end /= 2;
4451 pipe_mode->crtc_hsync_start /= 2;
4452 pipe_mode->crtc_hsync_end /= 2;
4453 pipe_mode->crtc_htotal /= 2;
4454 pipe_config->pipe_src_w /= 2;
4457 if (pipe_config->splitter.enable) {
4458 int n = pipe_config->splitter.link_count;
4459 int overlap = pipe_config->splitter.pixel_overlap;
4461 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4462 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4463 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4464 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4465 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4466 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4467 pipe_mode->crtc_clock *= n;
4470 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4472 if (DISPLAY_VER(dev_priv) < 4) {
4473 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
4476 * Enable double wide mode when the dot clock
4477 * is > 90% of the (display) core speed.
4479 if (intel_crtc_supports_double_wide(crtc) &&
4480 pipe_mode->crtc_clock > clock_limit) {
4481 clock_limit = dev_priv->max_dotclk_freq;
4482 pipe_config->double_wide = true;
4486 if (pipe_mode->crtc_clock > clock_limit) {
4487 drm_dbg_kms(&dev_priv->drm,
4488 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
4489 pipe_mode->crtc_clock, clock_limit,
4490 yesno(pipe_config->double_wide));
4495 * Pipe horizontal size must be even in:
4497 * - LVDS dual channel mode
4498 * - Double wide pipe
4500 if (pipe_config->pipe_src_w & 1) {
4501 if (pipe_config->double_wide) {
4502 drm_dbg_kms(&dev_priv->drm,
4503 "Odd pipe source width not supported with double wide pipe\n");
4507 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
4508 intel_is_dual_link_lvds(dev_priv)) {
4509 drm_dbg_kms(&dev_priv->drm,
4510 "Odd pipe source width not supported with dual link LVDS\n");
4515 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4516 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4518 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
4519 pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
4522 intel_crtc_compute_pixel_rate(pipe_config);
4524 if (pipe_config->has_pch_encoder)
4525 return ilk_fdi_compute_config(crtc, pipe_config);
4531 intel_reduce_m_n_ratio(u32 *num, u32 *den)
4533 while (*num > DATA_LINK_M_N_MASK ||
4534 *den > DATA_LINK_M_N_MASK) {
4540 static void compute_m_n(unsigned int m, unsigned int n,
4541 u32 *ret_m, u32 *ret_n,
4545 * Several DP dongles in particular seem to be fussy about
4546 * too large link M/N values. Give N value as 0x8000 that
4547 * should be acceptable by specific devices. 0x8000 is the
4548 * specified fixed N value for asynchronous clock mode,
4549 * which the devices expect also in synchronous clock mode.
4552 *ret_n = DP_LINK_CONSTANT_N_VALUE;
4554 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4556 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
4557 intel_reduce_m_n_ratio(ret_m, ret_n);
4561 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
4562 int pixel_clock, int link_clock,
4563 struct intel_link_m_n *m_n,
4564 bool constant_n, bool fec_enable)
4566 u32 data_clock = bits_per_pixel * pixel_clock;
4569 data_clock = intel_dp_mode_to_fec_clock(data_clock);
4572 compute_m_n(data_clock,
4573 link_clock * nlanes * 8,
4574 &m_n->gmch_m, &m_n->gmch_n,
4577 compute_m_n(pixel_clock, link_clock,
4578 &m_n->link_m, &m_n->link_n,
4582 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
4585 * There may be no VBT; and if the BIOS enabled SSC we can
4586 * just keep using it to avoid unnecessary flicker. Whereas if the
4587 * BIOS isn't using it, don't assume it will work even if the VBT
4588 * indicates as much.
4590 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
4591 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
4595 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
4596 drm_dbg_kms(&dev_priv->drm,
4597 "SSC %s by BIOS, overriding VBT which says %s\n",
4598 enableddisabled(bios_lvds_use_ssc),
4599 enableddisabled(dev_priv->vbt.lvds_use_ssc));
4600 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
4605 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
4606 const struct intel_link_m_n *m_n)
4608 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4609 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4610 enum pipe pipe = crtc->pipe;
4612 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
4613 TU_SIZE(m_n->tu) | m_n->gmch_m);
4614 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4615 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4616 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4619 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
4620 enum transcoder transcoder)
4622 if (IS_HASWELL(dev_priv))
4623 return transcoder == TRANSCODER_EDP;
4626 * Strictly speaking some registers are available before
4627 * gen7, but we only support DRRS on gen7+
4629 return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
4632 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
4633 const struct intel_link_m_n *m_n,
4634 const struct intel_link_m_n *m2_n2)
4636 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4638 enum pipe pipe = crtc->pipe;
4639 enum transcoder transcoder = crtc_state->cpu_transcoder;
4641 if (DISPLAY_VER(dev_priv) >= 5) {
4642 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
4643 TU_SIZE(m_n->tu) | m_n->gmch_m);
4644 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
4646 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
4648 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
4651 * M2_N2 registers are set only if DRRS is supported
4652 * (to make sure the registers are not unnecessarily accessed).
4654 if (m2_n2 && crtc_state->has_drrs &&
4655 transcoder_has_m2_n2(dev_priv, transcoder)) {
4656 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
4657 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
4658 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
4660 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
4662 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
4666 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
4667 TU_SIZE(m_n->tu) | m_n->gmch_m);
4668 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4669 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
4670 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
4674 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
4676 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
4677 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4680 dp_m_n = &crtc_state->dp_m_n;
4681 dp_m2_n2 = &crtc_state->dp_m2_n2;
4682 } else if (m_n == M2_N2) {
4685 * M2_N2 registers are not supported. Hence m2_n2 divider value
4686 * needs to be programmed into M1_N1.
4688 dp_m_n = &crtc_state->dp_m2_n2;
4690 drm_err(&i915->drm, "Unsupported divider value\n");
4694 if (crtc_state->has_pch_encoder)
4695 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
4697 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
4700 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
4702 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4703 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4704 enum pipe pipe = crtc->pipe;
4705 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4706 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
4707 u32 crtc_vtotal, crtc_vblank_end;
4710 /* We need to be careful not to changed the adjusted mode, for otherwise
4711 * the hw state checker will get angry at the mismatch. */
4712 crtc_vtotal = adjusted_mode->crtc_vtotal;
4713 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4715 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4716 /* the chip adds 2 halflines automatically */
4718 crtc_vblank_end -= 1;
4720 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
4721 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
4723 vsyncshift = adjusted_mode->crtc_hsync_start -
4724 adjusted_mode->crtc_htotal / 2;
4726 vsyncshift += adjusted_mode->crtc_htotal;
4729 if (DISPLAY_VER(dev_priv) > 3)
4730 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
4733 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
4734 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
4735 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
4736 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
4737 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
4738 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
4740 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
4741 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
4742 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
4743 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
4744 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
4745 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
4747 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4748 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4749 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4751 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
4752 (pipe == PIPE_B || pipe == PIPE_C))
4753 intel_de_write(dev_priv, VTOTAL(pipe),
4754 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
4758 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
4760 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4761 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4762 enum pipe pipe = crtc->pipe;
4764 /* pipesrc controls the size that is scaled from, which should
4765 * always be the user's requested size.
4767 intel_de_write(dev_priv, PIPESRC(pipe),
4768 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
4771 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
4773 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4774 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4776 if (DISPLAY_VER(dev_priv) == 2)
4779 if (DISPLAY_VER(dev_priv) >= 9 ||
4780 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
4781 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
4783 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
4786 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
4787 struct intel_crtc_state *pipe_config)
4789 struct drm_device *dev = crtc->base.dev;
4790 struct drm_i915_private *dev_priv = to_i915(dev);
4791 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4794 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
4795 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4796 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4798 if (!transcoder_is_dsi(cpu_transcoder)) {
4799 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
4800 pipe_config->hw.adjusted_mode.crtc_hblank_start =
4802 pipe_config->hw.adjusted_mode.crtc_hblank_end =
4803 ((tmp >> 16) & 0xffff) + 1;
4805 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
4806 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4807 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4809 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
4810 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4811 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4813 if (!transcoder_is_dsi(cpu_transcoder)) {
4814 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
4815 pipe_config->hw.adjusted_mode.crtc_vblank_start =
4817 pipe_config->hw.adjusted_mode.crtc_vblank_end =
4818 ((tmp >> 16) & 0xffff) + 1;
4820 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
4821 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4822 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4824 if (intel_pipe_is_interlaced(pipe_config)) {
4825 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4826 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
4827 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
4831 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
4832 struct intel_crtc_state *pipe_config)
4834 struct drm_device *dev = crtc->base.dev;
4835 struct drm_i915_private *dev_priv = to_i915(dev);
4838 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
4839 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4840 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4843 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
4845 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4846 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4851 /* we keep both pipes enabled on 830 */
4852 if (IS_I830(dev_priv))
4853 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
4855 if (crtc_state->double_wide)
4856 pipeconf |= PIPECONF_DOUBLE_WIDE;
4858 /* only g4x and later have fancy bpc/dither controls */
4859 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4860 IS_CHERRYVIEW(dev_priv)) {
4861 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4862 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
4863 pipeconf |= PIPECONF_DITHER_EN |
4864 PIPECONF_DITHER_TYPE_SP;
4866 switch (crtc_state->pipe_bpp) {
4868 pipeconf |= PIPECONF_6BPC;
4871 pipeconf |= PIPECONF_8BPC;
4874 pipeconf |= PIPECONF_10BPC;
4877 /* Case prevented by intel_choose_pipe_bpp_dither. */
4882 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
4883 if (DISPLAY_VER(dev_priv) < 4 ||
4884 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
4885 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4887 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
4889 pipeconf |= PIPECONF_PROGRESSIVE;
4892 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
4893 crtc_state->limited_color_range)
4894 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4896 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
4898 pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
4900 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
4901 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
4904 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
4906 if (IS_I830(dev_priv))
4909 return DISPLAY_VER(dev_priv) >= 4 ||
4910 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
4913 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
4915 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4916 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4919 if (!i9xx_has_pfit(dev_priv))
4922 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
4923 if (!(tmp & PFIT_ENABLE))
4926 /* Check whether the pfit is attached to our pipe. */
4927 if (DISPLAY_VER(dev_priv) < 4) {
4928 if (crtc->pipe != PIPE_B)
4931 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4935 crtc_state->gmch_pfit.control = tmp;
4936 crtc_state->gmch_pfit.pgm_ratios =
4937 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
4940 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
4941 struct intel_crtc_state *pipe_config)
4943 struct drm_device *dev = crtc->base.dev;
4944 struct drm_i915_private *dev_priv = to_i915(dev);
4945 enum pipe pipe = crtc->pipe;
4948 int refclk = 100000;
4950 /* In case of DSI, DPLL will not be used */
4951 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
4954 vlv_dpio_get(dev_priv);
4955 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
4956 vlv_dpio_put(dev_priv);
4958 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
4959 clock.m2 = mdiv & DPIO_M2DIV_MASK;
4960 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
4961 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
4962 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
4964 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
4967 static void chv_crtc_clock_get(struct intel_crtc *crtc,
4968 struct intel_crtc_state *pipe_config)
4970 struct drm_device *dev = crtc->base.dev;
4971 struct drm_i915_private *dev_priv = to_i915(dev);
4972 enum pipe pipe = crtc->pipe;
4973 enum dpio_channel port = vlv_pipe_to_channel(pipe);
4975 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
4976 int refclk = 100000;
4978 /* In case of DSI, DPLL will not be used */
4979 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
4982 vlv_dpio_get(dev_priv);
4983 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
4984 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
4985 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
4986 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
4987 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
4988 vlv_dpio_put(dev_priv);
4990 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
4991 clock.m2 = (pll_dw0 & 0xff) << 22;
4992 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
4993 clock.m2 |= pll_dw2 & 0x3fffff;
4994 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
4995 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
4996 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
4998 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
5001 static enum intel_output_format
5002 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
5004 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5007 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
5009 if (tmp & PIPEMISC_YUV420_ENABLE) {
5010 /* We support 4:2:0 in full blend mode only */
5011 drm_WARN_ON(&dev_priv->drm,
5012 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
5014 return INTEL_OUTPUT_FORMAT_YCBCR420;
5015 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
5016 return INTEL_OUTPUT_FORMAT_YCBCR444;
5018 return INTEL_OUTPUT_FORMAT_RGB;
5022 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
5024 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5025 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
5026 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5027 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
5030 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
5032 if (tmp & DISPPLANE_GAMMA_ENABLE)
5033 crtc_state->gamma_enable = true;
5035 if (!HAS_GMCH(dev_priv) &&
5036 tmp & DISPPLANE_PIPE_CSC_ENABLE)
5037 crtc_state->csc_enable = true;
5040 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5041 struct intel_crtc_state *pipe_config)
5043 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5044 enum intel_display_power_domain power_domain;
5045 intel_wakeref_t wakeref;
5049 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
5050 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
5054 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
5055 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5056 pipe_config->shared_dpll = NULL;
5060 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
5061 if (!(tmp & PIPECONF_ENABLE))
5064 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5065 IS_CHERRYVIEW(dev_priv)) {
5066 switch (tmp & PIPECONF_BPC_MASK) {
5068 pipe_config->pipe_bpp = 18;
5071 pipe_config->pipe_bpp = 24;
5073 case PIPECONF_10BPC:
5074 pipe_config->pipe_bpp = 30;
5081 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5082 (tmp & PIPECONF_COLOR_RANGE_SELECT))
5083 pipe_config->limited_color_range = true;
5085 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
5086 PIPECONF_GAMMA_MODE_SHIFT;
5088 if (IS_CHERRYVIEW(dev_priv))
5089 pipe_config->cgm_mode = intel_de_read(dev_priv,
5090 CGM_PIPE_MODE(crtc->pipe));
5092 i9xx_get_pipe_color_config(pipe_config);
5093 intel_color_get_config(pipe_config);
5095 if (DISPLAY_VER(dev_priv) < 4)
5096 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5098 intel_get_transcoder_timings(crtc, pipe_config);
5099 intel_get_pipe_src_size(crtc, pipe_config);
5101 i9xx_get_pfit_config(pipe_config);
5103 if (DISPLAY_VER(dev_priv) >= 4) {
5104 /* No way to read it out on pipes B and C */
5105 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
5106 tmp = dev_priv->chv_dpll_md[crtc->pipe];
5108 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
5109 pipe_config->pixel_multiplier =
5110 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5111 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5112 pipe_config->dpll_hw_state.dpll_md = tmp;
5113 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
5114 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
5115 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
5116 pipe_config->pixel_multiplier =
5117 ((tmp & SDVO_MULTIPLIER_MASK)
5118 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5120 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5121 * port and will be fixed up in the encoder->get_config
5123 pipe_config->pixel_multiplier = 1;
5125 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
5127 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
5128 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
5130 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
5133 /* Mask out read-only status bits. */
5134 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5135 DPLL_PORTC_READY_MASK |
5136 DPLL_PORTB_READY_MASK);
5139 if (IS_CHERRYVIEW(dev_priv))
5140 chv_crtc_clock_get(crtc, pipe_config);
5141 else if (IS_VALLEYVIEW(dev_priv))
5142 vlv_crtc_clock_get(crtc, pipe_config);
5144 i9xx_crtc_clock_get(crtc, pipe_config);
5147 * Normally the dotclock is filled in by the encoder .get_config()
5148 * but in case the pipe is enabled w/o any ports we need a sane
5151 pipe_config->hw.adjusted_mode.crtc_clock =
5152 pipe_config->port_clock / pipe_config->pixel_multiplier;
5157 intel_display_power_put(dev_priv, power_domain, wakeref);
5162 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
5164 struct intel_encoder *encoder;
5167 bool has_lvds = false;
5168 bool has_cpu_edp = false;
5169 bool has_panel = false;
5170 bool has_ck505 = false;
5171 bool can_ssc = false;
5172 bool using_ssc_source = false;
5174 /* We need to take the global config into account */
5175 for_each_intel_encoder(&dev_priv->drm, encoder) {
5176 switch (encoder->type) {
5177 case INTEL_OUTPUT_LVDS:
5181 case INTEL_OUTPUT_EDP:
5183 if (encoder->port == PORT_A)
5191 if (HAS_PCH_IBX(dev_priv)) {
5192 has_ck505 = dev_priv->vbt.display_clock_mode;
5193 can_ssc = has_ck505;
5199 /* Check if any DPLLs are using the SSC source */
5200 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
5201 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
5203 if (!(temp & DPLL_VCO_ENABLE))
5206 if ((temp & PLL_REF_INPUT_MASK) ==
5207 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5208 using_ssc_source = true;
5213 drm_dbg_kms(&dev_priv->drm,
5214 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
5215 has_panel, has_lvds, has_ck505, using_ssc_source);
5217 /* Ironlake: try to setup display ref clock before DPLL
5218 * enabling. This is only under driver's control after
5219 * PCH B stepping, previous chipset stepping should be
5220 * ignoring this setting.
5222 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
5224 /* As we must carefully and slowly disable/enable each source in turn,
5225 * compute the final state we want first and check if we need to
5226 * make any changes at all.
5229 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5231 final |= DREF_NONSPREAD_CK505_ENABLE;
5233 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5235 final &= ~DREF_SSC_SOURCE_MASK;
5236 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5237 final &= ~DREF_SSC1_ENABLE;
5240 final |= DREF_SSC_SOURCE_ENABLE;
5242 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5243 final |= DREF_SSC1_ENABLE;
5246 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5247 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5249 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5251 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5252 } else if (using_ssc_source) {
5253 final |= DREF_SSC_SOURCE_ENABLE;
5254 final |= DREF_SSC1_ENABLE;
5260 /* Always enable nonspread source */
5261 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5264 val |= DREF_NONSPREAD_CK505_ENABLE;
5266 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5269 val &= ~DREF_SSC_SOURCE_MASK;
5270 val |= DREF_SSC_SOURCE_ENABLE;
5272 /* SSC must be turned on before enabling the CPU output */
5273 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5274 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
5275 val |= DREF_SSC1_ENABLE;
5277 val &= ~DREF_SSC1_ENABLE;
5279 /* Get SSC going before enabling the outputs */
5280 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5281 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5284 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5286 /* Enable CPU source on CPU attached eDP */
5288 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5289 drm_dbg_kms(&dev_priv->drm,
5290 "Using SSC on eDP\n");
5291 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5293 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5295 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5297 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5298 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5301 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
5303 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5305 /* Turn off CPU output */
5306 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5308 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5309 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5312 if (!using_ssc_source) {
5313 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
5315 /* Turn off the SSC source */
5316 val &= ~DREF_SSC_SOURCE_MASK;
5317 val |= DREF_SSC_SOURCE_DISABLE;
5320 val &= ~DREF_SSC1_ENABLE;
5322 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5323 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5328 BUG_ON(val != final);
5331 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5335 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5336 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5337 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5339 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5340 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5341 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
5343 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5344 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5345 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5347 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5348 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5349 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
5352 /* WaMPhyProgramming:hsw */
5353 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5357 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5358 tmp &= ~(0xFF << 24);
5359 tmp |= (0x12 << 24);
5360 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5362 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5364 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5366 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5368 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5370 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5371 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5372 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5374 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5375 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5376 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5378 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5381 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5383 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5386 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5388 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5391 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5393 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5396 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5398 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5399 tmp &= ~(0xFF << 16);
5400 tmp |= (0x1C << 16);
5401 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5403 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5404 tmp &= ~(0xFF << 16);
5405 tmp |= (0x1C << 16);
5406 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5408 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5410 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5412 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5414 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5416 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5417 tmp &= ~(0xF << 28);
5419 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5421 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5422 tmp &= ~(0xF << 28);
5424 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5427 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5428 * Programming" based on the parameters passed:
5429 * - Sequence to enable CLKOUT_DP
5430 * - Sequence to enable CLKOUT_DP without spread
5431 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5433 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
5434 bool with_spread, bool with_fdi)
5438 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
5439 "FDI requires downspread\n"))
5441 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
5442 with_fdi, "LP PCH doesn't have FDI\n"))
5445 mutex_lock(&dev_priv->sb_lock);
5447 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5448 tmp &= ~SBI_SSCCTL_DISABLE;
5449 tmp |= SBI_SSCCTL_PATHALT;
5450 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5455 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5456 tmp &= ~SBI_SSCCTL_PATHALT;
5457 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5460 lpt_reset_fdi_mphy(dev_priv);
5461 lpt_program_fdi_mphy(dev_priv);
5465 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5466 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5467 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5468 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5470 mutex_unlock(&dev_priv->sb_lock);
5473 /* Sequence to disable CLKOUT_DP */
5474 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
5478 mutex_lock(&dev_priv->sb_lock);
5480 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5481 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5482 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5483 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5485 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5486 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5487 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5488 tmp |= SBI_SSCCTL_PATHALT;
5489 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5492 tmp |= SBI_SSCCTL_DISABLE;
5493 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5496 mutex_unlock(&dev_priv->sb_lock);
5499 #define BEND_IDX(steps) ((50 + (steps)) / 5)
5501 static const u16 sscdivintphase[] = {
5502 [BEND_IDX( 50)] = 0x3B23,
5503 [BEND_IDX( 45)] = 0x3B23,
5504 [BEND_IDX( 40)] = 0x3C23,
5505 [BEND_IDX( 35)] = 0x3C23,
5506 [BEND_IDX( 30)] = 0x3D23,
5507 [BEND_IDX( 25)] = 0x3D23,
5508 [BEND_IDX( 20)] = 0x3E23,
5509 [BEND_IDX( 15)] = 0x3E23,
5510 [BEND_IDX( 10)] = 0x3F23,
5511 [BEND_IDX( 5)] = 0x3F23,
5512 [BEND_IDX( 0)] = 0x0025,
5513 [BEND_IDX( -5)] = 0x0025,
5514 [BEND_IDX(-10)] = 0x0125,
5515 [BEND_IDX(-15)] = 0x0125,
5516 [BEND_IDX(-20)] = 0x0225,
5517 [BEND_IDX(-25)] = 0x0225,
5518 [BEND_IDX(-30)] = 0x0325,
5519 [BEND_IDX(-35)] = 0x0325,
5520 [BEND_IDX(-40)] = 0x0425,
5521 [BEND_IDX(-45)] = 0x0425,
5522 [BEND_IDX(-50)] = 0x0525,
5527 * steps -50 to 50 inclusive, in steps of 5
5528 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
5529 * change in clock period = -(steps / 10) * 5.787 ps
5531 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
5534 int idx = BEND_IDX(steps);
5536 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
5539 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
5542 mutex_lock(&dev_priv->sb_lock);
5544 if (steps % 10 != 0)
5548 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
5550 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
5552 tmp |= sscdivintphase[idx];
5553 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
5555 mutex_unlock(&dev_priv->sb_lock);
5560 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
5562 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
5563 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
5565 if ((ctl & SPLL_PLL_ENABLE) == 0)
5568 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
5569 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
5572 if (IS_BROADWELL(dev_priv) &&
5573 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
5579 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
5580 enum intel_dpll_id id)
5582 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
5583 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
5585 if ((ctl & WRPLL_PLL_ENABLE) == 0)
5588 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
5591 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
5592 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
5593 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
5599 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
5601 struct intel_encoder *encoder;
5602 bool has_fdi = false;
5604 for_each_intel_encoder(&dev_priv->drm, encoder) {
5605 switch (encoder->type) {
5606 case INTEL_OUTPUT_ANALOG:
5615 * The BIOS may have decided to use the PCH SSC
5616 * reference so we must not disable it until the
5617 * relevant PLLs have stopped relying on it. We'll
5618 * just leave the PCH SSC reference enabled in case
5619 * any active PLL is using it. It will get disabled
5620 * after runtime suspend if we don't have FDI.
5622 * TODO: Move the whole reference clock handling
5623 * to the modeset sequence proper so that we can
5624 * actually enable/disable/reconfigure these things
5625 * safely. To do that we need to introduce a real
5626 * clock hierarchy. That would also allow us to do
5627 * clock bending finally.
5629 dev_priv->pch_ssc_use = 0;
5631 if (spll_uses_pch_ssc(dev_priv)) {
5632 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
5633 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
5636 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
5637 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
5638 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
5641 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
5642 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
5643 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
5646 if (dev_priv->pch_ssc_use)
5650 lpt_bend_clkout_dp(dev_priv, 0);
5651 lpt_enable_clkout_dp(dev_priv, true, true);
5653 lpt_disable_clkout_dp(dev_priv);
5658 * Initialize reference clocks when the driver loads
5660 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
5662 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
5663 ilk_init_pch_refclk(dev_priv);
5664 else if (HAS_PCH_LPT(dev_priv))
5665 lpt_init_pch_refclk(dev_priv);
5668 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
5670 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5671 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5672 enum pipe pipe = crtc->pipe;
5677 switch (crtc_state->pipe_bpp) {
5679 val |= PIPECONF_6BPC;
5682 val |= PIPECONF_8BPC;
5685 val |= PIPECONF_10BPC;
5688 val |= PIPECONF_12BPC;
5691 /* Case prevented by intel_choose_pipe_bpp_dither. */
5695 if (crtc_state->dither)
5696 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5698 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5699 val |= PIPECONF_INTERLACED_ILK;
5701 val |= PIPECONF_PROGRESSIVE;
5704 * This would end up with an odd purple hue over
5705 * the entire display. Make sure we don't do it.
5707 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
5708 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
5710 if (crtc_state->limited_color_range &&
5711 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
5712 val |= PIPECONF_COLOR_RANGE_SELECT;
5714 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
5715 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
5717 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
5719 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
5721 intel_de_write(dev_priv, PIPECONF(pipe), val);
5722 intel_de_posting_read(dev_priv, PIPECONF(pipe));
5725 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
5727 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5728 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5729 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5732 if (IS_HASWELL(dev_priv) && crtc_state->dither)
5733 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5735 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5736 val |= PIPECONF_INTERLACED_ILK;
5738 val |= PIPECONF_PROGRESSIVE;
5740 if (IS_HASWELL(dev_priv) &&
5741 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
5742 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
5744 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
5745 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
5748 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
5750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5751 const struct intel_crtc_scaler_state *scaler_state =
5752 &crtc_state->scaler_state;
5754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5758 switch (crtc_state->pipe_bpp) {
5760 val |= PIPEMISC_DITHER_6_BPC;
5763 val |= PIPEMISC_DITHER_8_BPC;
5766 val |= PIPEMISC_DITHER_10_BPC;
5769 val |= PIPEMISC_DITHER_12_BPC;
5772 MISSING_CASE(crtc_state->pipe_bpp);
5776 if (crtc_state->dither)
5777 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
5779 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
5780 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
5781 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
5783 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5784 val |= PIPEMISC_YUV420_ENABLE |
5785 PIPEMISC_YUV420_MODE_FULL_BLEND;
5787 if (DISPLAY_VER(dev_priv) >= 11 &&
5788 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
5789 BIT(PLANE_CURSOR))) == 0)
5790 val |= PIPEMISC_HDR_MODE_PRECISION;
5792 if (DISPLAY_VER(dev_priv) >= 12)
5793 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
5795 if (IS_ALDERLAKE_P(dev_priv)) {
5796 bool scaler_in_use = false;
5798 for (i = 0; i < crtc->num_scalers; i++) {
5799 if (!scaler_state->scalers[i].in_use)
5802 scaler_in_use = true;
5806 intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
5807 PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
5808 scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
5809 PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
5812 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
5815 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
5817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5820 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
5822 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
5823 case PIPEMISC_DITHER_6_BPC:
5825 case PIPEMISC_DITHER_8_BPC:
5827 case PIPEMISC_DITHER_10_BPC:
5829 case PIPEMISC_DITHER_12_BPC:
5837 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
5840 * Account for spread spectrum to avoid
5841 * oversubscribing the link. Max center spread
5842 * is 2.5%; use 5% for safety's sake.
5844 u32 bps = target_clock * bpp * 21 / 20;
5845 return DIV_ROUND_UP(bps, link_bw * 8);
5848 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5849 struct intel_link_m_n *m_n)
5851 struct drm_device *dev = crtc->base.dev;
5852 struct drm_i915_private *dev_priv = to_i915(dev);
5853 enum pipe pipe = crtc->pipe;
5855 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
5856 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
5857 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
5859 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
5860 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
5861 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5864 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5865 enum transcoder transcoder,
5866 struct intel_link_m_n *m_n,
5867 struct intel_link_m_n *m2_n2)
5869 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5870 enum pipe pipe = crtc->pipe;
5872 if (DISPLAY_VER(dev_priv) >= 5) {
5873 m_n->link_m = intel_de_read(dev_priv,
5874 PIPE_LINK_M1(transcoder));
5875 m_n->link_n = intel_de_read(dev_priv,
5876 PIPE_LINK_N1(transcoder));
5877 m_n->gmch_m = intel_de_read(dev_priv,
5878 PIPE_DATA_M1(transcoder))
5880 m_n->gmch_n = intel_de_read(dev_priv,
5881 PIPE_DATA_N1(transcoder));
5882 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
5883 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5885 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
5886 m2_n2->link_m = intel_de_read(dev_priv,
5887 PIPE_LINK_M2(transcoder));
5888 m2_n2->link_n = intel_de_read(dev_priv,
5889 PIPE_LINK_N2(transcoder));
5890 m2_n2->gmch_m = intel_de_read(dev_priv,
5891 PIPE_DATA_M2(transcoder))
5893 m2_n2->gmch_n = intel_de_read(dev_priv,
5894 PIPE_DATA_N2(transcoder));
5895 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
5896 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5899 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
5900 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
5901 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
5903 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
5904 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
5905 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5909 void intel_dp_get_m_n(struct intel_crtc *crtc,
5910 struct intel_crtc_state *pipe_config)
5912 if (pipe_config->has_pch_encoder)
5913 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5915 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5916 &pipe_config->dp_m_n,
5917 &pipe_config->dp_m2_n2);
5920 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
5921 struct intel_crtc_state *pipe_config)
5923 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5924 &pipe_config->fdi_m_n, NULL);
5927 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
5930 drm_rect_init(&crtc_state->pch_pfit.dst,
5931 pos >> 16, pos & 0xffff,
5932 size >> 16, size & 0xffff);
5935 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
5937 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5938 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5939 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
5943 /* find scaler attached to this pipe */
5944 for (i = 0; i < crtc->num_scalers; i++) {
5947 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
5948 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
5952 crtc_state->pch_pfit.enabled = true;
5954 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
5955 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
5957 ilk_get_pfit_pos_size(crtc_state, pos, size);
5959 scaler_state->scalers[i].in_use = true;
5963 scaler_state->scaler_id = id;
5965 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
5967 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
5970 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
5972 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5973 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5976 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
5977 if ((ctl & PF_ENABLE) == 0)
5980 crtc_state->pch_pfit.enabled = true;
5982 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
5983 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
5985 ilk_get_pfit_pos_size(crtc_state, pos, size);
5988 * We currently do not free assignements of panel fitters on
5989 * ivb/hsw (since we don't use the higher upscaling modes which
5990 * differentiates them) so just WARN about this case for now.
5992 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
5993 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
5996 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
5997 struct intel_crtc_state *pipe_config)
5999 struct drm_device *dev = crtc->base.dev;
6000 struct drm_i915_private *dev_priv = to_i915(dev);
6001 enum intel_display_power_domain power_domain;
6002 intel_wakeref_t wakeref;
6006 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
6007 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
6011 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6012 pipe_config->shared_dpll = NULL;
6015 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
6016 if (!(tmp & PIPECONF_ENABLE))
6019 switch (tmp & PIPECONF_BPC_MASK) {
6021 pipe_config->pipe_bpp = 18;
6024 pipe_config->pipe_bpp = 24;
6026 case PIPECONF_10BPC:
6027 pipe_config->pipe_bpp = 30;
6029 case PIPECONF_12BPC:
6030 pipe_config->pipe_bpp = 36;
6036 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
6037 pipe_config->limited_color_range = true;
6039 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
6040 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
6041 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
6042 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
6045 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
6049 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
6050 PIPECONF_GAMMA_MODE_SHIFT;
6052 pipe_config->csc_mode = intel_de_read(dev_priv,
6053 PIPE_CSC_MODE(crtc->pipe));
6055 i9xx_get_pipe_color_config(pipe_config);
6056 intel_color_get_config(pipe_config);
6058 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6059 struct intel_shared_dpll *pll;
6060 enum intel_dpll_id pll_id;
6063 pipe_config->has_pch_encoder = true;
6065 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
6066 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6067 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6069 ilk_get_fdi_m_n_config(crtc, pipe_config);
6071 if (HAS_PCH_IBX(dev_priv)) {
6073 * The pipe->pch transcoder and pch transcoder->pll
6076 pll_id = (enum intel_dpll_id) crtc->pipe;
6078 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
6079 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6080 pll_id = DPLL_ID_PCH_PLL_B;
6082 pll_id= DPLL_ID_PCH_PLL_A;
6085 pipe_config->shared_dpll =
6086 intel_get_shared_dpll_by_id(dev_priv, pll_id);
6087 pll = pipe_config->shared_dpll;
6089 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
6090 &pipe_config->dpll_hw_state);
6091 drm_WARN_ON(dev, !pll_active);
6093 tmp = pipe_config->dpll_hw_state.dpll;
6094 pipe_config->pixel_multiplier =
6095 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6096 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6098 ilk_pch_clock_get(crtc, pipe_config);
6100 pipe_config->pixel_multiplier = 1;
6103 intel_get_transcoder_timings(crtc, pipe_config);
6104 intel_get_pipe_src_size(crtc, pipe_config);
6106 ilk_get_pfit_config(pipe_config);
6111 intel_display_power_put(dev_priv, power_domain, wakeref);
6116 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
6117 struct intel_crtc_state *pipe_config,
6118 struct intel_display_power_domain_set *power_domain_set)
6120 struct drm_device *dev = crtc->base.dev;
6121 struct drm_i915_private *dev_priv = to_i915(dev);
6122 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
6123 unsigned long enabled_panel_transcoders = 0;
6124 enum transcoder panel_transcoder;
6127 if (DISPLAY_VER(dev_priv) >= 11)
6128 panel_transcoder_mask |=
6129 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
6132 * The pipe->transcoder mapping is fixed with the exception of the eDP
6133 * and DSI transcoders handled below.
6135 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6138 * XXX: Do intel_display_power_get_if_enabled before reading this (for
6139 * consistency and less surprising code; it's in always on power).
6141 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
6142 panel_transcoder_mask) {
6143 bool force_thru = false;
6144 enum pipe trans_pipe;
6146 tmp = intel_de_read(dev_priv,
6147 TRANS_DDI_FUNC_CTL(panel_transcoder));
6148 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6152 * Log all enabled ones, only use the first one.
6154 * FIXME: This won't work for two separate DSI displays.
6156 enabled_panel_transcoders |= BIT(panel_transcoder);
6157 if (enabled_panel_transcoders != BIT(panel_transcoder))
6160 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6163 "unknown pipe linked to transcoder %s\n",
6164 transcoder_name(panel_transcoder));
6166 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6169 case TRANS_DDI_EDP_INPUT_A_ON:
6170 trans_pipe = PIPE_A;
6172 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6173 trans_pipe = PIPE_B;
6175 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6176 trans_pipe = PIPE_C;
6178 case TRANS_DDI_EDP_INPUT_D_ONOFF:
6179 trans_pipe = PIPE_D;
6183 if (trans_pipe == crtc->pipe) {
6184 pipe_config->cpu_transcoder = panel_transcoder;
6185 pipe_config->pch_pfit.force_thru = force_thru;
6190 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
6192 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
6193 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
6195 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6196 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6199 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
6201 return tmp & PIPECONF_ENABLE;
6204 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
6205 struct intel_crtc_state *pipe_config,
6206 struct intel_display_power_domain_set *power_domain_set)
6208 struct drm_device *dev = crtc->base.dev;
6209 struct drm_i915_private *dev_priv = to_i915(dev);
6210 enum transcoder cpu_transcoder;
6214 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
6216 cpu_transcoder = TRANSCODER_DSI_A;
6218 cpu_transcoder = TRANSCODER_DSI_C;
6220 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6221 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6225 * The PLL needs to be enabled with a valid divider
6226 * configuration, otherwise accessing DSI registers will hang
6227 * the machine. See BSpec North Display Engine
6228 * registers/MIPI[BXT]. We can break out here early, since we
6229 * need the same DSI PLL to be enabled for both DSI ports.
6231 if (!bxt_dsi_pll_is_enabled(dev_priv))
6234 /* XXX: this works for video mode only */
6235 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
6236 if (!(tmp & DPI_ENABLE))
6239 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
6240 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
6243 pipe_config->cpu_transcoder = cpu_transcoder;
6247 return transcoder_is_dsi(pipe_config->cpu_transcoder);
6250 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
6251 struct intel_crtc_state *pipe_config)
6253 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6254 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6258 if (transcoder_is_dsi(cpu_transcoder)) {
6259 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
6262 tmp = intel_de_read(dev_priv,
6263 TRANS_DDI_FUNC_CTL(cpu_transcoder));
6264 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6266 if (DISPLAY_VER(dev_priv) >= 12)
6267 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6269 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6273 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6274 * DDI E. So just check whether this pipe is wired to DDI E and whether
6275 * the PCH transcoder is on.
6277 if (DISPLAY_VER(dev_priv) < 9 &&
6278 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
6279 pipe_config->has_pch_encoder = true;
6281 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
6282 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6283 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6285 ilk_get_fdi_m_n_config(crtc, pipe_config);
6289 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
6290 struct intel_crtc_state *pipe_config)
6292 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6293 struct intel_display_power_domain_set power_domain_set = { };
6297 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6298 POWER_DOMAIN_PIPE(crtc->pipe)))
6301 pipe_config->shared_dpll = NULL;
6303 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
6305 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
6306 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
6307 drm_WARN_ON(&dev_priv->drm, active);
6311 intel_dsc_get_config(pipe_config);
6312 if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
6313 intel_uncompressed_joiner_get_config(pipe_config);
6316 /* bigjoiner slave doesn't enable transcoder */
6317 if (!pipe_config->bigjoiner_slave)
6321 pipe_config->pixel_multiplier = 1;
6323 /* we cannot read out most state, so don't bother.. */
6324 pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
6325 } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
6326 DISPLAY_VER(dev_priv) >= 11) {
6327 hsw_get_ddi_port_state(crtc, pipe_config);
6328 intel_get_transcoder_timings(crtc, pipe_config);
6331 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
6332 intel_vrr_get_config(crtc, pipe_config);
6334 intel_get_pipe_src_size(crtc, pipe_config);
6336 if (IS_HASWELL(dev_priv)) {
6337 u32 tmp = intel_de_read(dev_priv,
6338 PIPECONF(pipe_config->cpu_transcoder));
6340 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
6341 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
6343 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
6345 pipe_config->output_format =
6346 bdw_get_pipemisc_output_format(crtc);
6349 pipe_config->gamma_mode = intel_de_read(dev_priv,
6350 GAMMA_MODE(crtc->pipe));
6352 pipe_config->csc_mode = intel_de_read(dev_priv,
6353 PIPE_CSC_MODE(crtc->pipe));
6355 if (DISPLAY_VER(dev_priv) >= 9) {
6356 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
6358 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
6359 pipe_config->gamma_enable = true;
6361 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
6362 pipe_config->csc_enable = true;
6364 i9xx_get_pipe_color_config(pipe_config);
6367 intel_color_get_config(pipe_config);
6369 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
6370 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
6371 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6372 pipe_config->ips_linetime =
6373 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
6375 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6376 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
6377 if (DISPLAY_VER(dev_priv) >= 9)
6378 skl_get_pfit_config(pipe_config);
6380 ilk_get_pfit_config(pipe_config);
6383 if (hsw_crtc_supports_ips(crtc)) {
6384 if (IS_HASWELL(dev_priv))
6385 pipe_config->ips_enabled = intel_de_read(dev_priv,
6386 IPS_CTL) & IPS_ENABLE;
6389 * We cannot readout IPS state on broadwell, set to
6390 * true so we can set it to a defined state on first
6393 pipe_config->ips_enabled = true;
6397 if (pipe_config->bigjoiner_slave) {
6398 /* Cannot be read out as a slave, set to 0. */
6399 pipe_config->pixel_multiplier = 0;
6400 } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
6401 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
6402 pipe_config->pixel_multiplier =
6403 intel_de_read(dev_priv,
6404 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
6406 pipe_config->pixel_multiplier = 1;
6410 intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
6415 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
6417 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6418 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6420 if (!i915->display.get_pipe_config(crtc, crtc_state))
6423 crtc_state->hw.active = true;
6425 intel_crtc_readout_derived_state(crtc_state);
6430 /* VESA 640x480x72Hz mode to set on the pipe */
6431 static const struct drm_display_mode load_detect_mode = {
6432 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6433 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6436 struct drm_framebuffer *
6437 intel_framebuffer_create(struct drm_i915_gem_object *obj,
6438 struct drm_mode_fb_cmd2 *mode_cmd)
6440 struct intel_framebuffer *intel_fb;
6443 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6445 return ERR_PTR(-ENOMEM);
6447 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
6451 return &intel_fb->base;
6455 return ERR_PTR(ret);
6458 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
6459 struct drm_crtc *crtc)
6461 struct drm_plane *plane;
6462 struct drm_plane_state *plane_state;
6465 ret = drm_atomic_add_affected_planes(state, crtc);
6469 for_each_new_plane_in_state(state, plane, plane_state, i) {
6470 if (plane_state->crtc != crtc)
6473 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
6477 drm_atomic_set_fb_for_plane(plane_state, NULL);
6483 int intel_get_load_detect_pipe(struct drm_connector *connector,
6484 struct intel_load_detect_pipe *old,
6485 struct drm_modeset_acquire_ctx *ctx)
6487 struct intel_encoder *encoder =
6488 intel_attached_encoder(to_intel_connector(connector));
6489 struct intel_crtc *possible_crtc;
6490 struct intel_crtc *crtc = NULL;
6491 struct drm_device *dev = encoder->base.dev;
6492 struct drm_i915_private *dev_priv = to_i915(dev);
6493 struct drm_mode_config *config = &dev->mode_config;
6494 struct drm_atomic_state *state = NULL, *restore_state = NULL;
6495 struct drm_connector_state *connector_state;
6496 struct intel_crtc_state *crtc_state;
6499 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6500 connector->base.id, connector->name,
6501 encoder->base.base.id, encoder->base.name);
6503 old->restore_state = NULL;
6505 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
6508 * Algorithm gets a little messy:
6510 * - if the connector already has an assigned crtc, use it (but make
6511 * sure it's on first)
6513 * - try to find the first unused crtc that can drive this connector,
6514 * and use that if we find one
6517 /* See if we already have a CRTC for this connector */
6518 if (connector->state->crtc) {
6519 crtc = to_intel_crtc(connector->state->crtc);
6521 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6525 /* Make sure the crtc and connector are running */
6529 /* Find an unused one (if possible) */
6530 for_each_intel_crtc(dev, possible_crtc) {
6531 if (!(encoder->base.possible_crtcs &
6532 drm_crtc_mask(&possible_crtc->base)))
6535 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);
6539 if (possible_crtc->base.state->enable) {
6540 drm_modeset_unlock(&possible_crtc->base.mutex);
6544 crtc = possible_crtc;
6549 * If we didn't find an unused CRTC, don't use any.
6552 drm_dbg_kms(&dev_priv->drm,
6553 "no pipe available for load-detect\n");
6559 state = drm_atomic_state_alloc(dev);
6560 restore_state = drm_atomic_state_alloc(dev);
6561 if (!state || !restore_state) {
6566 state->acquire_ctx = ctx;
6567 restore_state->acquire_ctx = ctx;
6569 connector_state = drm_atomic_get_connector_state(state, connector);
6570 if (IS_ERR(connector_state)) {
6571 ret = PTR_ERR(connector_state);
6575 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);
6579 crtc_state = intel_atomic_get_crtc_state(state, crtc);
6580 if (IS_ERR(crtc_state)) {
6581 ret = PTR_ERR(crtc_state);
6585 crtc_state->uapi.active = true;
6587 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
6592 ret = intel_modeset_disable_planes(state, &crtc->base);
6596 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
6598 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base));
6600 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);
6602 drm_dbg_kms(&dev_priv->drm,
6603 "Failed to create a copy of old state to restore: %i\n",
6608 ret = drm_atomic_commit(state);
6610 drm_dbg_kms(&dev_priv->drm,
6611 "failed to set mode on load-detect pipe\n");
6615 old->restore_state = restore_state;
6616 drm_atomic_state_put(state);
6618 /* let the connector get through one full cycle before testing */
6619 intel_wait_for_vblank(dev_priv, crtc->pipe);
6624 drm_atomic_state_put(state);
6627 if (restore_state) {
6628 drm_atomic_state_put(restore_state);
6629 restore_state = NULL;
6632 if (ret == -EDEADLK)
6638 void intel_release_load_detect_pipe(struct drm_connector *connector,
6639 struct intel_load_detect_pipe *old,
6640 struct drm_modeset_acquire_ctx *ctx)
6642 struct intel_encoder *intel_encoder =
6643 intel_attached_encoder(to_intel_connector(connector));
6644 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
6645 struct drm_encoder *encoder = &intel_encoder->base;
6646 struct drm_atomic_state *state = old->restore_state;
6649 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6650 connector->base.id, connector->name,
6651 encoder->base.id, encoder->name);
6656 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
6658 drm_dbg_kms(&i915->drm,
6659 "Couldn't release load detect pipe: %i\n", ret);
6660 drm_atomic_state_put(state);
6663 static int i9xx_pll_refclk(struct drm_device *dev,
6664 const struct intel_crtc_state *pipe_config)
6666 struct drm_i915_private *dev_priv = to_i915(dev);
6667 u32 dpll = pipe_config->dpll_hw_state.dpll;
6669 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
6670 return dev_priv->vbt.lvds_ssc_freq;
6671 else if (HAS_PCH_SPLIT(dev_priv))
6673 else if (DISPLAY_VER(dev_priv) != 2)
6679 /* Returns the clock of the currently programmed mode of the given pipe. */
6680 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6681 struct intel_crtc_state *pipe_config)
6683 struct drm_device *dev = crtc->base.dev;
6684 struct drm_i915_private *dev_priv = to_i915(dev);
6685 enum pipe pipe = crtc->pipe;
6686 u32 dpll = pipe_config->dpll_hw_state.dpll;
6690 int refclk = i9xx_pll_refclk(dev, pipe_config);
6692 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6693 fp = pipe_config->dpll_hw_state.fp0;
6695 fp = pipe_config->dpll_hw_state.fp1;
6697 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6698 if (IS_PINEVIEW(dev_priv)) {
6699 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6700 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6702 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6703 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6706 if (DISPLAY_VER(dev_priv) != 2) {
6707 if (IS_PINEVIEW(dev_priv))
6708 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6709 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6711 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6712 DPLL_FPA01_P1_POST_DIV_SHIFT);
6714 switch (dpll & DPLL_MODE_MASK) {
6715 case DPLLB_MODE_DAC_SERIAL:
6716 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6719 case DPLLB_MODE_LVDS:
6720 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6724 drm_dbg_kms(&dev_priv->drm,
6725 "Unknown DPLL mode %08x in programmed "
6726 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6730 if (IS_PINEVIEW(dev_priv))
6731 port_clock = pnv_calc_dpll_params(refclk, &clock);
6733 port_clock = i9xx_calc_dpll_params(refclk, &clock);
6735 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
6737 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
6740 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6741 DPLL_FPA01_P1_POST_DIV_SHIFT);
6743 if (lvds & LVDS_CLKB_POWER_UP)
6748 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6751 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6752 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6754 if (dpll & PLL_P2_DIVIDE_BY_4)
6760 port_clock = i9xx_calc_dpll_params(refclk, &clock);
6764 * This value includes pixel_multiplier. We will use
6765 * port_clock to compute adjusted_mode.crtc_clock in the
6766 * encoder's get_config() function.
6768 pipe_config->port_clock = port_clock;
6771 int intel_dotclock_calculate(int link_freq,
6772 const struct intel_link_m_n *m_n)
6775 * The calculation for the data clock is:
6776 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
6777 * But we want to avoid losing precison if possible, so:
6778 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
6780 * and the link clock is simpler:
6781 * link_clock = (m * link_clock) / n
6787 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
6790 static void ilk_pch_clock_get(struct intel_crtc *crtc,
6791 struct intel_crtc_state *pipe_config)
6793 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6795 /* read out port_clock from the DPLL */
6796 i9xx_crtc_clock_get(crtc, pipe_config);
6799 * In case there is an active pipe without active ports,
6800 * we may need some idea for the dotclock anyway.
6801 * Calculate one based on the FDI configuration.
6803 pipe_config->hw.adjusted_mode.crtc_clock =
6804 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
6805 &pipe_config->fdi_m_n);
6808 /* Returns the currently programmed mode of the given encoder. */
6809 struct drm_display_mode *
6810 intel_encoder_current_mode(struct intel_encoder *encoder)
6812 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6813 struct intel_crtc_state *crtc_state;
6814 struct drm_display_mode *mode;
6815 struct intel_crtc *crtc;
6818 if (!encoder->get_hw_state(encoder, &pipe))
6821 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6823 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6827 crtc_state = intel_crtc_state_alloc(crtc);
6833 if (!intel_crtc_get_pipe_config(crtc_state)) {
6839 intel_encoder_get_config(encoder, crtc_state);
6841 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
6849 * intel_wm_need_update - Check whether watermarks need updating
6850 * @cur: current plane state
6851 * @new: new plane state
6853 * Check current plane state versus the new one to determine whether
6854 * watermarks need to be recalculated.
6856 * Returns true or false.
6858 static bool intel_wm_need_update(const struct intel_plane_state *cur,
6859 struct intel_plane_state *new)
6861 /* Update watermarks on tiling or size changes. */
6862 if (new->uapi.visible != cur->uapi.visible)
6865 if (!cur->hw.fb || !new->hw.fb)
6868 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
6869 cur->hw.rotation != new->hw.rotation ||
6870 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
6871 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
6872 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
6873 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
6879 static bool needs_scaling(const struct intel_plane_state *state)
6881 int src_w = drm_rect_width(&state->uapi.src) >> 16;
6882 int src_h = drm_rect_height(&state->uapi.src) >> 16;
6883 int dst_w = drm_rect_width(&state->uapi.dst);
6884 int dst_h = drm_rect_height(&state->uapi.dst);
6886 return (src_w != dst_w || src_h != dst_h);
6889 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
6890 struct intel_crtc_state *crtc_state,
6891 const struct intel_plane_state *old_plane_state,
6892 struct intel_plane_state *plane_state)
6894 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6895 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
6896 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6897 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
6898 bool was_crtc_enabled = old_crtc_state->hw.active;
6899 bool is_crtc_enabled = crtc_state->hw.active;
6900 bool turn_off, turn_on, visible, was_visible;
6903 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
6904 ret = skl_update_scaler_plane(crtc_state, plane_state);
6909 was_visible = old_plane_state->uapi.visible;
6910 visible = plane_state->uapi.visible;
6912 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
6913 was_visible = false;
6916 * Visibility is calculated as if the crtc was on, but
6917 * after scaler setup everything depends on it being off
6918 * when the crtc isn't active.
6920 * FIXME this is wrong for watermarks. Watermarks should also
6921 * be computed as if the pipe would be active. Perhaps move
6922 * per-plane wm computation to the .check_plane() hook, and
6923 * only combine the results from all planes in the current place?
6925 if (!is_crtc_enabled) {
6926 intel_plane_set_invisible(crtc_state, plane_state);
6930 if (!was_visible && !visible)
6933 turn_off = was_visible && (!visible || mode_changed);
6934 turn_on = visible && (!was_visible || mode_changed);
6936 drm_dbg_atomic(&dev_priv->drm,
6937 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
6938 crtc->base.base.id, crtc->base.name,
6939 plane->base.base.id, plane->base.name,
6940 was_visible, visible,
6941 turn_off, turn_on, mode_changed);
6944 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
6945 crtc_state->update_wm_pre = true;
6947 /* must disable cxsr around plane enable/disable */
6948 if (plane->id != PLANE_CURSOR)
6949 crtc_state->disable_cxsr = true;
6950 } else if (turn_off) {
6951 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
6952 crtc_state->update_wm_post = true;
6954 /* must disable cxsr around plane enable/disable */
6955 if (plane->id != PLANE_CURSOR)
6956 crtc_state->disable_cxsr = true;
6957 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
6958 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
6959 /* FIXME bollocks */
6960 crtc_state->update_wm_pre = true;
6961 crtc_state->update_wm_post = true;
6965 if (visible || was_visible)
6966 crtc_state->fb_bits |= plane->frontbuffer_bit;
6969 * ILK/SNB DVSACNTR/Sprite Enable
6970 * IVB SPR_CTL/Sprite Enable
6971 * "When in Self Refresh Big FIFO mode, a write to enable the
6972 * plane will be internally buffered and delayed while Big FIFO
6975 * Which means that enabling the sprite can take an extra frame
6976 * when we start in big FIFO mode (LP1+). Thus we need to drop
6977 * down to LP0 and wait for vblank in order to make sure the
6978 * sprite gets enabled on the next vblank after the register write.
6979 * Doing otherwise would risk enabling the sprite one frame after
6980 * we've already signalled flip completion. We can resume LP1+
6981 * once the sprite has been enabled.
6984 * WaCxSRDisabledForSpriteScaling:ivb
6985 * IVB SPR_SCALE/Scaling Enable
6986 * "Low Power watermarks must be disabled for at least one
6987 * frame before enabling sprite scaling, and kept disabled
6988 * until sprite scaling is disabled."
6990 * ILK/SNB DVSASCALE/Scaling Enable
6991 * "When in Self Refresh Big FIFO mode, scaling enable will be
6992 * masked off while Big FIFO mode is exiting."
6994 * Despite the w/a only being listed for IVB we assume that
6995 * the ILK/SNB note has similar ramifications, hence we apply
6996 * the w/a on all three platforms.
6998 * With experimental results seems this is needed also for primary
6999 * plane, not only sprite plane.
7001 if (plane->id != PLANE_CURSOR &&
7002 (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
7003 IS_IVYBRIDGE(dev_priv)) &&
7004 (turn_on || (!needs_scaling(old_plane_state) &&
7005 needs_scaling(plane_state))))
7006 crtc_state->disable_lp_wm = true;
7011 static bool encoders_cloneable(const struct intel_encoder *a,
7012 const struct intel_encoder *b)
7014 /* masks could be asymmetric, so check both ways */
7015 return a == b || (a->cloneable & (1 << b->type) &&
7016 b->cloneable & (1 << a->type));
7019 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
7020 struct intel_crtc *crtc,
7021 struct intel_encoder *encoder)
7023 struct intel_encoder *source_encoder;
7024 struct drm_connector *connector;
7025 struct drm_connector_state *connector_state;
7028 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
7029 if (connector_state->crtc != &crtc->base)
7033 to_intel_encoder(connector_state->best_encoder);
7034 if (!encoders_cloneable(encoder, source_encoder))
7041 static int icl_add_linked_planes(struct intel_atomic_state *state)
7043 struct intel_plane *plane, *linked;
7044 struct intel_plane_state *plane_state, *linked_plane_state;
7047 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7048 linked = plane_state->planar_linked_plane;
7053 linked_plane_state = intel_atomic_get_plane_state(state, linked);
7054 if (IS_ERR(linked_plane_state))
7055 return PTR_ERR(linked_plane_state);
7057 drm_WARN_ON(state->base.dev,
7058 linked_plane_state->planar_linked_plane != plane);
7059 drm_WARN_ON(state->base.dev,
7060 linked_plane_state->planar_slave == plane_state->planar_slave);
7066 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
7068 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7069 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7070 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
7071 struct intel_plane *plane, *linked;
7072 struct intel_plane_state *plane_state;
7075 if (DISPLAY_VER(dev_priv) < 11)
7079 * Destroy all old plane links and make the slave plane invisible
7080 * in the crtc_state->active_planes mask.
7082 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7083 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
7086 plane_state->planar_linked_plane = NULL;
7087 if (plane_state->planar_slave && !plane_state->uapi.visible) {
7088 crtc_state->enabled_planes &= ~BIT(plane->id);
7089 crtc_state->active_planes &= ~BIT(plane->id);
7090 crtc_state->update_planes |= BIT(plane->id);
7093 plane_state->planar_slave = false;
7096 if (!crtc_state->nv12_planes)
7099 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7100 struct intel_plane_state *linked_state = NULL;
7102 if (plane->pipe != crtc->pipe ||
7103 !(crtc_state->nv12_planes & BIT(plane->id)))
7106 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
7107 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
7110 if (crtc_state->active_planes & BIT(linked->id))
7113 linked_state = intel_atomic_get_plane_state(state, linked);
7114 if (IS_ERR(linked_state))
7115 return PTR_ERR(linked_state);
7120 if (!linked_state) {
7121 drm_dbg_kms(&dev_priv->drm,
7122 "Need %d free Y planes for planar YUV\n",
7123 hweight8(crtc_state->nv12_planes));
7128 plane_state->planar_linked_plane = linked;
7130 linked_state->planar_slave = true;
7131 linked_state->planar_linked_plane = plane;
7132 crtc_state->enabled_planes |= BIT(linked->id);
7133 crtc_state->active_planes |= BIT(linked->id);
7134 crtc_state->update_planes |= BIT(linked->id);
7135 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
7136 linked->base.name, plane->base.name);
7138 /* Copy parameters to slave plane */
7139 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
7140 linked_state->color_ctl = plane_state->color_ctl;
7141 linked_state->view = plane_state->view;
7143 intel_plane_copy_hw_state(linked_state, plane_state);
7144 linked_state->uapi.src = plane_state->uapi.src;
7145 linked_state->uapi.dst = plane_state->uapi.dst;
7147 if (icl_is_hdr_plane(dev_priv, plane->id)) {
7148 if (linked->id == PLANE_SPRITE5)
7149 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
7150 else if (linked->id == PLANE_SPRITE4)
7151 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
7152 else if (linked->id == PLANE_SPRITE3)
7153 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
7154 else if (linked->id == PLANE_SPRITE2)
7155 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
7157 MISSING_CASE(linked->id);
7164 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
7166 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
7167 struct intel_atomic_state *state =
7168 to_intel_atomic_state(new_crtc_state->uapi.state);
7169 const struct intel_crtc_state *old_crtc_state =
7170 intel_atomic_get_old_crtc_state(state, crtc);
7172 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
7175 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
7177 const struct drm_display_mode *pipe_mode =
7178 &crtc_state->hw.pipe_mode;
7181 if (!crtc_state->hw.enable)
7184 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7185 pipe_mode->crtc_clock);
7187 return min(linetime_wm, 0x1ff);
7190 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
7191 const struct intel_cdclk_state *cdclk_state)
7193 const struct drm_display_mode *pipe_mode =
7194 &crtc_state->hw.pipe_mode;
7197 if (!crtc_state->hw.enable)
7200 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7201 cdclk_state->logical.cdclk);
7203 return min(linetime_wm, 0x1ff);
7206 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
7208 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7210 const struct drm_display_mode *pipe_mode =
7211 &crtc_state->hw.pipe_mode;
7214 if (!crtc_state->hw.enable)
7217 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
7218 crtc_state->pixel_rate);
7220 /* Display WA #1135: BXT:ALL GLK:ALL */
7221 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
7222 dev_priv->ipc_enabled)
7225 return min(linetime_wm, 0x1ff);
7228 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
7229 struct intel_crtc *crtc)
7231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7232 struct intel_crtc_state *crtc_state =
7233 intel_atomic_get_new_crtc_state(state, crtc);
7234 const struct intel_cdclk_state *cdclk_state;
7236 if (DISPLAY_VER(dev_priv) >= 9)
7237 crtc_state->linetime = skl_linetime_wm(crtc_state);
7239 crtc_state->linetime = hsw_linetime_wm(crtc_state);
7241 if (!hsw_crtc_supports_ips(crtc))
7244 cdclk_state = intel_atomic_get_cdclk_state(state);
7245 if (IS_ERR(cdclk_state))
7246 return PTR_ERR(cdclk_state);
7248 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
7254 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
7255 struct intel_crtc *crtc)
7257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7258 struct intel_crtc_state *crtc_state =
7259 intel_atomic_get_new_crtc_state(state, crtc);
7260 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
7263 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
7264 mode_changed && !crtc_state->hw.active)
7265 crtc_state->update_wm_post = true;
7267 if (mode_changed && crtc_state->hw.enable &&
7268 dev_priv->display.crtc_compute_clock &&
7269 !crtc_state->bigjoiner_slave &&
7270 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
7271 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
7277 * May need to update pipe gamma enable bits
7278 * when C8 planes are getting enabled/disabled.
7280 if (c8_planes_changed(crtc_state))
7281 crtc_state->uapi.color_mgmt_changed = true;
7283 if (mode_changed || crtc_state->update_pipe ||
7284 crtc_state->uapi.color_mgmt_changed) {
7285 ret = intel_color_check(crtc_state);
7290 if (dev_priv->display.compute_pipe_wm) {
7291 ret = dev_priv->display.compute_pipe_wm(state, crtc);
7293 drm_dbg_kms(&dev_priv->drm,
7294 "Target pipe watermarks are invalid\n");
7300 if (dev_priv->display.compute_intermediate_wm) {
7301 if (drm_WARN_ON(&dev_priv->drm,
7302 !dev_priv->display.compute_pipe_wm))
7306 * Calculate 'intermediate' watermarks that satisfy both the
7307 * old state and the new state. We can program these
7310 ret = dev_priv->display.compute_intermediate_wm(state, crtc);
7312 drm_dbg_kms(&dev_priv->drm,
7313 "No valid intermediate pipe watermarks are possible\n");
7318 if (DISPLAY_VER(dev_priv) >= 9) {
7319 if (mode_changed || crtc_state->update_pipe) {
7320 ret = skl_update_scaler_crtc(crtc_state);
7325 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
7330 if (HAS_IPS(dev_priv)) {
7331 ret = hsw_compute_ips_config(crtc_state);
7336 if (DISPLAY_VER(dev_priv) >= 9 ||
7337 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7338 ret = hsw_compute_linetime_wm(state, crtc);
7344 if (!mode_changed) {
7345 ret = intel_psr2_sel_fetch_update(state, crtc);
7353 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
7355 struct intel_connector *connector;
7356 struct drm_connector_list_iter conn_iter;
7358 drm_connector_list_iter_begin(dev, &conn_iter);
7359 for_each_intel_connector_iter(connector, &conn_iter) {
7360 struct drm_connector_state *conn_state = connector->base.state;
7361 struct intel_encoder *encoder =
7362 to_intel_encoder(connector->base.encoder);
7364 if (conn_state->crtc)
7365 drm_connector_put(&connector->base);
7368 struct intel_crtc *crtc =
7369 to_intel_crtc(encoder->base.crtc);
7370 const struct intel_crtc_state *crtc_state =
7371 to_intel_crtc_state(crtc->base.state);
7373 conn_state->best_encoder = &encoder->base;
7374 conn_state->crtc = &crtc->base;
7375 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
7377 drm_connector_get(&connector->base);
7379 conn_state->best_encoder = NULL;
7380 conn_state->crtc = NULL;
7383 drm_connector_list_iter_end(&conn_iter);
7387 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
7388 struct intel_crtc_state *pipe_config)
7390 struct drm_connector *connector = conn_state->connector;
7391 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7392 const struct drm_display_info *info = &connector->display_info;
7395 switch (conn_state->max_bpc) {
7409 MISSING_CASE(conn_state->max_bpc);
7413 if (bpp < pipe_config->pipe_bpp) {
7414 drm_dbg_kms(&i915->drm,
7415 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
7416 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
7417 connector->base.id, connector->name,
7419 3 * conn_state->max_requested_bpc,
7420 pipe_config->pipe_bpp);
7422 pipe_config->pipe_bpp = bpp;
7429 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7430 struct intel_crtc_state *pipe_config)
7432 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7433 struct drm_atomic_state *state = pipe_config->uapi.state;
7434 struct drm_connector *connector;
7435 struct drm_connector_state *connector_state;
7438 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7439 IS_CHERRYVIEW(dev_priv)))
7441 else if (DISPLAY_VER(dev_priv) >= 5)
7446 pipe_config->pipe_bpp = bpp;
7448 /* Clamp display bpp to connector max bpp */
7449 for_each_new_connector_in_state(state, connector, connector_state, i) {
7452 if (connector_state->crtc != &crtc->base)
7455 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
7463 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
7464 const struct drm_display_mode *mode)
7466 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
7467 "type: 0x%x flags: 0x%x\n",
7469 mode->crtc_hdisplay, mode->crtc_hsync_start,
7470 mode->crtc_hsync_end, mode->crtc_htotal,
7471 mode->crtc_vdisplay, mode->crtc_vsync_start,
7472 mode->crtc_vsync_end, mode->crtc_vtotal,
7473 mode->type, mode->flags);
7477 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
7478 const char *id, unsigned int lane_count,
7479 const struct intel_link_m_n *m_n)
7481 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7483 drm_dbg_kms(&i915->drm,
7484 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7486 m_n->gmch_m, m_n->gmch_n,
7487 m_n->link_m, m_n->link_n, m_n->tu);
7491 intel_dump_infoframe(struct drm_i915_private *dev_priv,
7492 const union hdmi_infoframe *frame)
7494 if (!drm_debug_enabled(DRM_UT_KMS))
7497 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
7501 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
7502 const struct drm_dp_vsc_sdp *vsc)
7504 if (!drm_debug_enabled(DRM_UT_KMS))
7507 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
7510 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
7512 static const char * const output_type_str[] = {
7513 OUTPUT_TYPE(UNUSED),
7514 OUTPUT_TYPE(ANALOG),
7524 OUTPUT_TYPE(DP_MST),
7529 static void snprintf_output_types(char *buf, size_t len,
7530 unsigned int output_types)
7537 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
7540 if ((output_types & BIT(i)) == 0)
7543 r = snprintf(str, len, "%s%s",
7544 str != buf ? "," : "", output_type_str[i]);
7550 output_types &= ~BIT(i);
7553 WARN_ON_ONCE(output_types != 0);
7556 static const char * const output_format_str[] = {
7557 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
7558 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
7559 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
7562 static const char *output_formats(enum intel_output_format format)
7564 if (format >= ARRAY_SIZE(output_format_str))
7566 return output_format_str[format];
7569 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
7571 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
7572 struct drm_i915_private *i915 = to_i915(plane->base.dev);
7573 const struct drm_framebuffer *fb = plane_state->hw.fb;
7576 drm_dbg_kms(&i915->drm,
7577 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
7578 plane->base.base.id, plane->base.name,
7579 yesno(plane_state->uapi.visible));
7583 drm_dbg_kms(&i915->drm,
7584 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
7585 plane->base.base.id, plane->base.name,
7586 fb->base.id, fb->width, fb->height, &fb->format->format,
7587 fb->modifier, yesno(plane_state->uapi.visible));
7588 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
7589 plane_state->hw.rotation, plane_state->scaler_id);
7590 if (plane_state->uapi.visible)
7591 drm_dbg_kms(&i915->drm,
7592 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
7593 DRM_RECT_FP_ARG(&plane_state->uapi.src),
7594 DRM_RECT_ARG(&plane_state->uapi.dst));
7597 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
7598 struct intel_atomic_state *state,
7599 const char *context)
7601 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
7602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7603 const struct intel_plane_state *plane_state;
7604 struct intel_plane *plane;
7608 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
7609 crtc->base.base.id, crtc->base.name,
7610 yesno(pipe_config->hw.enable), context);
7612 if (!pipe_config->hw.enable)
7615 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
7616 drm_dbg_kms(&dev_priv->drm,
7617 "active: %s, output_types: %s (0x%x), output format: %s\n",
7618 yesno(pipe_config->hw.active),
7619 buf, pipe_config->output_types,
7620 output_formats(pipe_config->output_format));
7622 drm_dbg_kms(&dev_priv->drm,
7623 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
7624 transcoder_name(pipe_config->cpu_transcoder),
7625 pipe_config->pipe_bpp, pipe_config->dither);
7627 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
7628 transcoder_name(pipe_config->mst_master_transcoder));
7630 drm_dbg_kms(&dev_priv->drm,
7631 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
7632 transcoder_name(pipe_config->master_transcoder),
7633 pipe_config->sync_mode_slaves_mask);
7635 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n",
7636 pipe_config->bigjoiner_slave ? "slave" :
7637 pipe_config->bigjoiner ? "master" : "no");
7639 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
7640 enableddisabled(pipe_config->splitter.enable),
7641 pipe_config->splitter.link_count,
7642 pipe_config->splitter.pixel_overlap);
7644 if (pipe_config->has_pch_encoder)
7645 intel_dump_m_n_config(pipe_config, "fdi",
7646 pipe_config->fdi_lanes,
7647 &pipe_config->fdi_m_n);
7649 if (intel_crtc_has_dp_encoder(pipe_config)) {
7650 intel_dump_m_n_config(pipe_config, "dp m_n",
7651 pipe_config->lane_count, &pipe_config->dp_m_n);
7652 if (pipe_config->has_drrs)
7653 intel_dump_m_n_config(pipe_config, "dp m2_n2",
7654 pipe_config->lane_count,
7655 &pipe_config->dp_m2_n2);
7658 drm_dbg_kms(&dev_priv->drm,
7659 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
7660 pipe_config->has_audio, pipe_config->has_infoframe,
7661 pipe_config->infoframes.enable);
7663 if (pipe_config->infoframes.enable &
7664 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
7665 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
7666 pipe_config->infoframes.gcp);
7667 if (pipe_config->infoframes.enable &
7668 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
7669 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
7670 if (pipe_config->infoframes.enable &
7671 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
7672 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
7673 if (pipe_config->infoframes.enable &
7674 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
7675 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
7676 if (pipe_config->infoframes.enable &
7677 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
7678 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
7679 if (pipe_config->infoframes.enable &
7680 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
7681 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
7682 if (pipe_config->infoframes.enable &
7683 intel_hdmi_infoframe_enable(DP_SDP_VSC))
7684 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
7686 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
7687 yesno(pipe_config->vrr.enable),
7688 pipe_config->vrr.vmin, pipe_config->vrr.vmax,
7689 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
7690 pipe_config->vrr.flipline,
7691 intel_vrr_vmin_vblank_start(pipe_config),
7692 intel_vrr_vmax_vblank_start(pipe_config));
7694 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
7695 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
7696 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
7697 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
7698 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
7699 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
7700 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
7701 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
7702 drm_dbg_kms(&dev_priv->drm,
7703 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
7704 pipe_config->port_clock,
7705 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
7706 pipe_config->pixel_rate);
7708 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
7709 pipe_config->linetime, pipe_config->ips_linetime);
7711 if (DISPLAY_VER(dev_priv) >= 9)
7712 drm_dbg_kms(&dev_priv->drm,
7713 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
7715 pipe_config->scaler_state.scaler_users,
7716 pipe_config->scaler_state.scaler_id);
7718 if (HAS_GMCH(dev_priv))
7719 drm_dbg_kms(&dev_priv->drm,
7720 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7721 pipe_config->gmch_pfit.control,
7722 pipe_config->gmch_pfit.pgm_ratios,
7723 pipe_config->gmch_pfit.lvds_border_bits);
7725 drm_dbg_kms(&dev_priv->drm,
7726 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
7727 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
7728 enableddisabled(pipe_config->pch_pfit.enabled),
7729 yesno(pipe_config->pch_pfit.force_thru));
7731 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
7732 pipe_config->ips_enabled, pipe_config->double_wide);
7734 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
7736 if (IS_CHERRYVIEW(dev_priv))
7737 drm_dbg_kms(&dev_priv->drm,
7738 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
7739 pipe_config->cgm_mode, pipe_config->gamma_mode,
7740 pipe_config->gamma_enable, pipe_config->csc_enable);
7742 drm_dbg_kms(&dev_priv->drm,
7743 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
7744 pipe_config->csc_mode, pipe_config->gamma_mode,
7745 pipe_config->gamma_enable, pipe_config->csc_enable);
7747 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
7748 pipe_config->hw.degamma_lut ?
7749 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
7750 pipe_config->hw.gamma_lut ?
7751 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
7757 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7758 if (plane->pipe == crtc->pipe)
7759 intel_dump_plane_state(plane_state);
7763 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
7765 struct drm_device *dev = state->base.dev;
7766 struct drm_connector *connector;
7767 struct drm_connector_list_iter conn_iter;
7768 unsigned int used_ports = 0;
7769 unsigned int used_mst_ports = 0;
7773 * We're going to peek into connector->state,
7774 * hence connection_mutex must be held.
7776 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
7779 * Walk the connector list instead of the encoder
7780 * list to detect the problem on ddi platforms
7781 * where there's just one encoder per digital port.
7783 drm_connector_list_iter_begin(dev, &conn_iter);
7784 drm_for_each_connector_iter(connector, &conn_iter) {
7785 struct drm_connector_state *connector_state;
7786 struct intel_encoder *encoder;
7789 drm_atomic_get_new_connector_state(&state->base,
7791 if (!connector_state)
7792 connector_state = connector->state;
7794 if (!connector_state->best_encoder)
7797 encoder = to_intel_encoder(connector_state->best_encoder);
7799 drm_WARN_ON(dev, !connector_state->crtc);
7801 switch (encoder->type) {
7802 case INTEL_OUTPUT_DDI:
7803 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
7806 case INTEL_OUTPUT_DP:
7807 case INTEL_OUTPUT_HDMI:
7808 case INTEL_OUTPUT_EDP:
7809 /* the same port mustn't appear more than once */
7810 if (used_ports & BIT(encoder->port))
7813 used_ports |= BIT(encoder->port);
7815 case INTEL_OUTPUT_DP_MST:
7823 drm_connector_list_iter_end(&conn_iter);
7825 /* can't mix MST and SST/HDMI on the same port */
7826 if (used_ports & used_mst_ports)
7833 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
7834 struct intel_crtc_state *crtc_state)
7836 const struct intel_crtc_state *from_crtc_state = crtc_state;
7838 if (crtc_state->bigjoiner_slave) {
7839 from_crtc_state = intel_atomic_get_new_crtc_state(state,
7840 crtc_state->bigjoiner_linked_crtc);
7842 /* No need to copy state if the master state is unchanged */
7843 if (!from_crtc_state)
7847 intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
7851 intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
7852 struct intel_crtc_state *crtc_state)
7854 crtc_state->hw.enable = crtc_state->uapi.enable;
7855 crtc_state->hw.active = crtc_state->uapi.active;
7856 crtc_state->hw.mode = crtc_state->uapi.mode;
7857 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
7858 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
7860 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
7863 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
7865 if (crtc_state->bigjoiner_slave)
7868 crtc_state->uapi.enable = crtc_state->hw.enable;
7869 crtc_state->uapi.active = crtc_state->hw.active;
7870 drm_WARN_ON(crtc_state->uapi.crtc->dev,
7871 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
7873 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
7874 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
7876 /* copy color blobs to uapi */
7877 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
7878 crtc_state->hw.degamma_lut);
7879 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
7880 crtc_state->hw.gamma_lut);
7881 drm_property_replace_blob(&crtc_state->uapi.ctm,
7882 crtc_state->hw.ctm);
7886 copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
7887 const struct intel_crtc_state *from_crtc_state)
7889 struct intel_crtc_state *saved_state;
7890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7892 saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
7896 saved_state->uapi = crtc_state->uapi;
7897 saved_state->scaler_state = crtc_state->scaler_state;
7898 saved_state->shared_dpll = crtc_state->shared_dpll;
7899 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
7900 saved_state->crc_enabled = crtc_state->crc_enabled;
7902 intel_crtc_free_hw_state(crtc_state);
7903 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
7906 /* Re-init hw state */
7907 memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
7908 crtc_state->hw.enable = from_crtc_state->hw.enable;
7909 crtc_state->hw.active = from_crtc_state->hw.active;
7910 crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
7911 crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
7914 crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
7915 crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
7916 crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
7917 crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
7918 crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
7919 crtc_state->bigjoiner_slave = true;
7920 crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
7921 crtc_state->has_audio = false;
7927 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
7928 struct intel_crtc_state *crtc_state)
7930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7931 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7932 struct intel_crtc_state *saved_state;
7934 saved_state = intel_crtc_state_alloc(crtc);
7938 /* free the old crtc_state->hw members */
7939 intel_crtc_free_hw_state(crtc_state);
7941 /* FIXME: before the switch to atomic started, a new pipe_config was
7942 * kzalloc'd. Code that depends on any field being zero should be
7943 * fixed, so that the crtc_state can be safely duplicated. For now,
7944 * only fields that are know to not cause problems are preserved. */
7946 saved_state->uapi = crtc_state->uapi;
7947 saved_state->scaler_state = crtc_state->scaler_state;
7948 saved_state->shared_dpll = crtc_state->shared_dpll;
7949 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
7950 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
7951 sizeof(saved_state->icl_port_dplls));
7952 saved_state->crc_enabled = crtc_state->crc_enabled;
7953 if (IS_G4X(dev_priv) ||
7954 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7955 saved_state->wm = crtc_state->wm;
7957 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
7960 intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
7966 intel_modeset_pipe_config(struct intel_atomic_state *state,
7967 struct intel_crtc_state *pipe_config)
7969 struct drm_crtc *crtc = pipe_config->uapi.crtc;
7970 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7971 struct drm_connector *connector;
7972 struct drm_connector_state *connector_state;
7973 int base_bpp, ret, i;
7976 pipe_config->cpu_transcoder =
7977 (enum transcoder) to_intel_crtc(crtc)->pipe;
7980 * Sanitize sync polarity flags based on requested ones. If neither
7981 * positive or negative polarity is requested, treat this as meaning
7982 * negative polarity.
7984 if (!(pipe_config->hw.adjusted_mode.flags &
7985 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
7986 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
7988 if (!(pipe_config->hw.adjusted_mode.flags &
7989 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
7990 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
7992 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7997 base_bpp = pipe_config->pipe_bpp;
8000 * Determine the real pipe dimensions. Note that stereo modes can
8001 * increase the actual pipe size due to the frame doubling and
8002 * insertion of additional space for blanks between the frame. This
8003 * is stored in the crtc timings. We use the requested mode to do this
8004 * computation to clearly distinguish it from the adjusted mode, which
8005 * can be changed by the connectors in the below retry loop.
8007 drm_mode_get_hv_timing(&pipe_config->hw.mode,
8008 &pipe_config->pipe_src_w,
8009 &pipe_config->pipe_src_h);
8011 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
8012 struct intel_encoder *encoder =
8013 to_intel_encoder(connector_state->best_encoder);
8015 if (connector_state->crtc != crtc)
8018 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
8019 drm_dbg_kms(&i915->drm,
8020 "rejecting invalid cloning configuration\n");
8025 * Determine output_types before calling the .compute_config()
8026 * hooks so that the hooks can use this information safely.
8028 if (encoder->compute_output_type)
8029 pipe_config->output_types |=
8030 BIT(encoder->compute_output_type(encoder, pipe_config,
8033 pipe_config->output_types |= BIT(encoder->type);
8037 /* Ensure the port clock defaults are reset when retrying. */
8038 pipe_config->port_clock = 0;
8039 pipe_config->pixel_multiplier = 1;
8041 /* Fill in default crtc timings, allow encoders to overwrite them. */
8042 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
8043 CRTC_STEREO_DOUBLE);
8045 /* Pass our mode to the connectors and the CRTC to give them a chance to
8046 * adjust it according to limitations or connector properties, and also
8047 * a chance to reject the mode entirely.
8049 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
8050 struct intel_encoder *encoder =
8051 to_intel_encoder(connector_state->best_encoder);
8053 if (connector_state->crtc != crtc)
8056 ret = encoder->compute_config(encoder, pipe_config,
8059 if (ret != -EDEADLK)
8060 drm_dbg_kms(&i915->drm,
8061 "Encoder config failure: %d\n",
8067 /* Set default port clock if not overwritten by the encoder. Needs to be
8068 * done afterwards in case the encoder adjusts the mode. */
8069 if (!pipe_config->port_clock)
8070 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
8071 * pipe_config->pixel_multiplier;
8073 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8074 if (ret == -EDEADLK)
8077 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
8081 if (ret == I915_DISPLAY_CONFIG_RETRY) {
8082 if (drm_WARN(&i915->drm, !retry,
8083 "loop in pipe configuration computation\n"))
8086 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
8091 /* Dithering seems to not pass-through bits correctly when it should, so
8092 * only enable it on 6bpc panels and when its not a compliance
8093 * test requesting 6bpc video pattern.
8095 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
8096 !pipe_config->dither_force_disable;
8097 drm_dbg_kms(&i915->drm,
8098 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
8099 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8105 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
8107 struct intel_atomic_state *state =
8108 to_intel_atomic_state(crtc_state->uapi.state);
8109 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8110 struct drm_connector_state *conn_state;
8111 struct drm_connector *connector;
8114 for_each_new_connector_in_state(&state->base, connector,
8116 struct intel_encoder *encoder =
8117 to_intel_encoder(conn_state->best_encoder);
8120 if (conn_state->crtc != &crtc->base ||
8121 !encoder->compute_config_late)
8124 ret = encoder->compute_config_late(encoder, crtc_state,
8133 bool intel_fuzzy_clock_check(int clock1, int clock2)
8137 if (clock1 == clock2)
8140 if (!clock1 || !clock2)
8143 diff = abs(clock1 - clock2);
8145 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8152 intel_compare_m_n(unsigned int m, unsigned int n,
8153 unsigned int m2, unsigned int n2,
8156 if (m == m2 && n == n2)
8159 if (exact || !m || !n || !m2 || !n2)
8162 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
8169 } else if (n < n2) {
8179 return intel_fuzzy_clock_check(m, m2);
8183 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
8184 const struct intel_link_m_n *m2_n2,
8187 return m_n->tu == m2_n2->tu &&
8188 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
8189 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
8190 intel_compare_m_n(m_n->link_m, m_n->link_n,
8191 m2_n2->link_m, m2_n2->link_n, exact);
8195 intel_compare_infoframe(const union hdmi_infoframe *a,
8196 const union hdmi_infoframe *b)
8198 return memcmp(a, b, sizeof(*a)) == 0;
8202 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
8203 const struct drm_dp_vsc_sdp *b)
8205 return memcmp(a, b, sizeof(*a)) == 0;
8209 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
8210 bool fastset, const char *name,
8211 const union hdmi_infoframe *a,
8212 const union hdmi_infoframe *b)
8215 if (!drm_debug_enabled(DRM_UT_KMS))
8218 drm_dbg_kms(&dev_priv->drm,
8219 "fastset mismatch in %s infoframe\n", name);
8220 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8221 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
8222 drm_dbg_kms(&dev_priv->drm, "found:\n");
8223 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
8225 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
8226 drm_err(&dev_priv->drm, "expected:\n");
8227 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
8228 drm_err(&dev_priv->drm, "found:\n");
8229 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
8234 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
8235 bool fastset, const char *name,
8236 const struct drm_dp_vsc_sdp *a,
8237 const struct drm_dp_vsc_sdp *b)
8240 if (!drm_debug_enabled(DRM_UT_KMS))
8243 drm_dbg_kms(&dev_priv->drm,
8244 "fastset mismatch in %s dp sdp\n", name);
8245 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8246 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
8247 drm_dbg_kms(&dev_priv->drm, "found:\n");
8248 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
8250 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
8251 drm_err(&dev_priv->drm, "expected:\n");
8252 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
8253 drm_err(&dev_priv->drm, "found:\n");
8254 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
8258 static void __printf(4, 5)
8259 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
8260 const char *name, const char *format, ...)
8262 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
8263 struct va_format vaf;
8266 va_start(args, format);
8271 drm_dbg_kms(&i915->drm,
8272 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
8273 crtc->base.base.id, crtc->base.name, name, &vaf);
8275 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
8276 crtc->base.base.id, crtc->base.name, name, &vaf);
8281 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
8283 if (dev_priv->params.fastboot != -1)
8284 return dev_priv->params.fastboot;
8286 /* Enable fastboot by default on Skylake and newer */
8287 if (DISPLAY_VER(dev_priv) >= 9)
8290 /* Enable fastboot by default on VLV and CHV */
8291 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8294 /* Disabled by default on all others */
8299 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
8300 const struct intel_crtc_state *pipe_config,
8303 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
8304 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
8307 bool fixup_inherited = fastset &&
8308 current_config->inherited && !pipe_config->inherited;
8310 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
8311 drm_dbg_kms(&dev_priv->drm,
8312 "initial modeset and fastboot not set\n");
8316 #define PIPE_CONF_CHECK_X(name) do { \
8317 if (current_config->name != pipe_config->name) { \
8318 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8319 "(expected 0x%08x, found 0x%08x)", \
8320 current_config->name, \
8321 pipe_config->name); \
8326 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
8327 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
8328 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8329 "(expected 0x%08x, found 0x%08x)", \
8330 current_config->name & (mask), \
8331 pipe_config->name & (mask)); \
8336 #define PIPE_CONF_CHECK_I(name) do { \
8337 if (current_config->name != pipe_config->name) { \
8338 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8339 "(expected %i, found %i)", \
8340 current_config->name, \
8341 pipe_config->name); \
8346 #define PIPE_CONF_CHECK_BOOL(name) do { \
8347 if (current_config->name != pipe_config->name) { \
8348 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8349 "(expected %s, found %s)", \
8350 yesno(current_config->name), \
8351 yesno(pipe_config->name)); \
8357 * Checks state where we only read out the enabling, but not the entire
8358 * state itself (like full infoframes or ELD for audio). These states
8359 * require a full modeset on bootup to fix up.
8361 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
8362 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
8363 PIPE_CONF_CHECK_BOOL(name); \
8365 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8366 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
8367 yesno(current_config->name), \
8368 yesno(pipe_config->name)); \
8373 #define PIPE_CONF_CHECK_P(name) do { \
8374 if (current_config->name != pipe_config->name) { \
8375 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8376 "(expected %p, found %p)", \
8377 current_config->name, \
8378 pipe_config->name); \
8383 #define PIPE_CONF_CHECK_M_N(name) do { \
8384 if (!intel_compare_link_m_n(¤t_config->name, \
8385 &pipe_config->name,\
8387 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8388 "(expected tu %i gmch %i/%i link %i/%i, " \
8389 "found tu %i, gmch %i/%i link %i/%i)", \
8390 current_config->name.tu, \
8391 current_config->name.gmch_m, \
8392 current_config->name.gmch_n, \
8393 current_config->name.link_m, \
8394 current_config->name.link_n, \
8395 pipe_config->name.tu, \
8396 pipe_config->name.gmch_m, \
8397 pipe_config->name.gmch_n, \
8398 pipe_config->name.link_m, \
8399 pipe_config->name.link_n); \
8404 /* This is required for BDW+ where there is only one set of registers for
8405 * switching between high and low RR.
8406 * This macro can be used whenever a comparison has to be made between one
8407 * hw state and multiple sw state variables.
8409 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
8410 if (!intel_compare_link_m_n(¤t_config->name, \
8411 &pipe_config->name, !fastset) && \
8412 !intel_compare_link_m_n(¤t_config->alt_name, \
8413 &pipe_config->name, !fastset)) { \
8414 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8415 "(expected tu %i gmch %i/%i link %i/%i, " \
8416 "or tu %i gmch %i/%i link %i/%i, " \
8417 "found tu %i, gmch %i/%i link %i/%i)", \
8418 current_config->name.tu, \
8419 current_config->name.gmch_m, \
8420 current_config->name.gmch_n, \
8421 current_config->name.link_m, \
8422 current_config->name.link_n, \
8423 current_config->alt_name.tu, \
8424 current_config->alt_name.gmch_m, \
8425 current_config->alt_name.gmch_n, \
8426 current_config->alt_name.link_m, \
8427 current_config->alt_name.link_n, \
8428 pipe_config->name.tu, \
8429 pipe_config->name.gmch_m, \
8430 pipe_config->name.gmch_n, \
8431 pipe_config->name.link_m, \
8432 pipe_config->name.link_n); \
8437 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
8438 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8439 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8440 "(%x) (expected %i, found %i)", \
8442 current_config->name & (mask), \
8443 pipe_config->name & (mask)); \
8448 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
8449 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8450 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8451 "(expected %i, found %i)", \
8452 current_config->name, \
8453 pipe_config->name); \
8458 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
8459 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
8460 &pipe_config->infoframes.name)) { \
8461 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
8462 ¤t_config->infoframes.name, \
8463 &pipe_config->infoframes.name); \
8468 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
8469 if (!current_config->has_psr && !pipe_config->has_psr && \
8470 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
8471 &pipe_config->infoframes.name)) { \
8472 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
8473 ¤t_config->infoframes.name, \
8474 &pipe_config->infoframes.name); \
8479 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
8480 if (current_config->name1 != pipe_config->name1) { \
8481 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
8482 "(expected %i, found %i, won't compare lut values)", \
8483 current_config->name1, \
8484 pipe_config->name1); \
8487 if (!intel_color_lut_equal(current_config->name2, \
8488 pipe_config->name2, pipe_config->name1, \
8490 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
8491 "hw_state doesn't match sw_state"); \
8497 #define PIPE_CONF_QUIRK(quirk) \
8498 ((current_config->quirks | pipe_config->quirks) & (quirk))
8500 PIPE_CONF_CHECK_I(cpu_transcoder);
8502 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
8503 PIPE_CONF_CHECK_I(fdi_lanes);
8504 PIPE_CONF_CHECK_M_N(fdi_m_n);
8506 PIPE_CONF_CHECK_I(lane_count);
8507 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
8509 if (DISPLAY_VER(dev_priv) < 8) {
8510 PIPE_CONF_CHECK_M_N(dp_m_n);
8512 if (current_config->has_drrs)
8513 PIPE_CONF_CHECK_M_N(dp_m2_n2);
8515 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
8517 PIPE_CONF_CHECK_X(output_types);
8519 /* FIXME do the readout properly and get rid of this quirk */
8520 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8521 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
8522 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
8523 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
8524 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
8525 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
8526 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
8528 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
8529 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
8530 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
8531 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
8532 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
8533 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
8535 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
8536 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
8537 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
8538 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
8539 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
8540 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
8542 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
8543 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
8544 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
8545 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
8546 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
8547 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
8549 PIPE_CONF_CHECK_I(pixel_multiplier);
8551 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8552 DRM_MODE_FLAG_INTERLACE);
8554 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8555 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8556 DRM_MODE_FLAG_PHSYNC);
8557 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8558 DRM_MODE_FLAG_NHSYNC);
8559 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8560 DRM_MODE_FLAG_PVSYNC);
8561 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8562 DRM_MODE_FLAG_NVSYNC);
8566 PIPE_CONF_CHECK_I(output_format);
8567 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
8568 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
8569 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8570 PIPE_CONF_CHECK_BOOL(limited_color_range);
8572 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
8573 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
8574 PIPE_CONF_CHECK_BOOL(has_infoframe);
8575 /* FIXME do the readout properly and get rid of this quirk */
8576 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
8577 PIPE_CONF_CHECK_BOOL(fec_enable);
8579 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
8581 PIPE_CONF_CHECK_X(gmch_pfit.control);
8582 /* pfit ratios are autocomputed by the hw on gen4+ */
8583 if (DISPLAY_VER(dev_priv) < 4)
8584 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
8585 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
8588 * Changing the EDP transcoder input mux
8589 * (A_ONOFF vs. A_ON) requires a full modeset.
8591 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
8594 PIPE_CONF_CHECK_I(pipe_src_w);
8595 PIPE_CONF_CHECK_I(pipe_src_h);
8597 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
8598 if (current_config->pch_pfit.enabled) {
8599 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
8600 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
8601 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
8602 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
8605 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
8606 /* FIXME do the readout properly and get rid of this quirk */
8607 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
8608 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
8610 PIPE_CONF_CHECK_X(gamma_mode);
8611 if (IS_CHERRYVIEW(dev_priv))
8612 PIPE_CONF_CHECK_X(cgm_mode);
8614 PIPE_CONF_CHECK_X(csc_mode);
8615 PIPE_CONF_CHECK_BOOL(gamma_enable);
8616 PIPE_CONF_CHECK_BOOL(csc_enable);
8618 PIPE_CONF_CHECK_I(linetime);
8619 PIPE_CONF_CHECK_I(ips_linetime);
8621 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
8623 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
8625 PIPE_CONF_CHECK_BOOL(has_psr);
8626 PIPE_CONF_CHECK_BOOL(has_psr2);
8627 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
8628 PIPE_CONF_CHECK_I(dc3co_exitline);
8631 PIPE_CONF_CHECK_BOOL(double_wide);
8633 PIPE_CONF_CHECK_P(shared_dpll);
8635 /* FIXME do the readout properly and get rid of this quirk */
8636 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8637 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8638 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8639 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8640 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8641 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
8642 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
8643 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
8644 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
8645 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
8646 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
8647 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
8648 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
8649 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
8650 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
8651 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
8652 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
8653 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
8654 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
8655 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
8656 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
8657 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
8658 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
8659 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
8660 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
8661 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
8662 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
8663 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
8664 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
8665 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
8666 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
8667 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
8669 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
8670 PIPE_CONF_CHECK_X(dsi_pll.div);
8672 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
8673 PIPE_CONF_CHECK_I(pipe_bpp);
8675 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
8676 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
8677 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8679 PIPE_CONF_CHECK_I(min_voltage_level);
8682 if (fastset && (current_config->has_psr || pipe_config->has_psr))
8683 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
8684 ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
8686 PIPE_CONF_CHECK_X(infoframes.enable);
8688 PIPE_CONF_CHECK_X(infoframes.gcp);
8689 PIPE_CONF_CHECK_INFOFRAME(avi);
8690 PIPE_CONF_CHECK_INFOFRAME(spd);
8691 PIPE_CONF_CHECK_INFOFRAME(hdmi);
8692 PIPE_CONF_CHECK_INFOFRAME(drm);
8693 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
8695 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
8696 PIPE_CONF_CHECK_I(master_transcoder);
8697 PIPE_CONF_CHECK_BOOL(bigjoiner);
8698 PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
8699 PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
8701 PIPE_CONF_CHECK_I(dsc.compression_enable);
8702 PIPE_CONF_CHECK_I(dsc.dsc_split);
8703 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
8705 PIPE_CONF_CHECK_BOOL(splitter.enable);
8706 PIPE_CONF_CHECK_I(splitter.link_count);
8707 PIPE_CONF_CHECK_I(splitter.pixel_overlap);
8709 PIPE_CONF_CHECK_I(mst_master_transcoder);
8711 PIPE_CONF_CHECK_BOOL(vrr.enable);
8712 PIPE_CONF_CHECK_I(vrr.vmin);
8713 PIPE_CONF_CHECK_I(vrr.vmax);
8714 PIPE_CONF_CHECK_I(vrr.flipline);
8715 PIPE_CONF_CHECK_I(vrr.pipeline_full);
8716 PIPE_CONF_CHECK_I(vrr.guardband);
8718 #undef PIPE_CONF_CHECK_X
8719 #undef PIPE_CONF_CHECK_I
8720 #undef PIPE_CONF_CHECK_BOOL
8721 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
8722 #undef PIPE_CONF_CHECK_P
8723 #undef PIPE_CONF_CHECK_FLAGS
8724 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8725 #undef PIPE_CONF_CHECK_COLOR_LUT
8726 #undef PIPE_CONF_QUIRK
8731 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
8732 const struct intel_crtc_state *pipe_config)
8734 if (pipe_config->has_pch_encoder) {
8735 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
8736 &pipe_config->fdi_m_n);
8737 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
8740 * FDI already provided one idea for the dotclock.
8741 * Yell if the encoder disagrees.
8743 drm_WARN(&dev_priv->drm,
8744 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
8745 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
8746 fdi_dotclock, dotclock);
8750 static void verify_wm_state(struct intel_crtc *crtc,
8751 struct intel_crtc_state *new_crtc_state)
8753 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8754 struct skl_hw_state {
8755 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
8756 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
8757 struct skl_pipe_wm wm;
8759 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
8760 int level, max_level = ilk_wm_max_level(dev_priv);
8761 struct intel_plane *plane;
8762 u8 hw_enabled_slices;
8764 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)
8767 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
8771 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
8773 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
8775 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
8777 if (DISPLAY_VER(dev_priv) >= 11 &&
8778 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
8779 drm_err(&dev_priv->drm,
8780 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
8781 dev_priv->dbuf.enabled_slices,
8784 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
8785 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
8786 const struct skl_wm_level *hw_wm_level, *sw_wm_level;
8789 for (level = 0; level <= max_level; level++) {
8790 hw_wm_level = &hw->wm.planes[plane->id].wm[level];
8791 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
8793 if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
8796 drm_err(&dev_priv->drm,
8797 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8798 plane->base.base.id, plane->base.name, level,
8799 sw_wm_level->enable,
8800 sw_wm_level->blocks,
8802 hw_wm_level->enable,
8803 hw_wm_level->blocks,
8804 hw_wm_level->lines);
8807 hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
8808 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
8810 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8811 drm_err(&dev_priv->drm,
8812 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8813 plane->base.base.id, plane->base.name,
8814 sw_wm_level->enable,
8815 sw_wm_level->blocks,
8817 hw_wm_level->enable,
8818 hw_wm_level->blocks,
8819 hw_wm_level->lines);
8822 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
8823 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
8825 if (HAS_HW_SAGV_WM(dev_priv) &&
8826 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8827 drm_err(&dev_priv->drm,
8828 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8829 plane->base.base.id, plane->base.name,
8830 sw_wm_level->enable,
8831 sw_wm_level->blocks,
8833 hw_wm_level->enable,
8834 hw_wm_level->blocks,
8835 hw_wm_level->lines);
8838 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
8839 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
8841 if (HAS_HW_SAGV_WM(dev_priv) &&
8842 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8843 drm_err(&dev_priv->drm,
8844 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8845 plane->base.base.id, plane->base.name,
8846 sw_wm_level->enable,
8847 sw_wm_level->blocks,
8849 hw_wm_level->enable,
8850 hw_wm_level->blocks,
8851 hw_wm_level->lines);
8855 hw_ddb_entry = &hw->ddb_y[plane->id];
8856 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
8858 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
8859 drm_err(&dev_priv->drm,
8860 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
8861 plane->base.base.id, plane->base.name,
8862 sw_ddb_entry->start, sw_ddb_entry->end,
8863 hw_ddb_entry->start, hw_ddb_entry->end);
8871 verify_connector_state(struct intel_atomic_state *state,
8872 struct intel_crtc *crtc)
8874 struct drm_connector *connector;
8875 struct drm_connector_state *new_conn_state;
8878 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
8879 struct drm_encoder *encoder = connector->encoder;
8880 struct intel_crtc_state *crtc_state = NULL;
8882 if (new_conn_state->crtc != &crtc->base)
8886 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
8888 intel_connector_verify_state(crtc_state, new_conn_state);
8890 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
8891 "connector's atomic encoder doesn't match legacy encoder\n");
8896 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
8898 struct intel_encoder *encoder;
8899 struct drm_connector *connector;
8900 struct drm_connector_state *old_conn_state, *new_conn_state;
8903 for_each_intel_encoder(&dev_priv->drm, encoder) {
8904 bool enabled = false, found = false;
8907 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
8908 encoder->base.base.id,
8909 encoder->base.name);
8911 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
8912 new_conn_state, i) {
8913 if (old_conn_state->best_encoder == &encoder->base)
8916 if (new_conn_state->best_encoder != &encoder->base)
8918 found = enabled = true;
8920 I915_STATE_WARN(new_conn_state->crtc !=
8922 "connector's crtc doesn't match encoder crtc\n");
8928 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8929 "encoder's enabled state mismatch "
8930 "(expected %i, found %i)\n",
8931 !!encoder->base.crtc, enabled);
8933 if (!encoder->base.crtc) {
8936 active = encoder->get_hw_state(encoder, &pipe);
8937 I915_STATE_WARN(active,
8938 "encoder detached but still enabled on pipe %c.\n",
8945 verify_crtc_state(struct intel_crtc *crtc,
8946 struct intel_crtc_state *old_crtc_state,
8947 struct intel_crtc_state *new_crtc_state)
8949 struct drm_device *dev = crtc->base.dev;
8950 struct drm_i915_private *dev_priv = to_i915(dev);
8951 struct intel_encoder *encoder;
8952 struct intel_crtc_state *pipe_config = old_crtc_state;
8953 struct drm_atomic_state *state = old_crtc_state->uapi.state;
8954 struct intel_crtc *master = crtc;
8956 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
8957 intel_crtc_free_hw_state(old_crtc_state);
8958 intel_crtc_state_reset(old_crtc_state, crtc);
8959 old_crtc_state->uapi.state = state;
8961 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
8964 pipe_config->hw.enable = new_crtc_state->hw.enable;
8966 intel_crtc_get_pipe_config(pipe_config);
8968 /* we keep both pipes enabled on 830 */
8969 if (IS_I830(dev_priv) && pipe_config->hw.active)
8970 pipe_config->hw.active = new_crtc_state->hw.active;
8972 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
8973 "crtc active state doesn't match with hw state "
8974 "(expected %i, found %i)\n",
8975 new_crtc_state->hw.active, pipe_config->hw.active);
8977 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
8978 "transitional active state does not match atomic hw state "
8979 "(expected %i, found %i)\n",
8980 new_crtc_state->hw.active, crtc->active);
8982 if (new_crtc_state->bigjoiner_slave)
8983 master = new_crtc_state->bigjoiner_linked_crtc;
8985 for_each_encoder_on_crtc(dev, &master->base, encoder) {
8989 active = encoder->get_hw_state(encoder, &pipe);
8990 I915_STATE_WARN(active != new_crtc_state->hw.active,
8991 "[ENCODER:%i] active %i with crtc active %i\n",
8992 encoder->base.base.id, active,
8993 new_crtc_state->hw.active);
8995 I915_STATE_WARN(active && master->pipe != pipe,
8996 "Encoder connected to wrong pipe %c\n",
9000 intel_encoder_get_config(encoder, pipe_config);
9003 if (!new_crtc_state->hw.active)
9006 intel_pipe_config_sanity_check(dev_priv, pipe_config);
9008 if (!intel_pipe_config_compare(new_crtc_state,
9009 pipe_config, false)) {
9010 I915_STATE_WARN(1, "pipe state doesn't match!\n");
9011 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
9012 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
9017 intel_verify_planes(struct intel_atomic_state *state)
9019 struct intel_plane *plane;
9020 const struct intel_plane_state *plane_state;
9023 for_each_new_intel_plane_in_state(state, plane,
9025 assert_plane(plane, plane_state->planar_slave ||
9026 plane_state->uapi.visible);
9030 verify_single_dpll_state(struct drm_i915_private *dev_priv,
9031 struct intel_shared_dpll *pll,
9032 struct intel_crtc *crtc,
9033 struct intel_crtc_state *new_crtc_state)
9035 struct intel_dpll_hw_state dpll_hw_state;
9039 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9041 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
9043 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
9045 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
9046 I915_STATE_WARN(!pll->on && pll->active_mask,
9047 "pll in active use but not on in sw tracking\n");
9048 I915_STATE_WARN(pll->on && !pll->active_mask,
9049 "pll is on but not used by any active pipe\n");
9050 I915_STATE_WARN(pll->on != active,
9051 "pll on state mismatch (expected %i, found %i)\n",
9056 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
9057 "more active pll users than references: 0x%x vs 0x%x\n",
9058 pll->active_mask, pll->state.pipe_mask);
9063 pipe_mask = BIT(crtc->pipe);
9065 if (new_crtc_state->hw.active)
9066 I915_STATE_WARN(!(pll->active_mask & pipe_mask),
9067 "pll active mismatch (expected pipe %c in active mask 0x%x)\n",
9068 pipe_name(crtc->pipe), pll->active_mask);
9070 I915_STATE_WARN(pll->active_mask & pipe_mask,
9071 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
9072 pipe_name(crtc->pipe), pll->active_mask);
9074 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
9075 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
9076 pipe_mask, pll->state.pipe_mask);
9078 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
9080 sizeof(dpll_hw_state)),
9081 "pll hw state mismatch\n");
9085 verify_shared_dpll_state(struct intel_crtc *crtc,
9086 struct intel_crtc_state *old_crtc_state,
9087 struct intel_crtc_state *new_crtc_state)
9089 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9091 if (new_crtc_state->shared_dpll)
9092 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
9094 if (old_crtc_state->shared_dpll &&
9095 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
9096 u8 pipe_mask = BIT(crtc->pipe);
9097 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
9099 I915_STATE_WARN(pll->active_mask & pipe_mask,
9100 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
9101 pipe_name(crtc->pipe), pll->active_mask);
9102 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
9103 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
9104 pipe_name(crtc->pipe), pll->state.pipe_mask);
9109 intel_modeset_verify_crtc(struct intel_crtc *crtc,
9110 struct intel_atomic_state *state,
9111 struct intel_crtc_state *old_crtc_state,
9112 struct intel_crtc_state *new_crtc_state)
9114 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
9117 verify_wm_state(crtc, new_crtc_state);
9118 verify_connector_state(state, crtc);
9119 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
9120 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
9124 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
9128 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
9129 verify_single_dpll_state(dev_priv,
9130 &dev_priv->dpll.shared_dplls[i],
9135 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
9136 struct intel_atomic_state *state)
9138 verify_encoder_state(dev_priv, state);
9139 verify_connector_state(state, NULL);
9140 verify_disabled_dpll_state(dev_priv);
9143 int intel_modeset_all_pipes(struct intel_atomic_state *state)
9145 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9146 struct intel_crtc *crtc;
9149 * Add all pipes to the state, and force
9150 * a modeset on all the active ones.
9152 for_each_intel_crtc(&dev_priv->drm, crtc) {
9153 struct intel_crtc_state *crtc_state;
9156 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
9157 if (IS_ERR(crtc_state))
9158 return PTR_ERR(crtc_state);
9160 if (!crtc_state->hw.active ||
9161 drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
9164 crtc_state->uapi.mode_changed = true;
9166 ret = drm_atomic_add_affected_connectors(&state->base,
9171 ret = intel_atomic_add_affected_planes(state, crtc);
9175 crtc_state->update_planes |= crtc_state->active_planes;
9182 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
9184 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9185 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9186 struct drm_display_mode adjusted_mode =
9187 crtc_state->hw.adjusted_mode;
9189 if (crtc_state->vrr.enable) {
9190 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
9191 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
9192 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
9193 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
9196 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
9198 crtc->mode_flags = crtc_state->mode_flags;
9201 * The scanline counter increments at the leading edge of hsync.
9203 * On most platforms it starts counting from vtotal-1 on the
9204 * first active line. That means the scanline counter value is
9205 * always one less than what we would expect. Ie. just after
9206 * start of vblank, which also occurs at start of hsync (on the
9207 * last active line), the scanline counter will read vblank_start-1.
9209 * On gen2 the scanline counter starts counting from 1 instead
9210 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
9211 * to keep the value positive), instead of adding one.
9213 * On HSW+ the behaviour of the scanline counter depends on the output
9214 * type. For DP ports it behaves like most other platforms, but on HDMI
9215 * there's an extra 1 line difference. So we need to add two instead of
9218 * On VLV/CHV DSI the scanline counter would appear to increment
9219 * approx. 1/3 of a scanline before start of vblank. Unfortunately
9220 * that means we can't tell whether we're in vblank or not while
9221 * we're on that particular line. We must still set scanline_offset
9222 * to 1 so that the vblank timestamps come out correct when we query
9223 * the scanline counter from within the vblank interrupt handler.
9224 * However if queried just before the start of vblank we'll get an
9225 * answer that's slightly in the future.
9227 if (DISPLAY_VER(dev_priv) == 2) {
9230 vtotal = adjusted_mode.crtc_vtotal;
9231 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9234 crtc->scanline_offset = vtotal - 1;
9235 } else if (HAS_DDI(dev_priv) &&
9236 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
9237 crtc->scanline_offset = 2;
9239 crtc->scanline_offset = 1;
9243 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
9245 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9246 struct intel_crtc_state *new_crtc_state;
9247 struct intel_crtc *crtc;
9250 if (!dev_priv->display.crtc_compute_clock)
9253 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9254 if (!intel_crtc_needs_modeset(new_crtc_state))
9257 intel_release_shared_dplls(state, crtc);
9262 * This implements the workaround described in the "notes" section of the mode
9263 * set sequence documentation. When going from no pipes or single pipe to
9264 * multiple pipes, and planes are enabled after the pipe, we need to wait at
9265 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
9267 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
9269 struct intel_crtc_state *crtc_state;
9270 struct intel_crtc *crtc;
9271 struct intel_crtc_state *first_crtc_state = NULL;
9272 struct intel_crtc_state *other_crtc_state = NULL;
9273 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
9276 /* look at all crtc's that are going to be enabled in during modeset */
9277 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9278 if (!crtc_state->hw.active ||
9279 !intel_crtc_needs_modeset(crtc_state))
9282 if (first_crtc_state) {
9283 other_crtc_state = crtc_state;
9286 first_crtc_state = crtc_state;
9287 first_pipe = crtc->pipe;
9291 /* No workaround needed? */
9292 if (!first_crtc_state)
9295 /* w/a possibly needed, check how many crtc's are already enabled. */
9296 for_each_intel_crtc(state->base.dev, crtc) {
9297 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
9298 if (IS_ERR(crtc_state))
9299 return PTR_ERR(crtc_state);
9301 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
9303 if (!crtc_state->hw.active ||
9304 intel_crtc_needs_modeset(crtc_state))
9307 /* 2 or more enabled crtcs means no need for w/a */
9308 if (enabled_pipe != INVALID_PIPE)
9311 enabled_pipe = crtc->pipe;
9314 if (enabled_pipe != INVALID_PIPE)
9315 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
9316 else if (other_crtc_state)
9317 other_crtc_state->hsw_workaround_pipe = first_pipe;
9322 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
9325 const struct intel_crtc_state *crtc_state;
9326 struct intel_crtc *crtc;
9329 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9330 if (crtc_state->hw.active)
9331 active_pipes |= BIT(crtc->pipe);
9333 active_pipes &= ~BIT(crtc->pipe);
9336 return active_pipes;
9339 static int intel_modeset_checks(struct intel_atomic_state *state)
9341 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9343 state->modeset = true;
9345 if (IS_HASWELL(dev_priv))
9346 return hsw_mode_set_planes_workaround(state);
9352 * Handle calculation of various watermark data at the end of the atomic check
9353 * phase. The code here should be run after the per-crtc and per-plane 'check'
9354 * handlers to ensure that all derived state has been updated.
9356 static int calc_watermark_data(struct intel_atomic_state *state)
9358 struct drm_device *dev = state->base.dev;
9359 struct drm_i915_private *dev_priv = to_i915(dev);
9361 /* Is there platform-specific watermark information to calculate? */
9362 if (dev_priv->display.compute_global_watermarks)
9363 return dev_priv->display.compute_global_watermarks(state);
9368 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
9369 struct intel_crtc_state *new_crtc_state)
9371 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
9374 new_crtc_state->uapi.mode_changed = false;
9375 new_crtc_state->update_pipe = true;
9378 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
9379 struct intel_crtc_state *new_crtc_state)
9382 * If we're not doing the full modeset we want to
9383 * keep the current M/N values as they may be
9384 * sufficiently different to the computed values
9385 * to cause problems.
9387 * FIXME: should really copy more fuzzy state here
9389 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
9390 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
9391 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
9392 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
9395 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
9396 struct intel_crtc *crtc,
9399 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9400 struct intel_plane *plane;
9402 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
9403 struct intel_plane_state *plane_state;
9405 if ((plane_ids_mask & BIT(plane->id)) == 0)
9408 plane_state = intel_atomic_get_plane_state(state, plane);
9409 if (IS_ERR(plane_state))
9410 return PTR_ERR(plane_state);
9416 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
9417 struct intel_crtc *crtc)
9419 const struct intel_crtc_state *old_crtc_state =
9420 intel_atomic_get_old_crtc_state(state, crtc);
9421 const struct intel_crtc_state *new_crtc_state =
9422 intel_atomic_get_new_crtc_state(state, crtc);
9424 return intel_crtc_add_planes_to_state(state, crtc,
9425 old_crtc_state->enabled_planes |
9426 new_crtc_state->enabled_planes);
9429 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
9431 /* See {hsw,vlv,ivb}_plane_ratio() */
9432 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
9433 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9434 IS_IVYBRIDGE(dev_priv);
9437 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
9438 struct intel_crtc *crtc,
9439 struct intel_crtc *other)
9441 const struct intel_plane_state *plane_state;
9442 struct intel_plane *plane;
9446 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9447 if (plane->pipe == crtc->pipe)
9448 plane_ids |= BIT(plane->id);
9451 return intel_crtc_add_planes_to_state(state, other, plane_ids);
9454 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
9456 const struct intel_crtc_state *crtc_state;
9457 struct intel_crtc *crtc;
9460 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9463 if (!crtc_state->bigjoiner)
9466 ret = intel_crtc_add_bigjoiner_planes(state, crtc,
9467 crtc_state->bigjoiner_linked_crtc);
9475 static int intel_atomic_check_planes(struct intel_atomic_state *state)
9477 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9478 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9479 struct intel_plane_state *plane_state;
9480 struct intel_plane *plane;
9481 struct intel_crtc *crtc;
9484 ret = icl_add_linked_planes(state);
9488 ret = intel_bigjoiner_add_affected_planes(state);
9492 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9493 ret = intel_plane_atomic_check(state, plane);
9495 drm_dbg_atomic(&dev_priv->drm,
9496 "[PLANE:%d:%s] atomic driver check failed\n",
9497 plane->base.base.id, plane->base.name);
9502 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9503 new_crtc_state, i) {
9504 u8 old_active_planes, new_active_planes;
9506 ret = icl_check_nv12_planes(new_crtc_state);
9511 * On some platforms the number of active planes affects
9512 * the planes' minimum cdclk calculation. Add such planes
9513 * to the state before we compute the minimum cdclk.
9515 if (!active_planes_affects_min_cdclk(dev_priv))
9518 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9519 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9521 if (hweight8(old_active_planes) == hweight8(new_active_planes))
9524 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
9532 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
9533 bool *need_cdclk_calc)
9535 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9536 const struct intel_cdclk_state *old_cdclk_state;
9537 const struct intel_cdclk_state *new_cdclk_state;
9538 struct intel_plane_state *plane_state;
9539 struct intel_bw_state *new_bw_state;
9540 struct intel_plane *plane;
9546 * active_planes bitmask has been updated, and potentially
9547 * affected planes are part of the state. We can now
9548 * compute the minimum cdclk for each plane.
9550 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9551 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
9556 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
9557 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
9559 if (new_cdclk_state &&
9560 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
9561 *need_cdclk_calc = true;
9563 ret = dev_priv->display.bw_calc_min_cdclk(state);
9567 new_bw_state = intel_atomic_get_new_bw_state(state);
9569 if (!new_cdclk_state || !new_bw_state)
9572 for_each_pipe(dev_priv, pipe) {
9573 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
9576 * Currently do this change only if we need to increase
9578 if (new_bw_state->min_cdclk > min_cdclk)
9579 *need_cdclk_calc = true;
9585 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
9587 struct intel_crtc_state *crtc_state;
9588 struct intel_crtc *crtc;
9591 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9592 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
9595 ret = intel_crtc_atomic_check(state, crtc);
9597 drm_dbg_atomic(&i915->drm,
9598 "[CRTC:%d:%s] atomic driver check failed\n",
9599 crtc->base.base.id, crtc->base.name);
9607 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
9610 const struct intel_crtc_state *new_crtc_state;
9611 struct intel_crtc *crtc;
9614 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9615 if (new_crtc_state->hw.enable &&
9616 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
9617 intel_crtc_needs_modeset(new_crtc_state))
9624 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
9625 struct intel_crtc *crtc,
9626 struct intel_crtc_state *old_crtc_state,
9627 struct intel_crtc_state *new_crtc_state)
9629 struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
9630 struct intel_crtc *slave, *master;
9632 /* slave being enabled, is master is still claiming this crtc? */
9633 if (old_crtc_state->bigjoiner_slave) {
9635 master = old_crtc_state->bigjoiner_linked_crtc;
9636 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
9637 if (!master_crtc_state || !intel_crtc_needs_modeset(master_crtc_state))
9641 if (!new_crtc_state->bigjoiner)
9644 slave = intel_dsc_get_bigjoiner_secondary(crtc);
9646 DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
9647 "CRTC + 1 to be used, doesn't exist\n",
9648 crtc->base.base.id, crtc->base.name);
9652 new_crtc_state->bigjoiner_linked_crtc = slave;
9653 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
9655 if (IS_ERR(slave_crtc_state))
9656 return PTR_ERR(slave_crtc_state);
9658 /* master being enabled, slave was already configured? */
9659 if (slave_crtc_state->uapi.enable)
9662 DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
9663 slave->base.base.id, slave->base.name);
9665 return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
9668 DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
9669 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
9670 slave->base.base.id, slave->base.name,
9671 master->base.base.id, master->base.name);
9675 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
9676 struct intel_crtc_state *master_crtc_state)
9678 struct intel_crtc_state *slave_crtc_state =
9679 intel_atomic_get_new_crtc_state(state, master_crtc_state->bigjoiner_linked_crtc);
9681 slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
9682 slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
9683 slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
9684 intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
9688 * DOC: asynchronous flip implementation
9690 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
9691 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
9692 * Correspondingly, support is currently added for primary plane only.
9694 * Async flip can only change the plane surface address, so anything else
9695 * changing is rejected from the intel_atomic_check_async() function.
9696 * Once this check is cleared, flip done interrupt is enabled using
9697 * the intel_crtc_enable_flip_done() function.
9699 * As soon as the surface address register is written, flip done interrupt is
9700 * generated and the requested events are sent to the usersapce in the interrupt
9701 * handler itself. The timestamp and sequence sent during the flip done event
9702 * correspond to the last vblank and have no relation to the actual time when
9703 * the flip done event was sent.
9705 static int intel_atomic_check_async(struct intel_atomic_state *state)
9707 struct drm_i915_private *i915 = to_i915(state->base.dev);
9708 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9709 const struct intel_plane_state *new_plane_state, *old_plane_state;
9710 struct intel_crtc *crtc;
9711 struct intel_plane *plane;
9714 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9715 new_crtc_state, i) {
9716 if (intel_crtc_needs_modeset(new_crtc_state)) {
9717 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
9721 if (!new_crtc_state->hw.active) {
9722 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
9725 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
9726 drm_dbg_kms(&i915->drm,
9727 "Active planes cannot be changed during async flip\n");
9732 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
9733 new_plane_state, i) {
9735 * TODO: Async flip is only supported through the page flip IOCTL
9736 * as of now. So support currently added for primary plane only.
9737 * Support for other planes on platforms on which supports
9738 * this(vlv/chv and icl+) should be added when async flip is
9739 * enabled in the atomic IOCTL path.
9741 if (!plane->async_flip)
9745 * FIXME: This check is kept generic for all platforms.
9746 * Need to verify this for all gen9 and gen10 platforms to enable
9747 * this selectively if required.
9749 switch (new_plane_state->hw.fb->modifier) {
9750 case I915_FORMAT_MOD_X_TILED:
9751 case I915_FORMAT_MOD_Y_TILED:
9752 case I915_FORMAT_MOD_Yf_TILED:
9755 drm_dbg_kms(&i915->drm,
9756 "Linear memory/CCS does not support async flips\n");
9760 if (old_plane_state->view.color_plane[0].stride !=
9761 new_plane_state->view.color_plane[0].stride) {
9762 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
9766 if (old_plane_state->hw.fb->modifier !=
9767 new_plane_state->hw.fb->modifier) {
9768 drm_dbg_kms(&i915->drm,
9769 "Framebuffer modifiers cannot be changed in async flip\n");
9773 if (old_plane_state->hw.fb->format !=
9774 new_plane_state->hw.fb->format) {
9775 drm_dbg_kms(&i915->drm,
9776 "Framebuffer format cannot be changed in async flip\n");
9780 if (old_plane_state->hw.rotation !=
9781 new_plane_state->hw.rotation) {
9782 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
9786 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
9787 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
9788 drm_dbg_kms(&i915->drm,
9789 "Plane size/co-ordinates cannot be changed in async flip\n");
9793 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
9794 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
9798 if (old_plane_state->hw.pixel_blend_mode !=
9799 new_plane_state->hw.pixel_blend_mode) {
9800 drm_dbg_kms(&i915->drm,
9801 "Pixel blend mode cannot be changed in async flip\n");
9805 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
9806 drm_dbg_kms(&i915->drm,
9807 "Color encoding cannot be changed in async flip\n");
9811 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
9812 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
9820 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
9822 struct intel_crtc_state *crtc_state;
9823 struct intel_crtc *crtc;
9826 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9827 struct intel_crtc_state *linked_crtc_state;
9828 struct intel_crtc *linked_crtc;
9831 if (!crtc_state->bigjoiner)
9834 linked_crtc = crtc_state->bigjoiner_linked_crtc;
9835 linked_crtc_state = intel_atomic_get_crtc_state(&state->base, linked_crtc);
9836 if (IS_ERR(linked_crtc_state))
9837 return PTR_ERR(linked_crtc_state);
9839 if (!intel_crtc_needs_modeset(crtc_state))
9842 linked_crtc_state->uapi.mode_changed = true;
9844 ret = drm_atomic_add_affected_connectors(&state->base,
9845 &linked_crtc->base);
9849 ret = intel_atomic_add_affected_planes(state, linked_crtc);
9854 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9855 /* Kill old bigjoiner link, we may re-establish afterwards */
9856 if (intel_crtc_needs_modeset(crtc_state) &&
9857 crtc_state->bigjoiner && !crtc_state->bigjoiner_slave)
9858 kill_bigjoiner_slave(state, crtc_state);
9865 * intel_atomic_check - validate state object
9867 * @_state: state to validate
9869 static int intel_atomic_check(struct drm_device *dev,
9870 struct drm_atomic_state *_state)
9872 struct drm_i915_private *dev_priv = to_i915(dev);
9873 struct intel_atomic_state *state = to_intel_atomic_state(_state);
9874 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9875 struct intel_crtc *crtc;
9877 bool any_ms = false;
9879 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9880 new_crtc_state, i) {
9881 if (new_crtc_state->inherited != old_crtc_state->inherited)
9882 new_crtc_state->uapi.mode_changed = true;
9885 intel_vrr_check_modeset(state);
9887 ret = drm_atomic_helper_check_modeset(dev, &state->base);
9891 ret = intel_bigjoiner_add_affected_crtcs(state);
9895 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9896 new_crtc_state, i) {
9897 if (!intel_crtc_needs_modeset(new_crtc_state)) {
9899 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
9904 if (!new_crtc_state->uapi.enable) {
9905 if (!new_crtc_state->bigjoiner_slave) {
9906 intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
9912 ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
9916 ret = intel_modeset_pipe_config(state, new_crtc_state);
9920 ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
9926 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9927 new_crtc_state, i) {
9928 if (!intel_crtc_needs_modeset(new_crtc_state))
9931 ret = intel_modeset_pipe_config_late(new_crtc_state);
9935 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
9939 * Check if fastset is allowed by external dependencies like other
9940 * pipes and transcoders.
9942 * Right now it only forces a fullmodeset when the MST master
9943 * transcoder did not changed but the pipe of the master transcoder
9944 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
9945 * in case of port synced crtcs, if one of the synced crtcs
9946 * needs a full modeset, all other synced crtcs should be
9947 * forced a full modeset.
9949 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9950 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
9953 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
9954 enum transcoder master = new_crtc_state->mst_master_transcoder;
9956 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
9957 new_crtc_state->uapi.mode_changed = true;
9958 new_crtc_state->update_pipe = false;
9962 if (is_trans_port_sync_mode(new_crtc_state)) {
9963 u8 trans = new_crtc_state->sync_mode_slaves_mask;
9965 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
9966 trans |= BIT(new_crtc_state->master_transcoder);
9968 if (intel_cpu_transcoders_need_modeset(state, trans)) {
9969 new_crtc_state->uapi.mode_changed = true;
9970 new_crtc_state->update_pipe = false;
9974 if (new_crtc_state->bigjoiner) {
9975 struct intel_crtc_state *linked_crtc_state =
9976 intel_atomic_get_new_crtc_state(state, new_crtc_state->bigjoiner_linked_crtc);
9978 if (intel_crtc_needs_modeset(linked_crtc_state)) {
9979 new_crtc_state->uapi.mode_changed = true;
9980 new_crtc_state->update_pipe = false;
9985 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9986 new_crtc_state, i) {
9987 if (intel_crtc_needs_modeset(new_crtc_state)) {
9992 if (!new_crtc_state->update_pipe)
9995 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
9998 if (any_ms && !check_digital_port_conflicts(state)) {
9999 drm_dbg_kms(&dev_priv->drm,
10000 "rejecting conflicting digital port configuration\n");
10005 ret = drm_dp_mst_atomic_check(&state->base);
10009 ret = intel_atomic_check_planes(state);
10013 intel_fbc_choose_crtc(dev_priv, state);
10014 ret = calc_watermark_data(state);
10018 ret = intel_bw_atomic_check(state);
10022 ret = intel_atomic_check_cdclk(state, &any_ms);
10026 if (intel_any_crtc_needs_modeset(state))
10030 ret = intel_modeset_checks(state);
10034 ret = intel_modeset_calc_cdclk(state);
10038 intel_modeset_clear_plls(state);
10041 ret = intel_atomic_check_crtcs(state);
10045 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10046 new_crtc_state, i) {
10047 if (new_crtc_state->uapi.async_flip) {
10048 ret = intel_atomic_check_async(state);
10053 if (!intel_crtc_needs_modeset(new_crtc_state) &&
10054 !new_crtc_state->update_pipe)
10057 intel_dump_pipe_config(new_crtc_state, state,
10058 intel_crtc_needs_modeset(new_crtc_state) ?
10059 "[modeset]" : "[fastset]");
10065 if (ret == -EDEADLK)
10069 * FIXME would probably be nice to know which crtc specifically
10070 * caused the failure, in cases where we can pinpoint it.
10072 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10074 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
10079 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
10081 struct intel_crtc_state *crtc_state;
10082 struct intel_crtc *crtc;
10085 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
10089 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
10090 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
10092 if (mode_changed || crtc_state->update_pipe ||
10093 crtc_state->uapi.color_mgmt_changed) {
10094 intel_dsb_prepare(crtc_state);
10101 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
10102 struct intel_crtc_state *crtc_state)
10104 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10106 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
10107 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
10109 if (crtc_state->has_pch_encoder) {
10110 enum pipe pch_transcoder =
10111 intel_crtc_pch_transcoder(crtc);
10113 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
10117 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
10118 const struct intel_crtc_state *new_crtc_state)
10120 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
10121 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10124 * Update pipe size and adjust fitter if needed: the reason for this is
10125 * that in compute_mode_changes we check the native mode (not the pfit
10126 * mode) to see if we can flip rather than do a full mode set. In the
10127 * fastboot case, we'll flip, but if we don't update the pipesrc and
10128 * pfit state, we'll end up with a big fb scanned out into the wrong
10131 intel_set_pipe_src_size(new_crtc_state);
10133 /* on skylake this is done by detaching scalers */
10134 if (DISPLAY_VER(dev_priv) >= 9) {
10135 if (new_crtc_state->pch_pfit.enabled)
10136 skl_pfit_enable(new_crtc_state);
10137 } else if (HAS_PCH_SPLIT(dev_priv)) {
10138 if (new_crtc_state->pch_pfit.enabled)
10139 ilk_pfit_enable(new_crtc_state);
10140 else if (old_crtc_state->pch_pfit.enabled)
10141 ilk_pfit_disable(old_crtc_state);
10145 * The register is supposedly single buffered so perhaps
10146 * not 100% correct to do this here. But SKL+ calculate
10147 * this based on the adjust pixel rate so pfit changes do
10148 * affect it and so it must be updated for fastsets.
10149 * HSW/BDW only really need this here for fastboot, after
10150 * that the value should not change without a full modeset.
10152 if (DISPLAY_VER(dev_priv) >= 9 ||
10153 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
10154 hsw_set_linetime_wm(new_crtc_state);
10156 if (DISPLAY_VER(dev_priv) >= 11)
10157 icl_set_pipe_chicken(crtc);
10160 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
10161 struct intel_crtc *crtc)
10163 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10164 const struct intel_crtc_state *old_crtc_state =
10165 intel_atomic_get_old_crtc_state(state, crtc);
10166 const struct intel_crtc_state *new_crtc_state =
10167 intel_atomic_get_new_crtc_state(state, crtc);
10168 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10171 * During modesets pipe configuration was programmed as the
10172 * CRTC was enabled.
10175 if (new_crtc_state->uapi.color_mgmt_changed ||
10176 new_crtc_state->update_pipe)
10177 intel_color_commit(new_crtc_state);
10179 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
10180 bdw_set_pipemisc(new_crtc_state);
10182 if (new_crtc_state->update_pipe)
10183 intel_pipe_fastset(old_crtc_state, new_crtc_state);
10185 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
10188 if (dev_priv->display.atomic_update_watermarks)
10189 dev_priv->display.atomic_update_watermarks(state, crtc);
10192 static void commit_pipe_post_planes(struct intel_atomic_state *state,
10193 struct intel_crtc *crtc)
10195 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10196 const struct intel_crtc_state *new_crtc_state =
10197 intel_atomic_get_new_crtc_state(state, crtc);
10200 * Disable the scaler(s) after the plane(s) so that we don't
10201 * get a catastrophic underrun even if the two operations
10202 * end up happening in two different frames.
10204 if (DISPLAY_VER(dev_priv) >= 9 &&
10205 !intel_crtc_needs_modeset(new_crtc_state))
10206 skl_detach_scalers(new_crtc_state);
10209 static void intel_enable_crtc(struct intel_atomic_state *state,
10210 struct intel_crtc *crtc)
10212 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10213 const struct intel_crtc_state *new_crtc_state =
10214 intel_atomic_get_new_crtc_state(state, crtc);
10216 if (!intel_crtc_needs_modeset(new_crtc_state))
10219 intel_crtc_update_active_timings(new_crtc_state);
10221 dev_priv->display.crtc_enable(state, crtc);
10223 if (new_crtc_state->bigjoiner_slave)
10226 /* vblanks work again, re-enable pipe CRC. */
10227 intel_crtc_enable_pipe_crc(crtc);
10230 static void intel_update_crtc(struct intel_atomic_state *state,
10231 struct intel_crtc *crtc)
10233 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10234 const struct intel_crtc_state *old_crtc_state =
10235 intel_atomic_get_old_crtc_state(state, crtc);
10236 struct intel_crtc_state *new_crtc_state =
10237 intel_atomic_get_new_crtc_state(state, crtc);
10238 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10241 if (new_crtc_state->preload_luts &&
10242 (new_crtc_state->uapi.color_mgmt_changed ||
10243 new_crtc_state->update_pipe))
10244 intel_color_load_luts(new_crtc_state);
10246 intel_pre_plane_update(state, crtc);
10248 if (new_crtc_state->update_pipe)
10249 intel_encoders_update_pipe(state, crtc);
10252 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
10253 intel_fbc_disable(crtc);
10255 intel_fbc_enable(state, crtc);
10257 /* Perform vblank evasion around commit operation */
10258 intel_pipe_update_start(new_crtc_state);
10260 commit_pipe_pre_planes(state, crtc);
10262 if (DISPLAY_VER(dev_priv) >= 9)
10263 skl_update_planes_on_crtc(state, crtc);
10265 i9xx_update_planes_on_crtc(state, crtc);
10267 commit_pipe_post_planes(state, crtc);
10269 intel_pipe_update_end(new_crtc_state);
10272 * We usually enable FIFO underrun interrupts as part of the
10273 * CRTC enable sequence during modesets. But when we inherit a
10274 * valid pipe configuration from the BIOS we need to take care
10275 * of enabling them on the CRTC's first fastset.
10277 if (new_crtc_state->update_pipe && !modeset &&
10278 old_crtc_state->inherited)
10279 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
10282 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
10283 struct intel_crtc_state *old_crtc_state,
10284 struct intel_crtc_state *new_crtc_state,
10285 struct intel_crtc *crtc)
10287 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10289 drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
10291 intel_crtc_disable_planes(state, crtc);
10294 * We still need special handling for disabling bigjoiner master
10295 * and slaves since for slave we do not have encoder or plls
10296 * so we dont need to disable those.
10298 if (old_crtc_state->bigjoiner) {
10299 intel_crtc_disable_planes(state,
10300 old_crtc_state->bigjoiner_linked_crtc);
10301 old_crtc_state->bigjoiner_linked_crtc->active = false;
10305 * We need to disable pipe CRC before disabling the pipe,
10306 * or we race against vblank off.
10308 intel_crtc_disable_pipe_crc(crtc);
10310 dev_priv->display.crtc_disable(state, crtc);
10311 crtc->active = false;
10312 intel_fbc_disable(crtc);
10313 intel_disable_shared_dpll(old_crtc_state);
10315 /* FIXME unify this for all platforms */
10316 if (!new_crtc_state->hw.active &&
10317 !HAS_GMCH(dev_priv) &&
10318 dev_priv->display.initial_watermarks)
10319 dev_priv->display.initial_watermarks(state, crtc);
10322 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
10324 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10325 struct intel_crtc *crtc;
10329 /* Only disable port sync and MST slaves */
10330 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10331 new_crtc_state, i) {
10332 if (!intel_crtc_needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
10335 if (!old_crtc_state->hw.active)
10338 /* In case of Transcoder port Sync master slave CRTCs can be
10339 * assigned in any order and we need to make sure that
10340 * slave CRTCs are disabled first and then master CRTC since
10341 * Slave vblanks are masked till Master Vblanks.
10343 if (!is_trans_port_sync_slave(old_crtc_state) &&
10344 !intel_dp_mst_is_slave_trans(old_crtc_state))
10347 intel_pre_plane_update(state, crtc);
10348 intel_old_crtc_state_disables(state, old_crtc_state,
10349 new_crtc_state, crtc);
10350 handled |= BIT(crtc->pipe);
10353 /* Disable everything else left on */
10354 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10355 new_crtc_state, i) {
10356 if (!intel_crtc_needs_modeset(new_crtc_state) ||
10357 (handled & BIT(crtc->pipe)) ||
10358 old_crtc_state->bigjoiner_slave)
10361 intel_pre_plane_update(state, crtc);
10362 if (old_crtc_state->bigjoiner) {
10363 struct intel_crtc *slave =
10364 old_crtc_state->bigjoiner_linked_crtc;
10366 intel_pre_plane_update(state, slave);
10369 if (old_crtc_state->hw.active)
10370 intel_old_crtc_state_disables(state, old_crtc_state,
10371 new_crtc_state, crtc);
10375 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
10377 struct intel_crtc_state *new_crtc_state;
10378 struct intel_crtc *crtc;
10381 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10382 if (!new_crtc_state->hw.active)
10385 intel_enable_crtc(state, crtc);
10386 intel_update_crtc(state, crtc);
10390 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
10392 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10393 struct intel_crtc *crtc;
10394 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10395 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
10396 u8 update_pipes = 0, modeset_pipes = 0;
10399 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10400 enum pipe pipe = crtc->pipe;
10402 if (!new_crtc_state->hw.active)
10405 /* ignore allocations for crtc's that have been turned off. */
10406 if (!intel_crtc_needs_modeset(new_crtc_state)) {
10407 entries[pipe] = old_crtc_state->wm.skl.ddb;
10408 update_pipes |= BIT(pipe);
10410 modeset_pipes |= BIT(pipe);
10415 * Whenever the number of active pipes changes, we need to make sure we
10416 * update the pipes in the right order so that their ddb allocations
10417 * never overlap with each other between CRTC updates. Otherwise we'll
10418 * cause pipe underruns and other bad stuff.
10420 * So first lets enable all pipes that do not need a fullmodeset as
10421 * those don't have any external dependency.
10423 while (update_pipes) {
10424 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10425 new_crtc_state, i) {
10426 enum pipe pipe = crtc->pipe;
10428 if ((update_pipes & BIT(pipe)) == 0)
10431 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10432 entries, I915_MAX_PIPES, pipe))
10435 entries[pipe] = new_crtc_state->wm.skl.ddb;
10436 update_pipes &= ~BIT(pipe);
10438 intel_update_crtc(state, crtc);
10441 * If this is an already active pipe, it's DDB changed,
10442 * and this isn't the last pipe that needs updating
10443 * then we need to wait for a vblank to pass for the
10444 * new ddb allocation to take effect.
10446 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
10447 &old_crtc_state->wm.skl.ddb) &&
10448 (update_pipes | modeset_pipes))
10449 intel_wait_for_vblank(dev_priv, pipe);
10453 update_pipes = modeset_pipes;
10456 * Enable all pipes that needs a modeset and do not depends on other
10459 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10460 enum pipe pipe = crtc->pipe;
10462 if ((modeset_pipes & BIT(pipe)) == 0)
10465 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
10466 is_trans_port_sync_master(new_crtc_state) ||
10467 (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
10470 modeset_pipes &= ~BIT(pipe);
10472 intel_enable_crtc(state, crtc);
10476 * Then we enable all remaining pipes that depend on other
10477 * pipes: MST slaves and port sync masters, big joiner master
10479 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10480 enum pipe pipe = crtc->pipe;
10482 if ((modeset_pipes & BIT(pipe)) == 0)
10485 modeset_pipes &= ~BIT(pipe);
10487 intel_enable_crtc(state, crtc);
10491 * Finally we do the plane updates/etc. for all pipes that got enabled.
10493 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10494 enum pipe pipe = crtc->pipe;
10496 if ((update_pipes & BIT(pipe)) == 0)
10499 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10500 entries, I915_MAX_PIPES, pipe));
10502 entries[pipe] = new_crtc_state->wm.skl.ddb;
10503 update_pipes &= ~BIT(pipe);
10505 intel_update_crtc(state, crtc);
10508 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
10509 drm_WARN_ON(&dev_priv->drm, update_pipes);
10512 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
10514 struct intel_atomic_state *state, *next;
10515 struct llist_node *freed;
10517 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
10518 llist_for_each_entry_safe(state, next, freed, freed)
10519 drm_atomic_state_put(&state->base);
10522 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
10524 struct drm_i915_private *dev_priv =
10525 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
10527 intel_atomic_helper_free_state(dev_priv);
10530 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
10532 struct wait_queue_entry wait_fence, wait_reset;
10533 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
10535 init_wait_entry(&wait_fence, 0);
10536 init_wait_entry(&wait_reset, 0);
10538 prepare_to_wait(&intel_state->commit_ready.wait,
10539 &wait_fence, TASK_UNINTERRUPTIBLE);
10540 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10541 I915_RESET_MODESET),
10542 &wait_reset, TASK_UNINTERRUPTIBLE);
10545 if (i915_sw_fence_done(&intel_state->commit_ready) ||
10546 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
10551 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
10552 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10553 I915_RESET_MODESET),
10557 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
10559 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10560 struct intel_crtc *crtc;
10563 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10565 intel_dsb_cleanup(old_crtc_state);
10568 static void intel_atomic_cleanup_work(struct work_struct *work)
10570 struct intel_atomic_state *state =
10571 container_of(work, struct intel_atomic_state, base.commit_work);
10572 struct drm_i915_private *i915 = to_i915(state->base.dev);
10574 intel_cleanup_dsbs(state);
10575 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
10576 drm_atomic_helper_commit_cleanup_done(&state->base);
10577 drm_atomic_state_put(&state->base);
10579 intel_atomic_helper_free_state(i915);
10582 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
10584 struct drm_i915_private *i915 = to_i915(state->base.dev);
10585 struct intel_plane *plane;
10586 struct intel_plane_state *plane_state;
10589 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
10590 struct drm_framebuffer *fb = plane_state->hw.fb;
10594 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
10598 * The layout of the fast clear color value expected by HW
10599 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2):
10600 * - 4 x 4 bytes per-channel value
10601 * (in surface type specific float/int format provided by the fb user)
10602 * - 8 bytes native color value used by the display
10603 * (converted/written by GPU during a fast clear operation using the
10604 * above per-channel values)
10606 * The commit's FB prepare hook already ensured that FB obj is pinned and the
10607 * caller made sure that the object is synced wrt. the related color clear value
10610 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
10611 fb->offsets[2] + 16,
10612 &plane_state->ccval,
10613 sizeof(plane_state->ccval));
10614 /* The above could only fail if the FB obj has an unexpected backing store type. */
10615 drm_WARN_ON(&i915->drm, ret);
10619 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
10621 struct drm_device *dev = state->base.dev;
10622 struct drm_i915_private *dev_priv = to_i915(dev);
10623 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10624 struct intel_crtc *crtc;
10625 u64 put_domains[I915_MAX_PIPES] = {};
10626 intel_wakeref_t wakeref = 0;
10629 intel_atomic_commit_fence_wait(state);
10631 drm_atomic_helper_wait_for_dependencies(&state->base);
10633 if (state->modeset)
10634 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
10636 intel_atomic_prepare_plane_clear_colors(state);
10638 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10639 new_crtc_state, i) {
10640 if (intel_crtc_needs_modeset(new_crtc_state) ||
10641 new_crtc_state->update_pipe) {
10643 put_domains[crtc->pipe] =
10644 modeset_get_crtc_power_domains(new_crtc_state);
10648 intel_commit_modeset_disables(state);
10650 /* FIXME: Eventually get rid of our crtc->config pointer */
10651 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10652 crtc->config = new_crtc_state;
10654 if (state->modeset) {
10655 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
10657 intel_set_cdclk_pre_plane_update(state);
10659 intel_modeset_verify_disabled(dev_priv, state);
10662 intel_sagv_pre_plane_update(state);
10664 /* Complete the events for pipes that have now been disabled */
10665 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10666 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10668 /* Complete events for now disable pipes here. */
10669 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
10670 spin_lock_irq(&dev->event_lock);
10671 drm_crtc_send_vblank_event(&crtc->base,
10672 new_crtc_state->uapi.event);
10673 spin_unlock_irq(&dev->event_lock);
10675 new_crtc_state->uapi.event = NULL;
10679 if (state->modeset)
10680 intel_encoders_update_prepare(state);
10682 intel_dbuf_pre_plane_update(state);
10684 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10685 if (new_crtc_state->uapi.async_flip)
10686 intel_crtc_enable_flip_done(state, crtc);
10689 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10690 dev_priv->display.commit_modeset_enables(state);
10692 if (state->modeset) {
10693 intel_encoders_update_complete(state);
10695 intel_set_cdclk_post_plane_update(state);
10698 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
10699 * already, but still need the state for the delayed optimization. To
10701 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
10702 * - schedule that vblank worker _before_ calling hw_done
10703 * - at the start of commit_tail, cancel it _synchrously
10704 * - switch over to the vblank wait helper in the core after that since
10705 * we don't need out special handling any more.
10707 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
10709 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10710 if (new_crtc_state->uapi.async_flip)
10711 intel_crtc_disable_flip_done(state, crtc);
10713 if (new_crtc_state->hw.active &&
10714 !intel_crtc_needs_modeset(new_crtc_state) &&
10715 !new_crtc_state->preload_luts &&
10716 (new_crtc_state->uapi.color_mgmt_changed ||
10717 new_crtc_state->update_pipe))
10718 intel_color_load_luts(new_crtc_state);
10722 * Now that the vblank has passed, we can go ahead and program the
10723 * optimal watermarks on platforms that need two-step watermark
10726 * TODO: Move this (and other cleanup) to an async worker eventually.
10728 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10729 new_crtc_state, i) {
10731 * Gen2 reports pipe underruns whenever all planes are disabled.
10732 * So re-enable underrun reporting after some planes get enabled.
10734 * We do this before .optimize_watermarks() so that we have a
10735 * chance of catching underruns with the intermediate watermarks
10736 * vs. the new plane configuration.
10738 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
10739 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
10741 if (dev_priv->display.optimize_watermarks)
10742 dev_priv->display.optimize_watermarks(state, crtc);
10745 intel_dbuf_post_plane_update(state);
10747 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10748 intel_post_plane_update(state, crtc);
10750 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
10752 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
10755 * DSB cleanup is done in cleanup_work aligning with framebuffer
10756 * cleanup. So copy and reset the dsb structure to sync with
10757 * commit_done and later do dsb cleanup in cleanup_work.
10759 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
10762 /* Underruns don't always raise interrupts, so check manually */
10763 intel_check_cpu_fifo_underruns(dev_priv);
10764 intel_check_pch_fifo_underruns(dev_priv);
10766 if (state->modeset)
10767 intel_verify_planes(state);
10769 intel_sagv_post_plane_update(state);
10771 drm_atomic_helper_commit_hw_done(&state->base);
10773 if (state->modeset) {
10774 /* As one of the primary mmio accessors, KMS has a high
10775 * likelihood of triggering bugs in unclaimed access. After we
10776 * finish modesetting, see if an error has been flagged, and if
10777 * so enable debugging for the next modeset - and hope we catch
10780 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
10781 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
10783 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10786 * Defer the cleanup of the old state to a separate worker to not
10787 * impede the current task (userspace for blocking modesets) that
10788 * are executed inline. For out-of-line asynchronous modesets/flips,
10789 * deferring to a new worker seems overkill, but we would place a
10790 * schedule point (cond_resched()) here anyway to keep latencies
10793 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
10794 queue_work(system_highpri_wq, &state->base.commit_work);
10797 static void intel_atomic_commit_work(struct work_struct *work)
10799 struct intel_atomic_state *state =
10800 container_of(work, struct intel_atomic_state, base.commit_work);
10802 intel_atomic_commit_tail(state);
10805 static int __i915_sw_fence_call
10806 intel_atomic_commit_ready(struct i915_sw_fence *fence,
10807 enum i915_sw_fence_notify notify)
10809 struct intel_atomic_state *state =
10810 container_of(fence, struct intel_atomic_state, commit_ready);
10813 case FENCE_COMPLETE:
10814 /* we do blocking waits in the worker, nothing to do here */
10818 struct intel_atomic_helper *helper =
10819 &to_i915(state->base.dev)->atomic_helper;
10821 if (llist_add(&state->freed, &helper->free_list))
10822 schedule_work(&helper->free_work);
10827 return NOTIFY_DONE;
10830 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
10832 struct intel_plane_state *old_plane_state, *new_plane_state;
10833 struct intel_plane *plane;
10836 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
10837 new_plane_state, i)
10838 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
10839 to_intel_frontbuffer(new_plane_state->hw.fb),
10840 plane->frontbuffer_bit);
10843 static int intel_atomic_commit(struct drm_device *dev,
10844 struct drm_atomic_state *_state,
10847 struct intel_atomic_state *state = to_intel_atomic_state(_state);
10848 struct drm_i915_private *dev_priv = to_i915(dev);
10851 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
10853 drm_atomic_state_get(&state->base);
10854 i915_sw_fence_init(&state->commit_ready,
10855 intel_atomic_commit_ready);
10858 * The intel_legacy_cursor_update() fast path takes care
10859 * of avoiding the vblank waits for simple cursor
10860 * movement and flips. For cursor on/off and size changes,
10861 * we want to perform the vblank waits so that watermark
10862 * updates happen during the correct frames. Gen9+ have
10863 * double buffered watermarks and so shouldn't need this.
10865 * Unset state->legacy_cursor_update before the call to
10866 * drm_atomic_helper_setup_commit() because otherwise
10867 * drm_atomic_helper_wait_for_flip_done() is a noop and
10868 * we get FIFO underruns because we didn't wait
10871 * FIXME doing watermarks and fb cleanup from a vblank worker
10872 * (assuming we had any) would solve these problems.
10874 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
10875 struct intel_crtc_state *new_crtc_state;
10876 struct intel_crtc *crtc;
10879 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10880 if (new_crtc_state->wm.need_postvbl_update ||
10881 new_crtc_state->update_wm_post)
10882 state->base.legacy_cursor_update = false;
10885 ret = intel_atomic_prepare_commit(state);
10887 drm_dbg_atomic(&dev_priv->drm,
10888 "Preparing state failed with %i\n", ret);
10889 i915_sw_fence_commit(&state->commit_ready);
10890 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10894 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
10896 ret = drm_atomic_helper_swap_state(&state->base, true);
10898 intel_atomic_swap_global_state(state);
10901 struct intel_crtc_state *new_crtc_state;
10902 struct intel_crtc *crtc;
10905 i915_sw_fence_commit(&state->commit_ready);
10907 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10908 intel_dsb_cleanup(new_crtc_state);
10910 drm_atomic_helper_cleanup_planes(dev, &state->base);
10911 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10914 intel_shared_dpll_swap_state(state);
10915 intel_atomic_track_fbs(state);
10917 drm_atomic_state_get(&state->base);
10918 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
10920 i915_sw_fence_commit(&state->commit_ready);
10921 if (nonblock && state->modeset) {
10922 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
10923 } else if (nonblock) {
10924 queue_work(dev_priv->flip_wq, &state->base.commit_work);
10926 if (state->modeset)
10927 flush_workqueue(dev_priv->modeset_wq);
10928 intel_atomic_commit_tail(state);
10934 struct wait_rps_boost {
10935 struct wait_queue_entry wait;
10937 struct drm_crtc *crtc;
10938 struct i915_request *request;
10941 static int do_rps_boost(struct wait_queue_entry *_wait,
10942 unsigned mode, int sync, void *key)
10944 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
10945 struct i915_request *rq = wait->request;
10948 * If we missed the vblank, but the request is already running it
10949 * is reasonable to assume that it will complete before the next
10950 * vblank without our intervention, so leave RPS alone.
10952 if (!i915_request_started(rq))
10953 intel_rps_boost(rq);
10954 i915_request_put(rq);
10956 drm_crtc_vblank_put(wait->crtc);
10958 list_del(&wait->wait.entry);
10963 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
10964 struct dma_fence *fence)
10966 struct wait_rps_boost *wait;
10968 if (!dma_fence_is_i915(fence))
10971 if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
10974 if (drm_crtc_vblank_get(crtc))
10977 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
10979 drm_crtc_vblank_put(crtc);
10983 wait->request = to_request(dma_fence_get(fence));
10986 wait->wait.func = do_rps_boost;
10987 wait->wait.flags = 0;
10989 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
10992 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
10994 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
10995 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10996 struct drm_framebuffer *fb = plane_state->hw.fb;
10997 struct i915_vma *vma;
10999 plane->id == PLANE_CURSOR &&
11000 INTEL_INFO(dev_priv)->display.cursor_needs_physical;
11002 if (!intel_fb_uses_dpt(fb)) {
11003 vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
11004 &plane_state->view.gtt,
11005 intel_plane_uses_fence(plane_state),
11006 &plane_state->flags);
11008 return PTR_ERR(vma);
11010 plane_state->ggtt_vma = vma;
11012 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11014 vma = intel_dpt_pin(intel_fb->dpt_vm);
11016 return PTR_ERR(vma);
11018 plane_state->ggtt_vma = vma;
11020 vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
11021 &plane_state->flags, intel_fb->dpt_vm);
11023 intel_dpt_unpin(intel_fb->dpt_vm);
11024 plane_state->ggtt_vma = NULL;
11025 return PTR_ERR(vma);
11028 plane_state->dpt_vma = vma;
11030 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
11036 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
11038 struct drm_framebuffer *fb = old_plane_state->hw.fb;
11039 struct i915_vma *vma;
11041 if (!intel_fb_uses_dpt(fb)) {
11042 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
11044 intel_unpin_fb_vma(vma, old_plane_state->flags);
11046 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11048 vma = fetch_and_zero(&old_plane_state->dpt_vma);
11050 intel_unpin_fb_vma(vma, old_plane_state->flags);
11052 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
11054 intel_dpt_unpin(intel_fb->dpt_vm);
11059 * intel_prepare_plane_fb - Prepare fb for usage on plane
11060 * @_plane: drm plane to prepare for
11061 * @_new_plane_state: the plane state being prepared
11063 * Prepares a framebuffer for usage on a display plane. Generally this
11064 * involves pinning the underlying object and updating the frontbuffer tracking
11065 * bits. Some older platforms need special physical address handling for
11068 * Returns 0 on success, negative error code on failure.
11071 intel_prepare_plane_fb(struct drm_plane *_plane,
11072 struct drm_plane_state *_new_plane_state)
11074 struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
11075 struct intel_plane *plane = to_intel_plane(_plane);
11076 struct intel_plane_state *new_plane_state =
11077 to_intel_plane_state(_new_plane_state);
11078 struct intel_atomic_state *state =
11079 to_intel_atomic_state(new_plane_state->uapi.state);
11080 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11081 const struct intel_plane_state *old_plane_state =
11082 intel_atomic_get_old_plane_state(state, plane);
11083 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
11084 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
11088 const struct intel_crtc_state *crtc_state =
11089 intel_atomic_get_new_crtc_state(state,
11090 to_intel_crtc(old_plane_state->hw.crtc));
11092 /* Big Hammer, we also need to ensure that any pending
11093 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
11094 * current scanout is retired before unpinning the old
11095 * framebuffer. Note that we rely on userspace rendering
11096 * into the buffer attached to the pipe they are waiting
11097 * on. If not, userspace generates a GPU hang with IPEHR
11098 * point to the MI_WAIT_FOR_EVENT.
11100 * This should only fail upon a hung GPU, in which case we
11101 * can safely continue.
11103 if (intel_crtc_needs_modeset(crtc_state)) {
11104 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11105 old_obj->base.resv, NULL,
11113 if (new_plane_state->uapi.fence) { /* explicit fencing */
11114 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
11116 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
11117 new_plane_state->uapi.fence,
11118 i915_fence_timeout(dev_priv),
11128 ret = intel_plane_pin_fb(new_plane_state);
11132 i915_gem_object_wait_priority(obj, 0, &attr);
11133 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
11135 if (!new_plane_state->uapi.fence) { /* implicit fencing */
11136 struct dma_fence *fence;
11138 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11139 obj->base.resv, NULL,
11141 i915_fence_timeout(dev_priv),
11146 fence = dma_resv_get_excl_unlocked(obj->base.resv);
11148 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11150 dma_fence_put(fence);
11153 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11154 new_plane_state->uapi.fence);
11158 * We declare pageflips to be interactive and so merit a small bias
11159 * towards upclocking to deliver the frame on time. By only changing
11160 * the RPS thresholds to sample more regularly and aim for higher
11161 * clocks we can hopefully deliver low power workloads (like kodi)
11162 * that are not quite steady state without resorting to forcing
11163 * maximum clocks following a vblank miss (see do_rps_boost()).
11165 if (!state->rps_interactive) {
11166 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
11167 state->rps_interactive = true;
11173 intel_plane_unpin_fb(new_plane_state);
11179 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11180 * @plane: drm plane to clean up for
11181 * @_old_plane_state: the state from the previous modeset
11183 * Cleans up a framebuffer that has just been removed from a plane.
11186 intel_cleanup_plane_fb(struct drm_plane *plane,
11187 struct drm_plane_state *_old_plane_state)
11189 struct intel_plane_state *old_plane_state =
11190 to_intel_plane_state(_old_plane_state);
11191 struct intel_atomic_state *state =
11192 to_intel_atomic_state(old_plane_state->uapi.state);
11193 struct drm_i915_private *dev_priv = to_i915(plane->dev);
11194 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
11199 if (state->rps_interactive) {
11200 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
11201 state->rps_interactive = false;
11204 /* Should only be called after a successful intel_prepare_plane_fb()! */
11205 intel_plane_unpin_fb(old_plane_state);
11209 * intel_plane_destroy - destroy a plane
11210 * @plane: plane to destroy
11212 * Common destruction function for all types of planes (primary, cursor,
11215 void intel_plane_destroy(struct drm_plane *plane)
11217 drm_plane_cleanup(plane);
11218 kfree(to_intel_plane(plane));
11221 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
11223 struct intel_plane *plane;
11225 for_each_intel_plane(&dev_priv->drm, plane) {
11226 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11229 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
11234 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
11235 struct drm_file *file)
11237 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11238 struct drm_crtc *drmmode_crtc;
11239 struct intel_crtc *crtc;
11241 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
11245 crtc = to_intel_crtc(drmmode_crtc);
11246 pipe_from_crtc_id->pipe = crtc->pipe;
11251 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
11253 struct drm_device *dev = encoder->base.dev;
11254 struct intel_encoder *source_encoder;
11255 u32 possible_clones = 0;
11257 for_each_intel_encoder(dev, source_encoder) {
11258 if (encoders_cloneable(encoder, source_encoder))
11259 possible_clones |= drm_encoder_mask(&source_encoder->base);
11262 return possible_clones;
11265 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
11267 struct drm_device *dev = encoder->base.dev;
11268 struct intel_crtc *crtc;
11269 u32 possible_crtcs = 0;
11271 for_each_intel_crtc(dev, crtc) {
11272 if (encoder->pipe_mask & BIT(crtc->pipe))
11273 possible_crtcs |= drm_crtc_mask(&crtc->base);
11276 return possible_crtcs;
11279 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
11281 if (!IS_MOBILE(dev_priv))
11284 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
11287 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
11293 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
11295 if (DISPLAY_VER(dev_priv) >= 9)
11298 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
11301 if (HAS_PCH_LPT_H(dev_priv) &&
11302 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
11305 /* DDI E can't be used if DDI A requires 4 lanes */
11306 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
11309 if (!dev_priv->vbt.int_crt_support)
11315 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
11317 struct intel_encoder *encoder;
11318 bool dpd_is_edp = false;
11320 intel_pps_unlock_regs_wa(dev_priv);
11322 if (!HAS_DISPLAY(dev_priv))
11325 if (IS_ALDERLAKE_P(dev_priv)) {
11326 intel_ddi_init(dev_priv, PORT_A);
11327 intel_ddi_init(dev_priv, PORT_B);
11328 intel_ddi_init(dev_priv, PORT_TC1);
11329 intel_ddi_init(dev_priv, PORT_TC2);
11330 intel_ddi_init(dev_priv, PORT_TC3);
11331 intel_ddi_init(dev_priv, PORT_TC4);
11332 } else if (IS_ALDERLAKE_S(dev_priv)) {
11333 intel_ddi_init(dev_priv, PORT_A);
11334 intel_ddi_init(dev_priv, PORT_TC1);
11335 intel_ddi_init(dev_priv, PORT_TC2);
11336 intel_ddi_init(dev_priv, PORT_TC3);
11337 intel_ddi_init(dev_priv, PORT_TC4);
11338 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
11339 intel_ddi_init(dev_priv, PORT_A);
11340 intel_ddi_init(dev_priv, PORT_B);
11341 intel_ddi_init(dev_priv, PORT_TC1);
11342 intel_ddi_init(dev_priv, PORT_TC2);
11343 } else if (DISPLAY_VER(dev_priv) >= 12) {
11344 intel_ddi_init(dev_priv, PORT_A);
11345 intel_ddi_init(dev_priv, PORT_B);
11346 intel_ddi_init(dev_priv, PORT_TC1);
11347 intel_ddi_init(dev_priv, PORT_TC2);
11348 intel_ddi_init(dev_priv, PORT_TC3);
11349 intel_ddi_init(dev_priv, PORT_TC4);
11350 intel_ddi_init(dev_priv, PORT_TC5);
11351 intel_ddi_init(dev_priv, PORT_TC6);
11352 icl_dsi_init(dev_priv);
11353 } else if (IS_JSL_EHL(dev_priv)) {
11354 intel_ddi_init(dev_priv, PORT_A);
11355 intel_ddi_init(dev_priv, PORT_B);
11356 intel_ddi_init(dev_priv, PORT_C);
11357 intel_ddi_init(dev_priv, PORT_D);
11358 icl_dsi_init(dev_priv);
11359 } else if (DISPLAY_VER(dev_priv) == 11) {
11360 intel_ddi_init(dev_priv, PORT_A);
11361 intel_ddi_init(dev_priv, PORT_B);
11362 intel_ddi_init(dev_priv, PORT_C);
11363 intel_ddi_init(dev_priv, PORT_D);
11364 intel_ddi_init(dev_priv, PORT_E);
11365 intel_ddi_init(dev_priv, PORT_F);
11366 icl_dsi_init(dev_priv);
11367 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
11368 intel_ddi_init(dev_priv, PORT_A);
11369 intel_ddi_init(dev_priv, PORT_B);
11370 intel_ddi_init(dev_priv, PORT_C);
11371 vlv_dsi_init(dev_priv);
11372 } else if (DISPLAY_VER(dev_priv) >= 9) {
11373 intel_ddi_init(dev_priv, PORT_A);
11374 intel_ddi_init(dev_priv, PORT_B);
11375 intel_ddi_init(dev_priv, PORT_C);
11376 intel_ddi_init(dev_priv, PORT_D);
11377 intel_ddi_init(dev_priv, PORT_E);
11378 intel_ddi_init(dev_priv, PORT_F);
11379 } else if (HAS_DDI(dev_priv)) {
11382 if (intel_ddi_crt_present(dev_priv))
11383 intel_crt_init(dev_priv);
11385 /* Haswell uses DDI functions to detect digital outputs. */
11386 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
11388 intel_ddi_init(dev_priv, PORT_A);
11390 found = intel_de_read(dev_priv, SFUSE_STRAP);
11391 if (found & SFUSE_STRAP_DDIB_DETECTED)
11392 intel_ddi_init(dev_priv, PORT_B);
11393 if (found & SFUSE_STRAP_DDIC_DETECTED)
11394 intel_ddi_init(dev_priv, PORT_C);
11395 if (found & SFUSE_STRAP_DDID_DETECTED)
11396 intel_ddi_init(dev_priv, PORT_D);
11397 if (found & SFUSE_STRAP_DDIF_DETECTED)
11398 intel_ddi_init(dev_priv, PORT_F);
11399 } else if (HAS_PCH_SPLIT(dev_priv)) {
11403 * intel_edp_init_connector() depends on this completing first,
11404 * to prevent the registration of both eDP and LVDS and the
11405 * incorrect sharing of the PPS.
11407 intel_lvds_init(dev_priv);
11408 intel_crt_init(dev_priv);
11410 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
11412 if (ilk_has_edp_a(dev_priv))
11413 g4x_dp_init(dev_priv, DP_A, PORT_A);
11415 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
11416 /* PCH SDVOB multiplex with HDMIB */
11417 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
11419 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
11420 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
11421 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
11424 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
11425 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
11427 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
11428 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
11430 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
11431 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
11433 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
11434 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
11435 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
11436 bool has_edp, has_port;
11438 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
11439 intel_crt_init(dev_priv);
11442 * The DP_DETECTED bit is the latched state of the DDC
11443 * SDA pin at boot. However since eDP doesn't require DDC
11444 * (no way to plug in a DP->HDMI dongle) the DDC pins for
11445 * eDP ports may have been muxed to an alternate function.
11446 * Thus we can't rely on the DP_DETECTED bit alone to detect
11447 * eDP ports. Consult the VBT as well as DP_DETECTED to
11448 * detect eDP ports.
11450 * Sadly the straps seem to be missing sometimes even for HDMI
11451 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
11452 * and VBT for the presence of the port. Additionally we can't
11453 * trust the port type the VBT declares as we've seen at least
11454 * HDMI ports that the VBT claim are DP or eDP.
11456 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
11457 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
11458 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
11459 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
11460 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
11461 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
11463 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
11464 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
11465 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
11466 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
11467 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
11468 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
11470 if (IS_CHERRYVIEW(dev_priv)) {
11472 * eDP not supported on port D,
11473 * so no need to worry about it
11475 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
11476 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
11477 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
11478 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
11479 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
11482 vlv_dsi_init(dev_priv);
11483 } else if (IS_PINEVIEW(dev_priv)) {
11484 intel_lvds_init(dev_priv);
11485 intel_crt_init(dev_priv);
11486 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
11487 bool found = false;
11489 if (IS_MOBILE(dev_priv))
11490 intel_lvds_init(dev_priv);
11492 intel_crt_init(dev_priv);
11494 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11495 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
11496 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
11497 if (!found && IS_G4X(dev_priv)) {
11498 drm_dbg_kms(&dev_priv->drm,
11499 "probing HDMI on SDVOB\n");
11500 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
11503 if (!found && IS_G4X(dev_priv))
11504 g4x_dp_init(dev_priv, DP_B, PORT_B);
11507 /* Before G4X SDVOC doesn't have its own detect register */
11509 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11510 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
11511 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
11514 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
11516 if (IS_G4X(dev_priv)) {
11517 drm_dbg_kms(&dev_priv->drm,
11518 "probing HDMI on SDVOC\n");
11519 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
11521 if (IS_G4X(dev_priv))
11522 g4x_dp_init(dev_priv, DP_C, PORT_C);
11525 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
11526 g4x_dp_init(dev_priv, DP_D, PORT_D);
11528 if (SUPPORTS_TV(dev_priv))
11529 intel_tv_init(dev_priv);
11530 } else if (DISPLAY_VER(dev_priv) == 2) {
11531 if (IS_I85X(dev_priv))
11532 intel_lvds_init(dev_priv);
11534 intel_crt_init(dev_priv);
11535 intel_dvo_init(dev_priv);
11538 for_each_intel_encoder(&dev_priv->drm, encoder) {
11539 encoder->base.possible_crtcs =
11540 intel_encoder_possible_crtcs(encoder);
11541 encoder->base.possible_clones =
11542 intel_encoder_possible_clones(encoder);
11545 intel_init_pch_refclk(dev_priv);
11547 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
11550 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11552 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11554 drm_framebuffer_cleanup(fb);
11556 if (intel_fb_uses_dpt(fb))
11557 intel_dpt_destroy(intel_fb->dpt_vm);
11559 intel_frontbuffer_put(intel_fb->frontbuffer);
11564 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11565 struct drm_file *file,
11566 unsigned int *handle)
11568 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11569 struct drm_i915_private *i915 = to_i915(obj->base.dev);
11571 if (i915_gem_object_is_userptr(obj)) {
11572 drm_dbg(&i915->drm,
11573 "attempting to use a userptr for a framebuffer, denied\n");
11577 return drm_gem_handle_create(file, &obj->base, handle);
11580 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
11581 struct drm_file *file,
11582 unsigned flags, unsigned color,
11583 struct drm_clip_rect *clips,
11584 unsigned num_clips)
11586 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11588 i915_gem_object_flush_if_display(obj);
11589 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
11594 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11595 .destroy = intel_user_framebuffer_destroy,
11596 .create_handle = intel_user_framebuffer_create_handle,
11597 .dirty = intel_user_framebuffer_dirty,
11600 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
11601 struct drm_i915_gem_object *obj,
11602 struct drm_mode_fb_cmd2 *mode_cmd)
11604 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
11605 struct drm_framebuffer *fb = &intel_fb->base;
11607 unsigned int tiling, stride;
11611 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
11612 if (!intel_fb->frontbuffer)
11615 i915_gem_object_lock(obj, NULL);
11616 tiling = i915_gem_object_get_tiling(obj);
11617 stride = i915_gem_object_get_stride(obj);
11618 i915_gem_object_unlock(obj);
11620 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
11622 * If there's a fence, enforce that
11623 * the fb modifier and tiling mode match.
11625 if (tiling != I915_TILING_NONE &&
11626 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11627 drm_dbg_kms(&dev_priv->drm,
11628 "tiling_mode doesn't match fb modifier\n");
11632 if (tiling == I915_TILING_X) {
11633 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
11634 } else if (tiling == I915_TILING_Y) {
11635 drm_dbg_kms(&dev_priv->drm,
11636 "No Y tiling for legacy addfb\n");
11641 if (!drm_any_plane_has_format(&dev_priv->drm,
11642 mode_cmd->pixel_format,
11643 mode_cmd->modifier[0])) {
11644 drm_dbg_kms(&dev_priv->drm,
11645 "unsupported pixel format %p4cc / modifier 0x%llx\n",
11646 &mode_cmd->pixel_format, mode_cmd->modifier[0]);
11651 * gen2/3 display engine uses the fence if present,
11652 * so the tiling mode must match the fb modifier exactly.
11654 if (DISPLAY_VER(dev_priv) < 4 &&
11655 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11656 drm_dbg_kms(&dev_priv->drm,
11657 "tiling_mode must match fb modifier exactly on gen2/3\n");
11661 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
11662 mode_cmd->modifier[0]);
11663 if (mode_cmd->pitches[0] > max_stride) {
11664 drm_dbg_kms(&dev_priv->drm,
11665 "%s pitch (%u) must be at most %d\n",
11666 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
11667 "tiled" : "linear",
11668 mode_cmd->pitches[0], max_stride);
11673 * If there's a fence, enforce that
11674 * the fb pitch and fence stride match.
11676 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
11677 drm_dbg_kms(&dev_priv->drm,
11678 "pitch (%d) must match tiling stride (%d)\n",
11679 mode_cmd->pitches[0], stride);
11683 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11684 if (mode_cmd->offsets[0] != 0) {
11685 drm_dbg_kms(&dev_priv->drm,
11686 "plane 0 offset (0x%08x) must be 0\n",
11687 mode_cmd->offsets[0]);
11691 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
11693 for (i = 0; i < fb->format->num_planes; i++) {
11694 u32 stride_alignment;
11696 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
11697 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
11702 stride_alignment = intel_fb_stride_alignment(fb, i);
11703 if (fb->pitches[i] & (stride_alignment - 1)) {
11704 drm_dbg_kms(&dev_priv->drm,
11705 "plane %d pitch (%d) must be at least %u byte aligned\n",
11706 i, fb->pitches[i], stride_alignment);
11710 if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
11711 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
11713 if (fb->pitches[i] != ccs_aux_stride) {
11714 drm_dbg_kms(&dev_priv->drm,
11715 "ccs aux plane %d pitch (%d) must be %d\n",
11717 fb->pitches[i], ccs_aux_stride);
11722 /* TODO: Add POT stride remapping support for CCS formats as well. */
11723 if (IS_ALDERLAKE_P(dev_priv) &&
11724 mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
11725 !intel_fb_needs_pot_stride_remap(intel_fb) &&
11726 !is_power_of_2(mode_cmd->pitches[i])) {
11727 drm_dbg_kms(&dev_priv->drm,
11728 "plane %d pitch (%d) must be power of two for tiled buffers\n",
11729 i, mode_cmd->pitches[i]);
11733 fb->obj[i] = &obj->base;
11736 ret = intel_fill_fb_info(dev_priv, intel_fb);
11740 if (intel_fb_uses_dpt(fb)) {
11741 struct i915_address_space *vm;
11743 vm = intel_dpt_create(intel_fb);
11749 intel_fb->dpt_vm = vm;
11752 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
11754 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
11761 intel_frontbuffer_put(intel_fb->frontbuffer);
11765 static struct drm_framebuffer *
11766 intel_user_framebuffer_create(struct drm_device *dev,
11767 struct drm_file *filp,
11768 const struct drm_mode_fb_cmd2 *user_mode_cmd)
11770 struct drm_framebuffer *fb;
11771 struct drm_i915_gem_object *obj;
11772 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
11773 struct drm_i915_private *i915;
11775 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
11777 return ERR_PTR(-ENOENT);
11779 /* object is backed with LMEM for discrete */
11780 i915 = to_i915(obj->base.dev);
11781 if (HAS_LMEM(i915) && !i915_gem_object_validates_to_lmem(obj)) {
11782 /* object is "remote", not in local memory */
11783 i915_gem_object_put(obj);
11784 return ERR_PTR(-EREMOTE);
11787 fb = intel_framebuffer_create(obj, &mode_cmd);
11788 i915_gem_object_put(obj);
11793 static enum drm_mode_status
11794 intel_mode_valid(struct drm_device *dev,
11795 const struct drm_display_mode *mode)
11797 struct drm_i915_private *dev_priv = to_i915(dev);
11798 int hdisplay_max, htotal_max;
11799 int vdisplay_max, vtotal_max;
11802 * Can't reject DBLSCAN here because Xorg ddxen can add piles
11803 * of DBLSCAN modes to the output's mode list when they detect
11804 * the scaling mode property on the connector. And they don't
11805 * ask the kernel to validate those modes in any way until
11806 * modeset time at which point the client gets a protocol error.
11807 * So in order to not upset those clients we silently ignore the
11808 * DBLSCAN flag on such connectors. For other connectors we will
11809 * reject modes with the DBLSCAN flag in encoder->compute_config().
11810 * And we always reject DBLSCAN modes in connector->mode_valid()
11811 * as we never want such modes on the connector's mode list.
11814 if (mode->vscan > 1)
11815 return MODE_NO_VSCAN;
11817 if (mode->flags & DRM_MODE_FLAG_HSKEW)
11818 return MODE_H_ILLEGAL;
11820 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
11821 DRM_MODE_FLAG_NCSYNC |
11822 DRM_MODE_FLAG_PCSYNC))
11825 if (mode->flags & (DRM_MODE_FLAG_BCAST |
11826 DRM_MODE_FLAG_PIXMUX |
11827 DRM_MODE_FLAG_CLKDIV2))
11830 /* Transcoder timing limits */
11831 if (DISPLAY_VER(dev_priv) >= 11) {
11832 hdisplay_max = 16384;
11833 vdisplay_max = 8192;
11834 htotal_max = 16384;
11836 } else if (DISPLAY_VER(dev_priv) >= 9 ||
11837 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
11838 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
11839 vdisplay_max = 4096;
11842 } else if (DISPLAY_VER(dev_priv) >= 3) {
11843 hdisplay_max = 4096;
11844 vdisplay_max = 4096;
11848 hdisplay_max = 2048;
11849 vdisplay_max = 2048;
11854 if (mode->hdisplay > hdisplay_max ||
11855 mode->hsync_start > htotal_max ||
11856 mode->hsync_end > htotal_max ||
11857 mode->htotal > htotal_max)
11858 return MODE_H_ILLEGAL;
11860 if (mode->vdisplay > vdisplay_max ||
11861 mode->vsync_start > vtotal_max ||
11862 mode->vsync_end > vtotal_max ||
11863 mode->vtotal > vtotal_max)
11864 return MODE_V_ILLEGAL;
11866 if (DISPLAY_VER(dev_priv) >= 5) {
11867 if (mode->hdisplay < 64 ||
11868 mode->htotal - mode->hdisplay < 32)
11869 return MODE_H_ILLEGAL;
11871 if (mode->vtotal - mode->vdisplay < 5)
11872 return MODE_V_ILLEGAL;
11874 if (mode->htotal - mode->hdisplay < 32)
11875 return MODE_H_ILLEGAL;
11877 if (mode->vtotal - mode->vdisplay < 3)
11878 return MODE_V_ILLEGAL;
11884 enum drm_mode_status
11885 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
11886 const struct drm_display_mode *mode,
11889 int plane_width_max, plane_height_max;
11892 * intel_mode_valid() should be
11893 * sufficient on older platforms.
11895 if (DISPLAY_VER(dev_priv) < 9)
11899 * Most people will probably want a fullscreen
11900 * plane so let's not advertize modes that are
11901 * too big for that.
11903 if (DISPLAY_VER(dev_priv) >= 11) {
11904 plane_width_max = 5120 << bigjoiner;
11905 plane_height_max = 4320;
11907 plane_width_max = 5120;
11908 plane_height_max = 4096;
11911 if (mode->hdisplay > plane_width_max)
11912 return MODE_H_ILLEGAL;
11914 if (mode->vdisplay > plane_height_max)
11915 return MODE_V_ILLEGAL;
11920 static const struct drm_mode_config_funcs intel_mode_funcs = {
11921 .fb_create = intel_user_framebuffer_create,
11922 .get_format_info = intel_get_format_info,
11923 .output_poll_changed = intel_fbdev_output_poll_changed,
11924 .mode_valid = intel_mode_valid,
11925 .atomic_check = intel_atomic_check,
11926 .atomic_commit = intel_atomic_commit,
11927 .atomic_state_alloc = intel_atomic_state_alloc,
11928 .atomic_state_clear = intel_atomic_state_clear,
11929 .atomic_state_free = intel_atomic_state_free,
11933 * intel_init_display_hooks - initialize the display modesetting hooks
11934 * @dev_priv: device private
11936 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
11938 if (!HAS_DISPLAY(dev_priv))
11941 intel_init_cdclk_hooks(dev_priv);
11942 intel_init_audio_hooks(dev_priv);
11944 intel_dpll_init_clock_hook(dev_priv);
11946 if (DISPLAY_VER(dev_priv) >= 9) {
11947 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
11948 dev_priv->display.crtc_enable = hsw_crtc_enable;
11949 dev_priv->display.crtc_disable = hsw_crtc_disable;
11950 } else if (HAS_DDI(dev_priv)) {
11951 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
11952 dev_priv->display.crtc_enable = hsw_crtc_enable;
11953 dev_priv->display.crtc_disable = hsw_crtc_disable;
11954 } else if (HAS_PCH_SPLIT(dev_priv)) {
11955 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
11956 dev_priv->display.crtc_enable = ilk_crtc_enable;
11957 dev_priv->display.crtc_disable = ilk_crtc_disable;
11958 } else if (IS_CHERRYVIEW(dev_priv) ||
11959 IS_VALLEYVIEW(dev_priv)) {
11960 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11961 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11962 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11964 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11965 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11966 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11969 intel_fdi_init_hook(dev_priv);
11971 if (DISPLAY_VER(dev_priv) >= 9) {
11972 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
11973 dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
11975 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
11976 dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
11981 void intel_modeset_init_hw(struct drm_i915_private *i915)
11983 struct intel_cdclk_state *cdclk_state;
11985 if (!HAS_DISPLAY(i915))
11988 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
11990 intel_update_cdclk(i915);
11991 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
11992 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
11995 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
11997 struct drm_plane *plane;
11998 struct intel_crtc *crtc;
12000 for_each_intel_crtc(state->dev, crtc) {
12001 struct intel_crtc_state *crtc_state;
12003 crtc_state = intel_atomic_get_crtc_state(state, crtc);
12004 if (IS_ERR(crtc_state))
12005 return PTR_ERR(crtc_state);
12007 if (crtc_state->hw.active) {
12009 * Preserve the inherited flag to avoid
12010 * taking the full modeset path.
12012 crtc_state->inherited = true;
12016 drm_for_each_plane(plane, state->dev) {
12017 struct drm_plane_state *plane_state;
12019 plane_state = drm_atomic_get_plane_state(state, plane);
12020 if (IS_ERR(plane_state))
12021 return PTR_ERR(plane_state);
12028 * Calculate what we think the watermarks should be for the state we've read
12029 * out of the hardware and then immediately program those watermarks so that
12030 * we ensure the hardware settings match our internal state.
12032 * We can calculate what we think WM's should be by creating a duplicate of the
12033 * current state (which was constructed during hardware readout) and running it
12034 * through the atomic check code to calculate new watermark values in the
12037 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
12039 struct drm_atomic_state *state;
12040 struct intel_atomic_state *intel_state;
12041 struct intel_crtc *crtc;
12042 struct intel_crtc_state *crtc_state;
12043 struct drm_modeset_acquire_ctx ctx;
12047 /* Only supported on platforms that use atomic watermark design */
12048 if (!dev_priv->display.optimize_watermarks)
12051 state = drm_atomic_state_alloc(&dev_priv->drm);
12052 if (drm_WARN_ON(&dev_priv->drm, !state))
12055 intel_state = to_intel_atomic_state(state);
12057 drm_modeset_acquire_init(&ctx, 0);
12060 state->acquire_ctx = &ctx;
12063 * Hardware readout is the only time we don't want to calculate
12064 * intermediate watermarks (since we don't trust the current
12067 if (!HAS_GMCH(dev_priv))
12068 intel_state->skip_intermediate_wm = true;
12070 ret = sanitize_watermarks_add_affected(state);
12074 ret = intel_atomic_check(&dev_priv->drm, state);
12078 /* Write calculated watermark values back */
12079 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
12080 crtc_state->wm.need_postvbl_update = true;
12081 dev_priv->display.optimize_watermarks(intel_state, crtc);
12083 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
12087 if (ret == -EDEADLK) {
12088 drm_atomic_state_clear(state);
12089 drm_modeset_backoff(&ctx);
12094 * If we fail here, it means that the hardware appears to be
12095 * programmed in a way that shouldn't be possible, given our
12096 * understanding of watermark requirements. This might mean a
12097 * mistake in the hardware readout code or a mistake in the
12098 * watermark calculations for a given platform. Raise a WARN
12099 * so that this is noticeable.
12101 * If this actually happens, we'll have to just leave the
12102 * BIOS-programmed watermarks untouched and hope for the best.
12104 drm_WARN(&dev_priv->drm, ret,
12105 "Could not determine valid watermarks for inherited state\n");
12107 drm_atomic_state_put(state);
12109 drm_modeset_drop_locks(&ctx);
12110 drm_modeset_acquire_fini(&ctx);
12113 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
12115 if (IS_IRONLAKE(dev_priv)) {
12117 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
12119 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
12120 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
12121 dev_priv->fdi_pll_freq = 270000;
12126 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
12129 static int intel_initial_commit(struct drm_device *dev)
12131 struct drm_atomic_state *state = NULL;
12132 struct drm_modeset_acquire_ctx ctx;
12133 struct intel_crtc *crtc;
12136 state = drm_atomic_state_alloc(dev);
12140 drm_modeset_acquire_init(&ctx, 0);
12143 state->acquire_ctx = &ctx;
12145 for_each_intel_crtc(dev, crtc) {
12146 struct intel_crtc_state *crtc_state =
12147 intel_atomic_get_crtc_state(state, crtc);
12149 if (IS_ERR(crtc_state)) {
12150 ret = PTR_ERR(crtc_state);
12154 if (crtc_state->hw.active) {
12155 struct intel_encoder *encoder;
12158 * We've not yet detected sink capabilities
12159 * (audio,infoframes,etc.) and thus we don't want to
12160 * force a full state recomputation yet. We want that to
12161 * happen only for the first real commit from userspace.
12162 * So preserve the inherited flag for the time being.
12164 crtc_state->inherited = true;
12166 ret = drm_atomic_add_affected_planes(state, &crtc->base);
12171 * FIXME hack to force a LUT update to avoid the
12172 * plane update forcing the pipe gamma on without
12173 * having a proper LUT loaded. Remove once we
12174 * have readout for pipe gamma enable.
12176 crtc_state->uapi.color_mgmt_changed = true;
12178 for_each_intel_encoder_mask(dev, encoder,
12179 crtc_state->uapi.encoder_mask) {
12180 if (encoder->initial_fastset_check &&
12181 !encoder->initial_fastset_check(encoder, crtc_state)) {
12182 ret = drm_atomic_add_affected_connectors(state,
12191 ret = drm_atomic_commit(state);
12194 if (ret == -EDEADLK) {
12195 drm_atomic_state_clear(state);
12196 drm_modeset_backoff(&ctx);
12200 drm_atomic_state_put(state);
12202 drm_modeset_drop_locks(&ctx);
12203 drm_modeset_acquire_fini(&ctx);
12208 static void intel_mode_config_init(struct drm_i915_private *i915)
12210 struct drm_mode_config *mode_config = &i915->drm.mode_config;
12212 drm_mode_config_init(&i915->drm);
12213 INIT_LIST_HEAD(&i915->global_obj_list);
12215 mode_config->min_width = 0;
12216 mode_config->min_height = 0;
12218 mode_config->preferred_depth = 24;
12219 mode_config->prefer_shadow = 1;
12221 mode_config->funcs = &intel_mode_funcs;
12223 mode_config->async_page_flip = has_async_flips(i915);
12226 * Maximum framebuffer dimensions, chosen to match
12227 * the maximum render engine surface size on gen4+.
12229 if (DISPLAY_VER(i915) >= 7) {
12230 mode_config->max_width = 16384;
12231 mode_config->max_height = 16384;
12232 } else if (DISPLAY_VER(i915) >= 4) {
12233 mode_config->max_width = 8192;
12234 mode_config->max_height = 8192;
12235 } else if (DISPLAY_VER(i915) == 3) {
12236 mode_config->max_width = 4096;
12237 mode_config->max_height = 4096;
12239 mode_config->max_width = 2048;
12240 mode_config->max_height = 2048;
12243 if (IS_I845G(i915) || IS_I865G(i915)) {
12244 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
12245 mode_config->cursor_height = 1023;
12246 } else if (IS_I830(i915) || IS_I85X(i915) ||
12247 IS_I915G(i915) || IS_I915GM(i915)) {
12248 mode_config->cursor_width = 64;
12249 mode_config->cursor_height = 64;
12251 mode_config->cursor_width = 256;
12252 mode_config->cursor_height = 256;
12256 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
12258 intel_atomic_global_obj_cleanup(i915);
12259 drm_mode_config_cleanup(&i915->drm);
12262 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
12264 if (plane_config->fb) {
12265 struct drm_framebuffer *fb = &plane_config->fb->base;
12267 /* We may only have the stub and not a full framebuffer */
12268 if (drm_framebuffer_read_refcount(fb))
12269 drm_framebuffer_put(fb);
12274 if (plane_config->vma)
12275 i915_vma_put(plane_config->vma);
12278 /* part #1: call before irq install */
12279 int intel_modeset_init_noirq(struct drm_i915_private *i915)
12283 if (i915_inject_probe_failure(i915))
12286 if (HAS_DISPLAY(i915)) {
12287 ret = drm_vblank_init(&i915->drm,
12288 INTEL_NUM_PIPES(i915));
12293 intel_bios_init(i915);
12295 ret = intel_vga_register(i915);
12299 /* FIXME: completely on the wrong abstraction layer */
12300 intel_power_domains_init_hw(i915, false);
12302 if (!HAS_DISPLAY(i915))
12305 intel_dmc_ucode_init(i915);
12307 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
12308 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
12309 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
12311 i915->framestart_delay = 1; /* 1-4 */
12313 i915->window2_delay = 0; /* No DSB so no window2 delay */
12315 intel_mode_config_init(i915);
12317 ret = intel_cdclk_init(i915);
12319 goto cleanup_vga_client_pw_domain_dmc;
12321 ret = intel_dbuf_init(i915);
12323 goto cleanup_vga_client_pw_domain_dmc;
12325 ret = intel_bw_init(i915);
12327 goto cleanup_vga_client_pw_domain_dmc;
12329 init_llist_head(&i915->atomic_helper.free_list);
12330 INIT_WORK(&i915->atomic_helper.free_work,
12331 intel_atomic_helper_free_state_worker);
12333 intel_init_quirks(i915);
12335 intel_fbc_init(i915);
12339 cleanup_vga_client_pw_domain_dmc:
12340 intel_dmc_ucode_fini(i915);
12341 intel_power_domains_driver_remove(i915);
12342 intel_vga_unregister(i915);
12344 intel_bios_driver_remove(i915);
12349 /* part #2: call after irq install, but before gem init */
12350 int intel_modeset_init_nogem(struct drm_i915_private *i915)
12352 struct drm_device *dev = &i915->drm;
12354 struct intel_crtc *crtc;
12357 if (!HAS_DISPLAY(i915))
12360 intel_init_pm(i915);
12362 intel_panel_sanitize_ssc(i915);
12364 intel_pps_setup(i915);
12366 intel_gmbus_setup(i915);
12368 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
12369 INTEL_NUM_PIPES(i915),
12370 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
12372 for_each_pipe(i915, pipe) {
12373 ret = intel_crtc_init(i915, pipe);
12375 intel_mode_config_cleanup(i915);
12380 intel_plane_possible_crtcs_init(i915);
12381 intel_shared_dpll_init(dev);
12382 intel_update_fdi_pll_freq(i915);
12384 intel_update_czclk(i915);
12385 intel_modeset_init_hw(i915);
12386 intel_dpll_update_ref_clks(i915);
12388 intel_hdcp_component_init(i915);
12390 if (i915->max_cdclk_freq == 0)
12391 intel_update_max_cdclk(i915);
12394 * If the platform has HTI, we need to find out whether it has reserved
12395 * any display resources before we create our display outputs.
12397 if (INTEL_INFO(i915)->display.has_hti)
12398 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
12400 /* Just disable it once at startup */
12401 intel_vga_disable(i915);
12402 intel_setup_outputs(i915);
12404 drm_modeset_lock_all(dev);
12405 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
12406 drm_modeset_unlock_all(dev);
12408 for_each_intel_crtc(dev, crtc) {
12409 struct intel_initial_plane_config plane_config = {};
12411 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
12415 * Note that reserving the BIOS fb up front prevents us
12416 * from stuffing other stolen allocations like the ring
12417 * on top. This prevents some ugliness at boot time, and
12418 * can even allow for smooth boot transitions if the BIOS
12419 * fb is large enough for the active pipe configuration.
12421 i915->display.get_initial_plane_config(crtc, &plane_config);
12424 * If the fb is shared between multiple heads, we'll
12425 * just get the first one.
12427 intel_find_initial_plane_obj(crtc, &plane_config);
12429 plane_config_fini(&plane_config);
12433 * Make sure hardware watermarks really match the state we read out.
12434 * Note that we need to do this after reconstructing the BIOS fb's
12435 * since the watermark calculation done here will use pstate->fb.
12437 if (!HAS_GMCH(i915))
12438 sanitize_watermarks(i915);
12443 /* part #3: call after gem init */
12444 int intel_modeset_init(struct drm_i915_private *i915)
12448 if (!HAS_DISPLAY(i915))
12452 * Force all active planes to recompute their states. So that on
12453 * mode_setcrtc after probe, all the intel_plane_state variables
12454 * are already calculated and there is no assert_plane warnings
12457 ret = intel_initial_commit(&i915->drm);
12459 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
12461 intel_overlay_setup(i915);
12463 ret = intel_fbdev_init(&i915->drm);
12467 /* Only enable hotplug handling once the fbdev is fully set up. */
12468 intel_hpd_init(i915);
12469 intel_hpd_poll_disable(i915);
12471 intel_init_ipc(i915);
12476 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12478 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12479 /* 640x480@60Hz, ~25175 kHz */
12480 struct dpll clock = {
12490 drm_WARN_ON(&dev_priv->drm,
12491 i9xx_calc_dpll_params(48000, &clock) != 25154);
12493 drm_dbg_kms(&dev_priv->drm,
12494 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
12495 pipe_name(pipe), clock.vco, clock.dot);
12497 fp = i9xx_dpll_compute_fp(&clock);
12498 dpll = DPLL_DVO_2X_MODE |
12499 DPLL_VGA_MODE_DIS |
12500 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
12501 PLL_P2_DIVIDE_BY_4 |
12502 PLL_REF_INPUT_DREFCLK |
12505 intel_de_write(dev_priv, FP0(pipe), fp);
12506 intel_de_write(dev_priv, FP1(pipe), fp);
12508 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
12509 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
12510 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
12511 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
12512 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
12513 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
12514 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
12517 * Apparently we need to have VGA mode enabled prior to changing
12518 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
12519 * dividers, even though the register value does change.
12521 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
12522 intel_de_write(dev_priv, DPLL(pipe), dpll);
12524 /* Wait for the clocks to stabilize. */
12525 intel_de_posting_read(dev_priv, DPLL(pipe));
12528 /* The pixel multiplier can only be updated once the
12529 * DPLL is enabled and the clocks are stable.
12531 * So write it again.
12533 intel_de_write(dev_priv, DPLL(pipe), dpll);
12535 /* We do this three times for luck */
12536 for (i = 0; i < 3 ; i++) {
12537 intel_de_write(dev_priv, DPLL(pipe), dpll);
12538 intel_de_posting_read(dev_priv, DPLL(pipe));
12539 udelay(150); /* wait for warmup */
12542 intel_de_write(dev_priv, PIPECONF(pipe),
12543 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
12544 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12546 intel_wait_for_pipe_scanline_moving(crtc);
12549 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12551 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12553 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
12556 drm_WARN_ON(&dev_priv->drm,
12557 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
12558 DISPLAY_PLANE_ENABLE);
12559 drm_WARN_ON(&dev_priv->drm,
12560 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
12561 DISPLAY_PLANE_ENABLE);
12562 drm_WARN_ON(&dev_priv->drm,
12563 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
12564 DISPLAY_PLANE_ENABLE);
12565 drm_WARN_ON(&dev_priv->drm,
12566 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
12567 drm_WARN_ON(&dev_priv->drm,
12568 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
12570 intel_de_write(dev_priv, PIPECONF(pipe), 0);
12571 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12573 intel_wait_for_pipe_scanline_stopped(crtc);
12575 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
12576 intel_de_posting_read(dev_priv, DPLL(pipe));
12580 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
12582 struct intel_crtc *crtc;
12584 if (DISPLAY_VER(dev_priv) >= 4)
12587 for_each_intel_crtc(&dev_priv->drm, crtc) {
12588 struct intel_plane *plane =
12589 to_intel_plane(crtc->base.primary);
12590 struct intel_crtc *plane_crtc;
12593 if (!plane->get_hw_state(plane, &pipe))
12596 if (pipe == crtc->pipe)
12599 drm_dbg_kms(&dev_priv->drm,
12600 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
12601 plane->base.base.id, plane->base.name);
12603 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12604 intel_plane_disable_noatomic(plane_crtc, plane);
12608 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
12610 struct drm_device *dev = crtc->base.dev;
12611 struct intel_encoder *encoder;
12613 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
12619 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
12621 struct drm_device *dev = encoder->base.dev;
12622 struct intel_connector *connector;
12624 for_each_connector_on_encoder(dev, &encoder->base, connector)
12630 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
12631 enum pipe pch_transcoder)
12633 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
12634 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
12637 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
12639 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12640 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12641 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
12643 if (DISPLAY_VER(dev_priv) >= 9 ||
12644 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12645 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
12648 if (transcoder_is_dsi(cpu_transcoder))
12651 val = intel_de_read(dev_priv, reg);
12652 val &= ~HSW_FRAME_START_DELAY_MASK;
12653 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12654 intel_de_write(dev_priv, reg, val);
12656 i915_reg_t reg = PIPECONF(cpu_transcoder);
12659 val = intel_de_read(dev_priv, reg);
12660 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
12661 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12662 intel_de_write(dev_priv, reg, val);
12665 if (!crtc_state->has_pch_encoder)
12668 if (HAS_PCH_IBX(dev_priv)) {
12669 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
12672 val = intel_de_read(dev_priv, reg);
12673 val &= ~TRANS_FRAME_START_DELAY_MASK;
12674 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12675 intel_de_write(dev_priv, reg, val);
12677 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
12678 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
12681 val = intel_de_read(dev_priv, reg);
12682 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
12683 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12684 intel_de_write(dev_priv, reg, val);
12688 static void intel_sanitize_crtc(struct intel_crtc *crtc,
12689 struct drm_modeset_acquire_ctx *ctx)
12691 struct drm_device *dev = crtc->base.dev;
12692 struct drm_i915_private *dev_priv = to_i915(dev);
12693 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
12695 if (crtc_state->hw.active) {
12696 struct intel_plane *plane;
12698 /* Clear any frame start delays used for debugging left by the BIOS */
12699 intel_sanitize_frame_start_delay(crtc_state);
12701 /* Disable everything but the primary plane */
12702 for_each_intel_plane_on_crtc(dev, crtc, plane) {
12703 const struct intel_plane_state *plane_state =
12704 to_intel_plane_state(plane->base.state);
12706 if (plane_state->uapi.visible &&
12707 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
12708 intel_plane_disable_noatomic(crtc, plane);
12712 * Disable any background color set by the BIOS, but enable the
12713 * gamma and CSC to match how we program our planes.
12715 if (DISPLAY_VER(dev_priv) >= 9)
12716 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
12717 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
12720 /* Adjust the state of the output pipe according to whether we
12721 * have active connectors/encoders. */
12722 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
12723 !crtc_state->bigjoiner_slave)
12724 intel_crtc_disable_noatomic(crtc, ctx);
12726 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
12728 * We start out with underrun reporting disabled to avoid races.
12729 * For correct bookkeeping mark this on active crtcs.
12731 * Also on gmch platforms we dont have any hardware bits to
12732 * disable the underrun reporting. Which means we need to start
12733 * out with underrun reporting disabled also on inactive pipes,
12734 * since otherwise we'll complain about the garbage we read when
12735 * e.g. coming up after runtime pm.
12737 * No protection against concurrent access is required - at
12738 * worst a fifo underrun happens which also sets this to false.
12740 crtc->cpu_fifo_underrun_disabled = true;
12742 * We track the PCH trancoder underrun reporting state
12743 * within the crtc. With crtc for pipe A housing the underrun
12744 * reporting state for PCH transcoder A, crtc for pipe B housing
12745 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
12746 * and marking underrun reporting as disabled for the non-existing
12747 * PCH transcoders B and C would prevent enabling the south
12748 * error interrupt (see cpt_can_enable_serr_int()).
12750 if (has_pch_trancoder(dev_priv, crtc->pipe))
12751 crtc->pch_fifo_underrun_disabled = true;
12755 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
12757 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12760 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
12761 * the hardware when a high res displays plugged in. DPLL P
12762 * divider is zero, and the pipe timings are bonkers. We'll
12763 * try to disable everything in that case.
12765 * FIXME would be nice to be able to sanitize this state
12766 * without several WARNs, but for now let's take the easy
12769 return IS_SANDYBRIDGE(dev_priv) &&
12770 crtc_state->hw.active &&
12771 crtc_state->shared_dpll &&
12772 crtc_state->port_clock == 0;
12775 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12777 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12778 struct intel_connector *connector;
12779 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
12780 struct intel_crtc_state *crtc_state = crtc ?
12781 to_intel_crtc_state(crtc->base.state) : NULL;
12783 /* We need to check both for a crtc link (meaning that the
12784 * encoder is active and trying to read from a pipe) and the
12785 * pipe itself being active. */
12786 bool has_active_crtc = crtc_state &&
12787 crtc_state->hw.active;
12789 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
12790 drm_dbg_kms(&dev_priv->drm,
12791 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
12792 pipe_name(crtc->pipe));
12793 has_active_crtc = false;
12796 connector = intel_encoder_find_connector(encoder);
12797 if (connector && !has_active_crtc) {
12798 drm_dbg_kms(&dev_priv->drm,
12799 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12800 encoder->base.base.id,
12801 encoder->base.name);
12803 /* Connector is active, but has no active pipe. This is
12804 * fallout from our resume register restoring. Disable
12805 * the encoder manually again. */
12807 struct drm_encoder *best_encoder;
12809 drm_dbg_kms(&dev_priv->drm,
12810 "[ENCODER:%d:%s] manually disabled\n",
12811 encoder->base.base.id,
12812 encoder->base.name);
12814 /* avoid oopsing in case the hooks consult best_encoder */
12815 best_encoder = connector->base.state->best_encoder;
12816 connector->base.state->best_encoder = &encoder->base;
12818 /* FIXME NULL atomic state passed! */
12819 if (encoder->disable)
12820 encoder->disable(NULL, encoder, crtc_state,
12821 connector->base.state);
12822 if (encoder->post_disable)
12823 encoder->post_disable(NULL, encoder, crtc_state,
12824 connector->base.state);
12826 connector->base.state->best_encoder = best_encoder;
12828 encoder->base.crtc = NULL;
12830 /* Inconsistent output/port/pipe state happens presumably due to
12831 * a bug in one of the get_hw_state functions. Or someplace else
12832 * in our code, like the register restore mess on resume. Clamp
12833 * things to off as a safer default. */
12835 connector->base.dpms = DRM_MODE_DPMS_OFF;
12836 connector->base.encoder = NULL;
12839 /* notify opregion of the sanitized encoder state */
12840 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
12842 if (HAS_DDI(dev_priv))
12843 intel_ddi_sanitize_encoder_pll_mapping(encoder);
12846 /* FIXME read out full plane state for all planes */
12847 static void readout_plane_state(struct drm_i915_private *dev_priv)
12849 struct intel_plane *plane;
12850 struct intel_crtc *crtc;
12852 for_each_intel_plane(&dev_priv->drm, plane) {
12853 struct intel_plane_state *plane_state =
12854 to_intel_plane_state(plane->base.state);
12855 struct intel_crtc_state *crtc_state;
12856 enum pipe pipe = PIPE_A;
12859 visible = plane->get_hw_state(plane, &pipe);
12861 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12862 crtc_state = to_intel_crtc_state(crtc->base.state);
12864 intel_set_plane_visible(crtc_state, plane_state, visible);
12866 drm_dbg_kms(&dev_priv->drm,
12867 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
12868 plane->base.base.id, plane->base.name,
12869 enableddisabled(visible), pipe_name(pipe));
12872 for_each_intel_crtc(&dev_priv->drm, crtc) {
12873 struct intel_crtc_state *crtc_state =
12874 to_intel_crtc_state(crtc->base.state);
12876 fixup_plane_bitmasks(crtc_state);
12880 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12882 struct drm_i915_private *dev_priv = to_i915(dev);
12883 struct intel_cdclk_state *cdclk_state =
12884 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
12885 struct intel_dbuf_state *dbuf_state =
12886 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
12888 struct intel_crtc *crtc;
12889 struct intel_encoder *encoder;
12890 struct intel_connector *connector;
12891 struct drm_connector_list_iter conn_iter;
12892 u8 active_pipes = 0;
12894 for_each_intel_crtc(dev, crtc) {
12895 struct intel_crtc_state *crtc_state =
12896 to_intel_crtc_state(crtc->base.state);
12898 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
12899 intel_crtc_free_hw_state(crtc_state);
12900 intel_crtc_state_reset(crtc_state, crtc);
12902 intel_crtc_get_pipe_config(crtc_state);
12904 crtc_state->hw.enable = crtc_state->hw.active;
12906 crtc->base.enabled = crtc_state->hw.enable;
12907 crtc->active = crtc_state->hw.active;
12909 if (crtc_state->hw.active)
12910 active_pipes |= BIT(crtc->pipe);
12912 drm_dbg_kms(&dev_priv->drm,
12913 "[CRTC:%d:%s] hw state readout: %s\n",
12914 crtc->base.base.id, crtc->base.name,
12915 enableddisabled(crtc_state->hw.active));
12918 dev_priv->active_pipes = cdclk_state->active_pipes =
12919 dbuf_state->active_pipes = active_pipes;
12921 readout_plane_state(dev_priv);
12923 for_each_intel_encoder(dev, encoder) {
12926 if (encoder->get_hw_state(encoder, &pipe)) {
12927 struct intel_crtc_state *crtc_state;
12929 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12930 crtc_state = to_intel_crtc_state(crtc->base.state);
12932 encoder->base.crtc = &crtc->base;
12933 intel_encoder_get_config(encoder, crtc_state);
12934 if (encoder->sync_state)
12935 encoder->sync_state(encoder, crtc_state);
12937 /* read out to slave crtc as well for bigjoiner */
12938 if (crtc_state->bigjoiner) {
12939 /* encoder should read be linked to bigjoiner master */
12940 WARN_ON(crtc_state->bigjoiner_slave);
12942 crtc = crtc_state->bigjoiner_linked_crtc;
12943 crtc_state = to_intel_crtc_state(crtc->base.state);
12944 intel_encoder_get_config(encoder, crtc_state);
12947 encoder->base.crtc = NULL;
12950 drm_dbg_kms(&dev_priv->drm,
12951 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12952 encoder->base.base.id, encoder->base.name,
12953 enableddisabled(encoder->base.crtc),
12957 intel_dpll_readout_hw_state(dev_priv);
12959 drm_connector_list_iter_begin(dev, &conn_iter);
12960 for_each_intel_connector_iter(connector, &conn_iter) {
12961 if (connector->get_hw_state(connector)) {
12962 struct intel_crtc_state *crtc_state;
12963 struct intel_crtc *crtc;
12965 connector->base.dpms = DRM_MODE_DPMS_ON;
12967 encoder = intel_attached_encoder(connector);
12968 connector->base.encoder = &encoder->base;
12970 crtc = to_intel_crtc(encoder->base.crtc);
12971 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
12973 if (crtc_state && crtc_state->hw.active) {
12975 * This has to be done during hardware readout
12976 * because anything calling .crtc_disable may
12977 * rely on the connector_mask being accurate.
12979 crtc_state->uapi.connector_mask |=
12980 drm_connector_mask(&connector->base);
12981 crtc_state->uapi.encoder_mask |=
12982 drm_encoder_mask(&encoder->base);
12985 connector->base.dpms = DRM_MODE_DPMS_OFF;
12986 connector->base.encoder = NULL;
12988 drm_dbg_kms(&dev_priv->drm,
12989 "[CONNECTOR:%d:%s] hw state readout: %s\n",
12990 connector->base.base.id, connector->base.name,
12991 enableddisabled(connector->base.encoder));
12993 drm_connector_list_iter_end(&conn_iter);
12995 for_each_intel_crtc(dev, crtc) {
12996 struct intel_bw_state *bw_state =
12997 to_intel_bw_state(dev_priv->bw_obj.state);
12998 struct intel_crtc_state *crtc_state =
12999 to_intel_crtc_state(crtc->base.state);
13000 struct intel_plane *plane;
13003 if (crtc_state->bigjoiner_slave)
13006 if (crtc_state->hw.active) {
13008 * The initial mode needs to be set in order to keep
13009 * the atomic core happy. It wants a valid mode if the
13010 * crtc's enabled, so we do the above call.
13012 * But we don't set all the derived state fully, hence
13013 * set a flag to indicate that a full recalculation is
13014 * needed on the next commit.
13016 crtc_state->inherited = true;
13018 intel_crtc_update_active_timings(crtc_state);
13020 intel_crtc_copy_hw_to_uapi_state(crtc_state);
13023 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
13024 const struct intel_plane_state *plane_state =
13025 to_intel_plane_state(plane->base.state);
13028 * FIXME don't have the fb yet, so can't
13029 * use intel_plane_data_rate() :(
13031 if (plane_state->uapi.visible)
13032 crtc_state->data_rate[plane->id] =
13033 4 * crtc_state->pixel_rate;
13035 * FIXME don't have the fb yet, so can't
13036 * use plane->min_cdclk() :(
13038 if (plane_state->uapi.visible && plane->min_cdclk) {
13039 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
13040 crtc_state->min_cdclk[plane->id] =
13041 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
13043 crtc_state->min_cdclk[plane->id] =
13044 crtc_state->pixel_rate;
13046 drm_dbg_kms(&dev_priv->drm,
13047 "[PLANE:%d:%s] min_cdclk %d kHz\n",
13048 plane->base.base.id, plane->base.name,
13049 crtc_state->min_cdclk[plane->id]);
13052 if (crtc_state->hw.active) {
13053 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
13054 if (drm_WARN_ON(dev, min_cdclk < 0))
13058 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
13059 cdclk_state->min_voltage_level[crtc->pipe] =
13060 crtc_state->min_voltage_level;
13062 intel_bw_crtc_update(bw_state, crtc_state);
13064 intel_pipe_config_sanity_check(dev_priv, crtc_state);
13066 /* discard our incomplete slave state, copy it from master */
13067 if (crtc_state->bigjoiner && crtc_state->hw.active) {
13068 struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
13069 struct intel_crtc_state *slave_crtc_state =
13070 to_intel_crtc_state(slave->base.state);
13072 copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
13073 slave->base.mode = crtc->base.mode;
13075 cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
13076 cdclk_state->min_voltage_level[slave->pipe] =
13077 crtc_state->min_voltage_level;
13079 for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
13080 const struct intel_plane_state *plane_state =
13081 to_intel_plane_state(plane->base.state);
13084 * FIXME don't have the fb yet, so can't
13085 * use intel_plane_data_rate() :(
13087 if (plane_state->uapi.visible)
13088 crtc_state->data_rate[plane->id] =
13089 4 * crtc_state->pixel_rate;
13091 crtc_state->data_rate[plane->id] = 0;
13094 intel_bw_crtc_update(bw_state, slave_crtc_state);
13095 drm_calc_timestamping_constants(&slave->base,
13096 &slave_crtc_state->hw.adjusted_mode);
13102 get_encoder_power_domains(struct drm_i915_private *dev_priv)
13104 struct intel_encoder *encoder;
13106 for_each_intel_encoder(&dev_priv->drm, encoder) {
13107 struct intel_crtc_state *crtc_state;
13109 if (!encoder->get_power_domains)
13113 * MST-primary and inactive encoders don't have a crtc state
13114 * and neither of these require any power domain references.
13116 if (!encoder->base.crtc)
13119 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
13120 encoder->get_power_domains(encoder, crtc_state);
13124 static void intel_early_display_was(struct drm_i915_private *dev_priv)
13127 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
13128 * Also known as Wa_14010480278.
13130 if (IS_DISPLAY_VER(dev_priv, 10, 12))
13131 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
13132 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
13134 if (IS_HASWELL(dev_priv)) {
13136 * WaRsPkgCStateDisplayPMReq:hsw
13137 * System hang if this isn't done before disabling all planes!
13139 intel_de_write(dev_priv, CHICKEN_PAR1_1,
13140 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
13143 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
13144 /* Display WA #1142:kbl,cfl,cml */
13145 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
13146 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
13147 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
13148 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
13149 KBL_ARB_FILL_SPARE_14);
13153 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
13154 enum port port, i915_reg_t hdmi_reg)
13156 u32 val = intel_de_read(dev_priv, hdmi_reg);
13158 if (val & SDVO_ENABLE ||
13159 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
13162 drm_dbg_kms(&dev_priv->drm,
13163 "Sanitizing transcoder select for HDMI %c\n",
13166 val &= ~SDVO_PIPE_SEL_MASK;
13167 val |= SDVO_PIPE_SEL(PIPE_A);
13169 intel_de_write(dev_priv, hdmi_reg, val);
13172 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
13173 enum port port, i915_reg_t dp_reg)
13175 u32 val = intel_de_read(dev_priv, dp_reg);
13177 if (val & DP_PORT_EN ||
13178 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
13181 drm_dbg_kms(&dev_priv->drm,
13182 "Sanitizing transcoder select for DP %c\n",
13185 val &= ~DP_PIPE_SEL_MASK;
13186 val |= DP_PIPE_SEL(PIPE_A);
13188 intel_de_write(dev_priv, dp_reg, val);
13191 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
13194 * The BIOS may select transcoder B on some of the PCH
13195 * ports even it doesn't enable the port. This would trip
13196 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
13197 * Sanitize the transcoder select bits to prevent that. We
13198 * assume that the BIOS never actually enabled the port,
13199 * because if it did we'd actually have to toggle the port
13200 * on and back off to make the transcoder A select stick
13201 * (see. intel_dp_link_down(), intel_disable_hdmi(),
13202 * intel_disable_sdvo()).
13204 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
13205 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
13206 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
13208 /* PCH SDVOB multiplex with HDMIB */
13209 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
13210 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
13211 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
13214 /* Scan out the current hw modeset state,
13215 * and sanitizes it to the current state
13218 intel_modeset_setup_hw_state(struct drm_device *dev,
13219 struct drm_modeset_acquire_ctx *ctx)
13221 struct drm_i915_private *dev_priv = to_i915(dev);
13222 struct intel_encoder *encoder;
13223 struct intel_crtc *crtc;
13224 intel_wakeref_t wakeref;
13226 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
13228 intel_early_display_was(dev_priv);
13229 intel_modeset_readout_hw_state(dev);
13231 /* HW state is read out, now we need to sanitize this mess. */
13233 /* Sanitize the TypeC port mode upfront, encoders depend on this */
13234 for_each_intel_encoder(dev, encoder) {
13235 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
13237 /* We need to sanitize only the MST primary port. */
13238 if (encoder->type != INTEL_OUTPUT_DP_MST &&
13239 intel_phy_is_tc(dev_priv, phy))
13240 intel_tc_port_sanitize(enc_to_dig_port(encoder));
13243 get_encoder_power_domains(dev_priv);
13245 if (HAS_PCH_IBX(dev_priv))
13246 ibx_sanitize_pch_ports(dev_priv);
13249 * intel_sanitize_plane_mapping() may need to do vblank
13250 * waits, so we need vblank interrupts restored beforehand.
13252 for_each_intel_crtc(&dev_priv->drm, crtc) {
13253 struct intel_crtc_state *crtc_state =
13254 to_intel_crtc_state(crtc->base.state);
13256 drm_crtc_vblank_reset(&crtc->base);
13258 if (crtc_state->hw.active)
13259 intel_crtc_vblank_on(crtc_state);
13262 intel_sanitize_plane_mapping(dev_priv);
13264 for_each_intel_encoder(dev, encoder)
13265 intel_sanitize_encoder(encoder);
13267 for_each_intel_crtc(&dev_priv->drm, crtc) {
13268 struct intel_crtc_state *crtc_state =
13269 to_intel_crtc_state(crtc->base.state);
13271 intel_sanitize_crtc(crtc, ctx);
13272 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
13275 intel_modeset_update_connector_atomic_state(dev);
13277 intel_dpll_sanitize_state(dev_priv);
13279 if (IS_G4X(dev_priv)) {
13280 g4x_wm_get_hw_state(dev_priv);
13281 g4x_wm_sanitize(dev_priv);
13282 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13283 vlv_wm_get_hw_state(dev_priv);
13284 vlv_wm_sanitize(dev_priv);
13285 } else if (DISPLAY_VER(dev_priv) >= 9) {
13286 skl_wm_get_hw_state(dev_priv);
13287 } else if (HAS_PCH_SPLIT(dev_priv)) {
13288 ilk_wm_get_hw_state(dev_priv);
13291 for_each_intel_crtc(dev, crtc) {
13292 struct intel_crtc_state *crtc_state =
13293 to_intel_crtc_state(crtc->base.state);
13296 put_domains = modeset_get_crtc_power_domains(crtc_state);
13297 if (drm_WARN_ON(dev, put_domains))
13298 modeset_put_crtc_power_domains(crtc, put_domains);
13301 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
13304 void intel_display_resume(struct drm_device *dev)
13306 struct drm_i915_private *dev_priv = to_i915(dev);
13307 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
13308 struct drm_modeset_acquire_ctx ctx;
13311 if (!HAS_DISPLAY(dev_priv))
13314 dev_priv->modeset_restore_state = NULL;
13316 state->acquire_ctx = &ctx;
13318 drm_modeset_acquire_init(&ctx, 0);
13321 ret = drm_modeset_lock_all_ctx(dev, &ctx);
13322 if (ret != -EDEADLK)
13325 drm_modeset_backoff(&ctx);
13329 ret = __intel_display_resume(dev, state, &ctx);
13331 intel_enable_ipc(dev_priv);
13332 drm_modeset_drop_locks(&ctx);
13333 drm_modeset_acquire_fini(&ctx);
13336 drm_err(&dev_priv->drm,
13337 "Restoring old state failed with %i\n", ret);
13339 drm_atomic_state_put(state);
13342 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
13344 struct intel_connector *connector;
13345 struct drm_connector_list_iter conn_iter;
13347 /* Kill all the work that may have been queued by hpd. */
13348 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
13349 for_each_intel_connector_iter(connector, &conn_iter) {
13350 if (connector->modeset_retry_work.func)
13351 cancel_work_sync(&connector->modeset_retry_work);
13352 if (connector->hdcp.shim) {
13353 cancel_delayed_work_sync(&connector->hdcp.check_work);
13354 cancel_work_sync(&connector->hdcp.prop_work);
13357 drm_connector_list_iter_end(&conn_iter);
13360 /* part #1: call before irq uninstall */
13361 void intel_modeset_driver_remove(struct drm_i915_private *i915)
13363 if (!HAS_DISPLAY(i915))
13366 flush_workqueue(i915->flip_wq);
13367 flush_workqueue(i915->modeset_wq);
13369 flush_work(&i915->atomic_helper.free_work);
13370 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
13373 /* part #2: call after irq uninstall */
13374 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
13376 if (!HAS_DISPLAY(i915))
13380 * Due to the hpd irq storm handling the hotplug work can re-arm the
13381 * poll handlers. Hence disable polling after hpd handling is shut down.
13383 intel_hpd_poll_fini(i915);
13386 * MST topology needs to be suspended so we don't have any calls to
13387 * fbdev after it's finalized. MST will be destroyed later as part of
13388 * drm_mode_config_cleanup()
13390 intel_dp_mst_suspend(i915);
13392 /* poll work can call into fbdev, hence clean that up afterwards */
13393 intel_fbdev_fini(i915);
13395 intel_unregister_dsm_handler();
13397 intel_fbc_global_disable(i915);
13399 /* flush any delayed tasks or pending work */
13400 flush_scheduled_work();
13402 intel_hdcp_component_fini(i915);
13404 intel_mode_config_cleanup(i915);
13406 intel_overlay_cleanup(i915);
13408 intel_gmbus_teardown(i915);
13410 destroy_workqueue(i915->flip_wq);
13411 destroy_workqueue(i915->modeset_wq);
13413 intel_fbc_cleanup_cfb(i915);
13416 /* part #3: call after gem init */
13417 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
13419 intel_dmc_ucode_fini(i915);
13421 intel_power_domains_driver_remove(i915);
13423 intel_vga_unregister(i915);
13425 intel_bios_driver_remove(i915);
13428 void intel_display_driver_register(struct drm_i915_private *i915)
13430 if (!HAS_DISPLAY(i915))
13433 intel_display_debugfs_register(i915);
13435 /* Must be done after probing outputs */
13436 intel_opregion_register(i915);
13437 acpi_video_register();
13439 intel_audio_init(i915);
13442 * Some ports require correctly set-up hpd registers for
13443 * detection to work properly (leading to ghost connected
13444 * connector status), e.g. VGA on gm45. Hence we can only set
13445 * up the initial fbdev config after hpd irqs are fully
13446 * enabled. We do it last so that the async config cannot run
13447 * before the connectors are registered.
13449 intel_fbdev_initial_config_async(&i915->drm);
13452 * We need to coordinate the hotplugs with the asynchronous
13453 * fbdev configuration, for which we use the
13454 * fbdev->async_cookie.
13456 drm_kms_helper_poll_init(&i915->drm);
13459 void intel_display_driver_unregister(struct drm_i915_private *i915)
13461 if (!HAS_DISPLAY(i915))
13464 intel_fbdev_unregister(i915);
13465 intel_audio_deinit(i915);
13468 * After flushing the fbdev (incl. a late async config which
13469 * will have delayed queuing of a hotplug event), then flush
13470 * the hotplug events.
13472 drm_kms_helper_poll_fini(&i915->drm);
13473 drm_atomic_helper_shutdown(&i915->drm);
13475 acpi_video_unregister();
13476 intel_opregion_unregister(i915);