drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_crtc.h"
  35 #include "intel_ddi.h"
  36 #include "intel_ddi_buf_trans.h"
  37 #include "intel_de.h"
  38 #include "intel_display_types.h"
  39 #include "intel_dp.h"
  40 #include "intel_dp_link_training.h"
  41 #include "intel_dp_mst.h"
  42 #include "intel_dpio_phy.h"
  43 #include "intel_dsi.h"
  44 #include "intel_fdi.h"
  45 #include "intel_fifo_underrun.h"
  46 #include "intel_gmbus.h"
  47 #include "intel_hdcp.h"
  48 #include "intel_hdmi.h"
  49 #include "intel_hotplug.h"
  50 #include "intel_lspcon.h"
  51 #include "intel_panel.h"
  52 #include "intel_pps.h"
  53 #include "intel_psr.h"
  54 #include "intel_snps_phy.h"
  55 #include "intel_sprite.h"
  56 #include "intel_tc.h"
  57 #include "intel_vdsc.h"
  58 #include "intel_vrr.h"
  59 #include "skl_scaler.h"
  60 #include "skl_universal_plane.h"
  61
  62 static const u8 index_to_dp_signal_levels[] = {
  63         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  64         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  65         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  66         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  67         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  68         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  69         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  70         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  71         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  72         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  73 };
  74
  75 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  76                                 const struct intel_crtc_state *crtc_state)
  77 {
  78         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  79         int n_entries, level, default_entry;
  80
  81         n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry);
  82         if (n_entries == 0)
  83                 return 0;
  84         level = intel_bios_hdmi_level_shift(encoder);
  85         if (level < 0)
  86                 level = default_entry;
  87
  88         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
  89                 level = n_entries - 1;
  90
  91         return level;
  92 }
  93
  94 /*
  95  * Starting with Haswell, DDI port buffers must be programmed with correct
  96  * values in advance. This function programs the correct values for
  97  * DP/eDP/FDI use cases.
  98  */
  99 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 100                                 const struct intel_crtc_state *crtc_state)
 101 {
 102         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 103         u32 iboost_bit = 0;
 104         int i, n_entries;
 105         enum port port = encoder->port;
 106         const struct intel_ddi_buf_trans *ddi_translations;
 107
 108         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 109         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 110                 return;
 111
 112         /* If we're boosting the current, set bit 31 of trans1 */
 113         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
 114             intel_bios_encoder_dp_boost_level(encoder->devdata))
 115                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 116
 117         for (i = 0; i < n_entries; i++) {
 118                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
 119                                ddi_translations->entries[i].hsw.trans1 | iboost_bit);
 120                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
 121                                ddi_translations->entries[i].hsw.trans2);
 122         }
 123 }
 124
 125 /*
 126  * Starting with Haswell, DDI port buffers must be programmed with correct
 127  * values in advance. This function programs the correct values for
 128  * HDMI/DVI use cases.
 129  */
 130 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 131                                          const struct intel_crtc_state *crtc_state,
 132                                          int level)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 135         u32 iboost_bit = 0;
 136         int n_entries;
 137         enum port port = encoder->port;
 138         const struct intel_ddi_buf_trans *ddi_translations;
 139
 140         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 141         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 142                 return;
 143         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 144                 level = n_entries - 1;
 145
 146         /* If we're boosting the current, set bit 31 of trans1 */
 147         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
 148             intel_bios_encoder_hdmi_boost_level(encoder->devdata))
 149                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 150
 151         /* Entry 9 is for HDMI: */
 152         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
 153                        ddi_translations->entries[level].hsw.trans1 | iboost_bit);
 154         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
 155                        ddi_translations->entries[level].hsw.trans2);
 156 }
 157
 158 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 159                              enum port port)
 160 {
 161         if (IS_BROXTON(dev_priv)) {
 162                 udelay(16);
 163                 return;
 164         }
 165
 166         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 167                          DDI_BUF_IS_IDLE), 8))
 168                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 169                         port_name(port));
 170 }
 171
 172 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 173                                       enum port port)
 174 {
 175         int ret;
 176
 177         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
 178         if (DISPLAY_VER(dev_priv) < 10) {
 179                 usleep_range(518, 1000);
 180                 return;
 181         }
 182
 183         ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 184                           DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10);
 185
 186         if (ret)
 187                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
 188                         port_name(port));
 189 }
 190
 191 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 192 {
 193         switch (pll->info->id) {
 194         case DPLL_ID_WRPLL1:
 195                 return PORT_CLK_SEL_WRPLL1;
 196         case DPLL_ID_WRPLL2:
 197                 return PORT_CLK_SEL_WRPLL2;
 198         case DPLL_ID_SPLL:
 199                 return PORT_CLK_SEL_SPLL;
 200         case DPLL_ID_LCPLL_810:
 201                 return PORT_CLK_SEL_LCPLL_810;
 202         case DPLL_ID_LCPLL_1350:
 203                 return PORT_CLK_SEL_LCPLL_1350;
 204         case DPLL_ID_LCPLL_2700:
 205                 return PORT_CLK_SEL_LCPLL_2700;
 206         default:
 207                 MISSING_CASE(pll->info->id);
 208                 return PORT_CLK_SEL_NONE;
 209         }
 210 }
 211
 212 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 213                                   const struct intel_crtc_state *crtc_state)
 214 {
 215         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 216         int clock = crtc_state->port_clock;
 217         const enum intel_dpll_id id = pll->info->id;
 218
 219         switch (id) {
 220         default:
 221                 /*
 222                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
 223                  * here, so do warn if this get passed in
 224                  */
 225                 MISSING_CASE(id);
 226                 return DDI_CLK_SEL_NONE;
 227         case DPLL_ID_ICL_TBTPLL:
 228                 switch (clock) {
 229                 case 162000:
 230                         return DDI_CLK_SEL_TBT_162;
 231                 case 270000:
 232                         return DDI_CLK_SEL_TBT_270;
 233                 case 540000:
 234                         return DDI_CLK_SEL_TBT_540;
 235                 case 810000:
 236                         return DDI_CLK_SEL_TBT_810;
 237                 default:
 238                         MISSING_CASE(clock);
 239                         return DDI_CLK_SEL_NONE;
 240                 }
 241         case DPLL_ID_ICL_MGPLL1:
 242         case DPLL_ID_ICL_MGPLL2:
 243         case DPLL_ID_ICL_MGPLL3:
 244         case DPLL_ID_ICL_MGPLL4:
 245         case DPLL_ID_TGL_MGPLL5:
 246         case DPLL_ID_TGL_MGPLL6:
 247                 return DDI_CLK_SEL_MG;
 248         }
 249 }
 250
 251 static u32 ddi_buf_phy_link_rate(int port_clock)
 252 {
 253         switch (port_clock) {
 254         case 162000:
 255                 return DDI_BUF_PHY_LINK_RATE(0);
 256         case 216000:
 257                 return DDI_BUF_PHY_LINK_RATE(4);
 258         case 243000:
 259                 return DDI_BUF_PHY_LINK_RATE(5);
 260         case 270000:
 261                 return DDI_BUF_PHY_LINK_RATE(1);
 262         case 324000:
 263                 return DDI_BUF_PHY_LINK_RATE(6);
 264         case 432000:
 265                 return DDI_BUF_PHY_LINK_RATE(7);
 266         case 540000:
 267                 return DDI_BUF_PHY_LINK_RATE(2);
 268         case 810000:
 269                 return DDI_BUF_PHY_LINK_RATE(3);
 270         default:
 271                 MISSING_CASE(port_clock);
 272                 return DDI_BUF_PHY_LINK_RATE(0);
 273         }
 274 }
 275
 276 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 277                                       const struct intel_crtc_state *crtc_state)
 278 {
 279         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 280         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 281         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 282         enum phy phy = intel_port_to_phy(i915, encoder->port);
 283
 284         intel_dp->DP = dig_port->saved_port_bits |
 285                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 286         intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
 287
 288         if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
 289                 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 290                 if (dig_port->tc_mode != TC_PORT_TBT_ALT)
 291                         intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 292         }
 293 }
 294
 295 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 296                                  enum port port)
 297 {
 298         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 299
 300         switch (val) {
 301         case DDI_CLK_SEL_NONE:
 302                 return 0;
 303         case DDI_CLK_SEL_TBT_162:
 304                 return 162000;
 305         case DDI_CLK_SEL_TBT_270:
 306                 return 270000;
 307         case DDI_CLK_SEL_TBT_540:
 308                 return 540000;
 309         case DDI_CLK_SEL_TBT_810:
 310                 return 810000;
 311         default:
 312                 MISSING_CASE(val);
 313                 return 0;
 314         }
 315 }
 316
 317 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 318 {
 319         int dotclock;
 320
 321         if (pipe_config->has_pch_encoder)
 322                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 323                                                     &pipe_config->fdi_m_n);
 324         else if (intel_crtc_has_dp_encoder(pipe_config))
 325                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 326                                                     &pipe_config->dp_m_n);
 327         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
 328                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
 329         else
 330                 dotclock = pipe_config->port_clock;
 331
 332         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
 333             !intel_crtc_has_dp_encoder(pipe_config))
 334                 dotclock *= 2;
 335
 336         if (pipe_config->pixel_multiplier)
 337                 dotclock /= pipe_config->pixel_multiplier;
 338
 339         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 340 }
 341
 342 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 343                           const struct drm_connector_state *conn_state)
 344 {
 345         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 346         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 347         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 348         u32 temp;
 349
 350         if (!intel_crtc_has_dp_encoder(crtc_state))
 351                 return;
 352
 353         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
 354
 355         temp = DP_MSA_MISC_SYNC_CLOCK;
 356
 357         switch (crtc_state->pipe_bpp) {
 358         case 18:
 359                 temp |= DP_MSA_MISC_6_BPC;
 360                 break;
 361         case 24:
 362                 temp |= DP_MSA_MISC_8_BPC;
 363                 break;
 364         case 30:
 365                 temp |= DP_MSA_MISC_10_BPC;
 366                 break;
 367         case 36:
 368                 temp |= DP_MSA_MISC_12_BPC;
 369                 break;
 370         default:
 371                 MISSING_CASE(crtc_state->pipe_bpp);
 372                 break;
 373         }
 374
 375         /* nonsense combination */
 376         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
 377                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 378
 379         if (crtc_state->limited_color_range)
 380                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
 381
 382         /*
 383          * As per DP 1.2 spec section 2.3.4.3 while sending
 384          * YCBCR 444 signals we should program MSA MISC1/0 fields with
 385          * colorspace information.
 386          */
 387         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 388                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
 389
 390         /*
 391          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 392          * of Color Encoding Format and Content Color Gamut] while sending
 393          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 394          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 395          */
 396         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 397                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 398
 399         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
 400 }
 401
 402 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
 403 {
 404         if (master_transcoder == TRANSCODER_EDP)
 405                 return 0;
 406         else
 407                 return master_transcoder + 1;
 408 }
 409
 410 /*
 411  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 412  *
 413  * Only intended to be used by intel_ddi_enable_transcoder_func() and
 414  * intel_ddi_config_transcoder_func().
 415  */
 416 static u32
 417 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 418                                       const struct intel_crtc_state *crtc_state)
 419 {
 420         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 421         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 422         enum pipe pipe = crtc->pipe;
 423         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 424         enum port port = encoder->port;
 425         u32 temp;
 426
 427         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 428         temp = TRANS_DDI_FUNC_ENABLE;
 429         if (DISPLAY_VER(dev_priv) >= 12)
 430                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
 431         else
 432                 temp |= TRANS_DDI_SELECT_PORT(port);
 433
 434         switch (crtc_state->pipe_bpp) {
 435         case 18:
 436                 temp |= TRANS_DDI_BPC_6;
 437                 break;
 438         case 24:
 439                 temp |= TRANS_DDI_BPC_8;
 440                 break;
 441         case 30:
 442                 temp |= TRANS_DDI_BPC_10;
 443                 break;
 444         case 36:
 445                 temp |= TRANS_DDI_BPC_12;
 446                 break;
 447         default:
 448                 BUG();
 449         }
 450
 451         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 452                 temp |= TRANS_DDI_PVSYNC;
 453         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 454                 temp |= TRANS_DDI_PHSYNC;
 455
 456         if (cpu_transcoder == TRANSCODER_EDP) {
 457                 switch (pipe) {
 458                 case PIPE_A:
 459                         /* On Haswell, can only use the always-on power well for
 460                          * eDP when not using the panel fitter, and when not
 461                          * using motion blur mitigation (which we don't
 462                          * support). */
 463                         if (crtc_state->pch_pfit.force_thru)
 464                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 465                         else
 466                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 467                         break;
 468                 case PIPE_B:
 469                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 470                         break;
 471                 case PIPE_C:
 472                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 473                         break;
 474                 default:
 475                         BUG();
 476                         break;
 477                 }
 478         }
 479
 480         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 481                 if (crtc_state->has_hdmi_sink)
 482                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 483                 else
 484                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 485
 486                 if (crtc_state->hdmi_scrambling)
 487                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
 488                 if (crtc_state->hdmi_high_tmds_clock_ratio)
 489                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
 490         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 491                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 492                 temp |= (crtc_state->fdi_lanes - 1) << 1;
 493         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 494                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 495                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 496
 497                 if (DISPLAY_VER(dev_priv) >= 12) {
 498                         enum transcoder master;
 499
 500                         master = crtc_state->mst_master_transcoder;
 501                         drm_WARN_ON(&dev_priv->drm,
 502                                     master == INVALID_TRANSCODER);
 503                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
 504                 }
 505         } else {
 506                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 507                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 508         }
 509
 510         if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
 511             crtc_state->master_transcoder != INVALID_TRANSCODER) {
 512                 u8 master_select =
 513                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
 514
 515                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
 516                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
 517         }
 518
 519         return temp;
 520 }
 521
 522 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 523                                       const struct intel_crtc_state *crtc_state)
 524 {
 525         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 526         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 527         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 528
 529         if (DISPLAY_VER(dev_priv) >= 11) {
 530                 enum transcoder master_transcoder = crtc_state->master_transcoder;
 531                 u32 ctl2 = 0;
 532
 533                 if (master_transcoder != INVALID_TRANSCODER) {
 534                         u8 master_select =
 535                                 bdw_trans_port_sync_master_select(master_transcoder);
 536
 537                         ctl2 |= PORT_SYNC_MODE_ENABLE |
 538                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
 539                 }
 540
 541                 intel_de_write(dev_priv,
 542                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 543         }
 544
 545         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 546                        intel_ddi_transcoder_func_reg_val_get(encoder,
 547                                                              crtc_state));
 548 }
 549
 550 /*
 551  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
 552  * bit.
 553  */
 554 static void
 555 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 556                                  const struct intel_crtc_state *crtc_state)
 557 {
 558         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 559         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 560         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 561         u32 ctl;
 562
 563         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 564         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 565         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 566 }
 567
 568 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 569 {
 570         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 571         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 572         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 573         u32 ctl;
 574
 575         if (DISPLAY_VER(dev_priv) >= 11)
 576                 intel_de_write(dev_priv,
 577                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 578
 579         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 580
 581         drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 582
 583         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 584
 585         if (IS_DISPLAY_VER(dev_priv, 8, 10))
 586                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
 587                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 588
 589         if (DISPLAY_VER(dev_priv) >= 12) {
 590                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
 591                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 592                                  TRANS_DDI_MODE_SELECT_MASK);
 593                 }
 594         } else {
 595                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 596         }
 597
 598         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 599
 600         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
 601             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 602                 drm_dbg_kms(&dev_priv->drm,
 603                             "Quirk Increase DDI disabled time\n");
 604                 /* Quirk time at 100ms for reliable operation */
 605                 msleep(100);
 606         }
 607 }
 608
 609 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 610                                enum transcoder cpu_transcoder,
 611                                bool enable, u32 hdcp_mask)
 612 {
 613         struct drm_device *dev = intel_encoder->base.dev;
 614         struct drm_i915_private *dev_priv = to_i915(dev);
 615         intel_wakeref_t wakeref;
 616         int ret = 0;
 617         u32 tmp;
 618
 619         wakeref = intel_display_power_get_if_enabled(dev_priv,
 620                                                      intel_encoder->power_domain);
 621         if (drm_WARN_ON(dev, !wakeref))
 622                 return -ENXIO;
 623
 624         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 625         if (enable)
 626                 tmp |= hdcp_mask;
 627         else
 628                 tmp &= ~hdcp_mask;
 629         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
 630         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 631         return ret;
 632 }
 633
 634 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 635 {
 636         struct drm_device *dev = intel_connector->base.dev;
 637         struct drm_i915_private *dev_priv = to_i915(dev);
 638         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 639         int type = intel_connector->base.connector_type;
 640         enum port port = encoder->port;
 641         enum transcoder cpu_transcoder;
 642         intel_wakeref_t wakeref;
 643         enum pipe pipe = 0;
 644         u32 tmp;
 645         bool ret;
 646
 647         wakeref = intel_display_power_get_if_enabled(dev_priv,
 648                                                      encoder->power_domain);
 649         if (!wakeref)
 650                 return false;
 651
 652         if (!encoder->get_hw_state(encoder, &pipe)) {
 653                 ret = false;
 654                 goto out;
 655         }
 656
 657         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
 658                 cpu_transcoder = TRANSCODER_EDP;
 659         else
 660                 cpu_transcoder = (enum transcoder) pipe;
 661
 662         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 663
 664         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 665         case TRANS_DDI_MODE_SELECT_HDMI:
 666         case TRANS_DDI_MODE_SELECT_DVI:
 667                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
 668                 break;
 669
 670         case TRANS_DDI_MODE_SELECT_DP_SST:
 671                 ret = type == DRM_MODE_CONNECTOR_eDP ||
 672                       type == DRM_MODE_CONNECTOR_DisplayPort;
 673                 break;
 674
 675         case TRANS_DDI_MODE_SELECT_DP_MST:
 676                 /* if the transcoder is in MST state then
 677                  * connector isn't connected */
 678                 ret = false;
 679                 break;
 680
 681         case TRANS_DDI_MODE_SELECT_FDI:
 682                 ret = type == DRM_MODE_CONNECTOR_VGA;
 683                 break;
 684
 685         default:
 686                 ret = false;
 687                 break;
 688         }
 689
 690 out:
 691         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 692
 693         return ret;
 694 }
 695
 696 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 697                                         u8 *pipe_mask, bool *is_dp_mst)
 698 {
 699         struct drm_device *dev = encoder->base.dev;
 700         struct drm_i915_private *dev_priv = to_i915(dev);
 701         enum port port = encoder->port;
 702         intel_wakeref_t wakeref;
 703         enum pipe p;
 704         u32 tmp;
 705         u8 mst_pipe_mask;
 706
 707         *pipe_mask = 0;
 708         *is_dp_mst = false;
 709
 710         wakeref = intel_display_power_get_if_enabled(dev_priv,
 711                                                      encoder->power_domain);
 712         if (!wakeref)
 713                 return;
 714
 715         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 716         if (!(tmp & DDI_BUF_CTL_ENABLE))
 717                 goto out;
 718
 719         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 720                 tmp = intel_de_read(dev_priv,
 721                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 722
 723                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 724                 default:
 725                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
 726                         fallthrough;
 727                 case TRANS_DDI_EDP_INPUT_A_ON:
 728                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
 729                         *pipe_mask = BIT(PIPE_A);
 730                         break;
 731                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
 732                         *pipe_mask = BIT(PIPE_B);
 733                         break;
 734                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
 735                         *pipe_mask = BIT(PIPE_C);
 736                         break;
 737                 }
 738
 739                 goto out;
 740         }
 741
 742         mst_pipe_mask = 0;
 743         for_each_pipe(dev_priv, p) {
 744                 enum transcoder cpu_transcoder = (enum transcoder)p;
 745                 unsigned int port_mask, ddi_select;
 746                 intel_wakeref_t trans_wakeref;
 747
 748                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 749                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 750                 if (!trans_wakeref)
 751                         continue;
 752
 753                 if (DISPLAY_VER(dev_priv) >= 12) {
 754                         port_mask = TGL_TRANS_DDI_PORT_MASK;
 755                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
 756                 } else {
 757                         port_mask = TRANS_DDI_PORT_MASK;
 758                         ddi_select = TRANS_DDI_SELECT_PORT(port);
 759                 }
 760
 761                 tmp = intel_de_read(dev_priv,
 762                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
 763                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 764                                         trans_wakeref);
 765
 766                 if ((tmp & port_mask) != ddi_select)
 767                         continue;
 768
 769                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
 770                     TRANS_DDI_MODE_SELECT_DP_MST)
 771                         mst_pipe_mask |= BIT(p);
 772
 773                 *pipe_mask |= BIT(p);
 774         }
 775
 776         if (!*pipe_mask)
 777                 drm_dbg_kms(&dev_priv->drm,
 778                             "No pipe for [ENCODER:%d:%s] found\n",
 779                             encoder->base.base.id, encoder->base.name);
 780
 781         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 782                 drm_dbg_kms(&dev_priv->drm,
 783                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
 784                             encoder->base.base.id, encoder->base.name,
 785                             *pipe_mask);
 786                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
 787         }
 788
 789         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 790                 drm_dbg_kms(&dev_priv->drm,
 791                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
 792                             encoder->base.base.id, encoder->base.name,
 793                             *pipe_mask, mst_pipe_mask);
 794         else
 795                 *is_dp_mst = mst_pipe_mask;
 796
 797 out:
 798         if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
 799                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
 800                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 801                             BXT_PHY_LANE_POWERDOWN_ACK |
 802                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 803                         drm_err(&dev_priv->drm,
 804                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
 805                                 encoder->base.base.id, encoder->base.name, tmp);
 806         }
 807
 808         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 809 }
 810
 811 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 812                             enum pipe *pipe)
 813 {
 814         u8 pipe_mask;
 815         bool is_mst;
 816
 817         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
 818
 819         if (is_mst || !pipe_mask)
 820                 return false;
 821
 822         *pipe = ffs(pipe_mask) - 1;
 823
 824         return true;
 825 }
 826
 827 static enum intel_display_power_domain
 828 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 829 {
 830         /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 831          * DC states enabled at the same time, while for driver initiated AUX
 832          * transfers we need the same AUX IOs to be powered but with DC states
 833          * disabled. Accordingly use the AUX power domain here which leaves DC
 834          * states enabled.
 835          * However, for non-A AUX ports the corresponding non-EDP transcoders
 836          * would have already enabled power well 2 and DC_OFF. This means we can
 837          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
 838          * specific AUX_IO reference without powering up any extra wells.
 839          * Note that PSR is enabled only on Port A even though this function
 840          * returns the correct domain for other ports too.
 841          */
 842         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
 843                                               intel_aux_power_domain(dig_port);
 844 }
 845
 846 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 847                                         struct intel_crtc_state *crtc_state)
 848 {
 849         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 850         struct intel_digital_port *dig_port;
 851         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 852
 853         /*
 854          * TODO: Add support for MST encoders. Atm, the following should never
 855          * happen since fake-MST encoders don't set their get_power_domains()
 856          * hook.
 857          */
 858         if (drm_WARN_ON(&dev_priv->drm,
 859                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
 860                 return;
 861
 862         dig_port = enc_to_dig_port(encoder);
 863
 864         if (!intel_phy_is_tc(dev_priv, phy) ||
 865             dig_port->tc_mode != TC_PORT_TBT_ALT) {
 866                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 867                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
 868                                                                    dig_port->ddi_io_power_domain);
 869         }
 870
 871         /*
 872          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
 873          * ports.
 874          */
 875         if (intel_crtc_has_dp_encoder(crtc_state) ||
 876             intel_phy_is_tc(dev_priv, phy)) {
 877                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 878                 dig_port->aux_wakeref =
 879                         intel_display_power_get(dev_priv,
 880                                                 intel_ddi_main_link_aux_domain(dig_port));
 881         }
 882 }
 883
 884 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
 885                                  const struct intel_crtc_state *crtc_state)
 886 {
 887         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 888         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 889         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 890         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 891         u32 val;
 892
 893         if (cpu_transcoder != TRANSCODER_EDP) {
 894                 if (DISPLAY_VER(dev_priv) >= 13)
 895                         val = TGL_TRANS_CLK_SEL_PORT(phy);
 896                 else if (DISPLAY_VER(dev_priv) >= 12)
 897                         val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
 898                 else
 899                         val = TRANS_CLK_SEL_PORT(encoder->port);
 900
 901                 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
 902         }
 903 }
 904
 905 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
 906 {
 907         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 908         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 909
 910         if (cpu_transcoder != TRANSCODER_EDP) {
 911                 if (DISPLAY_VER(dev_priv) >= 12)
 912                         intel_de_write(dev_priv,
 913                                        TRANS_CLK_SEL(cpu_transcoder),
 914                                        TGL_TRANS_CLK_SEL_DISABLED);
 915                 else
 916                         intel_de_write(dev_priv,
 917                                        TRANS_CLK_SEL(cpu_transcoder),
 918                                        TRANS_CLK_SEL_DISABLED);
 919         }
 920 }
 921
 922 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 923                                 enum port port, u8 iboost)
 924 {
 925         u32 tmp;
 926
 927         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
 928         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
 929         if (iboost)
 930                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
 931         else
 932                 tmp |= BALANCE_LEG_DISABLE(port);
 933         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
 934 }
 935
 936 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 937                                const struct intel_crtc_state *crtc_state,
 938                                int level)
 939 {
 940         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 941         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 942         u8 iboost;
 943
 944         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 945                 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata);
 946         else
 947                 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata);
 948
 949         if (iboost == 0) {
 950                 const struct intel_ddi_buf_trans *ddi_translations;
 951                 int n_entries;
 952
 953                 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 954                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 955                         return;
 956                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 957                         level = n_entries - 1;
 958
 959                 iboost = ddi_translations->entries[level].hsw.i_boost;
 960         }
 961
 962         /* Make sure that the requested I_boost is valid */
 963         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
 964                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
 965                 return;
 966         }
 967
 968         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
 969
 970         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
 971                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
 972 }
 973
 974 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
 975                                     const struct intel_crtc_state *crtc_state,
 976                                     int level)
 977 {
 978         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 979         const struct intel_ddi_buf_trans *ddi_translations;
 980         enum port port = encoder->port;
 981         int n_entries;
 982
 983         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 984         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 985                 return;
 986         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 987                 level = n_entries - 1;
 988
 989         bxt_ddi_phy_set_signal_level(dev_priv, port,
 990                                      ddi_translations->entries[level].bxt.margin,
 991                                      ddi_translations->entries[level].bxt.scale,
 992                                      ddi_translations->entries[level].bxt.enable,
 993                                      ddi_translations->entries[level].bxt.deemphasis);
 994 }
 995
 996 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
 997                                    const struct intel_crtc_state *crtc_state)
 998 {
 999         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1000         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1001         int n_entries;
1002
1003         encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1004
1005         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1006                 n_entries = 1;
1007         if (drm_WARN_ON(&dev_priv->drm,
1008                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1009                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1010
1011         return index_to_dp_signal_levels[n_entries - 1] &
1012                 DP_TRAIN_VOLTAGE_SWING_MASK;
1013 }
1014
1015 /*
1016  * We assume that the full set of pre-emphasis values can be
1017  * used on all DDI platforms. Should that change we need to
1018  * rethink this code.
1019  */
1020 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1021 {
1022         return DP_TRAIN_PRE_EMPH_LEVEL_3;
1023 }
1024
1025 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1026                                          const struct intel_crtc_state *crtc_state,
1027                                          int level)
1028 {
1029         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1030         const struct intel_ddi_buf_trans *ddi_translations;
1031         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1032         int n_entries, ln;
1033         u32 val;
1034
1035         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1036         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1037                 return;
1038         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1039                 level = n_entries - 1;
1040
1041         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1042                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1043
1044                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1045                 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
1046                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1047                              intel_dp->hobl_active ? val : 0);
1048         }
1049
1050         /* Set PORT_TX_DW5 */
1051         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1052         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1053                   TAP2_DISABLE | TAP3_DISABLE);
1054         val |= SCALING_MODE_SEL(0x2);
1055         val |= RTERM_SELECT(0x6);
1056         val |= TAP3_DISABLE;
1057         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1058
1059         /* Program PORT_TX_DW2 */
1060         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
1061         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1062                  RCOMP_SCALAR_MASK);
1063         val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
1064         val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
1065         /* Program Rcomp scalar for every table entry */
1066         val |= RCOMP_SCALAR(0x98);
1067         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
1068
1069         /* Program PORT_TX_DW4 */
1070         /* We cannot write to GRP. It would overwrite individual loadgen. */
1071         for (ln = 0; ln <= 3; ln++) {
1072                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1073                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1074                          CURSOR_COEFF_MASK);
1075                 val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
1076                 val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
1077                 val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
1078                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1079         }
1080
1081         /* Program PORT_TX_DW7 */
1082         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
1083         val &= ~N_SCALAR_MASK;
1084         val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
1085         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
1086 }
1087
1088 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1089                                               const struct intel_crtc_state *crtc_state,
1090                                               int level)
1091 {
1092         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1093         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1094         int width, rate, ln;
1095         u32 val;
1096
1097         width = crtc_state->lane_count;
1098         rate = crtc_state->port_clock;
1099
1100         /*
1101          * 1. If port type is eDP or DP,
1102          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1103          * else clear to 0b.
1104          */
1105         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
1106         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1107                 val &= ~COMMON_KEEPER_EN;
1108         else
1109                 val |= COMMON_KEEPER_EN;
1110         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1111
1112         /* 2. Program loadgen select */
1113         /*
1114          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1115          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1116          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1117          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1118          */
1119         for (ln = 0; ln <= 3; ln++) {
1120                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1121                 val &= ~LOADGEN_SELECT;
1122
1123                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
1124                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
1125                         val |= LOADGEN_SELECT;
1126                 }
1127                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1128         }
1129
1130         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1131         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
1132         val |= SUS_CLOCK_CONFIG;
1133         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
1134
1135         /* 4. Clear training enable to change swing values */
1136         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1137         val &= ~TX_TRAINING_EN;
1138         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1139
1140         /* 5. Program swing and de-emphasis */
1141         icl_ddi_combo_vswing_program(encoder, crtc_state, level);
1142
1143         /* 6. Set training enable to trigger update */
1144         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1145         val |= TX_TRAINING_EN;
1146         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1147 }
1148
1149 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1150                                            const struct intel_crtc_state *crtc_state,
1151                                            int level)
1152 {
1153         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1154         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1155         const struct intel_ddi_buf_trans *ddi_translations;
1156         int n_entries, ln;
1157         u32 val;
1158
1159         if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1160                 return;
1161
1162         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1163         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1164                 return;
1165         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1166                 level = n_entries - 1;
1167
1168         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
1169         for (ln = 0; ln < 2; ln++) {
1170                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
1171                 val &= ~CRI_USE_FS32;
1172                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
1173
1174                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
1175                 val &= ~CRI_USE_FS32;
1176                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
1177         }
1178
1179         /* Program MG_TX_SWINGCTRL with values from vswing table */
1180         for (ln = 0; ln < 2; ln++) {
1181                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
1182                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1183                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1184                         ddi_translations->entries[level].mg.cri_txdeemph_override_17_12);
1185                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
1186
1187                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
1188                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1189                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1190                         ddi_translations->entries[level].mg.cri_txdeemph_override_17_12);
1191                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
1192         }
1193
1194         /* Program MG_TX_DRVCTRL with values from vswing table */
1195         for (ln = 0; ln < 2; ln++) {
1196                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
1197                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1198                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1199                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1200                         ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) |
1201                         CRI_TXDEEMPH_OVERRIDE_11_6(
1202                                 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) |
1203                         CRI_TXDEEMPH_OVERRIDE_EN;
1204                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
1205
1206                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
1207                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1208                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1209                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1210                         ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) |
1211                         CRI_TXDEEMPH_OVERRIDE_11_6(
1212                                 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) |
1213                         CRI_TXDEEMPH_OVERRIDE_EN;
1214                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
1215
1216                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1217         }
1218
1219         /*
1220          * Program MG_CLKHUB<LN, port being used> with value from frequency table
1221          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1222          * values from table for which TX1 and TX2 enabled.
1223          */
1224         for (ln = 0; ln < 2; ln++) {
1225                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
1226                 if (crtc_state->port_clock < 300000)
1227                         val |= CFG_LOW_RATE_LKREN_EN;
1228                 else
1229                         val &= ~CFG_LOW_RATE_LKREN_EN;
1230                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
1231         }
1232
1233         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1234         for (ln = 0; ln < 2; ln++) {
1235                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
1236                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1237                 if (crtc_state->port_clock <= 500000) {
1238                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1239                 } else {
1240                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1241                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1242                 }
1243                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
1244
1245                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
1246                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1247                 if (crtc_state->port_clock <= 500000) {
1248                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1249                 } else {
1250                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1251                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1252                 }
1253                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
1254         }
1255
1256         /* Program MG_TX_PISO_READLOAD with values from vswing table */
1257         for (ln = 0; ln < 2; ln++) {
1258                 val = intel_de_read(dev_priv,
1259                                     MG_TX1_PISO_READLOAD(ln, tc_port));
1260                 val |= CRI_CALCINIT;
1261                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1262                                val);
1263
1264                 val = intel_de_read(dev_priv,
1265                                     MG_TX2_PISO_READLOAD(ln, tc_port));
1266                 val |= CRI_CALCINIT;
1267                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1268                                val);
1269         }
1270 }
1271
1272 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
1273                                     const struct intel_crtc_state *crtc_state,
1274                                     int level)
1275 {
1276         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1277         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1278
1279         if (intel_phy_is_combo(dev_priv, phy))
1280                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1281         else
1282                 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1283 }
1284
1285 static void
1286 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1287                                 const struct intel_crtc_state *crtc_state,
1288                                 int level)
1289 {
1290         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1291         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1292         const struct intel_ddi_buf_trans *ddi_translations;
1293         u32 val, dpcnt_mask, dpcnt_val;
1294         int n_entries, ln;
1295
1296         if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1297                 return;
1298
1299         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1300         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1301                 return;
1302         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1303                 level = n_entries - 1;
1304
1305         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
1306                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1307                       DKL_TX_VSWING_CONTROL_MASK);
1308         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations->entries[level].dkl.dkl_vswing_control);
1309         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control);
1310         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control);
1311
1312         for (ln = 0; ln < 2; ln++) {
1313                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
1314                                HIP_INDEX_VAL(tc_port, ln));
1315
1316                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
1317
1318                 /* All the registers are RMW */
1319                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
1320                 val &= ~dpcnt_mask;
1321                 val |= dpcnt_val;
1322                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
1323
1324                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
1325                 val &= ~dpcnt_mask;
1326                 val |= dpcnt_val;
1327                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
1328
1329                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
1330                 val &= ~DKL_TX_DP20BITMODE;
1331                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
1332
1333                 if ((intel_crtc_has_dp_encoder(crtc_state) &&
1334                      crtc_state->port_clock == 162000) ||
1335                     (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1336                      crtc_state->port_clock == 594000))
1337                         val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
1338                 else
1339                         val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
1340         }
1341 }
1342
1343 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
1344                                     const struct intel_crtc_state *crtc_state,
1345                                     int level)
1346 {
1347         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1348         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1349
1350         if (intel_phy_is_combo(dev_priv, phy))
1351                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1352         else
1353                 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1354 }
1355
1356 static int translate_signal_level(struct intel_dp *intel_dp,
1357                                   u8 signal_levels)
1358 {
1359         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1360         int i;
1361
1362         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1363                 if (index_to_dp_signal_levels[i] == signal_levels)
1364                         return i;
1365         }
1366
1367         drm_WARN(&i915->drm, 1,
1368                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1369                  signal_levels);
1370
1371         return 0;
1372 }
1373
1374 static int intel_ddi_dp_level(struct intel_dp *intel_dp)
1375 {
1376         u8 train_set = intel_dp->train_set[0];
1377         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1378                                         DP_TRAIN_PRE_EMPHASIS_MASK);
1379
1380         return translate_signal_level(intel_dp, signal_levels);
1381 }
1382
1383 static void
1384 dg2_set_signal_levels(struct intel_dp *intel_dp,
1385                       const struct intel_crtc_state *crtc_state)
1386 {
1387         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1388         int level = intel_ddi_dp_level(intel_dp);
1389
1390         intel_snps_phy_ddi_vswing_sequence(encoder, level);
1391 }
1392
1393 static void
1394 tgl_set_signal_levels(struct intel_dp *intel_dp,
1395                       const struct intel_crtc_state *crtc_state)
1396 {
1397         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1398         int level = intel_ddi_dp_level(intel_dp);
1399
1400         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
1401 }
1402
1403 static void
1404 icl_set_signal_levels(struct intel_dp *intel_dp,
1405                       const struct intel_crtc_state *crtc_state)
1406 {
1407         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1408         int level = intel_ddi_dp_level(intel_dp);
1409
1410         icl_ddi_vswing_sequence(encoder, crtc_state, level);
1411 }
1412
1413 static void
1414 bxt_set_signal_levels(struct intel_dp *intel_dp,
1415                       const struct intel_crtc_state *crtc_state)
1416 {
1417         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1418         int level = intel_ddi_dp_level(intel_dp);
1419
1420         bxt_ddi_vswing_sequence(encoder, crtc_state, level);
1421 }
1422
1423 static void
1424 hsw_set_signal_levels(struct intel_dp *intel_dp,
1425                       const struct intel_crtc_state *crtc_state)
1426 {
1427         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1428         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1429         int level = intel_ddi_dp_level(intel_dp);
1430         enum port port = encoder->port;
1431         u32 signal_levels;
1432
1433         signal_levels = DDI_BUF_TRANS_SELECT(level);
1434
1435         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1436                     signal_levels);
1437
1438         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1439         intel_dp->DP |= signal_levels;
1440
1441         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
1442                 skl_ddi_set_iboost(encoder, crtc_state, level);
1443
1444         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1445         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1446 }
1447
1448 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1449                                   u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1450 {
1451         mutex_lock(&i915->dpll.lock);
1452
1453         intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1454
1455         /*
1456          * "This step and the step before must be
1457          *  done with separate register writes."
1458          */
1459         intel_de_rmw(i915, reg, clk_off, 0);
1460
1461         mutex_unlock(&i915->dpll.lock);
1462 }
1463
1464 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1465                                    u32 clk_off)
1466 {
1467         mutex_lock(&i915->dpll.lock);
1468
1469         intel_de_rmw(i915, reg, 0, clk_off);
1470
1471         mutex_unlock(&i915->dpll.lock);
1472 }
1473
1474 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1475                                       u32 clk_off)
1476 {
1477         return !(intel_de_read(i915, reg) & clk_off);
1478 }
1479
1480 static struct intel_shared_dpll *
1481 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1482                  u32 clk_sel_mask, u32 clk_sel_shift)
1483 {
1484         enum intel_dpll_id id;
1485
1486         id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1487
1488         return intel_get_shared_dpll_by_id(i915, id);
1489 }
1490
1491 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1492                                   const struct intel_crtc_state *crtc_state)
1493 {
1494         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1495         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1496         enum phy phy = intel_port_to_phy(i915, encoder->port);
1497
1498         if (drm_WARN_ON(&i915->drm, !pll))
1499                 return;
1500
1501         _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1502                               ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1503                               pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1504                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1505 }
1506
1507 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1508 {
1509         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1510         enum phy phy = intel_port_to_phy(i915, encoder->port);
1511
1512         _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1513                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1514 }
1515
1516 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1517 {
1518         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1519         enum phy phy = intel_port_to_phy(i915, encoder->port);
1520
1521         return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1522                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1523 }
1524
1525 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1526 {
1527         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1528         enum phy phy = intel_port_to_phy(i915, encoder->port);
1529
1530         return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1531                                 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1532                                 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1533 }
1534
1535 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1536                                  const struct intel_crtc_state *crtc_state)
1537 {
1538         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1539         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1540         enum phy phy = intel_port_to_phy(i915, encoder->port);
1541
1542         if (drm_WARN_ON(&i915->drm, !pll))
1543                 return;
1544
1545         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1546                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1547                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1548                               RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1549 }
1550
1551 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1552 {
1553         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1554         enum phy phy = intel_port_to_phy(i915, encoder->port);
1555
1556         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1557                                RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1558 }
1559
1560 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1561 {
1562         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1563         enum phy phy = intel_port_to_phy(i915, encoder->port);
1564
1565         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1566                                          RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1567 }
1568
1569 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1570 {
1571         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1572         enum phy phy = intel_port_to_phy(i915, encoder->port);
1573
1574         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1575                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1576                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1577 }
1578
1579 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1580                                  const struct intel_crtc_state *crtc_state)
1581 {
1582         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1583         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1584         enum phy phy = intel_port_to_phy(i915, encoder->port);
1585
1586         if (drm_WARN_ON(&i915->drm, !pll))
1587                 return;
1588
1589         /*
1590          * If we fail this, something went very wrong: first 2 PLLs should be
1591          * used by first 2 phys and last 2 PLLs by last phys
1592          */
1593         if (drm_WARN_ON(&i915->drm,
1594                         (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1595                         (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1596                 return;
1597
1598         _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1599                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1600                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1601                               DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1602 }
1603
1604 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1605 {
1606         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1607         enum phy phy = intel_port_to_phy(i915, encoder->port);
1608
1609         _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1610                                DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1611 }
1612
1613 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1614 {
1615         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1616         enum phy phy = intel_port_to_phy(i915, encoder->port);
1617
1618         return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1619                                          DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1620 }
1621
1622 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1623 {
1624         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1625         enum phy phy = intel_port_to_phy(i915, encoder->port);
1626         enum intel_dpll_id id;
1627         u32 val;
1628
1629         val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1630         val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1631         val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1632         id = val;
1633
1634         /*
1635          * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1636          * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1637          * bit for phy C and D.
1638          */
1639         if (phy >= PHY_C)
1640                 id += DPLL_ID_DG1_DPLL2;
1641
1642         return intel_get_shared_dpll_by_id(i915, id);
1643 }
1644
1645 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1646                                        const struct intel_crtc_state *crtc_state)
1647 {
1648         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1649         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1650         enum phy phy = intel_port_to_phy(i915, encoder->port);
1651
1652         if (drm_WARN_ON(&i915->drm, !pll))
1653                 return;
1654
1655         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1656                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1657                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1658                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1659 }
1660
1661 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1662 {
1663         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1664         enum phy phy = intel_port_to_phy(i915, encoder->port);
1665
1666         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1667                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1668 }
1669
1670 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1671 {
1672         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1673         enum phy phy = intel_port_to_phy(i915, encoder->port);
1674
1675         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1676                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1677 }
1678
1679 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1680 {
1681         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1682         enum phy phy = intel_port_to_phy(i915, encoder->port);
1683
1684         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1685                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1686                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1687 }
1688
1689 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1690                                     const struct intel_crtc_state *crtc_state)
1691 {
1692         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1693         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1694         enum port port = encoder->port;
1695
1696         if (drm_WARN_ON(&i915->drm, !pll))
1697                 return;
1698
1699         /*
1700          * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1701          *  MG does not exist, but the programming is required to ungate DDIC and DDID."
1702          */
1703         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1704
1705         icl_ddi_combo_enable_clock(encoder, crtc_state);
1706 }
1707
1708 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1709 {
1710         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1711         enum port port = encoder->port;
1712
1713         icl_ddi_combo_disable_clock(encoder);
1714
1715         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1716 }
1717
1718 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1719 {
1720         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1721         enum port port = encoder->port;
1722         u32 tmp;
1723
1724         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1725
1726         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1727                 return false;
1728
1729         return icl_ddi_combo_is_clock_enabled(encoder);
1730 }
1731
1732 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1733                                     const struct intel_crtc_state *crtc_state)
1734 {
1735         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1736         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1737         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1738         enum port port = encoder->port;
1739
1740         if (drm_WARN_ON(&i915->drm, !pll))
1741                 return;
1742
1743         intel_de_write(i915, DDI_CLK_SEL(port),
1744                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1745
1746         mutex_lock(&i915->dpll.lock);
1747
1748         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1749                      ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1750
1751         mutex_unlock(&i915->dpll.lock);
1752 }
1753
1754 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1755 {
1756         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1757         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1758         enum port port = encoder->port;
1759
1760         mutex_lock(&i915->dpll.lock);
1761
1762         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1763                      0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1764
1765         mutex_unlock(&i915->dpll.lock);
1766
1767         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1768 }
1769
1770 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1771 {
1772         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1773         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1774         enum port port = encoder->port;
1775         u32 tmp;
1776
1777         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1778
1779         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1780                 return false;
1781
1782         tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1783
1784         return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1785 }
1786
1787 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1788 {
1789         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1790         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1791         enum port port = encoder->port;
1792         enum intel_dpll_id id;
1793         u32 tmp;
1794
1795         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1796
1797         switch (tmp & DDI_CLK_SEL_MASK) {
1798         case DDI_CLK_SEL_TBT_162:
1799         case DDI_CLK_SEL_TBT_270:
1800         case DDI_CLK_SEL_TBT_540:
1801         case DDI_CLK_SEL_TBT_810:
1802                 id = DPLL_ID_ICL_TBTPLL;
1803                 break;
1804         case DDI_CLK_SEL_MG:
1805                 id = icl_tc_port_to_pll_id(tc_port);
1806                 break;
1807         default:
1808                 MISSING_CASE(tmp);
1809                 fallthrough;
1810         case DDI_CLK_SEL_NONE:
1811                 return NULL;
1812         }
1813
1814         return intel_get_shared_dpll_by_id(i915, id);
1815 }
1816
1817 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1818 {
1819         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1820         enum intel_dpll_id id;
1821
1822         switch (encoder->port) {
1823         case PORT_A:
1824                 id = DPLL_ID_SKL_DPLL0;
1825                 break;
1826         case PORT_B:
1827                 id = DPLL_ID_SKL_DPLL1;
1828                 break;
1829         case PORT_C:
1830                 id = DPLL_ID_SKL_DPLL2;
1831                 break;
1832         default:
1833                 MISSING_CASE(encoder->port);
1834                 return NULL;
1835         }
1836
1837         return intel_get_shared_dpll_by_id(i915, id);
1838 }
1839
1840 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1841                                  const struct intel_crtc_state *crtc_state)
1842 {
1843         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1844         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1845         enum port port = encoder->port;
1846
1847         if (drm_WARN_ON(&i915->drm, !pll))
1848                 return;
1849
1850         mutex_lock(&i915->dpll.lock);
1851
1852         intel_de_rmw(i915, DPLL_CTRL2,
1853                      DPLL_CTRL2_DDI_CLK_OFF(port) |
1854                      DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1855                      DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1856                      DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1857
1858         mutex_unlock(&i915->dpll.lock);
1859 }
1860
1861 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1862 {
1863         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1864         enum port port = encoder->port;
1865
1866         mutex_lock(&i915->dpll.lock);
1867
1868         intel_de_rmw(i915, DPLL_CTRL2,
1869                      0, DPLL_CTRL2_DDI_CLK_OFF(port));
1870
1871         mutex_unlock(&i915->dpll.lock);
1872 }
1873
1874 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1875 {
1876         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1877         enum port port = encoder->port;
1878
1879         /*
1880          * FIXME Not sure if the override affects both
1881          * the PLL selection and the CLK_OFF bit.
1882          */
1883         return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1884 }
1885
1886 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1887 {
1888         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1889         enum port port = encoder->port;
1890         enum intel_dpll_id id;
1891         u32 tmp;
1892
1893         tmp = intel_de_read(i915, DPLL_CTRL2);
1894
1895         /*
1896          * FIXME Not sure if the override affects both
1897          * the PLL selection and the CLK_OFF bit.
1898          */
1899         if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1900                 return NULL;
1901
1902         id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1903                 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1904
1905         return intel_get_shared_dpll_by_id(i915, id);
1906 }
1907
1908 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1909                           const struct intel_crtc_state *crtc_state)
1910 {
1911         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1912         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1913         enum port port = encoder->port;
1914
1915         if (drm_WARN_ON(&i915->drm, !pll))
1916                 return;
1917
1918         intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1919 }
1920
1921 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1922 {
1923         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1924         enum port port = encoder->port;
1925
1926         intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1927 }
1928
1929 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1930 {
1931         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1932         enum port port = encoder->port;
1933
1934         return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1935 }
1936
1937 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1938 {
1939         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1940         enum port port = encoder->port;
1941         enum intel_dpll_id id;
1942         u32 tmp;
1943
1944         tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1945
1946         switch (tmp & PORT_CLK_SEL_MASK) {
1947         case PORT_CLK_SEL_WRPLL1:
1948                 id = DPLL_ID_WRPLL1;
1949                 break;
1950         case PORT_CLK_SEL_WRPLL2:
1951                 id = DPLL_ID_WRPLL2;
1952                 break;
1953         case PORT_CLK_SEL_SPLL:
1954                 id = DPLL_ID_SPLL;
1955                 break;
1956         case PORT_CLK_SEL_LCPLL_810:
1957                 id = DPLL_ID_LCPLL_810;
1958                 break;
1959         case PORT_CLK_SEL_LCPLL_1350:
1960                 id = DPLL_ID_LCPLL_1350;
1961                 break;
1962         case PORT_CLK_SEL_LCPLL_2700:
1963                 id = DPLL_ID_LCPLL_2700;
1964                 break;
1965         default:
1966                 MISSING_CASE(tmp);
1967                 fallthrough;
1968         case PORT_CLK_SEL_NONE:
1969                 return NULL;
1970         }
1971
1972         return intel_get_shared_dpll_by_id(i915, id);
1973 }
1974
1975 void intel_ddi_enable_clock(struct intel_encoder *encoder,
1976                             const struct intel_crtc_state *crtc_state)
1977 {
1978         if (encoder->enable_clock)
1979                 encoder->enable_clock(encoder, crtc_state);
1980 }
1981
1982 static void intel_ddi_disable_clock(struct intel_encoder *encoder)
1983 {
1984         if (encoder->disable_clock)
1985                 encoder->disable_clock(encoder);
1986 }
1987
1988 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
1989 {
1990         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1991         u32 port_mask;
1992         bool ddi_clk_needed;
1993
1994         /*
1995          * In case of DP MST, we sanitize the primary encoder only, not the
1996          * virtual ones.
1997          */
1998         if (encoder->type == INTEL_OUTPUT_DP_MST)
1999                 return;
2000
2001         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2002                 u8 pipe_mask;
2003                 bool is_mst;
2004
2005                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2006                 /*
2007                  * In the unlikely case that BIOS enables DP in MST mode, just
2008                  * warn since our MST HW readout is incomplete.
2009                  */
2010                 if (drm_WARN_ON(&i915->drm, is_mst))
2011                         return;
2012         }
2013
2014         port_mask = BIT(encoder->port);
2015         ddi_clk_needed = encoder->base.crtc;
2016
2017         if (encoder->type == INTEL_OUTPUT_DSI) {
2018                 struct intel_encoder *other_encoder;
2019
2020                 port_mask = intel_dsi_encoder_ports(encoder);
2021                 /*
2022                  * Sanity check that we haven't incorrectly registered another
2023                  * encoder using any of the ports of this DSI encoder.
2024                  */
2025                 for_each_intel_encoder(&i915->drm, other_encoder) {
2026                         if (other_encoder == encoder)
2027                                 continue;
2028
2029                         if (drm_WARN_ON(&i915->drm,
2030                                         port_mask & BIT(other_encoder->port)))
2031                                 return;
2032                 }
2033                 /*
2034                  * For DSI we keep the ddi clocks gated
2035                  * except during enable/disable sequence.
2036                  */
2037                 ddi_clk_needed = false;
2038         }
2039
2040         if (ddi_clk_needed || !encoder->is_clock_enabled ||
2041             !encoder->is_clock_enabled(encoder))
2042                 return;
2043
2044         drm_notice(&i915->drm,
2045                    "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2046                    encoder->base.base.id, encoder->base.name);
2047
2048         encoder->disable_clock(encoder);
2049 }
2050
2051 static void
2052 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2053                        const struct intel_crtc_state *crtc_state)
2054 {
2055         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2056         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2057         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2058         u32 ln0, ln1, pin_assignment;
2059         u8 width;
2060
2061         if (!intel_phy_is_tc(dev_priv, phy) ||
2062             dig_port->tc_mode == TC_PORT_TBT_ALT)
2063                 return;
2064
2065         if (DISPLAY_VER(dev_priv) >= 12) {
2066                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2067                                HIP_INDEX_VAL(tc_port, 0x0));
2068                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2069                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2070                                HIP_INDEX_VAL(tc_port, 0x1));
2071                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2072         } else {
2073                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2074                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2075         }
2076
2077         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2078         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2079
2080         /* DPPATC */
2081         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2082         width = crtc_state->lane_count;
2083
2084         switch (pin_assignment) {
2085         case 0x0:
2086                 drm_WARN_ON(&dev_priv->drm,
2087                             dig_port->tc_mode != TC_PORT_LEGACY);
2088                 if (width == 1) {
2089                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2090                 } else {
2091                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2092                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2093                 }
2094                 break;
2095         case 0x1:
2096                 if (width == 4) {
2097                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2098                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2099                 }
2100                 break;
2101         case 0x2:
2102                 if (width == 2) {
2103                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2104                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2105                 }
2106                 break;
2107         case 0x3:
2108         case 0x5:
2109                 if (width == 1) {
2110                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2111                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2112                 } else {
2113                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2114                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2115                 }
2116                 break;
2117         case 0x4:
2118         case 0x6:
2119                 if (width == 1) {
2120                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2121                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2122                 } else {
2123                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2124                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2125                 }
2126                 break;
2127         default:
2128                 MISSING_CASE(pin_assignment);
2129         }
2130
2131         if (DISPLAY_VER(dev_priv) >= 12) {
2132                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2133                                HIP_INDEX_VAL(tc_port, 0x0));
2134                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
2135                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2136                                HIP_INDEX_VAL(tc_port, 0x1));
2137                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
2138         } else {
2139                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2140                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2141         }
2142 }
2143
2144 static enum transcoder
2145 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2146 {
2147         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2148                 return crtc_state->mst_master_transcoder;
2149         else
2150                 return crtc_state->cpu_transcoder;
2151 }
2152
2153 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2154                          const struct intel_crtc_state *crtc_state)
2155 {
2156         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2157
2158         if (DISPLAY_VER(dev_priv) >= 12)
2159                 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2160         else
2161                 return DP_TP_CTL(encoder->port);
2162 }
2163
2164 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2165                             const struct intel_crtc_state *crtc_state)
2166 {
2167         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2168
2169         if (DISPLAY_VER(dev_priv) >= 12)
2170                 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2171         else
2172                 return DP_TP_STATUS(encoder->port);
2173 }
2174
2175 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2176                                                           const struct intel_crtc_state *crtc_state,
2177                                                           bool enable)
2178 {
2179         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2180
2181         if (!crtc_state->vrr.enable)
2182                 return;
2183
2184         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2185                                enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2186                 drm_dbg_kms(&i915->drm,
2187                             "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2188                             enabledisable(enable));
2189 }
2190
2191 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2192                                         const struct intel_crtc_state *crtc_state)
2193 {
2194         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2195
2196         if (!crtc_state->fec_enable)
2197                 return;
2198
2199         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2200                 drm_dbg_kms(&i915->drm,
2201                             "Failed to set FEC_READY in the sink\n");
2202 }
2203
2204 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2205                                  const struct intel_crtc_state *crtc_state)
2206 {
2207         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2208         struct intel_dp *intel_dp;
2209         u32 val;
2210
2211         if (!crtc_state->fec_enable)
2212                 return;
2213
2214         intel_dp = enc_to_intel_dp(encoder);
2215         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2216         val |= DP_TP_CTL_FEC_ENABLE;
2217         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2218 }
2219
2220 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2221                                         const struct intel_crtc_state *crtc_state)
2222 {
2223         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2224         struct intel_dp *intel_dp;
2225         u32 val;
2226
2227         if (!crtc_state->fec_enable)
2228                 return;
2229
2230         intel_dp = enc_to_intel_dp(encoder);
2231         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2232         val &= ~DP_TP_CTL_FEC_ENABLE;
2233         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2234         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2235 }
2236
2237 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2238                                      const struct intel_crtc_state *crtc_state)
2239 {
2240         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2241         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2242         enum phy phy = intel_port_to_phy(i915, encoder->port);
2243
2244         if (intel_phy_is_combo(i915, phy)) {
2245                 bool lane_reversal =
2246                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2247
2248                 intel_combo_phy_power_up_lanes(i915, phy, false,
2249                                                crtc_state->lane_count,
2250                                                lane_reversal);
2251         }
2252 }
2253
2254 /* Splitter enable for eDP MSO is limited to certain pipes. */
2255 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2256 {
2257         if (IS_ALDERLAKE_P(i915))
2258                 return BIT(PIPE_A) | BIT(PIPE_B);
2259         else
2260                 return BIT(PIPE_A);
2261 }
2262
2263 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2264                                      struct intel_crtc_state *pipe_config)
2265 {
2266         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2267         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2268         enum pipe pipe = crtc->pipe;
2269         u32 dss1;
2270
2271         if (!HAS_MSO(i915))
2272                 return;
2273
2274         dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2275
2276         pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2277         if (!pipe_config->splitter.enable)
2278                 return;
2279
2280         if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2281                 pipe_config->splitter.enable = false;
2282                 return;
2283         }
2284
2285         switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2286         default:
2287                 drm_WARN(&i915->drm, true,
2288                          "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2289                 fallthrough;
2290         case SPLITTER_CONFIGURATION_2_SEGMENT:
2291                 pipe_config->splitter.link_count = 2;
2292                 break;
2293         case SPLITTER_CONFIGURATION_4_SEGMENT:
2294                 pipe_config->splitter.link_count = 4;
2295                 break;
2296         }
2297
2298         pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2299 }
2300
2301 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2302 {
2303         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2304         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2305         enum pipe pipe = crtc->pipe;
2306         u32 dss1 = 0;
2307
2308         if (!HAS_MSO(i915))
2309                 return;
2310
2311         if (crtc_state->splitter.enable) {
2312                 dss1 |= SPLITTER_ENABLE;
2313                 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2314                 if (crtc_state->splitter.link_count == 2)
2315                         dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2316                 else
2317                         dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2318         }
2319
2320         intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2321                      SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2322                      OVERLAP_PIXELS_MASK, dss1);
2323 }
2324
2325 static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
2326                                   struct intel_encoder *encoder,
2327                                   const struct intel_crtc_state *crtc_state,
2328                                   const struct drm_connector_state *conn_state)
2329 {
2330         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2331         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2332         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2333         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2334         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2335         int level = intel_ddi_dp_level(intel_dp);
2336
2337         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2338                                  crtc_state->lane_count);
2339
2340         /*
2341          * 1. Enable Power Wells
2342          *
2343          * This was handled at the beginning of intel_atomic_commit_tail(),
2344          * before we called down into this function.
2345          */
2346
2347         /* 2. Enable Panel Power if PPS is required */
2348         intel_pps_on(intel_dp);
2349
2350         /*
2351          * 3. Enable the port PLL.
2352          */
2353         intel_ddi_enable_clock(encoder, crtc_state);
2354
2355         /* 4. Enable IO power */
2356         if (!intel_phy_is_tc(dev_priv, phy) ||
2357             dig_port->tc_mode != TC_PORT_TBT_ALT)
2358                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2359                                                                    dig_port->ddi_io_power_domain);
2360
2361         /*
2362          * 5. The rest of the below are substeps under the bspec's "Enable and
2363          * Train Display Port" step.  Note that steps that are specific to
2364          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2365          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2366          * us when active_mst_links==0, so any steps designated for "single
2367          * stream or multi-stream master transcoder" can just be performed
2368          * unconditionally here.
2369          */
2370
2371         /*
2372          * 5.a Configure Transcoder Clock Select to direct the Port clock to the
2373          * Transcoder.
2374          */
2375         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2376
2377         /* 5.b Not relevant to i915 for now */
2378
2379         /*
2380          * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2381          * Transport Select
2382          */
2383         intel_ddi_config_transcoder_func(encoder, crtc_state);
2384
2385         /*
2386          * 5.d Configure & enable DP_TP_CTL with link training pattern 1
2387          * selected
2388          *
2389          * This will be handled by the intel_dp_start_link_train() farther
2390          * down this function.
2391          */
2392
2393         /* 5.e Configure voltage swing and related IO settings */
2394         intel_snps_phy_ddi_vswing_sequence(encoder, level);
2395
2396         /*
2397          * 5.f Configure and enable DDI_BUF_CTL
2398          * 5.g Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
2399          *     after 1200 us.
2400          *
2401          * We only configure what the register value will be here.  Actual
2402          * enabling happens during link training farther down.
2403          */
2404         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2405
2406         if (!is_mst)
2407                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2408
2409         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2410         /*
2411          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2412          * in the FEC_CONFIGURATION register to 1 before initiating link
2413          * training
2414          */
2415         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2416
2417         /*
2418          * 5.h Follow DisplayPort specification training sequence (see notes for
2419          *     failure handling)
2420          * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2421          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2422          *     (timeout after 800 us)
2423          */
2424         intel_dp_start_link_train(intel_dp, crtc_state);
2425
2426         /* 5.j Set DP_TP_CTL link training to Normal */
2427         if (!is_trans_port_sync_mode(crtc_state))
2428                 intel_dp_stop_link_train(intel_dp, crtc_state);
2429
2430         /* 5.k Configure and enable FEC if needed */
2431         intel_ddi_enable_fec(encoder, crtc_state);
2432         intel_dsc_enable(encoder, crtc_state);
2433 }
2434
2435 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2436                                   struct intel_encoder *encoder,
2437                                   const struct intel_crtc_state *crtc_state,
2438                                   const struct drm_connector_state *conn_state)
2439 {
2440         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2441         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2442         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2443         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2444         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2445         int level = intel_ddi_dp_level(intel_dp);
2446
2447         intel_dp_set_link_params(intel_dp,
2448                                  crtc_state->port_clock,
2449                                  crtc_state->lane_count);
2450
2451         /*
2452          * 1. Enable Power Wells
2453          *
2454          * This was handled at the beginning of intel_atomic_commit_tail(),
2455          * before we called down into this function.
2456          */
2457
2458         /* 2. Enable Panel Power if PPS is required */
2459         intel_pps_on(intel_dp);
2460
2461         /*
2462          * 3. For non-TBT Type-C ports, set FIA lane count
2463          * (DFLEXDPSP.DPX4TXLATC)
2464          *
2465          * This was done before tgl_ddi_pre_enable_dp by
2466          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2467          */
2468
2469         /*
2470          * 4. Enable the port PLL.
2471          *
2472          * The PLL enabling itself was already done before this function by
2473          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
2474          * configure the PLL to port mapping here.
2475          */
2476         intel_ddi_enable_clock(encoder, crtc_state);
2477
2478         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2479         if (!intel_phy_is_tc(dev_priv, phy) ||
2480             dig_port->tc_mode != TC_PORT_TBT_ALT) {
2481                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2482                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2483                                                                    dig_port->ddi_io_power_domain);
2484         }
2485
2486         /* 6. Program DP_MODE */
2487         icl_program_mg_dp_mode(dig_port, crtc_state);
2488
2489         /*
2490          * 7. The rest of the below are substeps under the bspec's "Enable and
2491          * Train Display Port" step.  Note that steps that are specific to
2492          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2493          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2494          * us when active_mst_links==0, so any steps designated for "single
2495          * stream or multi-stream master transcoder" can just be performed
2496          * unconditionally here.
2497          */
2498
2499         /*
2500          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2501          * Transcoder.
2502          */
2503         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2504
2505         /*
2506          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2507          * Transport Select
2508          */
2509         intel_ddi_config_transcoder_func(encoder, crtc_state);
2510
2511         /*
2512          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2513          * selected
2514          *
2515          * This will be handled by the intel_dp_start_link_train() farther
2516          * down this function.
2517          */
2518
2519         /* 7.e Configure voltage swing and related IO settings */
2520         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
2521
2522         /*
2523          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2524          * the used lanes of the DDI.
2525          */
2526         intel_ddi_power_up_lanes(encoder, crtc_state);
2527
2528         /*
2529          * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2530          */
2531         intel_ddi_mso_configure(crtc_state);
2532
2533         /*
2534          * 7.g Configure and enable DDI_BUF_CTL
2535          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
2536          *     after 500 us.
2537          *
2538          * We only configure what the register value will be here.  Actual
2539          * enabling happens during link training farther down.
2540          */
2541         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2542
2543         if (!is_mst)
2544                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2545
2546         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2547         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2548         /*
2549          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2550          * in the FEC_CONFIGURATION register to 1 before initiating link
2551          * training
2552          */
2553         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2554
2555         intel_dp_check_frl_training(intel_dp);
2556         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2557
2558         /*
2559          * 7.i Follow DisplayPort specification training sequence (see notes for
2560          *     failure handling)
2561          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2562          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2563          *     (timeout after 800 us)
2564          */
2565         intel_dp_start_link_train(intel_dp, crtc_state);
2566
2567         /* 7.k Set DP_TP_CTL link training to Normal */
2568         if (!is_trans_port_sync_mode(crtc_state))
2569                 intel_dp_stop_link_train(intel_dp, crtc_state);
2570
2571         /* 7.l Configure and enable FEC if needed */
2572         intel_ddi_enable_fec(encoder, crtc_state);
2573         if (!crtc_state->bigjoiner)
2574                 intel_dsc_enable(encoder, crtc_state);
2575 }
2576
2577 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2578                                   struct intel_encoder *encoder,
2579                                   const struct intel_crtc_state *crtc_state,
2580                                   const struct drm_connector_state *conn_state)
2581 {
2582         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2583         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2584         enum port port = encoder->port;
2585         enum phy phy = intel_port_to_phy(dev_priv, port);
2586         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2587         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2588         int level = intel_ddi_dp_level(intel_dp);
2589
2590         if (DISPLAY_VER(dev_priv) < 11)
2591                 drm_WARN_ON(&dev_priv->drm,
2592                             is_mst && (port == PORT_A || port == PORT_E));
2593         else
2594                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2595
2596         intel_dp_set_link_params(intel_dp,
2597                                  crtc_state->port_clock,
2598                                  crtc_state->lane_count);
2599
2600         intel_pps_on(intel_dp);
2601
2602         intel_ddi_enable_clock(encoder, crtc_state);
2603
2604         if (!intel_phy_is_tc(dev_priv, phy) ||
2605             dig_port->tc_mode != TC_PORT_TBT_ALT) {
2606                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2607                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2608                                                                    dig_port->ddi_io_power_domain);
2609         }
2610
2611         icl_program_mg_dp_mode(dig_port, crtc_state);
2612
2613         if (DISPLAY_VER(dev_priv) >= 11)
2614                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
2615         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2616                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
2617         else
2618                 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2619
2620         intel_ddi_power_up_lanes(encoder, crtc_state);
2621
2622         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2623         if (!is_mst)
2624                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2625         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2626         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2627                                               true);
2628         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2629         intel_dp_start_link_train(intel_dp, crtc_state);
2630         if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2631             !is_trans_port_sync_mode(crtc_state))
2632                 intel_dp_stop_link_train(intel_dp, crtc_state);
2633
2634         intel_ddi_enable_fec(encoder, crtc_state);
2635
2636         if (!is_mst)
2637                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
2638
2639         if (!crtc_state->bigjoiner)
2640                 intel_dsc_enable(encoder, crtc_state);
2641 }
2642
2643 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2644                                     struct intel_encoder *encoder,
2645                                     const struct intel_crtc_state *crtc_state,
2646                                     const struct drm_connector_state *conn_state)
2647 {
2648         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2649
2650         if (IS_DG2(dev_priv))
2651                 dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2652         else if (DISPLAY_VER(dev_priv) >= 12)
2653                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2654         else
2655                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2656
2657         /* MST will call a setting of MSA after an allocating of Virtual Channel
2658          * from MST encoder pre_enable callback.
2659          */
2660         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2661                 intel_ddi_set_dp_msa(crtc_state, conn_state);
2662
2663                 intel_dp_set_m_n(crtc_state, M1_N1);
2664         }
2665 }
2666
2667 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2668                                       struct intel_encoder *encoder,
2669                                       const struct intel_crtc_state *crtc_state,
2670                                       const struct drm_connector_state *conn_state)
2671 {
2672         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2673         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2674         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2675
2676         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2677         intel_ddi_enable_clock(encoder, crtc_state);
2678
2679         drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2680         dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2681                                                            dig_port->ddi_io_power_domain);
2682
2683         icl_program_mg_dp_mode(dig_port, crtc_state);
2684
2685         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2686
2687         dig_port->set_infoframes(encoder,
2688                                  crtc_state->has_infoframe,
2689                                  crtc_state, conn_state);
2690 }
2691
2692 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2693                                  struct intel_encoder *encoder,
2694                                  const struct intel_crtc_state *crtc_state,
2695                                  const struct drm_connector_state *conn_state)
2696 {
2697         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2698         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2699         enum pipe pipe = crtc->pipe;
2700
2701         /*
2702          * When called from DP MST code:
2703          * - conn_state will be NULL
2704          * - encoder will be the main encoder (ie. mst->primary)
2705          * - the main connector associated with this port
2706          *   won't be active or linked to a crtc
2707          * - crtc_state will be the state of the first stream to
2708          *   be activated on this port, and it may not be the same
2709          *   stream that will be deactivated last, but each stream
2710          *   should have a state that is identical when it comes to
2711          *   the DP link parameteres
2712          */
2713
2714         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2715
2716         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2717
2718         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2719                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2720                                           conn_state);
2721         } else {
2722                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2723
2724                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2725                                         conn_state);
2726
2727                 /* FIXME precompute everything properly */
2728                 /* FIXME how do we turn infoframes off again? */
2729                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
2730                         dig_port->set_infoframes(encoder,
2731                                                  crtc_state->has_infoframe,
2732                                                  crtc_state, conn_state);
2733         }
2734 }
2735
2736 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2737                                   const struct intel_crtc_state *crtc_state)
2738 {
2739         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2740         enum port port = encoder->port;
2741         bool wait = false;
2742         u32 val;
2743
2744         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2745         if (val & DDI_BUF_CTL_ENABLE) {
2746                 val &= ~DDI_BUF_CTL_ENABLE;
2747                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2748                 wait = true;
2749         }
2750
2751         if (intel_crtc_has_dp_encoder(crtc_state)) {
2752                 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2753                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2754                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2755                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2756         }
2757
2758         /* Disable FEC in DP Sink */
2759         intel_ddi_disable_fec_state(encoder, crtc_state);
2760
2761         if (wait)
2762                 intel_wait_ddi_buf_idle(dev_priv, port);
2763 }
2764
2765 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2766                                       struct intel_encoder *encoder,
2767                                       const struct intel_crtc_state *old_crtc_state,
2768                                       const struct drm_connector_state *old_conn_state)
2769 {
2770         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2771         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2772         struct intel_dp *intel_dp = &dig_port->dp;
2773         bool is_mst = intel_crtc_has_type(old_crtc_state,
2774                                           INTEL_OUTPUT_DP_MST);
2775         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2776
2777         if (!is_mst)
2778                 intel_dp_set_infoframes(encoder, false,
2779                                         old_crtc_state, old_conn_state);
2780
2781         /*
2782          * Power down sink before disabling the port, otherwise we end
2783          * up getting interrupts from the sink on detecting link loss.
2784          */
2785         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2786
2787         if (DISPLAY_VER(dev_priv) >= 12) {
2788                 if (is_mst) {
2789                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2790                         u32 val;
2791
2792                         val = intel_de_read(dev_priv,
2793                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
2794                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
2795                                  TRANS_DDI_MODE_SELECT_MASK);
2796                         intel_de_write(dev_priv,
2797                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
2798                                        val);
2799                 }
2800         } else {
2801                 if (!is_mst)
2802                         intel_ddi_disable_pipe_clock(old_crtc_state);
2803         }
2804
2805         intel_disable_ddi_buf(encoder, old_crtc_state);
2806
2807         /*
2808          * From TGL spec: "If single stream or multi-stream master transcoder:
2809          * Configure Transcoder Clock select to direct no clock to the
2810          * transcoder"
2811          */
2812         if (DISPLAY_VER(dev_priv) >= 12)
2813                 intel_ddi_disable_pipe_clock(old_crtc_state);
2814
2815         intel_pps_vdd_on(intel_dp);
2816         intel_pps_off(intel_dp);
2817
2818         if (!intel_phy_is_tc(dev_priv, phy) ||
2819             dig_port->tc_mode != TC_PORT_TBT_ALT)
2820                 intel_display_power_put(dev_priv,
2821                                         dig_port->ddi_io_power_domain,
2822                                         fetch_and_zero(&dig_port->ddi_io_wakeref));
2823
2824         intel_ddi_disable_clock(encoder);
2825 }
2826
2827 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2828                                         struct intel_encoder *encoder,
2829                                         const struct intel_crtc_state *old_crtc_state,
2830                                         const struct drm_connector_state *old_conn_state)
2831 {
2832         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2833         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2834         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2835
2836         dig_port->set_infoframes(encoder, false,
2837                                  old_crtc_state, old_conn_state);
2838
2839         intel_ddi_disable_pipe_clock(old_crtc_state);
2840
2841         intel_disable_ddi_buf(encoder, old_crtc_state);
2842
2843         intel_display_power_put(dev_priv,
2844                                 dig_port->ddi_io_power_domain,
2845                                 fetch_and_zero(&dig_port->ddi_io_wakeref));
2846
2847         intel_ddi_disable_clock(encoder);
2848
2849         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2850 }
2851
2852 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2853                                    struct intel_encoder *encoder,
2854                                    const struct intel_crtc_state *old_crtc_state,
2855                                    const struct drm_connector_state *old_conn_state)
2856 {
2857         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2858         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2859         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2860         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
2861
2862         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2863                 intel_crtc_vblank_off(old_crtc_state);
2864
2865                 intel_disable_pipe(old_crtc_state);
2866
2867                 intel_vrr_disable(old_crtc_state);
2868
2869                 intel_ddi_disable_transcoder_func(old_crtc_state);
2870
2871                 intel_dsc_disable(old_crtc_state);
2872
2873                 if (DISPLAY_VER(dev_priv) >= 9)
2874                         skl_scaler_disable(old_crtc_state);
2875                 else
2876                         ilk_pfit_disable(old_crtc_state);
2877         }
2878
2879         if (old_crtc_state->bigjoiner_linked_crtc) {
2880                 struct intel_atomic_state *state =
2881                         to_intel_atomic_state(old_crtc_state->uapi.state);
2882                 struct intel_crtc *slave =
2883                         old_crtc_state->bigjoiner_linked_crtc;
2884                 const struct intel_crtc_state *old_slave_crtc_state =
2885                         intel_atomic_get_old_crtc_state(state, slave);
2886
2887                 intel_crtc_vblank_off(old_slave_crtc_state);
2888
2889                 intel_dsc_disable(old_slave_crtc_state);
2890                 skl_scaler_disable(old_slave_crtc_state);
2891         }
2892
2893         /*
2894          * When called from DP MST code:
2895          * - old_conn_state will be NULL
2896          * - encoder will be the main encoder (ie. mst->primary)
2897          * - the main connector associated with this port
2898          *   won't be active or linked to a crtc
2899          * - old_crtc_state will be the state of the last stream to
2900          *   be deactivated on this port, and it may not be the same
2901          *   stream that was activated last, but each stream
2902          *   should have a state that is identical when it comes to
2903          *   the DP link parameteres
2904          */
2905
2906         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2907                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
2908                                             old_conn_state);
2909         else
2910                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
2911                                           old_conn_state);
2912
2913         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
2914                 intel_display_power_put(dev_priv,
2915                                         intel_ddi_main_link_aux_domain(dig_port),
2916                                         fetch_and_zero(&dig_port->aux_wakeref));
2917
2918         if (is_tc_port)
2919                 intel_tc_port_put_link(dig_port);
2920 }
2921
2922 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
2923                                 struct intel_encoder *encoder,
2924                                 const struct intel_crtc_state *old_crtc_state,
2925                                 const struct drm_connector_state *old_conn_state)
2926 {
2927         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2928         u32 val;
2929
2930         /*
2931          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2932          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2933          * step 13 is the correct place for it. Step 18 is where it was
2934          * originally before the BUN.
2935          */
2936         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2937         val &= ~FDI_RX_ENABLE;
2938         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2939
2940         intel_disable_ddi_buf(encoder, old_crtc_state);
2941         intel_ddi_disable_clock(encoder);
2942
2943         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
2944         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2945         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2946         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
2947
2948         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2949         val &= ~FDI_PCDCLK;
2950         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2951
2952         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2953         val &= ~FDI_RX_PLL_ENABLE;
2954         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2955 }
2956
2957 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
2958                                             struct intel_encoder *encoder,
2959                                             const struct intel_crtc_state *crtc_state)
2960 {
2961         const struct drm_connector_state *conn_state;
2962         struct drm_connector *conn;
2963         int i;
2964
2965         if (!crtc_state->sync_mode_slaves_mask)
2966                 return;
2967
2968         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2969                 struct intel_encoder *slave_encoder =
2970                         to_intel_encoder(conn_state->best_encoder);
2971                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
2972                 const struct intel_crtc_state *slave_crtc_state;
2973
2974                 if (!slave_crtc)
2975                         continue;
2976
2977                 slave_crtc_state =
2978                         intel_atomic_get_new_crtc_state(state, slave_crtc);
2979
2980                 if (slave_crtc_state->master_transcoder !=
2981                     crtc_state->cpu_transcoder)
2982                         continue;
2983
2984                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
2985                                          slave_crtc_state);
2986         }
2987
2988         usleep_range(200, 400);
2989
2990         intel_dp_stop_link_train(enc_to_intel_dp(encoder),
2991                                  crtc_state);
2992 }
2993
2994 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
2995                                 struct intel_encoder *encoder,
2996                                 const struct intel_crtc_state *crtc_state,
2997                                 const struct drm_connector_state *conn_state)
2998 {
2999         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3000         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3001         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3002         enum port port = encoder->port;
3003
3004         if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
3005                 intel_dp_stop_link_train(intel_dp, crtc_state);
3006
3007         intel_edp_backlight_on(crtc_state, conn_state);
3008         intel_psr_enable(intel_dp, crtc_state, conn_state);
3009
3010         if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
3011                 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3012
3013         intel_edp_drrs_enable(intel_dp, crtc_state);
3014
3015         if (crtc_state->has_audio)
3016                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3017
3018         trans_port_sync_stop_link_train(state, encoder, crtc_state);
3019 }
3020
3021 static i915_reg_t
3022 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3023                                enum port port)
3024 {
3025         static const enum transcoder trans[] = {
3026                 [PORT_A] = TRANSCODER_EDP,
3027                 [PORT_B] = TRANSCODER_A,
3028                 [PORT_C] = TRANSCODER_B,
3029                 [PORT_D] = TRANSCODER_C,
3030                 [PORT_E] = TRANSCODER_A,
3031         };
3032
3033         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
3034
3035         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3036                 port = PORT_A;
3037
3038         return CHICKEN_TRANS(trans[port]);
3039 }
3040
3041 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3042                                   struct intel_encoder *encoder,
3043                                   const struct intel_crtc_state *crtc_state,
3044                                   const struct drm_connector_state *conn_state)
3045 {
3046         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3047         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3048         struct drm_connector *connector = conn_state->connector;
3049         int level = intel_ddi_hdmi_level(encoder, crtc_state);
3050         enum port port = encoder->port;
3051
3052         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3053                                                crtc_state->hdmi_high_tmds_clock_ratio,
3054                                                crtc_state->hdmi_scrambling))
3055                 drm_dbg_kms(&dev_priv->drm,
3056                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3057                             connector->base.id, connector->name);
3058
3059         if (IS_DG2(dev_priv))
3060                 intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX);
3061         else if (DISPLAY_VER(dev_priv) >= 12)
3062                 tgl_ddi_vswing_sequence(encoder, crtc_state, level);
3063         else if (DISPLAY_VER(dev_priv) == 11)
3064                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
3065         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3066                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3067         else
3068                 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state, level);
3069
3070         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
3071                 skl_ddi_set_iboost(encoder, crtc_state, level);
3072
3073         /* Display WA #1143: skl,kbl,cfl */
3074         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
3075                 /*
3076                  * For some reason these chicken bits have been
3077                  * stuffed into a transcoder register, event though
3078                  * the bits affect a specific DDI port rather than
3079                  * a specific transcoder.
3080                  */
3081                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3082                 u32 val;
3083
3084                 val = intel_de_read(dev_priv, reg);
3085
3086                 if (port == PORT_E)
3087                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3088                                 DDIE_TRAINING_OVERRIDE_VALUE;
3089                 else
3090                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3091                                 DDI_TRAINING_OVERRIDE_VALUE;
3092
3093                 intel_de_write(dev_priv, reg, val);
3094                 intel_de_posting_read(dev_priv, reg);
3095
3096                 udelay(1);
3097
3098                 if (port == PORT_E)
3099                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3100                                  DDIE_TRAINING_OVERRIDE_VALUE);
3101                 else
3102                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3103                                  DDI_TRAINING_OVERRIDE_VALUE);
3104
3105                 intel_de_write(dev_priv, reg, val);
3106         }
3107
3108         intel_ddi_power_up_lanes(encoder, crtc_state);
3109
3110         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3111          * are ignored so nothing special needs to be done besides
3112          * enabling the port.
3113          *
3114          * On ADL_P the PHY link rate and lane count must be programmed but
3115          * these are both 0 for HDMI.
3116          */
3117         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3118                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3119
3120         if (crtc_state->has_audio)
3121                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3122 }
3123
3124 static void intel_enable_ddi(struct intel_atomic_state *state,
3125                              struct intel_encoder *encoder,
3126                              const struct intel_crtc_state *crtc_state,
3127                              const struct drm_connector_state *conn_state)
3128 {
3129         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3130
3131         if (!crtc_state->bigjoiner_slave)
3132                 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3133
3134         intel_vrr_enable(encoder, crtc_state);
3135
3136         intel_enable_pipe(crtc_state);
3137
3138         intel_crtc_vblank_on(crtc_state);
3139
3140         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3141                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3142         else
3143                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3144
3145         /* Enable hdcp if it's desired */
3146         if (conn_state->content_protection ==
3147             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3148                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3149                                   crtc_state,
3150                                   (u8)conn_state->hdcp_content_type);
3151 }
3152
3153 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3154                                  struct intel_encoder *encoder,
3155                                  const struct intel_crtc_state *old_crtc_state,
3156                                  const struct drm_connector_state *old_conn_state)
3157 {
3158         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3159
3160         intel_dp->link_trained = false;
3161
3162         intel_edp_backlight_off(old_conn_state);
3163         /* Disable the decompression in DP Sink */
3164         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3165                                               false);
3166         /* Disable Ignore_MSA bit in DP Sink */
3167         intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3168                                                       false);
3169 }
3170
3171 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3172                                    struct intel_encoder *encoder,
3173                                    const struct intel_crtc_state *old_crtc_state,
3174                                    const struct drm_connector_state *old_conn_state)
3175 {
3176         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3177         struct drm_connector *connector = old_conn_state->connector;
3178
3179         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3180                                                false, false))
3181                 drm_dbg_kms(&i915->drm,
3182                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3183                             connector->base.id, connector->name);
3184 }
3185
3186 static void intel_pre_disable_ddi(struct intel_atomic_state *state,
3187                                   struct intel_encoder *encoder,
3188                                   const struct intel_crtc_state *old_crtc_state,
3189                                   const struct drm_connector_state *old_conn_state)
3190 {
3191         struct intel_dp *intel_dp;
3192
3193         if (old_crtc_state->has_audio)
3194                 intel_audio_codec_disable(encoder, old_crtc_state,
3195                                           old_conn_state);
3196
3197         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3198                 return;
3199
3200         intel_dp = enc_to_intel_dp(encoder);
3201         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3202         intel_psr_disable(intel_dp, old_crtc_state);
3203 }
3204
3205 static void intel_disable_ddi(struct intel_atomic_state *state,
3206                               struct intel_encoder *encoder,
3207                               const struct intel_crtc_state *old_crtc_state,
3208                               const struct drm_connector_state *old_conn_state)
3209 {
3210         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3211
3212         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3213                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3214                                        old_conn_state);
3215         else
3216                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3217                                      old_conn_state);
3218 }
3219
3220 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3221                                      struct intel_encoder *encoder,
3222                                      const struct intel_crtc_state *crtc_state,
3223                                      const struct drm_connector_state *conn_state)
3224 {
3225         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3226
3227         intel_ddi_set_dp_msa(crtc_state, conn_state);
3228
3229         intel_psr_update(intel_dp, crtc_state, conn_state);
3230         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3231         intel_edp_drrs_update(intel_dp, crtc_state);
3232
3233         intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
3234 }
3235
3236 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3237                            struct intel_encoder *encoder,
3238                            const struct intel_crtc_state *crtc_state,
3239                            const struct drm_connector_state *conn_state)
3240 {
3241
3242         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3243             !intel_encoder_is_mst(encoder))
3244                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3245                                          conn_state);
3246
3247         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3248 }
3249
3250 static void
3251 intel_ddi_update_prepare(struct intel_atomic_state *state,
3252                          struct intel_encoder *encoder,
3253                          struct intel_crtc *crtc)
3254 {
3255         struct intel_crtc_state *crtc_state =
3256                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3257         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3258
3259         drm_WARN_ON(state->base.dev, crtc && crtc->active);
3260
3261         intel_tc_port_get_link(enc_to_dig_port(encoder),
3262                                required_lanes);
3263         if (crtc_state && crtc_state->hw.active)
3264                 intel_update_active_dpll(state, crtc, encoder);
3265 }
3266
3267 static void
3268 intel_ddi_update_complete(struct intel_atomic_state *state,
3269                           struct intel_encoder *encoder,
3270                           struct intel_crtc *crtc)
3271 {
3272         intel_tc_port_put_link(enc_to_dig_port(encoder));
3273 }
3274
3275 static void
3276 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3277                          struct intel_encoder *encoder,
3278                          const struct intel_crtc_state *crtc_state,
3279                          const struct drm_connector_state *conn_state)
3280 {
3281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3282         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3283         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3284         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3285
3286         if (is_tc_port)
3287                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3288
3289         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
3290                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
3291                 dig_port->aux_wakeref =
3292                         intel_display_power_get(dev_priv,
3293                                                 intel_ddi_main_link_aux_domain(dig_port));
3294         }
3295
3296         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3297                 /*
3298                  * Program the lane count for static/dynamic connections on
3299                  * Type-C ports.  Skip this step for TBT.
3300                  */
3301                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3302         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3303                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3304                                                 crtc_state->lane_lat_optim_mask);
3305 }
3306
3307 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3308                                            const struct intel_crtc_state *crtc_state)
3309 {
3310         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3311         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3312         enum port port = encoder->port;
3313         u32 dp_tp_ctl, ddi_buf_ctl;
3314         bool wait = false;
3315
3316         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3317
3318         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3319                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3320                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3321                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3322                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3323                         wait = true;
3324                 }
3325
3326                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3327                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3328                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3329                 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3330
3331                 if (wait)
3332                         intel_wait_ddi_buf_idle(dev_priv, port);
3333         }
3334
3335         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3336         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3337                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3338         } else {
3339                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3340                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3341                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3342         }
3343         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3344         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3345
3346         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3347         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3348         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3349
3350         intel_wait_ddi_buf_active(dev_priv, port);
3351 }
3352
3353 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3354                                      const struct intel_crtc_state *crtc_state,
3355                                      u8 dp_train_pat)
3356 {
3357         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3359         u32 temp;
3360
3361         temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3362
3363         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3364         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3365         case DP_TRAINING_PATTERN_DISABLE:
3366                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3367                 break;
3368         case DP_TRAINING_PATTERN_1:
3369                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3370                 break;
3371         case DP_TRAINING_PATTERN_2:
3372                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3373                 break;
3374         case DP_TRAINING_PATTERN_3:
3375                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3376                 break;
3377         case DP_TRAINING_PATTERN_4:
3378                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3379                 break;
3380         }
3381
3382         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3383 }
3384
3385 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3386                                           const struct intel_crtc_state *crtc_state)
3387 {
3388         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3389         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3390         enum port port = encoder->port;
3391         u32 val;
3392
3393         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3394         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3395         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3396         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3397
3398         /*
3399          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3400          * reason we need to set idle transmission mode is to work around a HW
3401          * issue where we enable the pipe while not in idle link-training mode.
3402          * In this case there is requirement to wait for a minimum number of
3403          * idle patterns to be sent.
3404          */
3405         if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3406                 return;
3407
3408         if (intel_de_wait_for_set(dev_priv,
3409                                   dp_tp_status_reg(encoder, crtc_state),
3410                                   DP_TP_STATUS_IDLE_DONE, 1))
3411                 drm_err(&dev_priv->drm,
3412                         "Timed out waiting for DP idle patterns\n");
3413 }
3414
3415 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3416                                        enum transcoder cpu_transcoder)
3417 {
3418         if (cpu_transcoder == TRANSCODER_EDP)
3419                 return false;
3420
3421         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3422                 return false;
3423
3424         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3425                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3426 }
3427
3428 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3429                                          struct intel_crtc_state *crtc_state)
3430 {
3431         if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3432                 crtc_state->min_voltage_level = 2;
3433         else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3434                 crtc_state->min_voltage_level = 3;
3435         else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3436                 crtc_state->min_voltage_level = 1;
3437 }
3438
3439 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3440                                                      enum transcoder cpu_transcoder)
3441 {
3442         u32 master_select;
3443
3444         if (DISPLAY_VER(dev_priv) >= 11) {
3445                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3446
3447                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3448                         return INVALID_TRANSCODER;
3449
3450                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3451         } else {
3452                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3453
3454                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3455                         return INVALID_TRANSCODER;
3456
3457                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3458         }
3459
3460         if (master_select == 0)
3461                 return TRANSCODER_EDP;
3462         else
3463                 return master_select - 1;
3464 }
3465
3466 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3467 {
3468         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3469         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3470                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3471         enum transcoder cpu_transcoder;
3472
3473         crtc_state->master_transcoder =
3474                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3475
3476         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3477                 enum intel_display_power_domain power_domain;
3478                 intel_wakeref_t trans_wakeref;
3479
3480                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3481                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3482                                                                    power_domain);
3483
3484                 if (!trans_wakeref)
3485                         continue;
3486
3487                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3488                     crtc_state->cpu_transcoder)
3489                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3490
3491                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3492         }
3493
3494         drm_WARN_ON(&dev_priv->drm,
3495                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
3496                     crtc_state->sync_mode_slaves_mask);
3497 }
3498
3499 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3500                                     struct intel_crtc_state *pipe_config)
3501 {
3502         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3503         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3504         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3505         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3506         u32 temp, flags = 0;
3507
3508         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3509         if (temp & TRANS_DDI_PHSYNC)
3510                 flags |= DRM_MODE_FLAG_PHSYNC;
3511         else
3512                 flags |= DRM_MODE_FLAG_NHSYNC;
3513         if (temp & TRANS_DDI_PVSYNC)
3514                 flags |= DRM_MODE_FLAG_PVSYNC;
3515         else
3516                 flags |= DRM_MODE_FLAG_NVSYNC;
3517
3518         pipe_config->hw.adjusted_mode.flags |= flags;
3519
3520         switch (temp & TRANS_DDI_BPC_MASK) {
3521         case TRANS_DDI_BPC_6:
3522                 pipe_config->pipe_bpp = 18;
3523                 break;
3524         case TRANS_DDI_BPC_8:
3525                 pipe_config->pipe_bpp = 24;
3526                 break;
3527         case TRANS_DDI_BPC_10:
3528                 pipe_config->pipe_bpp = 30;
3529                 break;
3530         case TRANS_DDI_BPC_12:
3531                 pipe_config->pipe_bpp = 36;
3532                 break;
3533         default:
3534                 break;
3535         }
3536
3537         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3538         case TRANS_DDI_MODE_SELECT_HDMI:
3539                 pipe_config->has_hdmi_sink = true;
3540
3541                 pipe_config->infoframes.enable |=
3542                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3543
3544                 if (pipe_config->infoframes.enable)
3545                         pipe_config->has_infoframe = true;
3546
3547                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3548                         pipe_config->hdmi_scrambling = true;
3549                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3550                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3551                 fallthrough;
3552         case TRANS_DDI_MODE_SELECT_DVI:
3553                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3554                 pipe_config->lane_count = 4;
3555                 break;
3556         case TRANS_DDI_MODE_SELECT_FDI:
3557                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3558                 break;
3559         case TRANS_DDI_MODE_SELECT_DP_SST:
3560                 if (encoder->type == INTEL_OUTPUT_EDP)
3561                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3562                 else
3563                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3564                 pipe_config->lane_count =
3565                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3566                 intel_dp_get_m_n(crtc, pipe_config);
3567
3568                 if (DISPLAY_VER(dev_priv) >= 11) {
3569                         i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3570
3571                         pipe_config->fec_enable =
3572                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3573
3574                         drm_dbg_kms(&dev_priv->drm,
3575                                     "[ENCODER:%d:%s] Fec status: %u\n",
3576                                     encoder->base.base.id, encoder->base.name,
3577                                     pipe_config->fec_enable);
3578                 }
3579
3580                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3581                         pipe_config->infoframes.enable |=
3582                                 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3583                 else
3584                         pipe_config->infoframes.enable |=
3585                                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3586                 break;
3587         case TRANS_DDI_MODE_SELECT_DP_MST:
3588                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3589                 pipe_config->lane_count =
3590                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3591
3592                 if (DISPLAY_VER(dev_priv) >= 12)
3593                         pipe_config->mst_master_transcoder =
3594                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3595
3596                 intel_dp_get_m_n(crtc, pipe_config);
3597
3598                 pipe_config->infoframes.enable |=
3599                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3600                 break;
3601         default:
3602                 break;
3603         }
3604 }
3605
3606 static void intel_ddi_get_config(struct intel_encoder *encoder,
3607                                  struct intel_crtc_state *pipe_config)
3608 {
3609         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3610         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3611
3612         /* XXX: DSI transcoder paranoia */
3613         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3614                 return;
3615
3616         if (pipe_config->bigjoiner_slave) {
3617                 /* read out pipe settings from master */
3618                 enum transcoder save = pipe_config->cpu_transcoder;
3619
3620                 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
3621                 WARN_ON(pipe_config->output_types);
3622                 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
3623                 intel_ddi_read_func_ctl(encoder, pipe_config);
3624                 pipe_config->cpu_transcoder = save;
3625         } else {
3626                 intel_ddi_read_func_ctl(encoder, pipe_config);
3627         }
3628
3629         intel_ddi_mso_get_config(encoder, pipe_config);
3630
3631         pipe_config->has_audio =
3632                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3633
3634         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3635             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3636                 /*
3637                  * This is a big fat ugly hack.
3638                  *
3639                  * Some machines in UEFI boot mode provide us a VBT that has 18
3640                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3641                  * unknown we fail to light up. Yet the same BIOS boots up with
3642                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3643                  * max, not what it tells us to use.
3644                  *
3645                  * Note: This will still be broken if the eDP panel is not lit
3646                  * up by the BIOS, and thus we can't get the mode at module
3647                  * load.
3648                  */
3649                 drm_dbg_kms(&dev_priv->drm,
3650                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3651                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3652                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3653         }
3654
3655         if (!pipe_config->bigjoiner_slave)
3656                 ddi_dotclock_get(pipe_config);
3657
3658         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3659                 pipe_config->lane_lat_optim_mask =
3660                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3661
3662         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3663
3664         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3665
3666         intel_read_infoframe(encoder, pipe_config,
3667                              HDMI_INFOFRAME_TYPE_AVI,
3668                              &pipe_config->infoframes.avi);
3669         intel_read_infoframe(encoder, pipe_config,
3670                              HDMI_INFOFRAME_TYPE_SPD,
3671                              &pipe_config->infoframes.spd);
3672         intel_read_infoframe(encoder, pipe_config,
3673                              HDMI_INFOFRAME_TYPE_VENDOR,
3674                              &pipe_config->infoframes.hdmi);
3675         intel_read_infoframe(encoder, pipe_config,
3676                              HDMI_INFOFRAME_TYPE_DRM,
3677                              &pipe_config->infoframes.drm);
3678
3679         if (DISPLAY_VER(dev_priv) >= 8)
3680                 bdw_get_trans_port_sync_config(pipe_config);
3681
3682         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3683         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3684
3685         intel_psr_get_config(encoder, pipe_config);
3686 }
3687
3688 void intel_ddi_get_clock(struct intel_encoder *encoder,
3689                          struct intel_crtc_state *crtc_state,
3690                          struct intel_shared_dpll *pll)
3691 {
3692         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3693         enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3694         struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3695         bool pll_active;
3696
3697         if (drm_WARN_ON(&i915->drm, !pll))
3698                 return;
3699
3700         port_dpll->pll = pll;
3701         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3702         drm_WARN_ON(&i915->drm, !pll_active);
3703
3704         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3705
3706         crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3707                                                      &crtc_state->dpll_hw_state);
3708 }
3709
3710 static void dg2_ddi_get_config(struct intel_encoder *encoder,
3711                                 struct intel_crtc_state *crtc_state)
3712 {
3713         intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
3714         crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
3715
3716         intel_ddi_get_config(encoder, crtc_state);
3717 }
3718
3719 static void adls_ddi_get_config(struct intel_encoder *encoder,
3720                                 struct intel_crtc_state *crtc_state)
3721 {
3722         intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3723         intel_ddi_get_config(encoder, crtc_state);
3724 }
3725
3726 static void rkl_ddi_get_config(struct intel_encoder *encoder,
3727                                struct intel_crtc_state *crtc_state)
3728 {
3729         intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3730         intel_ddi_get_config(encoder, crtc_state);
3731 }
3732
3733 static void dg1_ddi_get_config(struct intel_encoder *encoder,
3734                                struct intel_crtc_state *crtc_state)
3735 {
3736         intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3737         intel_ddi_get_config(encoder, crtc_state);
3738 }
3739
3740 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3741                                      struct intel_crtc_state *crtc_state)
3742 {
3743         intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3744         intel_ddi_get_config(encoder, crtc_state);
3745 }
3746
3747 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3748                                  struct intel_crtc_state *crtc_state,
3749                                  struct intel_shared_dpll *pll)
3750 {
3751         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3752         enum icl_port_dpll_id port_dpll_id;
3753         struct icl_port_dpll *port_dpll;
3754         bool pll_active;
3755
3756         if (drm_WARN_ON(&i915->drm, !pll))
3757                 return;
3758
3759         if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
3760                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3761         else
3762                 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3763
3764         port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3765
3766         port_dpll->pll = pll;
3767         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3768         drm_WARN_ON(&i915->drm, !pll_active);
3769
3770         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3771
3772         if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
3773                 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3774         else
3775                 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3776                                                              &crtc_state->dpll_hw_state);
3777 }
3778
3779 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3780                                   struct intel_crtc_state *crtc_state)
3781 {
3782         icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3783         intel_ddi_get_config(encoder, crtc_state);
3784 }
3785
3786 static void bxt_ddi_get_config(struct intel_encoder *encoder,
3787                                struct intel_crtc_state *crtc_state)
3788 {
3789         intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3790         intel_ddi_get_config(encoder, crtc_state);
3791 }
3792
3793 static void skl_ddi_get_config(struct intel_encoder *encoder,
3794                                struct intel_crtc_state *crtc_state)
3795 {
3796         intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3797         intel_ddi_get_config(encoder, crtc_state);
3798 }
3799
3800 void hsw_ddi_get_config(struct intel_encoder *encoder,
3801                         struct intel_crtc_state *crtc_state)
3802 {
3803         intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3804         intel_ddi_get_config(encoder, crtc_state);
3805 }
3806
3807 static void intel_ddi_sync_state(struct intel_encoder *encoder,
3808                                  const struct intel_crtc_state *crtc_state)
3809 {
3810         if (intel_crtc_has_dp_encoder(crtc_state))
3811                 intel_dp_sync_state(encoder, crtc_state);
3812 }
3813
3814 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
3815                                             struct intel_crtc_state *crtc_state)
3816 {
3817         if (intel_crtc_has_dp_encoder(crtc_state))
3818                 return intel_dp_initial_fastset_check(encoder, crtc_state);
3819
3820         return true;
3821 }
3822
3823 static enum intel_output_type
3824 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3825                               struct intel_crtc_state *crtc_state,
3826                               struct drm_connector_state *conn_state)
3827 {
3828         switch (conn_state->connector->connector_type) {
3829         case DRM_MODE_CONNECTOR_HDMIA:
3830                 return INTEL_OUTPUT_HDMI;
3831         case DRM_MODE_CONNECTOR_eDP:
3832                 return INTEL_OUTPUT_EDP;
3833         case DRM_MODE_CONNECTOR_DisplayPort:
3834                 return INTEL_OUTPUT_DP;
3835         default:
3836                 MISSING_CASE(conn_state->connector->connector_type);
3837                 return INTEL_OUTPUT_UNUSED;
3838         }
3839 }
3840
3841 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3842                                     struct intel_crtc_state *pipe_config,
3843                                     struct drm_connector_state *conn_state)
3844 {
3845         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3846         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3847         enum port port = encoder->port;
3848         int ret;
3849
3850         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
3851                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3852
3853         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
3854                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3855         } else {
3856                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3857         }
3858
3859         if (ret)
3860                 return ret;
3861
3862         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3863             pipe_config->cpu_transcoder == TRANSCODER_EDP)
3864                 pipe_config->pch_pfit.force_thru =
3865                         pipe_config->pch_pfit.enabled ||
3866                         pipe_config->crc_enabled;
3867
3868         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3869                 pipe_config->lane_lat_optim_mask =
3870                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3871
3872         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3873
3874         return 0;
3875 }
3876
3877 static bool mode_equal(const struct drm_display_mode *mode1,
3878                        const struct drm_display_mode *mode2)
3879 {
3880         return drm_mode_match(mode1, mode2,
3881                               DRM_MODE_MATCH_TIMINGS |
3882                               DRM_MODE_MATCH_FLAGS |
3883                               DRM_MODE_MATCH_3D_FLAGS) &&
3884                 mode1->clock == mode2->clock; /* we want an exact match */
3885 }
3886
3887 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
3888                       const struct intel_link_m_n *m_n_2)
3889 {
3890         return m_n_1->tu == m_n_2->tu &&
3891                 m_n_1->gmch_m == m_n_2->gmch_m &&
3892                 m_n_1->gmch_n == m_n_2->gmch_n &&
3893                 m_n_1->link_m == m_n_2->link_m &&
3894                 m_n_1->link_n == m_n_2->link_n;
3895 }
3896
3897 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
3898                                        const struct intel_crtc_state *crtc_state2)
3899 {
3900         return crtc_state1->hw.active && crtc_state2->hw.active &&
3901                 crtc_state1->output_types == crtc_state2->output_types &&
3902                 crtc_state1->output_format == crtc_state2->output_format &&
3903                 crtc_state1->lane_count == crtc_state2->lane_count &&
3904                 crtc_state1->port_clock == crtc_state2->port_clock &&
3905                 mode_equal(&crtc_state1->hw.adjusted_mode,
3906                            &crtc_state2->hw.adjusted_mode) &&
3907                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
3908 }
3909
3910 static u8
3911 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
3912                                 int tile_group_id)
3913 {
3914         struct drm_connector *connector;
3915         const struct drm_connector_state *conn_state;
3916         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
3917         struct intel_atomic_state *state =
3918                 to_intel_atomic_state(ref_crtc_state->uapi.state);
3919         u8 transcoders = 0;
3920         int i;
3921
3922         /*
3923          * We don't enable port sync on BDW due to missing w/as and
3924          * due to not having adjusted the modeset sequence appropriately.
3925          */
3926         if (DISPLAY_VER(dev_priv) < 9)
3927                 return 0;
3928
3929         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
3930                 return 0;
3931
3932         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
3933                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
3934                 const struct intel_crtc_state *crtc_state;
3935
3936                 if (!crtc)
3937                         continue;
3938
3939                 if (!connector->has_tile ||
3940                     connector->tile_group->id !=
3941                     tile_group_id)
3942                         continue;
3943                 crtc_state = intel_atomic_get_new_crtc_state(state,
3944                                                              crtc);
3945                 if (!crtcs_port_sync_compatible(ref_crtc_state,
3946                                                 crtc_state))
3947                         continue;
3948                 transcoders |= BIT(crtc_state->cpu_transcoder);
3949         }
3950
3951         return transcoders;
3952 }
3953
3954 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
3955                                          struct intel_crtc_state *crtc_state,
3956                                          struct drm_connector_state *conn_state)
3957 {
3958         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3959         struct drm_connector *connector = conn_state->connector;
3960         u8 port_sync_transcoders = 0;
3961
3962         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
3963                     encoder->base.base.id, encoder->base.name,
3964                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
3965
3966         if (connector->has_tile)
3967                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
3968                                                                         connector->tile_group->id);
3969
3970         /*
3971          * EDP Transcoders cannot be ensalved
3972          * make them a master always when present
3973          */
3974         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
3975                 crtc_state->master_transcoder = TRANSCODER_EDP;
3976         else
3977                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
3978
3979         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
3980                 crtc_state->master_transcoder = INVALID_TRANSCODER;
3981                 crtc_state->sync_mode_slaves_mask =
3982                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
3983         }
3984
3985         return 0;
3986 }
3987
3988 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3989 {
3990         struct drm_i915_private *i915 = to_i915(encoder->dev);
3991         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
3992
3993         intel_dp_encoder_flush_work(encoder);
3994         intel_display_power_flush_work(i915);
3995
3996         drm_encoder_cleanup(encoder);
3997         if (dig_port)
3998                 kfree(dig_port->hdcp_port_data.streams);
3999         kfree(dig_port);
4000 }
4001
4002 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4003 {
4004         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
4005
4006         intel_dp->reset_link_params = true;
4007
4008         intel_pps_encoder_reset(intel_dp);
4009 }
4010
4011 static const struct drm_encoder_funcs intel_ddi_funcs = {
4012         .reset = intel_ddi_encoder_reset,
4013         .destroy = intel_ddi_encoder_destroy,
4014 };
4015
4016 static struct intel_connector *
4017 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4018 {
4019         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4020         struct intel_connector *connector;
4021         enum port port = dig_port->base.port;
4022
4023         connector = intel_connector_alloc();
4024         if (!connector)
4025                 return NULL;
4026
4027         dig_port->dp.output_reg = DDI_BUF_CTL(port);
4028         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4029         dig_port->dp.set_link_train = intel_ddi_set_link_train;
4030         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4031
4032         if (IS_DG2(dev_priv))
4033                 dig_port->dp.set_signal_levels = dg2_set_signal_levels;
4034         else if (DISPLAY_VER(dev_priv) >= 12)
4035                 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
4036         else if (DISPLAY_VER(dev_priv) >= 11)
4037                 dig_port->dp.set_signal_levels = icl_set_signal_levels;
4038         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4039                 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
4040         else
4041                 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
4042
4043         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4044         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4045
4046         if (!intel_dp_init_connector(dig_port, connector)) {
4047                 kfree(connector);
4048                 return NULL;
4049         }
4050
4051         return connector;
4052 }
4053
4054 static int modeset_pipe(struct drm_crtc *crtc,
4055                         struct drm_modeset_acquire_ctx *ctx)
4056 {
4057         struct drm_atomic_state *state;
4058         struct drm_crtc_state *crtc_state;
4059         int ret;
4060
4061         state = drm_atomic_state_alloc(crtc->dev);
4062         if (!state)
4063                 return -ENOMEM;
4064
4065         state->acquire_ctx = ctx;
4066
4067         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4068         if (IS_ERR(crtc_state)) {
4069                 ret = PTR_ERR(crtc_state);
4070                 goto out;
4071         }
4072
4073         crtc_state->connectors_changed = true;
4074
4075         ret = drm_atomic_commit(state);
4076 out:
4077         drm_atomic_state_put(state);
4078
4079         return ret;
4080 }
4081
4082 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4083                                  struct drm_modeset_acquire_ctx *ctx)
4084 {
4085         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4086         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4087         struct intel_connector *connector = hdmi->attached_connector;
4088         struct i2c_adapter *adapter =
4089                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4090         struct drm_connector_state *conn_state;
4091         struct intel_crtc_state *crtc_state;
4092         struct intel_crtc *crtc;
4093         u8 config;
4094         int ret;
4095
4096         if (!connector || connector->base.status != connector_status_connected)
4097                 return 0;
4098
4099         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4100                                ctx);
4101         if (ret)
4102                 return ret;
4103
4104         conn_state = connector->base.state;
4105
4106         crtc = to_intel_crtc(conn_state->crtc);
4107         if (!crtc)
4108                 return 0;
4109
4110         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4111         if (ret)
4112                 return ret;
4113
4114         crtc_state = to_intel_crtc_state(crtc->base.state);
4115
4116         drm_WARN_ON(&dev_priv->drm,
4117                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4118
4119         if (!crtc_state->hw.active)
4120                 return 0;
4121
4122         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4123             !crtc_state->hdmi_scrambling)
4124                 return 0;
4125
4126         if (conn_state->commit &&
4127             !try_wait_for_completion(&conn_state->commit->hw_done))
4128                 return 0;
4129
4130         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4131         if (ret < 0) {
4132                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4133                         ret);
4134                 return 0;
4135         }
4136
4137         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4138             crtc_state->hdmi_high_tmds_clock_ratio &&
4139             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4140             crtc_state->hdmi_scrambling)
4141                 return 0;
4142
4143         /*
4144          * HDMI 2.0 says that one should not send scrambled data
4145          * prior to configuring the sink scrambling, and that
4146          * TMDS clock/data transmission should be suspended when
4147          * changing the TMDS clock rate in the sink. So let's
4148          * just do a full modeset here, even though some sinks
4149          * would be perfectly happy if were to just reconfigure
4150          * the SCDC settings on the fly.
4151          */
4152         return modeset_pipe(&crtc->base, ctx);
4153 }
4154
4155 static enum intel_hotplug_state
4156 intel_ddi_hotplug(struct intel_encoder *encoder,
4157                   struct intel_connector *connector)
4158 {
4159         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4160         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4161         struct intel_dp *intel_dp = &dig_port->dp;
4162         enum phy phy = intel_port_to_phy(i915, encoder->port);
4163         bool is_tc = intel_phy_is_tc(i915, phy);
4164         struct drm_modeset_acquire_ctx ctx;
4165         enum intel_hotplug_state state;
4166         int ret;
4167
4168         if (intel_dp->compliance.test_active &&
4169             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4170                 intel_dp_phy_test(encoder);
4171                 /* just do the PHY test and nothing else */
4172                 return INTEL_HOTPLUG_UNCHANGED;
4173         }
4174
4175         state = intel_encoder_hotplug(encoder, connector);
4176
4177         drm_modeset_acquire_init(&ctx, 0);
4178
4179         for (;;) {
4180                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4181                         ret = intel_hdmi_reset_link(encoder, &ctx);
4182                 else
4183                         ret = intel_dp_retrain_link(encoder, &ctx);
4184
4185                 if (ret == -EDEADLK) {
4186                         drm_modeset_backoff(&ctx);
4187                         continue;
4188                 }
4189
4190                 break;
4191         }
4192
4193         drm_modeset_drop_locks(&ctx);
4194         drm_modeset_acquire_fini(&ctx);
4195         drm_WARN(encoder->base.dev, ret,
4196                  "Acquiring modeset locks failed with %i\n", ret);
4197
4198         /*
4199          * Unpowered type-c dongles can take some time to boot and be
4200          * responsible, so here giving some time to those dongles to power up
4201          * and then retrying the probe.
4202          *
4203          * On many platforms the HDMI live state signal is known to be
4204          * unreliable, so we can't use it to detect if a sink is connected or
4205          * not. Instead we detect if it's connected based on whether we can
4206          * read the EDID or not. That in turn has a problem during disconnect,
4207          * since the HPD interrupt may be raised before the DDC lines get
4208          * disconnected (due to how the required length of DDC vs. HPD
4209          * connector pins are specified) and so we'll still be able to get a
4210          * valid EDID. To solve this schedule another detection cycle if this
4211          * time around we didn't detect any change in the sink's connection
4212          * status.
4213          *
4214          * Type-c connectors which get their HPD signal deasserted then
4215          * reasserted, without unplugging/replugging the sink from the
4216          * connector, introduce a delay until the AUX channel communication
4217          * becomes functional. Retry the detection for 5 seconds on type-c
4218          * connectors to account for this delay.
4219          */
4220         if (state == INTEL_HOTPLUG_UNCHANGED &&
4221             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4222             !dig_port->dp.is_mst)
4223                 state = INTEL_HOTPLUG_RETRY;
4224
4225         return state;
4226 }
4227
4228 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4229 {
4230         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4231         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4232
4233         return intel_de_read(dev_priv, SDEISR) & bit;
4234 }
4235
4236 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4237 {
4238         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4239         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4240
4241         return intel_de_read(dev_priv, DEISR) & bit;
4242 }
4243
4244 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4245 {
4246         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4247         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4248
4249         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4250 }
4251
4252 static struct intel_connector *
4253 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4254 {
4255         struct intel_connector *connector;
4256         enum port port = dig_port->base.port;
4257
4258         connector = intel_connector_alloc();
4259         if (!connector)
4260                 return NULL;
4261
4262         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4263         intel_hdmi_init_connector(dig_port, connector);
4264
4265         return connector;
4266 }
4267
4268 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4269 {
4270         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4271
4272         if (dig_port->base.port != PORT_A)
4273                 return false;
4274
4275         if (dig_port->saved_port_bits & DDI_A_4_LANES)
4276                 return false;
4277
4278         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4279          *                     supported configuration
4280          */
4281         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4282                 return true;
4283
4284         return false;
4285 }
4286
4287 static int
4288 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4289 {
4290         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4291         enum port port = dig_port->base.port;
4292         int max_lanes = 4;
4293
4294         if (DISPLAY_VER(dev_priv) >= 11)
4295                 return max_lanes;
4296
4297         if (port == PORT_A || port == PORT_E) {
4298                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4299                         max_lanes = port == PORT_A ? 4 : 0;
4300                 else
4301                         /* Both A and E share 2 lanes */
4302                         max_lanes = 2;
4303         }
4304
4305         /*
4306          * Some BIOS might fail to set this bit on port A if eDP
4307          * wasn't lit up at boot.  Force this bit set when needed
4308          * so we use the proper lane count for our calculations.
4309          */
4310         if (intel_ddi_a_force_4_lanes(dig_port)) {
4311                 drm_dbg_kms(&dev_priv->drm,
4312                             "Forcing DDI_A_4_LANES for port A\n");
4313                 dig_port->saved_port_bits |= DDI_A_4_LANES;
4314                 max_lanes = 4;
4315         }
4316
4317         return max_lanes;
4318 }
4319
4320 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4321 {
4322         return i915->hti_state & HDPORT_ENABLED &&
4323                i915->hti_state & HDPORT_DDI_USED(phy);
4324 }
4325
4326 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4327                                   enum port port)
4328 {
4329         if (port >= PORT_D_XELPD)
4330                 return HPD_PORT_D + port - PORT_D_XELPD;
4331         else if (port >= PORT_TC1)
4332                 return HPD_PORT_TC1 + port - PORT_TC1;
4333         else
4334                 return HPD_PORT_A + port - PORT_A;
4335 }
4336
4337 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4338                                 enum port port)
4339 {
4340         if (port >= PORT_TC1)
4341                 return HPD_PORT_C + port - PORT_TC1;
4342         else
4343                 return HPD_PORT_A + port - PORT_A;
4344 }
4345
4346 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4347                                 enum port port)
4348 {
4349         if (port >= PORT_TC1)
4350                 return HPD_PORT_TC1 + port - PORT_TC1;
4351         else
4352                 return HPD_PORT_A + port - PORT_A;
4353 }
4354
4355 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4356                                 enum port port)
4357 {
4358         if (HAS_PCH_TGP(dev_priv))
4359                 return tgl_hpd_pin(dev_priv, port);
4360
4361         if (port >= PORT_TC1)
4362                 return HPD_PORT_C + port - PORT_TC1;
4363         else
4364                 return HPD_PORT_A + port - PORT_A;
4365 }
4366
4367 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4368                                 enum port port)
4369 {
4370         if (port >= PORT_C)
4371                 return HPD_PORT_TC1 + port - PORT_C;
4372         else
4373                 return HPD_PORT_A + port - PORT_A;
4374 }
4375
4376 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4377                                 enum port port)
4378 {
4379         if (port == PORT_D)
4380                 return HPD_PORT_A;
4381
4382         if (HAS_PCH_MCC(dev_priv))
4383                 return icl_hpd_pin(dev_priv, port);
4384
4385         return HPD_PORT_A + port - PORT_A;
4386 }
4387
4388 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4389 {
4390         if (HAS_PCH_TGP(dev_priv))
4391                 return icl_hpd_pin(dev_priv, port);
4392
4393         return HPD_PORT_A + port - PORT_A;
4394 }
4395
4396 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4397 {
4398         if (DISPLAY_VER(i915) >= 12)
4399                 return port >= PORT_TC1;
4400         else if (DISPLAY_VER(i915) >= 11)
4401                 return port >= PORT_C;
4402         else
4403                 return false;
4404 }
4405
4406 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4407 {
4408         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4409         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4410         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4411         enum phy phy = intel_port_to_phy(i915, encoder->port);
4412
4413         intel_dp_encoder_suspend(encoder);
4414
4415         if (!intel_phy_is_tc(i915, phy))
4416                 return;
4417
4418         intel_tc_port_disconnect_phy(dig_port);
4419 }
4420
4421 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4422 {
4423         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4424         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4425         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4426         enum phy phy = intel_port_to_phy(i915, encoder->port);
4427
4428         intel_dp_encoder_shutdown(encoder);
4429
4430         if (!intel_phy_is_tc(i915, phy))
4431                 return;
4432
4433         intel_tc_port_disconnect_phy(dig_port);
4434 }
4435
4436 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4437 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4438
4439 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4440 {
4441         struct intel_digital_port *dig_port;
4442         struct intel_encoder *encoder;
4443         const struct intel_bios_encoder_data *devdata;
4444         bool init_hdmi, init_dp;
4445         enum phy phy = intel_port_to_phy(dev_priv, port);
4446
4447         /*
4448          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4449          * have taken over some of the PHYs and made them unavailable to the
4450          * driver.  In that case we should skip initializing the corresponding
4451          * outputs.
4452          */
4453         if (hti_uses_phy(dev_priv, phy)) {
4454                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4455                             port_name(port), phy_name(phy));
4456                 return;
4457         }
4458
4459         devdata = intel_bios_encoder_data_lookup(dev_priv, port);
4460         if (!devdata) {
4461                 drm_dbg_kms(&dev_priv->drm,
4462                             "VBT says port %c is not present\n",
4463                             port_name(port));
4464                 return;
4465         }
4466
4467         init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4468                 intel_bios_encoder_supports_hdmi(devdata);
4469         init_dp = intel_bios_encoder_supports_dp(devdata);
4470
4471         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4472                 /*
4473                  * Lspcon device needs to be driven with DP connector
4474                  * with special detection sequence. So make sure DP
4475                  * is initialized before lspcon.
4476                  */
4477                 init_dp = true;
4478                 init_hdmi = false;
4479                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4480                             port_name(port));
4481         }
4482
4483         if (!init_dp && !init_hdmi) {
4484                 drm_dbg_kms(&dev_priv->drm,
4485                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4486                             port_name(port));
4487                 return;
4488         }
4489
4490         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4491         if (!dig_port)
4492                 return;
4493
4494         encoder = &dig_port->base;
4495         encoder->devdata = devdata;
4496
4497         if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4498                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4499                                  DRM_MODE_ENCODER_TMDS,
4500                                  "DDI %c/PHY %c",
4501                                  port_name(port - PORT_D_XELPD + PORT_D),
4502                                  phy_name(phy));
4503         } else if (DISPLAY_VER(dev_priv) >= 12) {
4504                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4505
4506                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4507                                  DRM_MODE_ENCODER_TMDS,
4508                                  "DDI %s%c/PHY %s%c",
4509                                  port >= PORT_TC1 ? "TC" : "",
4510                                  port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4511                                  tc_port != TC_PORT_NONE ? "TC" : "",
4512                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4513         } else if (DISPLAY_VER(dev_priv) >= 11) {
4514                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4515
4516                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4517                                  DRM_MODE_ENCODER_TMDS,
4518                                  "DDI %c%s/PHY %s%c",
4519                                  port_name(port),
4520                                  port >= PORT_C ? " (TC)" : "",
4521                                  tc_port != TC_PORT_NONE ? "TC" : "",
4522                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4523         } else {
4524                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4525                                  DRM_MODE_ENCODER_TMDS,
4526                                  "DDI %c/PHY %c", port_name(port),  phy_name(phy));
4527         }
4528
4529         mutex_init(&dig_port->hdcp_mutex);
4530         dig_port->num_hdcp_streams = 0;
4531
4532         encoder->hotplug = intel_ddi_hotplug;
4533         encoder->compute_output_type = intel_ddi_compute_output_type;
4534         encoder->compute_config = intel_ddi_compute_config;
4535         encoder->compute_config_late = intel_ddi_compute_config_late;
4536         encoder->enable = intel_enable_ddi;
4537         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4538         encoder->pre_enable = intel_ddi_pre_enable;
4539         encoder->pre_disable = intel_pre_disable_ddi;
4540         encoder->disable = intel_disable_ddi;
4541         encoder->post_disable = intel_ddi_post_disable;
4542         encoder->update_pipe = intel_ddi_update_pipe;
4543         encoder->get_hw_state = intel_ddi_get_hw_state;
4544         encoder->sync_state = intel_ddi_sync_state;
4545         encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4546         encoder->suspend = intel_ddi_encoder_suspend;
4547         encoder->shutdown = intel_ddi_encoder_shutdown;
4548         encoder->get_power_domains = intel_ddi_get_power_domains;
4549
4550         encoder->type = INTEL_OUTPUT_DDI;
4551         encoder->power_domain = intel_port_to_power_domain(port);
4552         encoder->port = port;
4553         encoder->cloneable = 0;
4554         encoder->pipe_mask = ~0;
4555
4556         if (IS_DG2(dev_priv)) {
4557                 encoder->enable_clock = intel_mpllb_enable;
4558                 encoder->disable_clock = intel_mpllb_disable;
4559                 encoder->get_config = dg2_ddi_get_config;
4560         } else if (IS_ALDERLAKE_S(dev_priv)) {
4561                 encoder->enable_clock = adls_ddi_enable_clock;
4562                 encoder->disable_clock = adls_ddi_disable_clock;
4563                 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4564                 encoder->get_config = adls_ddi_get_config;
4565         } else if (IS_ROCKETLAKE(dev_priv)) {
4566                 encoder->enable_clock = rkl_ddi_enable_clock;
4567                 encoder->disable_clock = rkl_ddi_disable_clock;
4568                 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4569                 encoder->get_config = rkl_ddi_get_config;
4570         } else if (IS_DG1(dev_priv)) {
4571                 encoder->enable_clock = dg1_ddi_enable_clock;
4572                 encoder->disable_clock = dg1_ddi_disable_clock;
4573                 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4574                 encoder->get_config = dg1_ddi_get_config;
4575         } else if (IS_JSL_EHL(dev_priv)) {
4576                 if (intel_ddi_is_tc(dev_priv, port)) {
4577                         encoder->enable_clock = jsl_ddi_tc_enable_clock;
4578                         encoder->disable_clock = jsl_ddi_tc_disable_clock;
4579                         encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
4580                         encoder->get_config = icl_ddi_combo_get_config;
4581                 } else {
4582                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4583                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4584                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4585                         encoder->get_config = icl_ddi_combo_get_config;
4586                 }
4587         } else if (DISPLAY_VER(dev_priv) >= 11) {
4588                 if (intel_ddi_is_tc(dev_priv, port)) {
4589                         encoder->enable_clock = icl_ddi_tc_enable_clock;
4590                         encoder->disable_clock = icl_ddi_tc_disable_clock;
4591                         encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
4592                         encoder->get_config = icl_ddi_tc_get_config;
4593                 } else {
4594                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4595                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4596                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4597                         encoder->get_config = icl_ddi_combo_get_config;
4598                 }
4599         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4600                 /* BXT/GLK have fixed PLL->port mapping */
4601                 encoder->get_config = bxt_ddi_get_config;
4602         } else if (DISPLAY_VER(dev_priv) == 9) {
4603                 encoder->enable_clock = skl_ddi_enable_clock;
4604                 encoder->disable_clock = skl_ddi_disable_clock;
4605                 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4606                 encoder->get_config = skl_ddi_get_config;
4607         } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4608                 encoder->enable_clock = hsw_ddi_enable_clock;
4609                 encoder->disable_clock = hsw_ddi_disable_clock;
4610                 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4611                 encoder->get_config = hsw_ddi_get_config;
4612         }
4613
4614         intel_ddi_buf_trans_init(encoder);
4615
4616         if (DISPLAY_VER(dev_priv) >= 13)
4617                 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4618         else if (IS_DG1(dev_priv))
4619                 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4620         else if (IS_ROCKETLAKE(dev_priv))
4621                 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4622         else if (DISPLAY_VER(dev_priv) >= 12)
4623                 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4624         else if (IS_JSL_EHL(dev_priv))
4625                 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4626         else if (DISPLAY_VER(dev_priv) == 11)
4627                 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4628         else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4629                 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4630         else
4631                 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4632
4633         if (DISPLAY_VER(dev_priv) >= 11)
4634                 dig_port->saved_port_bits =
4635                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4636                         & DDI_BUF_PORT_REVERSAL;
4637         else
4638                 dig_port->saved_port_bits =
4639                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4640                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4641
4642         if (intel_bios_is_lane_reversal_needed(dev_priv, port))
4643                 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4644
4645         dig_port->dp.output_reg = INVALID_MMIO_REG;
4646         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4647         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4648
4649         if (intel_phy_is_tc(dev_priv, phy)) {
4650                 bool is_legacy =
4651                         !intel_bios_encoder_supports_typec_usb(devdata) &&
4652                         !intel_bios_encoder_supports_tbt(devdata);
4653
4654                 intel_tc_port_init(dig_port, is_legacy);
4655
4656                 encoder->update_prepare = intel_ddi_update_prepare;
4657                 encoder->update_complete = intel_ddi_update_complete;
4658         }
4659
4660         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4661         dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4662                                               port - PORT_A;
4663
4664         if (init_dp) {
4665                 if (!intel_ddi_init_dp_connector(dig_port))
4666                         goto err;
4667
4668                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
4669
4670                 if (dig_port->dp.mso_link_count)
4671                         encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4672         }
4673
4674         /* In theory we don't need the encoder->type check, but leave it just in
4675          * case we have some really bad VBTs... */
4676         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4677                 if (!intel_ddi_init_hdmi_connector(dig_port))
4678                         goto err;
4679         }
4680
4681         if (DISPLAY_VER(dev_priv) >= 11) {
4682                 if (intel_phy_is_tc(dev_priv, phy))
4683                         dig_port->connected = intel_tc_port_connected;
4684                 else
4685                         dig_port->connected = lpt_digital_port_connected;
4686         } else if (DISPLAY_VER(dev_priv) >= 8) {
4687                 if (port == PORT_A || IS_GEMINILAKE(dev_priv) ||
4688                     IS_BROXTON(dev_priv))
4689                         dig_port->connected = bdw_digital_port_connected;
4690                 else
4691                         dig_port->connected = lpt_digital_port_connected;
4692         } else {
4693                 if (port == PORT_A)
4694                         dig_port->connected = hsw_digital_port_connected;
4695                 else
4696                         dig_port->connected = lpt_digital_port_connected;
4697         }
4698
4699         intel_infoframe_init(dig_port);
4700
4701         return;
4702
4703 err:
4704         drm_encoder_cleanup(&encoder->base);
4705         kfree(dig_port);
4706 }