drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_13_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v13_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_13_0_2_offset.h"
  43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_13_0_2_offset.h"
  45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
  47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
  60
  61 #define SMU13_VOLTAGE_SCALE 4
  62
  63 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  64
  65 #define LINK_WIDTH_MAX                          6
  66 #define LINK_SPEED_MAX                          3
  67
  68 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  69 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  70 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  71 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  72 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  73 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  74
  75 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  76 static const int link_speed[] = {25, 50, 80, 160};
  77
  78 int smu_v13_0_init_microcode(struct smu_context *smu)
  79 {
  80         struct amdgpu_device *adev = smu->adev;
  81         const char *chip_name;
  82         char fw_name[30];
  83         int err = 0;
  84         const struct smc_firmware_header_v1_0 *hdr;
  85         const struct common_firmware_header *header;
  86         struct amdgpu_firmware_info *ucode = NULL;
  87
  88         /* doesn't need to load smu firmware in IOV mode */
  89         if (amdgpu_sriov_vf(adev))
  90                 return 0;
  91
  92         switch (adev->asic_type) {
  93         case CHIP_ALDEBARAN:
  94                 chip_name = "aldebaran";
  95                 break;
  96         default:
  97                 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
  98                 return -EINVAL;
  99         }
 100
 101         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 102
 103         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 104         if (err)
 105                 goto out;
 106         err = amdgpu_ucode_validate(adev->pm.fw);
 107         if (err)
 108                 goto out;
 109
 110         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 111         amdgpu_ucode_print_smc_hdr(&hdr->header);
 112         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 113
 114         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 115                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 116                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 117                 ucode->fw = adev->pm.fw;
 118                 header = (const struct common_firmware_header *)ucode->fw->data;
 119                 adev->firmware.fw_size +=
 120                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 121         }
 122
 123 out:
 124         if (err) {
 125                 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
 126                           fw_name);
 127                 release_firmware(adev->pm.fw);
 128                 adev->pm.fw = NULL;
 129         }
 130         return err;
 131 }
 132
 133 void smu_v13_0_fini_microcode(struct smu_context *smu)
 134 {
 135         struct amdgpu_device *adev = smu->adev;
 136
 137         release_firmware(adev->pm.fw);
 138         adev->pm.fw = NULL;
 139         adev->pm.fw_version = 0;
 140 }
 141
 142 int smu_v13_0_load_microcode(struct smu_context *smu)
 143 {
 144 #if 0
 145         struct amdgpu_device *adev = smu->adev;
 146         const uint32_t *src;
 147         const struct smc_firmware_header_v1_0 *hdr;
 148         uint32_t addr_start = MP1_SRAM;
 149         uint32_t i;
 150         uint32_t smc_fw_size;
 151         uint32_t mp1_fw_flags;
 152
 153         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 154         src = (const uint32_t *)(adev->pm.fw->data +
 155                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 156         smc_fw_size = hdr->header.ucode_size_bytes;
 157
 158         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 159                 WREG32_PCIE(addr_start, src[i]);
 160                 addr_start += 4;
 161         }
 162
 163         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 164                     1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 165         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 166                     1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 167
 168         for (i = 0; i < adev->usec_timeout; i++) {
 169                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 170                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 171                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 172                     MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 173                         break;
 174                 udelay(1);
 175         }
 176
 177         if (i == adev->usec_timeout)
 178                 return -ETIME;
 179 #endif
 180         return 0;
 181 }
 182
 183 int smu_v13_0_check_fw_status(struct smu_context *smu)
 184 {
 185         struct amdgpu_device *adev = smu->adev;
 186         uint32_t mp1_fw_flags;
 187
 188         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 189                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 190
 191         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 192             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 193                 return 0;
 194
 195         return -EIO;
 196 }
 197
 198 int smu_v13_0_check_fw_version(struct smu_context *smu)
 199 {
 200         uint32_t if_version = 0xff, smu_version = 0xff;
 201         uint16_t smu_major;
 202         uint8_t smu_minor, smu_debug;
 203         int ret = 0;
 204
 205         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 206         if (ret)
 207                 return ret;
 208
 209         smu_major = (smu_version >> 16) & 0xffff;
 210         smu_minor = (smu_version >> 8) & 0xff;
 211         smu_debug = (smu_version >> 0) & 0xff;
 212
 213         switch (smu->adev->asic_type) {
 214         case CHIP_ALDEBARAN:
 215                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
 216                 break;
 217         case CHIP_YELLOW_CARP:
 218                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
 219                 break;
 220         default:
 221                 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 222                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
 223                 break;
 224         }
 225
 226         dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
 227                          smu_version, smu_major, smu_minor, smu_debug);
 228
 229         /*
 230          * 1. if_version mismatch is not critical as our fw is designed
 231          * to be backward compatible.
 232          * 2. New fw usually brings some optimizations. But that's visible
 233          * only on the paired driver.
 234          * Considering above, we just leave user a warning message instead
 235          * of halt driver loading.
 236          */
 237         if (if_version != smu->smc_driver_if_version) {
 238                 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 239                          "smu fw version = 0x%08x (%d.%d.%d)\n",
 240                          smu->smc_driver_if_version, if_version,
 241                          smu_version, smu_major, smu_minor, smu_debug);
 242                 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
 243         }
 244
 245         return ret;
 246 }
 247
 248 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 249                                       uint32_t *size, uint32_t pptable_id)
 250 {
 251         struct amdgpu_device *adev = smu->adev;
 252         const struct smc_firmware_header_v2_1 *v2_1;
 253         struct smc_soft_pptable_entry *entries;
 254         uint32_t pptable_count = 0;
 255         int i = 0;
 256
 257         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 258         entries = (struct smc_soft_pptable_entry *)
 259                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 260         pptable_count = le32_to_cpu(v2_1->pptable_count);
 261         for (i = 0; i < pptable_count; i++) {
 262                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 263                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 264                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 265                         break;
 266                 }
 267         }
 268
 269         if (i == pptable_count)
 270                 return -EINVAL;
 271
 272         return 0;
 273 }
 274
 275 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
 276 {
 277         struct amdgpu_device *adev = smu->adev;
 278         uint16_t atom_table_size;
 279         uint8_t frev, crev;
 280         int ret, index;
 281
 282         dev_info(adev->dev, "use vbios provided pptable\n");
 283         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 284                                             powerplayinfo);
 285
 286         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 287                                              (uint8_t **)table);
 288         if (ret)
 289                 return ret;
 290
 291         if (size)
 292                 *size = atom_table_size;
 293
 294         return 0;
 295 }
 296
 297 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
 298                                                uint32_t pptable_id)
 299 {
 300         const struct smc_firmware_header_v1_0 *hdr;
 301         struct amdgpu_device *adev = smu->adev;
 302         uint16_t version_major, version_minor;
 303         int ret;
 304
 305         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 306         if (!hdr)
 307                 return -EINVAL;
 308
 309         dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
 310
 311         version_major = le16_to_cpu(hdr->header.header_version_major);
 312         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 313         if (version_major != 2) {
 314                 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
 315                         version_major, version_minor);
 316                 return -EINVAL;
 317         }
 318
 319         switch (version_minor) {
 320         case 1:
 321                 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
 322                 break;
 323         default:
 324                 ret = -EINVAL;
 325                 break;
 326         }
 327
 328         return ret;
 329 }
 330
 331 int smu_v13_0_setup_pptable(struct smu_context *smu)
 332 {
 333         struct amdgpu_device *adev = smu->adev;
 334         uint32_t size = 0, pptable_id = 0;
 335         void *table;
 336         int ret = 0;
 337
 338         /* override pptable_id from driver parameter */
 339         if (amdgpu_smu_pptable_id >= 0) {
 340                 pptable_id = amdgpu_smu_pptable_id;
 341                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 342         } else {
 343                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 344         }
 345
 346         /* force using vbios pptable in sriov mode */
 347         if (amdgpu_sriov_vf(adev) || !pptable_id)
 348                 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
 349         else
 350                 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 351
 352         if (ret)
 353                 return ret;
 354
 355         if (!smu->smu_table.power_play_table)
 356                 smu->smu_table.power_play_table = table;
 357         if (!smu->smu_table.power_play_table_size)
 358                 smu->smu_table.power_play_table_size = size;
 359
 360         return 0;
 361 }
 362
 363 int smu_v13_0_init_smc_tables(struct smu_context *smu)
 364 {
 365         struct smu_table_context *smu_table = &smu->smu_table;
 366         struct smu_table *tables = smu_table->tables;
 367         int ret = 0;
 368
 369         smu_table->driver_pptable =
 370                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 371         if (!smu_table->driver_pptable) {
 372                 ret = -ENOMEM;
 373                 goto err0_out;
 374         }
 375
 376         smu_table->max_sustainable_clocks =
 377                 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
 378         if (!smu_table->max_sustainable_clocks) {
 379                 ret = -ENOMEM;
 380                 goto err1_out;
 381         }
 382
 383         /* Aldebaran does not support OVERDRIVE */
 384         if (tables[SMU_TABLE_OVERDRIVE].size) {
 385                 smu_table->overdrive_table =
 386                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 387                 if (!smu_table->overdrive_table) {
 388                         ret = -ENOMEM;
 389                         goto err2_out;
 390                 }
 391
 392                 smu_table->boot_overdrive_table =
 393                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 394                 if (!smu_table->boot_overdrive_table) {
 395                         ret = -ENOMEM;
 396                         goto err3_out;
 397                 }
 398         }
 399
 400         return 0;
 401
 402 err3_out:
 403         kfree(smu_table->overdrive_table);
 404 err2_out:
 405         kfree(smu_table->max_sustainable_clocks);
 406 err1_out:
 407         kfree(smu_table->driver_pptable);
 408 err0_out:
 409         return ret;
 410 }
 411
 412 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
 413 {
 414         struct smu_table_context *smu_table = &smu->smu_table;
 415         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 416
 417         kfree(smu_table->gpu_metrics_table);
 418         kfree(smu_table->boot_overdrive_table);
 419         kfree(smu_table->overdrive_table);
 420         kfree(smu_table->max_sustainable_clocks);
 421         kfree(smu_table->driver_pptable);
 422         smu_table->gpu_metrics_table = NULL;
 423         smu_table->boot_overdrive_table = NULL;
 424         smu_table->overdrive_table = NULL;
 425         smu_table->max_sustainable_clocks = NULL;
 426         smu_table->driver_pptable = NULL;
 427         kfree(smu_table->hardcode_pptable);
 428         smu_table->hardcode_pptable = NULL;
 429
 430         kfree(smu_table->metrics_table);
 431         kfree(smu_table->watermarks_table);
 432         smu_table->metrics_table = NULL;
 433         smu_table->watermarks_table = NULL;
 434         smu_table->metrics_time = 0;
 435
 436         kfree(smu_dpm->dpm_context);
 437         kfree(smu_dpm->golden_dpm_context);
 438         kfree(smu_dpm->dpm_current_power_state);
 439         kfree(smu_dpm->dpm_request_power_state);
 440         smu_dpm->dpm_context = NULL;
 441         smu_dpm->golden_dpm_context = NULL;
 442         smu_dpm->dpm_context_size = 0;
 443         smu_dpm->dpm_current_power_state = NULL;
 444         smu_dpm->dpm_request_power_state = NULL;
 445
 446         return 0;
 447 }
 448
 449 int smu_v13_0_init_power(struct smu_context *smu)
 450 {
 451         struct smu_power_context *smu_power = &smu->smu_power;
 452
 453         if (smu_power->power_context || smu_power->power_context_size != 0)
 454                 return -EINVAL;
 455
 456         smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 457                                            GFP_KERNEL);
 458         if (!smu_power->power_context)
 459                 return -ENOMEM;
 460         smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
 461
 462         return 0;
 463 }
 464
 465 int smu_v13_0_fini_power(struct smu_context *smu)
 466 {
 467         struct smu_power_context *smu_power = &smu->smu_power;
 468
 469         if (!smu_power->power_context || smu_power->power_context_size == 0)
 470                 return -EINVAL;
 471
 472         kfree(smu_power->power_context);
 473         smu_power->power_context = NULL;
 474         smu_power->power_context_size = 0;
 475
 476         return 0;
 477 }
 478
 479 static int smu_v13_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 480                                             uint8_t clk_id,
 481                                             uint8_t syspll_id,
 482                                             uint32_t *clk_freq)
 483 {
 484         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 485         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 486         int ret, index;
 487
 488         input.clk_id = clk_id;
 489         input.syspll_id = syspll_id;
 490         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 491         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 492                                             getsmuclockinfo);
 493
 494         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 495                                         (uint32_t *)&input);
 496         if (ret)
 497                 return -EINVAL;
 498
 499         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 500         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 501
 502         return 0;
 503 }
 504
 505 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
 506 {
 507         int ret, index;
 508         uint16_t size;
 509         uint8_t frev, crev;
 510         struct atom_common_table_header *header;
 511         struct atom_firmware_info_v3_4 *v_3_4;
 512         struct atom_firmware_info_v3_3 *v_3_3;
 513         struct atom_firmware_info_v3_1 *v_3_1;
 514
 515         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 516                                             firmwareinfo);
 517
 518         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 519                                              (uint8_t **)&header);
 520         if (ret)
 521                 return ret;
 522
 523         if (header->format_revision != 3) {
 524                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
 525                 return -EINVAL;
 526         }
 527
 528         switch (header->content_revision) {
 529         case 0:
 530         case 1:
 531         case 2:
 532                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 533                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 534                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 535                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 536                 smu->smu_table.boot_values.socclk = 0;
 537                 smu->smu_table.boot_values.dcefclk = 0;
 538                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 539                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 540                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 541                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 542                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 543                 smu->smu_table.boot_values.pp_table_id = 0;
 544                 break;
 545         case 3:
 546                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 547                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 548                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 549                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 550                 smu->smu_table.boot_values.socclk = 0;
 551                 smu->smu_table.boot_values.dcefclk = 0;
 552                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 553                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 554                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 555                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 556                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 557                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 558                 break;
 559         case 4:
 560         default:
 561                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 562                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 563                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 564                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 565                 smu->smu_table.boot_values.socclk = 0;
 566                 smu->smu_table.boot_values.dcefclk = 0;
 567                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 568                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 569                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 570                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 571                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 572                 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
 573                 break;
 574         }
 575
 576         smu->smu_table.boot_values.format_revision = header->format_revision;
 577         smu->smu_table.boot_values.content_revision = header->content_revision;
 578
 579         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 580                                          (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 581                                          (uint8_t)0,
 582                                          &smu->smu_table.boot_values.socclk);
 583
 584         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 585                                          (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 586                                          (uint8_t)0,
 587                                          &smu->smu_table.boot_values.dcefclk);
 588
 589         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 590                                          (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 591                                          (uint8_t)0,
 592                                          &smu->smu_table.boot_values.eclk);
 593
 594         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 595                                          (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 596                                          (uint8_t)0,
 597                                          &smu->smu_table.boot_values.vclk);
 598
 599         smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 600                                          (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 601                                          (uint8_t)0,
 602                                          &smu->smu_table.boot_values.dclk);
 603
 604         if ((smu->smu_table.boot_values.format_revision == 3) &&
 605             (smu->smu_table.boot_values.content_revision >= 2))
 606                 smu_v13_0_atom_get_smu_clockinfo(smu->adev,
 607                                                  (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 608                                                  (uint8_t)SMU11_SYSPLL1_2_ID,
 609                                                  &smu->smu_table.boot_values.fclk);
 610
 611         return 0;
 612 }
 613
 614
 615 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
 616 {
 617         struct smu_table_context *smu_table = &smu->smu_table;
 618         struct smu_table *memory_pool = &smu_table->memory_pool;
 619         int ret = 0;
 620         uint64_t address;
 621         uint32_t address_low, address_high;
 622
 623         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 624                 return ret;
 625
 626         address = memory_pool->mc_address;
 627         address_high = (uint32_t)upper_32_bits(address);
 628         address_low  = (uint32_t)lower_32_bits(address);
 629
 630         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 631                                               address_high, NULL);
 632         if (ret)
 633                 return ret;
 634         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 635                                               address_low, NULL);
 636         if (ret)
 637                 return ret;
 638         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 639                                               (uint32_t)memory_pool->size, NULL);
 640         if (ret)
 641                 return ret;
 642
 643         return ret;
 644 }
 645
 646 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 647 {
 648         int ret;
 649
 650         ret = smu_cmn_send_smc_msg_with_param(smu,
 651                                               SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 652         if (ret)
 653                 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
 654
 655         return ret;
 656 }
 657
 658 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
 659 {
 660         struct smu_table *driver_table = &smu->smu_table.driver_table;
 661         int ret = 0;
 662
 663         if (driver_table->mc_address) {
 664                 ret = smu_cmn_send_smc_msg_with_param(smu,
 665                                                       SMU_MSG_SetDriverDramAddrHigh,
 666                                                       upper_32_bits(driver_table->mc_address),
 667                                                       NULL);
 668                 if (!ret)
 669                         ret = smu_cmn_send_smc_msg_with_param(smu,
 670                                                               SMU_MSG_SetDriverDramAddrLow,
 671                                                               lower_32_bits(driver_table->mc_address),
 672                                                               NULL);
 673         }
 674
 675         return ret;
 676 }
 677
 678 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
 679 {
 680         int ret = 0;
 681         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 682
 683         if (tool_table->mc_address) {
 684                 ret = smu_cmn_send_smc_msg_with_param(smu,
 685                                                       SMU_MSG_SetToolsDramAddrHigh,
 686                                                       upper_32_bits(tool_table->mc_address),
 687                                                       NULL);
 688                 if (!ret)
 689                         ret = smu_cmn_send_smc_msg_with_param(smu,
 690                                                               SMU_MSG_SetToolsDramAddrLow,
 691                                                               lower_32_bits(tool_table->mc_address),
 692                                                               NULL);
 693         }
 694
 695         return ret;
 696 }
 697
 698 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
 699 {
 700         int ret = 0;
 701
 702         if (!smu->pm_enabled)
 703                 return ret;
 704
 705         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 706
 707         return ret;
 708 }
 709
 710
 711 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
 712 {
 713         struct smu_feature *feature = &smu->smu_feature;
 714         int ret = 0;
 715         uint32_t feature_mask[2];
 716
 717         mutex_lock(&feature->mutex);
 718         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 719                 goto failed;
 720
 721         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 722
 723         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 724                                               feature_mask[1], NULL);
 725         if (ret)
 726                 goto failed;
 727
 728         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 729                                               feature_mask[0], NULL);
 730         if (ret)
 731                 goto failed;
 732
 733 failed:
 734         mutex_unlock(&feature->mutex);
 735         return ret;
 736 }
 737
 738 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
 739 {
 740         int ret = 0;
 741         struct amdgpu_device *adev = smu->adev;
 742
 743         switch (adev->asic_type) {
 744         case CHIP_YELLOW_CARP:
 745                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 746                         return 0;
 747                 if (enable)
 748                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
 749                 else
 750                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
 751                 break;
 752         default:
 753                 break;
 754         }
 755
 756         return ret;
 757 }
 758
 759 int smu_v13_0_system_features_control(struct smu_context *smu,
 760                                       bool en)
 761 {
 762         struct smu_feature *feature = &smu->smu_feature;
 763         uint32_t feature_mask[2];
 764         int ret = 0;
 765
 766         ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 767                                          SMU_MSG_DisableAllSmuFeatures), NULL);
 768         if (ret)
 769                 return ret;
 770
 771         bitmap_zero(feature->enabled, feature->feature_num);
 772         bitmap_zero(feature->supported, feature->feature_num);
 773
 774         if (en) {
 775                 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 776                 if (ret)
 777                         return ret;
 778
 779                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 780                             feature->feature_num);
 781                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 782                             feature->feature_num);
 783         }
 784
 785         return ret;
 786 }
 787
 788 int smu_v13_0_notify_display_change(struct smu_context *smu)
 789 {
 790         int ret = 0;
 791
 792         if (!smu->pm_enabled)
 793                 return ret;
 794
 795         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 796             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 797                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 798
 799         return ret;
 800 }
 801
 802         static int
 803 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 804                                     enum smu_clk_type clock_select)
 805 {
 806         int ret = 0;
 807         int clk_id;
 808
 809         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 810             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 811                 return 0;
 812
 813         clk_id = smu_cmn_to_asic_specific_index(smu,
 814                                                 CMN2ASIC_MAPPING_CLK,
 815                                                 clock_select);
 816         if (clk_id < 0)
 817                 return -EINVAL;
 818
 819         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 820                                               clk_id << 16, clock);
 821         if (ret) {
 822                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 823                 return ret;
 824         }
 825
 826         if (*clock != 0)
 827                 return 0;
 828
 829         /* if DC limit is zero, return AC limit */
 830         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 831                                               clk_id << 16, clock);
 832         if (ret) {
 833                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 834                 return ret;
 835         }
 836
 837         return 0;
 838 }
 839
 840 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
 841 {
 842         struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
 843                 smu->smu_table.max_sustainable_clocks;
 844         int ret = 0;
 845
 846         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 847         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 848         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 849         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 850         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 851         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 852
 853         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 854                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 855                                                           &(max_sustainable_clocks->uclock),
 856                                                           SMU_UCLK);
 857                 if (ret) {
 858                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 859                                 __func__);
 860                         return ret;
 861                 }
 862         }
 863
 864         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 865                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 866                                                           &(max_sustainable_clocks->soc_clock),
 867                                                           SMU_SOCCLK);
 868                 if (ret) {
 869                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 870                                 __func__);
 871                         return ret;
 872                 }
 873         }
 874
 875         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 876                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 877                                                           &(max_sustainable_clocks->dcef_clock),
 878                                                           SMU_DCEFCLK);
 879                 if (ret) {
 880                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 881                                 __func__);
 882                         return ret;
 883                 }
 884
 885                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 886                                                           &(max_sustainable_clocks->display_clock),
 887                                                           SMU_DISPCLK);
 888                 if (ret) {
 889                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 890                                 __func__);
 891                         return ret;
 892                 }
 893                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 894                                                           &(max_sustainable_clocks->phy_clock),
 895                                                           SMU_PHYCLK);
 896                 if (ret) {
 897                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 898                                 __func__);
 899                         return ret;
 900                 }
 901                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 902                                                           &(max_sustainable_clocks->pixel_clock),
 903                                                           SMU_PIXCLK);
 904                 if (ret) {
 905                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 906                                 __func__);
 907                         return ret;
 908                 }
 909         }
 910
 911         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 912                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 913
 914         return 0;
 915 }
 916
 917 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
 918                                       uint32_t *power_limit)
 919 {
 920         int power_src;
 921         int ret = 0;
 922
 923         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 924                 return -EINVAL;
 925
 926         power_src = smu_cmn_to_asic_specific_index(smu,
 927                                                    CMN2ASIC_MAPPING_PWR,
 928                                                    smu->adev->pm.ac_power ?
 929                                                    SMU_POWER_SOURCE_AC :
 930                                                    SMU_POWER_SOURCE_DC);
 931         if (power_src < 0)
 932                 return -EINVAL;
 933
 934         ret = smu_cmn_send_smc_msg_with_param(smu,
 935                                               SMU_MSG_GetPptLimit,
 936                                               power_src << 16,
 937                                               power_limit);
 938         if (ret)
 939                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 940
 941         return ret;
 942 }
 943
 944 int smu_v13_0_set_power_limit(struct smu_context *smu, uint32_t n)
 945 {
 946         int ret = 0;
 947
 948         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 949                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 950                 return -EOPNOTSUPP;
 951         }
 952
 953         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
 954         if (ret) {
 955                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 956                 return ret;
 957         }
 958
 959         smu->current_power_limit = n;
 960
 961         return 0;
 962 }
 963
 964 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
 965 {
 966         if (smu->smu_table.thermal_controller_type)
 967                 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
 968
 969         return 0;
 970 }
 971
 972 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
 973 {
 974         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
 975 }
 976
 977 static uint16_t convert_to_vddc(uint8_t vid)
 978 {
 979         return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
 980 }
 981
 982 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
 983 {
 984         struct amdgpu_device *adev = smu->adev;
 985         uint32_t vdd = 0, val_vid = 0;
 986
 987         if (!value)
 988                 return -EINVAL;
 989         val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
 990                    SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
 991                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
 992
 993         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
 994
 995         *value = vdd;
 996
 997         return 0;
 998
 999 }
1000
1001 int
1002 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1003                                         struct pp_display_clock_request
1004                                         *clock_req)
1005 {
1006         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1007         int ret = 0;
1008         enum smu_clk_type clk_select = 0;
1009         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1010
1011         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1012             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1013                 switch (clk_type) {
1014                 case amd_pp_dcef_clock:
1015                         clk_select = SMU_DCEFCLK;
1016                         break;
1017                 case amd_pp_disp_clock:
1018                         clk_select = SMU_DISPCLK;
1019                         break;
1020                 case amd_pp_pixel_clock:
1021                         clk_select = SMU_PIXCLK;
1022                         break;
1023                 case amd_pp_phy_clock:
1024                         clk_select = SMU_PHYCLK;
1025                         break;
1026                 case amd_pp_mem_clock:
1027                         clk_select = SMU_UCLK;
1028                         break;
1029                 default:
1030                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1031                         ret = -EINVAL;
1032                         break;
1033                 }
1034
1035                 if (ret)
1036                         goto failed;
1037
1038                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1039                         return 0;
1040
1041                 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1042
1043                 if(clk_select == SMU_UCLK)
1044                         smu->hard_min_uclk_req_from_dal = clk_freq;
1045         }
1046
1047 failed:
1048         return ret;
1049 }
1050
1051 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1052 {
1053         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1054                 return AMD_FAN_CTRL_MANUAL;
1055         else
1056                 return AMD_FAN_CTRL_AUTO;
1057 }
1058
1059         static int
1060 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1061 {
1062         int ret = 0;
1063
1064         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1065                 return 0;
1066
1067         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1068         if (ret)
1069                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1070                         __func__, (auto_fan_control ? "Start" : "Stop"));
1071
1072         return ret;
1073 }
1074
1075         static int
1076 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1077 {
1078         struct amdgpu_device *adev = smu->adev;
1079
1080         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1081                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1082                                    CG_FDO_CTRL2, TMIN, 0));
1083         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1084                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1085                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1086
1087         return 0;
1088 }
1089
1090         int
1091 smu_v13_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1092 {
1093         struct amdgpu_device *adev = smu->adev;
1094         uint32_t duty100, duty;
1095         uint64_t tmp64;
1096
1097         if (speed > 100)
1098                 speed = 100;
1099
1100         if (smu_v13_0_auto_fan_control(smu, 0))
1101                 return -EINVAL;
1102
1103         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1104                                 CG_FDO_CTRL1, FMAX_DUTY100);
1105         if (!duty100)
1106                 return -EINVAL;
1107
1108         tmp64 = (uint64_t)speed * duty100;
1109         do_div(tmp64, 100);
1110         duty = (uint32_t)tmp64;
1111
1112         WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1113                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1114                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1115
1116         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1117 }
1118
1119         int
1120 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1121                                uint32_t mode)
1122 {
1123         int ret = 0;
1124
1125         switch (mode) {
1126         case AMD_FAN_CTRL_NONE:
1127                 ret = smu_v13_0_set_fan_speed_percent(smu, 100);
1128                 break;
1129         case AMD_FAN_CTRL_MANUAL:
1130                 ret = smu_v13_0_auto_fan_control(smu, 0);
1131                 break;
1132         case AMD_FAN_CTRL_AUTO:
1133                 ret = smu_v13_0_auto_fan_control(smu, 1);
1134                 break;
1135         default:
1136                 break;
1137         }
1138
1139         if (ret) {
1140                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1141                 return -EINVAL;
1142         }
1143
1144         return ret;
1145 }
1146
1147 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1148                                 uint32_t speed)
1149 {
1150         struct amdgpu_device *adev = smu->adev;
1151         int ret;
1152         uint32_t tach_period, crystal_clock_freq;
1153
1154         if (!speed)
1155                 return -EINVAL;
1156
1157         ret = smu_v13_0_auto_fan_control(smu, 0);
1158         if (ret)
1159                 return ret;
1160
1161         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1162         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1163         WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1164                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1165                                    CG_TACH_CTRL, TARGET_PERIOD,
1166                                    tach_period));
1167
1168         ret = smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1169
1170         return ret;
1171 }
1172
1173 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1174                               uint32_t pstate)
1175 {
1176         int ret = 0;
1177         ret = smu_cmn_send_smc_msg_with_param(smu,
1178                                               SMU_MSG_SetXgmiMode,
1179                                               pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1180                                               NULL);
1181         return ret;
1182 }
1183
1184 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1185                                    struct amdgpu_irq_src *source,
1186                                    unsigned tyep,
1187                                    enum amdgpu_interrupt_state state)
1188 {
1189         struct smu_context *smu = &adev->smu;
1190         uint32_t low, high;
1191         uint32_t val = 0;
1192
1193         switch (state) {
1194         case AMDGPU_IRQ_STATE_DISABLE:
1195                 /* For THM irqs */
1196                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1197                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1198                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1199                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1200
1201                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1202
1203                 /* For MP1 SW irqs */
1204                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1205                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1206                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1207
1208                 break;
1209         case AMDGPU_IRQ_STATE_ENABLE:
1210                 /* For THM irqs */
1211                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1212                           smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1213                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1214                            smu->thermal_range.software_shutdown_temp);
1215
1216                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1217                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1218                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1219                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1220                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1221                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1222                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1223                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1224                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1225
1226                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1227                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1228                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1229                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1230
1231                 /* For MP1 SW irqs */
1232                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1233                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1234                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1235                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1236
1237                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1238                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1239                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1240
1241                 break;
1242         default:
1243                 break;
1244         }
1245
1246         return 0;
1247 }
1248
1249 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1250 {
1251         return smu_cmn_send_smc_msg(smu,
1252                                     SMU_MSG_ReenableAcDcInterrupt,
1253                                     NULL);
1254 }
1255
1256 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1257 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1258 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1259
1260 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1261                                  struct amdgpu_irq_src *source,
1262                                  struct amdgpu_iv_entry *entry)
1263 {
1264         struct smu_context *smu = &adev->smu;
1265         uint32_t client_id = entry->client_id;
1266         uint32_t src_id = entry->src_id;
1267         /*
1268          * ctxid is used to distinguish different
1269          * events for SMCToHost interrupt.
1270          */
1271         uint32_t ctxid = entry->src_data[0];
1272         uint32_t data;
1273
1274         if (client_id == SOC15_IH_CLIENTID_THM) {
1275                 switch (src_id) {
1276                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1277                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1278                         /*
1279                          * SW CTF just occurred.
1280                          * Try to do a graceful shutdown to prevent further damage.
1281                          */
1282                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1283                         orderly_poweroff(true);
1284                         break;
1285                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1286                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1287                         break;
1288                 default:
1289                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1290                                   src_id);
1291                         break;
1292                 }
1293         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1294                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1295                 /*
1296                  * HW CTF just occurred. Shutdown to prevent further damage.
1297                  */
1298                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1299                 orderly_poweroff(true);
1300         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1301                 if (src_id == 0xfe) {
1302                         /* ACK SMUToHost interrupt */
1303                         data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1304                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1305                         WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1306
1307                         switch (ctxid) {
1308                         case 0x3:
1309                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1310                                 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1311                                 break;
1312                         case 0x4:
1313                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1314                                 smu_v13_0_ack_ac_dc_interrupt(&adev->smu);
1315                                 break;
1316                         case 0x7:
1317                                 /*
1318                                  * Increment the throttle interrupt counter
1319                                  */
1320                                 atomic64_inc(&smu->throttle_int_counter);
1321
1322                                 if (!atomic_read(&adev->throttling_logging_enabled))
1323                                         return 0;
1324
1325                                 if (__ratelimit(&adev->throttling_logging_rs))
1326                                         schedule_work(&smu->throttling_logging_work);
1327
1328                                 break;
1329                         }
1330                 }
1331         }
1332
1333         return 0;
1334 }
1335
1336 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1337 {
1338         .set = smu_v13_0_set_irq_state,
1339         .process = smu_v13_0_irq_process,
1340 };
1341
1342 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1343 {
1344         struct amdgpu_device *adev = smu->adev;
1345         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1346         int ret = 0;
1347
1348         irq_src->num_types = 1;
1349         irq_src->funcs = &smu_v13_0_irq_funcs;
1350
1351         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1352                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1353                                 irq_src);
1354         if (ret)
1355                 return ret;
1356
1357         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1358                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1359                                 irq_src);
1360         if (ret)
1361                 return ret;
1362
1363         /* Register CTF(GPIO_19) interrupt */
1364         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1365                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1366                                 irq_src);
1367         if (ret)
1368                 return ret;
1369
1370         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1371                                 0xfe,
1372                                 irq_src);
1373         if (ret)
1374                 return ret;
1375
1376         return ret;
1377 }
1378
1379 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1380                                                struct pp_smu_nv_clock_table *max_clocks)
1381 {
1382         struct smu_table_context *table_context = &smu->smu_table;
1383         struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1384
1385         if (!max_clocks || !table_context->max_sustainable_clocks)
1386                 return -EINVAL;
1387
1388         sustainable_clocks = table_context->max_sustainable_clocks;
1389
1390         max_clocks->dcfClockInKhz =
1391                 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1392         max_clocks->displayClockInKhz =
1393                 (unsigned int) sustainable_clocks->display_clock * 1000;
1394         max_clocks->phyClockInKhz =
1395                 (unsigned int) sustainable_clocks->phy_clock * 1000;
1396         max_clocks->pixelClockInKhz =
1397                 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1398         max_clocks->uClockInKhz =
1399                 (unsigned int) sustainable_clocks->uclock * 1000;
1400         max_clocks->socClockInKhz =
1401                 (unsigned int) sustainable_clocks->soc_clock * 1000;
1402         max_clocks->dscClockInKhz = 0;
1403         max_clocks->dppClockInKhz = 0;
1404         max_clocks->fabricClockInKhz = 0;
1405
1406         return 0;
1407 }
1408
1409 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1410 {
1411         int ret = 0;
1412
1413         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1414
1415         return ret;
1416 }
1417
1418 int smu_v13_0_mode1_reset(struct smu_context *smu)
1419 {
1420         u32 smu_version;
1421         int ret = 0;
1422         /*
1423         * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07
1424         */
1425         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1426         if (smu_version < 0x00440700)
1427                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1428         else
1429                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL);
1430
1431         if (!ret)
1432                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1433
1434         return ret;
1435 }
1436
1437 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1438                                              uint64_t event_arg)
1439 {
1440         int ret = 0;
1441
1442         dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1443         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1444
1445         return ret;
1446 }
1447
1448 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1449                              uint64_t event_arg)
1450 {
1451         int ret = -EINVAL;
1452
1453         switch (event) {
1454         case SMU_EVENT_RESET_COMPLETE:
1455                 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1456                 break;
1457         default:
1458                 break;
1459         }
1460
1461         return ret;
1462 }
1463
1464 int smu_v13_0_mode2_reset(struct smu_context *smu)
1465 {
1466         int ret;
1467
1468         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1469                         SMU_RESET_MODE_2, NULL);
1470         /*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
1471         if (!ret)
1472                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1473
1474         return ret;
1475 }
1476
1477 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1478                                     uint32_t *min, uint32_t *max)
1479 {
1480         int ret = 0, clk_id = 0;
1481         uint32_t param = 0;
1482         uint32_t clock_limit;
1483
1484         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1485                 switch (clk_type) {
1486                 case SMU_MCLK:
1487                 case SMU_UCLK:
1488                         clock_limit = smu->smu_table.boot_values.uclk;
1489                         break;
1490                 case SMU_GFXCLK:
1491                 case SMU_SCLK:
1492                         clock_limit = smu->smu_table.boot_values.gfxclk;
1493                         break;
1494                 case SMU_SOCCLK:
1495                         clock_limit = smu->smu_table.boot_values.socclk;
1496                         break;
1497                 default:
1498                         clock_limit = 0;
1499                         break;
1500                 }
1501
1502                 /* clock in Mhz unit */
1503                 if (min)
1504                         *min = clock_limit / 100;
1505                 if (max)
1506                         *max = clock_limit / 100;
1507
1508                 return 0;
1509         }
1510
1511         clk_id = smu_cmn_to_asic_specific_index(smu,
1512                                                 CMN2ASIC_MAPPING_CLK,
1513                                                 clk_type);
1514         if (clk_id < 0) {
1515                 ret = -EINVAL;
1516                 goto failed;
1517         }
1518         param = (clk_id & 0xffff) << 16;
1519
1520         if (max) {
1521                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1522                 if (ret)
1523                         goto failed;
1524         }
1525
1526         if (min) {
1527                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1528                 if (ret)
1529                         goto failed;
1530         }
1531
1532 failed:
1533         return ret;
1534 }
1535
1536 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1537                                           enum smu_clk_type clk_type,
1538                                           uint32_t min,
1539                                           uint32_t max)
1540 {
1541         struct amdgpu_device *adev = smu->adev;
1542         int ret = 0, clk_id = 0;
1543         uint32_t param;
1544
1545         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1546                 return 0;
1547
1548         clk_id = smu_cmn_to_asic_specific_index(smu,
1549                                                 CMN2ASIC_MAPPING_CLK,
1550                                                 clk_type);
1551         if (clk_id < 0)
1552                 return clk_id;
1553
1554         if (clk_type == SMU_GFXCLK)
1555                 amdgpu_gfx_off_ctrl(adev, false);
1556
1557         if (max > 0) {
1558                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1559                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1560                                                       param, NULL);
1561                 if (ret)
1562                         goto out;
1563         }
1564
1565         if (min > 0) {
1566                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1567                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1568                                                       param, NULL);
1569                 if (ret)
1570                         goto out;
1571         }
1572
1573 out:
1574         if (clk_type == SMU_GFXCLK)
1575                 amdgpu_gfx_off_ctrl(adev, true);
1576
1577         return ret;
1578 }
1579
1580 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1581                                           enum smu_clk_type clk_type,
1582                                           uint32_t min,
1583                                           uint32_t max)
1584 {
1585         int ret = 0, clk_id = 0;
1586         uint32_t param;
1587
1588         if (min <= 0 && max <= 0)
1589                 return -EINVAL;
1590
1591         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1592                 return 0;
1593
1594         clk_id = smu_cmn_to_asic_specific_index(smu,
1595                                                 CMN2ASIC_MAPPING_CLK,
1596                                                 clk_type);
1597         if (clk_id < 0)
1598                 return clk_id;
1599
1600         if (max > 0) {
1601                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1602                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1603                                                       param, NULL);
1604                 if (ret)
1605                         return ret;
1606         }
1607
1608         if (min > 0) {
1609                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1610                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1611                                                       param, NULL);
1612                 if (ret)
1613                         return ret;
1614         }
1615
1616         return ret;
1617 }
1618
1619 int smu_v13_0_set_performance_level(struct smu_context *smu,
1620                                     enum amd_dpm_forced_level level)
1621 {
1622         struct smu_13_0_dpm_context *dpm_context =
1623                 smu->smu_dpm.dpm_context;
1624         struct smu_13_0_dpm_table *gfx_table =
1625                 &dpm_context->dpm_tables.gfx_table;
1626         struct smu_13_0_dpm_table *mem_table =
1627                 &dpm_context->dpm_tables.uclk_table;
1628         struct smu_13_0_dpm_table *soc_table =
1629                 &dpm_context->dpm_tables.soc_table;
1630         struct smu_umd_pstate_table *pstate_table =
1631                 &smu->pstate_table;
1632         struct amdgpu_device *adev = smu->adev;
1633         uint32_t sclk_min = 0, sclk_max = 0;
1634         uint32_t mclk_min = 0, mclk_max = 0;
1635         uint32_t socclk_min = 0, socclk_max = 0;
1636         int ret = 0;
1637
1638         switch (level) {
1639         case AMD_DPM_FORCED_LEVEL_HIGH:
1640                 sclk_min = sclk_max = gfx_table->max;
1641                 mclk_min = mclk_max = mem_table->max;
1642                 socclk_min = socclk_max = soc_table->max;
1643                 break;
1644         case AMD_DPM_FORCED_LEVEL_LOW:
1645                 sclk_min = sclk_max = gfx_table->min;
1646                 mclk_min = mclk_max = mem_table->min;
1647                 socclk_min = socclk_max = soc_table->min;
1648                 break;
1649         case AMD_DPM_FORCED_LEVEL_AUTO:
1650                 sclk_min = gfx_table->min;
1651                 sclk_max = gfx_table->max;
1652                 mclk_min = mem_table->min;
1653                 mclk_max = mem_table->max;
1654                 socclk_min = soc_table->min;
1655                 socclk_max = soc_table->max;
1656                 break;
1657         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1658                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1659                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1660                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1661                 break;
1662         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1663                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1664                 break;
1665         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1666                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1667                 break;
1668         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1669                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1670                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1671                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1672                 break;
1673         case AMD_DPM_FORCED_LEVEL_MANUAL:
1674         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1675                 return 0;
1676         default:
1677                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1678                 return -EINVAL;
1679         }
1680
1681         mclk_min = mclk_max = 0;
1682         socclk_min = socclk_max = 0;
1683
1684         if (sclk_min && sclk_max) {
1685                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1686                                                             SMU_GFXCLK,
1687                                                             sclk_min,
1688                                                             sclk_max);
1689                 if (ret)
1690                         return ret;
1691
1692                 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1693                 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1694         }
1695
1696         if (mclk_min && mclk_max) {
1697                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1698                                                             SMU_MCLK,
1699                                                             mclk_min,
1700                                                             mclk_max);
1701                 if (ret)
1702                         return ret;
1703
1704                 pstate_table->uclk_pstate.curr.min = mclk_min;
1705                 pstate_table->uclk_pstate.curr.max = mclk_max;
1706         }
1707
1708         if (socclk_min && socclk_max) {
1709                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1710                                                             SMU_SOCCLK,
1711                                                             socclk_min,
1712                                                             socclk_max);
1713                 if (ret)
1714                         return ret;
1715
1716                 pstate_table->socclk_pstate.curr.min = socclk_min;
1717                 pstate_table->socclk_pstate.curr.max = socclk_max;
1718         }
1719
1720         return ret;
1721 }
1722
1723 int smu_v13_0_set_power_source(struct smu_context *smu,
1724                                enum smu_power_src_type power_src)
1725 {
1726         int pwr_source;
1727
1728         pwr_source = smu_cmn_to_asic_specific_index(smu,
1729                                                     CMN2ASIC_MAPPING_PWR,
1730                                                     (uint32_t)power_src);
1731         if (pwr_source < 0)
1732                 return -EINVAL;
1733
1734         return smu_cmn_send_smc_msg_with_param(smu,
1735                                                SMU_MSG_NotifyPowerSource,
1736                                                pwr_source,
1737                                                NULL);
1738 }
1739
1740 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1741                                     enum smu_clk_type clk_type,
1742                                     uint16_t level,
1743                                     uint32_t *value)
1744 {
1745         int ret = 0, clk_id = 0;
1746         uint32_t param;
1747
1748         if (!value)
1749                 return -EINVAL;
1750
1751         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1752                 return 0;
1753
1754         clk_id = smu_cmn_to_asic_specific_index(smu,
1755                                                 CMN2ASIC_MAPPING_CLK,
1756                                                 clk_type);
1757         if (clk_id < 0)
1758                 return clk_id;
1759
1760         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1761
1762         ret = smu_cmn_send_smc_msg_with_param(smu,
1763                                               SMU_MSG_GetDpmFreqByIndex,
1764                                               param,
1765                                               value);
1766         if (ret)
1767                 return ret;
1768
1769         /*
1770          * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
1771          * now, we un-support it
1772          */
1773         *value = *value & 0x7fffffff;
1774
1775         return ret;
1776 }
1777
1778 int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1779                                   enum smu_clk_type clk_type,
1780                                   uint32_t *value)
1781 {
1782         int ret;
1783
1784         ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1785         /* FW returns 0 based max level, increment by one */
1786         if (!ret && value)
1787                 ++(*value);
1788
1789         return ret;
1790 }
1791
1792 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1793                                    enum smu_clk_type clk_type,
1794                                    struct smu_13_0_dpm_table *single_dpm_table)
1795 {
1796         int ret = 0;
1797         uint32_t clk;
1798         int i;
1799
1800         ret = smu_v13_0_get_dpm_level_count(smu,
1801                                             clk_type,
1802                                             &single_dpm_table->count);
1803         if (ret) {
1804                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1805                 return ret;
1806         }
1807
1808         for (i = 0; i < single_dpm_table->count; i++) {
1809                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1810                                                       clk_type,
1811                                                       i,
1812                                                       &clk);
1813                 if (ret) {
1814                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1815                         return ret;
1816                 }
1817
1818                 single_dpm_table->dpm_levels[i].value = clk;
1819                 single_dpm_table->dpm_levels[i].enabled = true;
1820
1821                 if (i == 0)
1822                         single_dpm_table->min = clk;
1823                 else if (i == single_dpm_table->count - 1)
1824                         single_dpm_table->max = clk;
1825         }
1826
1827         return 0;
1828 }
1829
1830 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
1831                                   enum smu_clk_type clk_type,
1832                                   uint32_t *min_value,
1833                                   uint32_t *max_value)
1834 {
1835         uint32_t level_count = 0;
1836         int ret = 0;
1837
1838         if (!min_value && !max_value)
1839                 return -EINVAL;
1840
1841         if (min_value) {
1842                 /* by default, level 0 clock value as min value */
1843                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1844                                                       clk_type,
1845                                                       0,
1846                                                       min_value);
1847                 if (ret)
1848                         return ret;
1849         }
1850
1851         if (max_value) {
1852                 ret = smu_v13_0_get_dpm_level_count(smu,
1853                                                     clk_type,
1854                                                     &level_count);
1855                 if (ret)
1856                         return ret;
1857
1858                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1859                                                       clk_type,
1860                                                       level_count - 1,
1861                                                       max_value);
1862                 if (ret)
1863                         return ret;
1864         }
1865
1866         return ret;
1867 }
1868
1869 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1870 {
1871         struct amdgpu_device *adev = smu->adev;
1872
1873         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1874                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1875                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1876 }
1877
1878 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1879 {
1880         uint32_t width_level;
1881
1882         width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1883         if (width_level > LINK_WIDTH_MAX)
1884                 width_level = 0;
1885
1886         return link_width[width_level];
1887 }
1888
1889 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1890 {
1891         struct amdgpu_device *adev = smu->adev;
1892
1893         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1894                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1895                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1896 }
1897
1898 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1899 {
1900         uint32_t speed_level;
1901
1902         speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1903         if (speed_level > LINK_SPEED_MAX)
1904                 speed_level = 0;
1905
1906         return link_speed[speed_level];
1907 }
1908