drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_v11_0.h"
  29 #include "smu11_driver_if_vangogh.h"
  30 #include "vangogh_ppt.h"
  31 #include "smu_v11_5_ppsmc.h"
  32 #include "smu_v11_5_pmfw.h"
  33 #include "smu_cmn.h"
  34 #include "soc15_common.h"
  35 #include "asic_reg/gc/gc_10_3_0_offset.h"
  36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
  37 #include <asm/processor.h>
  38
  39 /*
  40  * DO NOT use these for err/warn/info/debug messages.
  41  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  42  * They are more MGPU friendly.
  43  */
  44 #undef pr_err
  45 #undef pr_warn
  46 #undef pr_info
  47 #undef pr_debug
  48
  49 #define FEATURE_MASK(feature) (1ULL << feature)
  50 #define SMC_DPM_FEATURE ( \
  51         FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
  52         FEATURE_MASK(FEATURE_VCN_DPM_BIT)        | \
  53         FEATURE_MASK(FEATURE_FCLK_DPM_BIT)       | \
  54         FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)     | \
  55         FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)     | \
  56         FEATURE_MASK(FEATURE_LCLK_DPM_BIT)       | \
  57         FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)    | \
  58         FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
  59         FEATURE_MASK(FEATURE_GFX_DPM_BIT))
  60
  61 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
  62         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  0),
  63         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                0),
  64         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,   0),
  65         MSG_MAP(EnableGfxOff,                   PPSMC_MSG_EnableGfxOff,                 0),
  66         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,          0),
  67         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,               0),
  68         MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,   0),
  69         MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile,             0),
  70         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 0),
  71         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   0),
  72         MSG_MAP(RlcPowerNotify,                 PPSMC_MSG_RlcPowerNotify,               0),
  73         MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,                0),
  74         MSG_MAP(SetSoftMinGfxclk,               PPSMC_MSG_SetSoftMinGfxclk,             0),
  75         MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,          0),
  76         MSG_MAP(SetHardMinIspiclkByFreq,        PPSMC_MSG_SetHardMinIspiclkByFreq,      0),
  77         MSG_MAP(SetHardMinIspxclkByFreq,        PPSMC_MSG_SetHardMinIspxclkByFreq,      0),
  78         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        0),
  79         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         0),
  80         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        0),
  81         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        0),
  82         MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,         0),
  83         MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,        0),
  84         MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,       0),
  85         MSG_MAP(SetSoftMinFclk,                 PPSMC_MSG_SetSoftMinFclk,               0),
  86         MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,                0),
  87         MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode,               0),
  88         MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,   0),
  89         MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,             0),
  90         MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,             0),
  91         MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,             0),
  92         MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,       0),
  93         MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,         0),
  94         MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,                        0),
  95         MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,      0),
  96         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                        0),
  97         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                          0),
  98         MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,         0),
  99         MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,       0),
 100         MSG_MAP(PowerUpCvip,                    PPSMC_MSG_PowerUpCvip,                          0),
 101         MSG_MAP(PowerDownCvip,                  PPSMC_MSG_PowerDownCvip,                        0),
 102         MSG_MAP(GetPptLimit,                        PPSMC_MSG_GetPptLimit,                      0),
 103         MSG_MAP(GetThermalLimit,                    PPSMC_MSG_GetThermalLimit,          0),
 104         MSG_MAP(GetCurrentTemperature,              PPSMC_MSG_GetCurrentTemperature, 0),
 105         MSG_MAP(GetCurrentPower,                    PPSMC_MSG_GetCurrentPower,           0),
 106         MSG_MAP(GetCurrentVoltage,                  PPSMC_MSG_GetCurrentVoltage,         0),
 107         MSG_MAP(GetCurrentCurrent,                  PPSMC_MSG_GetCurrentCurrent,         0),
 108         MSG_MAP(GetAverageCpuActivity,              PPSMC_MSG_GetAverageCpuActivity, 0),
 109         MSG_MAP(GetAverageGfxActivity,              PPSMC_MSG_GetAverageGfxActivity, 0),
 110         MSG_MAP(GetAveragePower,                    PPSMC_MSG_GetAveragePower,           0),
 111         MSG_MAP(GetAverageTemperature,              PPSMC_MSG_GetAverageTemperature, 0),
 112         MSG_MAP(SetAveragePowerTimeConstant,        PPSMC_MSG_SetAveragePowerTimeConstant,                      0),
 113         MSG_MAP(SetAverageActivityTimeConstant,     PPSMC_MSG_SetAverageActivityTimeConstant,           0),
 114         MSG_MAP(SetAverageTemperatureTimeConstant,  PPSMC_MSG_SetAverageTemperatureTimeConstant,        0),
 115         MSG_MAP(SetMitigationEndHysteresis,         PPSMC_MSG_SetMitigationEndHysteresis,                       0),
 116         MSG_MAP(GetCurrentFreq,                     PPSMC_MSG_GetCurrentFreq,                                           0),
 117         MSG_MAP(SetReducedPptLimit,                 PPSMC_MSG_SetReducedPptLimit,                                       0),
 118         MSG_MAP(SetReducedThermalLimit,             PPSMC_MSG_SetReducedThermalLimit,                           0),
 119         MSG_MAP(DramLogSetDramAddr,                 PPSMC_MSG_DramLogSetDramAddr,                                       0),
 120         MSG_MAP(StartDramLogging,                   PPSMC_MSG_StartDramLogging,                                         0),
 121         MSG_MAP(StopDramLogging,                    PPSMC_MSG_StopDramLogging,                                          0),
 122         MSG_MAP(SetSoftMinCclk,                     PPSMC_MSG_SetSoftMinCclk,                                           0),
 123         MSG_MAP(SetSoftMaxCclk,                     PPSMC_MSG_SetSoftMaxCclk,                                           0),
 124         MSG_MAP(RequestActiveWgp,                   PPSMC_MSG_RequestActiveWgp,                     0),
 125         MSG_MAP(SetFastPPTLimit,                    PPSMC_MSG_SetFastPPTLimit,                                          0),
 126         MSG_MAP(SetSlowPPTLimit,                    PPSMC_MSG_SetSlowPPTLimit,                                          0),
 127         MSG_MAP(GetFastPPTLimit,                    PPSMC_MSG_GetFastPPTLimit,                                          0),
 128         MSG_MAP(GetSlowPPTLimit,                    PPSMC_MSG_GetSlowPPTLimit,                                          0),
 129 };
 130
 131 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
 132         FEA_MAP(PPT),
 133         FEA_MAP(TDC),
 134         FEA_MAP(THERMAL),
 135         FEA_MAP(DS_GFXCLK),
 136         FEA_MAP(DS_SOCCLK),
 137         FEA_MAP(DS_LCLK),
 138         FEA_MAP(DS_FCLK),
 139         FEA_MAP(DS_MP1CLK),
 140         FEA_MAP(DS_MP0CLK),
 141         FEA_MAP(ATHUB_PG),
 142         FEA_MAP(CCLK_DPM),
 143         FEA_MAP(FAN_CONTROLLER),
 144         FEA_MAP(ULV),
 145         FEA_MAP(VCN_DPM),
 146         FEA_MAP(LCLK_DPM),
 147         FEA_MAP(SHUBCLK_DPM),
 148         FEA_MAP(DCFCLK_DPM),
 149         FEA_MAP(DS_DCFCLK),
 150         FEA_MAP(S0I2),
 151         FEA_MAP(SMU_LOW_POWER),
 152         FEA_MAP(GFX_DEM),
 153         FEA_MAP(PSI),
 154         FEA_MAP(PROCHOT),
 155         FEA_MAP(CPUOFF),
 156         FEA_MAP(STAPM),
 157         FEA_MAP(S0I3),
 158         FEA_MAP(DF_CSTATES),
 159         FEA_MAP(PERF_LIMIT),
 160         FEA_MAP(CORE_DLDO),
 161         FEA_MAP(RSMU_LOW_POWER),
 162         FEA_MAP(SMN_LOW_POWER),
 163         FEA_MAP(THM_LOW_POWER),
 164         FEA_MAP(SMUIO_LOW_POWER),
 165         FEA_MAP(MP1_LOW_POWER),
 166         FEA_MAP(DS_VCN),
 167         FEA_MAP(CPPC),
 168         FEA_MAP(OS_CSTATES),
 169         FEA_MAP(ISP_DPM),
 170         FEA_MAP(A55_DPM),
 171         FEA_MAP(CVIP_DSP_DPM),
 172         FEA_MAP(MSMU_LOW_POWER),
 173         FEA_MAP_REVERSE(SOCCLK),
 174         FEA_MAP_REVERSE(FCLK),
 175         FEA_MAP_HALF_REVERSE(GFX),
 176 };
 177
 178 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
 179         TAB_MAP_VALID(WATERMARKS),
 180         TAB_MAP_VALID(SMU_METRICS),
 181         TAB_MAP_VALID(CUSTOM_DPM),
 182         TAB_MAP_VALID(DPMCLOCKS),
 183 };
 184
 185 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 186         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 187         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 188         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 189         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 190         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 191 };
 192
 193 static const uint8_t vangogh_throttler_map[] = {
 194         [THROTTLER_STATUS_BIT_SPL]      = (SMU_THROTTLER_SPL_BIT),
 195         [THROTTLER_STATUS_BIT_FPPT]     = (SMU_THROTTLER_FPPT_BIT),
 196         [THROTTLER_STATUS_BIT_SPPT]     = (SMU_THROTTLER_SPPT_BIT),
 197         [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
 198         [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
 199         [THROTTLER_STATUS_BIT_THM_GFX]  = (SMU_THROTTLER_TEMP_GPU_BIT),
 200         [THROTTLER_STATUS_BIT_THM_SOC]  = (SMU_THROTTLER_TEMP_SOC_BIT),
 201         [THROTTLER_STATUS_BIT_TDC_VDD]  = (SMU_THROTTLER_TDC_VDD_BIT),
 202         [THROTTLER_STATUS_BIT_TDC_SOC]  = (SMU_THROTTLER_TDC_SOC_BIT),
 203         [THROTTLER_STATUS_BIT_TDC_GFX]  = (SMU_THROTTLER_TDC_GFX_BIT),
 204         [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
 205 };
 206
 207 static int vangogh_tables_init(struct smu_context *smu)
 208 {
 209         struct smu_table_context *smu_table = &smu->smu_table;
 210         struct smu_table *tables = smu_table->tables;
 211         struct amdgpu_device *adev = smu->adev;
 212         uint32_t if_version;
 213         uint32_t ret = 0;
 214
 215         ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
 216         if (ret) {
 217                 dev_err(adev->dev, "Failed to get smu if version!\n");
 218                 goto err0_out;
 219         }
 220
 221         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 222                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 223         SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
 224                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 225         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 226                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 227         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
 228                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 229
 230         if (if_version < 0x3) {
 231                 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t),
 232                                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 233                 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL);
 234         } else {
 235                 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 236                                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 237                 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 238         }
 239         if (!smu_table->metrics_table)
 240                 goto err0_out;
 241         smu_table->metrics_time = 0;
 242
 243         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
 244         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 245         if (!smu_table->gpu_metrics_table)
 246                 goto err1_out;
 247
 248         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 249         if (!smu_table->watermarks_table)
 250                 goto err2_out;
 251
 252         smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
 253         if (!smu_table->clocks_table)
 254                 goto err3_out;
 255
 256         return 0;
 257
 258 err3_out:
 259         kfree(smu_table->watermarks_table);
 260 err2_out:
 261         kfree(smu_table->gpu_metrics_table);
 262 err1_out:
 263         kfree(smu_table->metrics_table);
 264 err0_out:
 265         return -ENOMEM;
 266 }
 267
 268 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
 269                                        MetricsMember_t member,
 270                                        uint32_t *value)
 271 {
 272         struct smu_table_context *smu_table = &smu->smu_table;
 273         SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
 274         int ret = 0;
 275
 276         mutex_lock(&smu->metrics_lock);
 277
 278         ret = smu_cmn_get_metrics_table_locked(smu,
 279                                                NULL,
 280                                                false);
 281         if (ret) {
 282                 mutex_unlock(&smu->metrics_lock);
 283                 return ret;
 284         }
 285
 286         switch (member) {
 287         case METRICS_CURR_GFXCLK:
 288                 *value = metrics->GfxclkFrequency;
 289                 break;
 290         case METRICS_AVERAGE_SOCCLK:
 291                 *value = metrics->SocclkFrequency;
 292                 break;
 293         case METRICS_AVERAGE_VCLK:
 294                 *value = metrics->VclkFrequency;
 295                 break;
 296         case METRICS_AVERAGE_DCLK:
 297                 *value = metrics->DclkFrequency;
 298                 break;
 299         case METRICS_CURR_UCLK:
 300                 *value = metrics->MemclkFrequency;
 301                 break;
 302         case METRICS_AVERAGE_GFXACTIVITY:
 303                 *value = metrics->GfxActivity / 100;
 304                 break;
 305         case METRICS_AVERAGE_VCNACTIVITY:
 306                 *value = metrics->UvdActivity;
 307                 break;
 308         case METRICS_AVERAGE_SOCKETPOWER:
 309                 *value = (metrics->CurrentSocketPower << 8) /
 310                 1000 ;
 311                 break;
 312         case METRICS_TEMPERATURE_EDGE:
 313                 *value = metrics->GfxTemperature / 100 *
 314                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 315                 break;
 316         case METRICS_TEMPERATURE_HOTSPOT:
 317                 *value = metrics->SocTemperature / 100 *
 318                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 319                 break;
 320         case METRICS_THROTTLER_STATUS:
 321                 *value = metrics->ThrottlerStatus;
 322                 break;
 323         case METRICS_VOLTAGE_VDDGFX:
 324                 *value = metrics->Voltage[2];
 325                 break;
 326         case METRICS_VOLTAGE_VDDSOC:
 327                 *value = metrics->Voltage[1];
 328                 break;
 329         case METRICS_AVERAGE_CPUCLK:
 330                 memcpy(value, &metrics->CoreFrequency[0],
 331                        smu->cpu_core_num * sizeof(uint16_t));
 332                 break;
 333         default:
 334                 *value = UINT_MAX;
 335                 break;
 336         }
 337
 338         mutex_unlock(&smu->metrics_lock);
 339
 340         return ret;
 341 }
 342
 343 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
 344                                        MetricsMember_t member,
 345                                        uint32_t *value)
 346 {
 347         struct smu_table_context *smu_table = &smu->smu_table;
 348         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 349         int ret = 0;
 350
 351         mutex_lock(&smu->metrics_lock);
 352
 353         ret = smu_cmn_get_metrics_table_locked(smu,
 354                                                NULL,
 355                                                false);
 356         if (ret) {
 357                 mutex_unlock(&smu->metrics_lock);
 358                 return ret;
 359         }
 360
 361         switch (member) {
 362         case METRICS_CURR_GFXCLK:
 363                 *value = metrics->Current.GfxclkFrequency;
 364                 break;
 365         case METRICS_AVERAGE_SOCCLK:
 366                 *value = metrics->Current.SocclkFrequency;
 367                 break;
 368         case METRICS_AVERAGE_VCLK:
 369                 *value = metrics->Current.VclkFrequency;
 370                 break;
 371         case METRICS_AVERAGE_DCLK:
 372                 *value = metrics->Current.DclkFrequency;
 373                 break;
 374         case METRICS_CURR_UCLK:
 375                 *value = metrics->Current.MemclkFrequency;
 376                 break;
 377         case METRICS_AVERAGE_GFXACTIVITY:
 378                 *value = metrics->Current.GfxActivity;
 379                 break;
 380         case METRICS_AVERAGE_VCNACTIVITY:
 381                 *value = metrics->Current.UvdActivity;
 382                 break;
 383         case METRICS_AVERAGE_SOCKETPOWER:
 384                 *value = (metrics->Current.CurrentSocketPower << 8) /
 385                 1000;
 386                 break;
 387         case METRICS_TEMPERATURE_EDGE:
 388                 *value = metrics->Current.GfxTemperature / 100 *
 389                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 390                 break;
 391         case METRICS_TEMPERATURE_HOTSPOT:
 392                 *value = metrics->Current.SocTemperature / 100 *
 393                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 394                 break;
 395         case METRICS_THROTTLER_STATUS:
 396                 *value = metrics->Current.ThrottlerStatus;
 397                 break;
 398         case METRICS_VOLTAGE_VDDGFX:
 399                 *value = metrics->Current.Voltage[2];
 400                 break;
 401         case METRICS_VOLTAGE_VDDSOC:
 402                 *value = metrics->Current.Voltage[1];
 403                 break;
 404         case METRICS_AVERAGE_CPUCLK:
 405                 memcpy(value, &metrics->Current.CoreFrequency[0],
 406                        smu->cpu_core_num * sizeof(uint16_t));
 407                 break;
 408         default:
 409                 *value = UINT_MAX;
 410                 break;
 411         }
 412
 413         mutex_unlock(&smu->metrics_lock);
 414
 415         return ret;
 416 }
 417
 418 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
 419                                        MetricsMember_t member,
 420                                        uint32_t *value)
 421 {
 422         struct amdgpu_device *adev = smu->adev;
 423         uint32_t if_version;
 424         int ret = 0;
 425
 426         ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
 427         if (ret) {
 428                 dev_err(adev->dev, "Failed to get smu if version!\n");
 429                 return ret;
 430         }
 431
 432         if (if_version < 0x3)
 433                 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
 434         else
 435                 ret = vangogh_get_smu_metrics_data(smu, member, value);
 436
 437         return ret;
 438 }
 439
 440 static int vangogh_allocate_dpm_context(struct smu_context *smu)
 441 {
 442         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 443
 444         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 445                                        GFP_KERNEL);
 446         if (!smu_dpm->dpm_context)
 447                 return -ENOMEM;
 448
 449         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 450
 451         return 0;
 452 }
 453
 454 static int vangogh_init_smc_tables(struct smu_context *smu)
 455 {
 456         int ret = 0;
 457
 458         ret = vangogh_tables_init(smu);
 459         if (ret)
 460                 return ret;
 461
 462         ret = vangogh_allocate_dpm_context(smu);
 463         if (ret)
 464                 return ret;
 465
 466 #ifdef CONFIG_X86
 467         /* AMD x86 APU only */
 468         smu->cpu_core_num = boot_cpu_data.x86_max_cores;
 469 #else
 470         smu->cpu_core_num = 4;
 471 #endif
 472
 473         return smu_v11_0_init_smc_tables(smu);
 474 }
 475
 476 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 477 {
 478         int ret = 0;
 479
 480         if (enable) {
 481                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 482                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 483                 if (ret)
 484                         return ret;
 485         } else {
 486                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 487                 if (ret)
 488                         return ret;
 489         }
 490
 491         return ret;
 492 }
 493
 494 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 495 {
 496         int ret = 0;
 497
 498         if (enable) {
 499                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 500                 if (ret)
 501                         return ret;
 502         } else {
 503                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 504                 if (ret)
 505                         return ret;
 506         }
 507
 508         return ret;
 509 }
 510
 511 static bool vangogh_is_dpm_running(struct smu_context *smu)
 512 {
 513         struct amdgpu_device *adev = smu->adev;
 514         int ret = 0;
 515         uint32_t feature_mask[2];
 516         uint64_t feature_enabled;
 517
 518         /* we need to re-init after suspend so return false */
 519         if (adev->in_suspend)
 520                 return false;
 521
 522         ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
 523
 524         if (ret)
 525                 return false;
 526
 527         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
 528                                 ((uint64_t)feature_mask[1] << 32));
 529
 530         return !!(feature_enabled & SMC_DPM_FEATURE);
 531 }
 532
 533 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
 534                                                 uint32_t dpm_level, uint32_t *freq)
 535 {
 536         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 537
 538         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 539                 return -EINVAL;
 540
 541         switch (clk_type) {
 542         case SMU_SOCCLK:
 543                 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
 544                         return -EINVAL;
 545                 *freq = clk_table->SocClocks[dpm_level];
 546                 break;
 547         case SMU_VCLK:
 548                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 549                         return -EINVAL;
 550                 *freq = clk_table->VcnClocks[dpm_level].vclk;
 551                 break;
 552         case SMU_DCLK:
 553                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 554                         return -EINVAL;
 555                 *freq = clk_table->VcnClocks[dpm_level].dclk;
 556                 break;
 557         case SMU_UCLK:
 558         case SMU_MCLK:
 559                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 560                         return -EINVAL;
 561                 *freq = clk_table->DfPstateTable[dpm_level].memclk;
 562
 563                 break;
 564         case SMU_FCLK:
 565                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 566                         return -EINVAL;
 567                 *freq = clk_table->DfPstateTable[dpm_level].fclk;
 568                 break;
 569         default:
 570                 return -EINVAL;
 571         }
 572
 573         return 0;
 574 }
 575
 576 static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
 577                         enum smu_clk_type clk_type, char *buf)
 578 {
 579         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 580         SmuMetrics_legacy_t metrics;
 581         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 582         int i, size = 0, ret = 0;
 583         uint32_t cur_value = 0, value = 0, count = 0;
 584         bool cur_value_match_level = false;
 585
 586         memset(&metrics, 0, sizeof(metrics));
 587
 588         ret = smu_cmn_get_metrics_table(smu, &metrics, false);
 589         if (ret)
 590                 return ret;
 591
 592         switch (clk_type) {
 593         case SMU_OD_SCLK:
 594                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 595                         size = sysfs_emit(buf, "%s:\n", "OD_SCLK");
 596                         size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 597                         (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
 598                         size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 599                         (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
 600                 }
 601                 break;
 602         case SMU_OD_CCLK:
 603                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 604                         size = sysfs_emit(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
 605                         size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 606                         (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
 607                         size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 608                         (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
 609                 }
 610                 break;
 611         case SMU_OD_RANGE:
 612                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 613                         size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
 614                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
 615                                 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
 616                         size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
 617                                 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
 618                 }
 619                 break;
 620         case SMU_SOCCLK:
 621                 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
 622                 count = clk_table->NumSocClkLevelsEnabled;
 623                 cur_value = metrics.SocclkFrequency;
 624                 break;
 625         case SMU_VCLK:
 626                 count = clk_table->VcnClkLevelsEnabled;
 627                 cur_value = metrics.VclkFrequency;
 628                 break;
 629         case SMU_DCLK:
 630                 count = clk_table->VcnClkLevelsEnabled;
 631                 cur_value = metrics.DclkFrequency;
 632                 break;
 633         case SMU_MCLK:
 634                 count = clk_table->NumDfPstatesEnabled;
 635                 cur_value = metrics.MemclkFrequency;
 636                 break;
 637         case SMU_FCLK:
 638                 count = clk_table->NumDfPstatesEnabled;
 639                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
 640                 if (ret)
 641                         return ret;
 642                 break;
 643         default:
 644                 break;
 645         }
 646
 647         switch (clk_type) {
 648         case SMU_SOCCLK:
 649         case SMU_VCLK:
 650         case SMU_DCLK:
 651         case SMU_MCLK:
 652         case SMU_FCLK:
 653                 for (i = 0; i < count; i++) {
 654                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
 655                         if (ret)
 656                                 return ret;
 657                         if (!value)
 658                                 continue;
 659                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
 660                                         cur_value == value ? "*" : "");
 661                         if (cur_value == value)
 662                                 cur_value_match_level = true;
 663                 }
 664
 665                 if (!cur_value_match_level)
 666                         size += sysfs_emit_at(buf, size, "   %uMhz *\n", cur_value);
 667                 break;
 668         default:
 669                 break;
 670         }
 671
 672         return size;
 673 }
 674
 675 static int vangogh_print_clk_levels(struct smu_context *smu,
 676                         enum smu_clk_type clk_type, char *buf)
 677 {
 678         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 679         SmuMetrics_t metrics;
 680         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 681         int i, size = 0, ret = 0;
 682         uint32_t cur_value = 0, value = 0, count = 0;
 683         bool cur_value_match_level = false;
 684
 685         memset(&metrics, 0, sizeof(metrics));
 686
 687         ret = smu_cmn_get_metrics_table(smu, &metrics, false);
 688         if (ret)
 689                 return ret;
 690
 691         switch (clk_type) {
 692         case SMU_OD_SCLK:
 693                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 694                         size = sysfs_emit(buf, "%s:\n", "OD_SCLK");
 695                         size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 696                         (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
 697                         size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 698                         (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
 699                 }
 700                 break;
 701         case SMU_OD_CCLK:
 702                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 703                         size = sysfs_emit(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
 704                         size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 705                         (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
 706                         size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 707                         (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
 708                 }
 709                 break;
 710         case SMU_OD_RANGE:
 711                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 712                         size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
 713                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
 714                                 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
 715                         size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
 716                                 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
 717                 }
 718                 break;
 719         case SMU_SOCCLK:
 720                 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
 721                 count = clk_table->NumSocClkLevelsEnabled;
 722                 cur_value = metrics.Current.SocclkFrequency;
 723                 break;
 724         case SMU_VCLK:
 725                 count = clk_table->VcnClkLevelsEnabled;
 726                 cur_value = metrics.Current.VclkFrequency;
 727                 break;
 728         case SMU_DCLK:
 729                 count = clk_table->VcnClkLevelsEnabled;
 730                 cur_value = metrics.Current.DclkFrequency;
 731                 break;
 732         case SMU_MCLK:
 733                 count = clk_table->NumDfPstatesEnabled;
 734                 cur_value = metrics.Current.MemclkFrequency;
 735                 break;
 736         case SMU_FCLK:
 737                 count = clk_table->NumDfPstatesEnabled;
 738                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
 739                 if (ret)
 740                         return ret;
 741                 break;
 742         default:
 743                 break;
 744         }
 745
 746         switch (clk_type) {
 747         case SMU_SOCCLK:
 748         case SMU_VCLK:
 749         case SMU_DCLK:
 750         case SMU_MCLK:
 751         case SMU_FCLK:
 752                 for (i = 0; i < count; i++) {
 753                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
 754                         if (ret)
 755                                 return ret;
 756                         if (!value)
 757                                 continue;
 758                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
 759                                         cur_value == value ? "*" : "");
 760                         if (cur_value == value)
 761                                 cur_value_match_level = true;
 762                 }
 763
 764                 if (!cur_value_match_level)
 765                         size += sysfs_emit_at(buf, size, "   %uMhz *\n", cur_value);
 766                 break;
 767         default:
 768                 break;
 769         }
 770
 771         return size;
 772 }
 773
 774 static int vangogh_common_print_clk_levels(struct smu_context *smu,
 775                         enum smu_clk_type clk_type, char *buf)
 776 {
 777         struct amdgpu_device *adev = smu->adev;
 778         uint32_t if_version;
 779         int ret = 0;
 780
 781         ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
 782         if (ret) {
 783                 dev_err(adev->dev, "Failed to get smu if version!\n");
 784                 return ret;
 785         }
 786
 787         if (if_version < 0x3)
 788                 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
 789         else
 790                 ret = vangogh_print_clk_levels(smu, clk_type, buf);
 791
 792         return ret;
 793 }
 794
 795 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
 796                                          enum amd_dpm_forced_level level,
 797                                          uint32_t *vclk_mask,
 798                                          uint32_t *dclk_mask,
 799                                          uint32_t *mclk_mask,
 800                                          uint32_t *fclk_mask,
 801                                          uint32_t *soc_mask)
 802 {
 803         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 804
 805         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
 806                 if (mclk_mask)
 807                         *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
 808
 809                 if (fclk_mask)
 810                         *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
 811
 812                 if (soc_mask)
 813                         *soc_mask = 0;
 814         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
 815                 if (mclk_mask)
 816                         *mclk_mask = 0;
 817
 818                 if (fclk_mask)
 819                         *fclk_mask = 0;
 820
 821                 if (soc_mask)
 822                         *soc_mask = 1;
 823
 824                 if (vclk_mask)
 825                         *vclk_mask = 1;
 826
 827                 if (dclk_mask)
 828                         *dclk_mask = 1;
 829         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
 830                 if (mclk_mask)
 831                         *mclk_mask = 0;
 832
 833                 if (fclk_mask)
 834                         *fclk_mask = 0;
 835
 836                 if (soc_mask)
 837                         *soc_mask = 1;
 838
 839                 if (vclk_mask)
 840                         *vclk_mask = 1;
 841
 842                 if (dclk_mask)
 843                         *dclk_mask = 1;
 844         }
 845
 846         return 0;
 847 }
 848
 849 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
 850                                 enum smu_clk_type clk_type)
 851 {
 852         enum smu_feature_mask feature_id = 0;
 853
 854         switch (clk_type) {
 855         case SMU_MCLK:
 856         case SMU_UCLK:
 857         case SMU_FCLK:
 858                 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
 859                 break;
 860         case SMU_GFXCLK:
 861         case SMU_SCLK:
 862                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 863                 break;
 864         case SMU_SOCCLK:
 865                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 866                 break;
 867         case SMU_VCLK:
 868         case SMU_DCLK:
 869                 feature_id = SMU_FEATURE_VCN_DPM_BIT;
 870                 break;
 871         default:
 872                 return true;
 873         }
 874
 875         if (!smu_cmn_feature_is_enabled(smu, feature_id))
 876                 return false;
 877
 878         return true;
 879 }
 880
 881 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
 882                                         enum smu_clk_type clk_type,
 883                                         uint32_t *min,
 884                                         uint32_t *max)
 885 {
 886         int ret = 0;
 887         uint32_t soc_mask;
 888         uint32_t vclk_mask;
 889         uint32_t dclk_mask;
 890         uint32_t mclk_mask;
 891         uint32_t fclk_mask;
 892         uint32_t clock_limit;
 893
 894         if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
 895                 switch (clk_type) {
 896                 case SMU_MCLK:
 897                 case SMU_UCLK:
 898                         clock_limit = smu->smu_table.boot_values.uclk;
 899                         break;
 900                 case SMU_FCLK:
 901                         clock_limit = smu->smu_table.boot_values.fclk;
 902                         break;
 903                 case SMU_GFXCLK:
 904                 case SMU_SCLK:
 905                         clock_limit = smu->smu_table.boot_values.gfxclk;
 906                         break;
 907                 case SMU_SOCCLK:
 908                         clock_limit = smu->smu_table.boot_values.socclk;
 909                         break;
 910                 case SMU_VCLK:
 911                         clock_limit = smu->smu_table.boot_values.vclk;
 912                         break;
 913                 case SMU_DCLK:
 914                         clock_limit = smu->smu_table.boot_values.dclk;
 915                         break;
 916                 default:
 917                         clock_limit = 0;
 918                         break;
 919                 }
 920
 921                 /* clock in Mhz unit */
 922                 if (min)
 923                         *min = clock_limit / 100;
 924                 if (max)
 925                         *max = clock_limit / 100;
 926
 927                 return 0;
 928         }
 929         if (max) {
 930                 ret = vangogh_get_profiling_clk_mask(smu,
 931                                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
 932                                                         &vclk_mask,
 933                                                         &dclk_mask,
 934                                                         &mclk_mask,
 935                                                         &fclk_mask,
 936                                                         &soc_mask);
 937                 if (ret)
 938                         goto failed;
 939
 940                 switch (clk_type) {
 941                 case SMU_UCLK:
 942                 case SMU_MCLK:
 943                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
 944                         if (ret)
 945                                 goto failed;
 946                         break;
 947                 case SMU_SOCCLK:
 948                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
 949                         if (ret)
 950                                 goto failed;
 951                         break;
 952                 case SMU_FCLK:
 953                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
 954                         if (ret)
 955                                 goto failed;
 956                         break;
 957                 case SMU_VCLK:
 958                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
 959                         if (ret)
 960                                 goto failed;
 961                         break;
 962                 case SMU_DCLK:
 963                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
 964                         if (ret)
 965                                 goto failed;
 966                         break;
 967                 default:
 968                         ret = -EINVAL;
 969                         goto failed;
 970                 }
 971         }
 972         if (min) {
 973                 switch (clk_type) {
 974                 case SMU_UCLK:
 975                 case SMU_MCLK:
 976                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
 977                         if (ret)
 978                                 goto failed;
 979                         break;
 980                 case SMU_SOCCLK:
 981                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
 982                         if (ret)
 983                                 goto failed;
 984                         break;
 985                 case SMU_FCLK:
 986                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
 987                         if (ret)
 988                                 goto failed;
 989                         break;
 990                 case SMU_VCLK:
 991                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
 992                         if (ret)
 993                                 goto failed;
 994                         break;
 995                 case SMU_DCLK:
 996                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
 997                         if (ret)
 998                                 goto failed;
 999                         break;
1000                 default:
1001                         ret = -EINVAL;
1002                         goto failed;
1003                 }
1004         }
1005 failed:
1006         return ret;
1007 }
1008
1009 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1010                                            char *buf)
1011 {
1012         static const char *profile_name[] = {
1013                                         "BOOTUP_DEFAULT",
1014                                         "3D_FULL_SCREEN",
1015                                         "POWER_SAVING",
1016                                         "VIDEO",
1017                                         "VR",
1018                                         "COMPUTE",
1019                                         "CUSTOM"};
1020         uint32_t i, size = 0;
1021         int16_t workload_type = 0;
1022
1023         if (!buf)
1024                 return -EINVAL;
1025
1026         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1027                 /*
1028                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1029                  * Not all profile modes are supported on vangogh.
1030                  */
1031                 workload_type = smu_cmn_to_asic_specific_index(smu,
1032                                                                CMN2ASIC_MAPPING_WORKLOAD,
1033                                                                i);
1034
1035                 if (workload_type < 0)
1036                         continue;
1037
1038                 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1039                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1040         }
1041
1042         return size;
1043 }
1044
1045 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1046 {
1047         int workload_type, ret;
1048         uint32_t profile_mode = input[size];
1049
1050         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1051                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1052                 return -EINVAL;
1053         }
1054
1055         if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
1056                         profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
1057                 return 0;
1058
1059         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1060         workload_type = smu_cmn_to_asic_specific_index(smu,
1061                                                        CMN2ASIC_MAPPING_WORKLOAD,
1062                                                        profile_mode);
1063         if (workload_type < 0) {
1064                 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
1065                                         profile_mode);
1066                 return -EINVAL;
1067         }
1068
1069         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1070                                     1 << workload_type,
1071                                     NULL);
1072         if (ret) {
1073                 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
1074                                         workload_type);
1075                 return ret;
1076         }
1077
1078         smu->power_profile_mode = profile_mode;
1079
1080         return 0;
1081 }
1082
1083 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1084                                           enum smu_clk_type clk_type,
1085                                           uint32_t min,
1086                                           uint32_t max)
1087 {
1088         int ret = 0;
1089
1090         if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1091                 return 0;
1092
1093         switch (clk_type) {
1094         case SMU_GFXCLK:
1095         case SMU_SCLK:
1096                 ret = smu_cmn_send_smc_msg_with_param(smu,
1097                                                         SMU_MSG_SetHardMinGfxClk,
1098                                                         min, NULL);
1099                 if (ret)
1100                         return ret;
1101
1102                 ret = smu_cmn_send_smc_msg_with_param(smu,
1103                                                         SMU_MSG_SetSoftMaxGfxClk,
1104                                                         max, NULL);
1105                 if (ret)
1106                         return ret;
1107                 break;
1108         case SMU_FCLK:
1109                 ret = smu_cmn_send_smc_msg_with_param(smu,
1110                                                         SMU_MSG_SetHardMinFclkByFreq,
1111                                                         min, NULL);
1112                 if (ret)
1113                         return ret;
1114
1115                 ret = smu_cmn_send_smc_msg_with_param(smu,
1116                                                         SMU_MSG_SetSoftMaxFclkByFreq,
1117                                                         max, NULL);
1118                 if (ret)
1119                         return ret;
1120                 break;
1121         case SMU_SOCCLK:
1122                 ret = smu_cmn_send_smc_msg_with_param(smu,
1123                                                         SMU_MSG_SetHardMinSocclkByFreq,
1124                                                         min, NULL);
1125                 if (ret)
1126                         return ret;
1127
1128                 ret = smu_cmn_send_smc_msg_with_param(smu,
1129                                                         SMU_MSG_SetSoftMaxSocclkByFreq,
1130                                                         max, NULL);
1131                 if (ret)
1132                         return ret;
1133                 break;
1134         case SMU_VCLK:
1135                 ret = smu_cmn_send_smc_msg_with_param(smu,
1136                                                         SMU_MSG_SetHardMinVcn,
1137                                                         min << 16, NULL);
1138                 if (ret)
1139                         return ret;
1140                 ret = smu_cmn_send_smc_msg_with_param(smu,
1141                                                         SMU_MSG_SetSoftMaxVcn,
1142                                                         max << 16, NULL);
1143                 if (ret)
1144                         return ret;
1145                 break;
1146         case SMU_DCLK:
1147                 ret = smu_cmn_send_smc_msg_with_param(smu,
1148                                                         SMU_MSG_SetHardMinVcn,
1149                                                         min, NULL);
1150                 if (ret)
1151                         return ret;
1152                 ret = smu_cmn_send_smc_msg_with_param(smu,
1153                                                         SMU_MSG_SetSoftMaxVcn,
1154                                                         max, NULL);
1155                 if (ret)
1156                         return ret;
1157                 break;
1158         default:
1159                 return -EINVAL;
1160         }
1161
1162         return ret;
1163 }
1164
1165 static int vangogh_force_clk_levels(struct smu_context *smu,
1166                                    enum smu_clk_type clk_type, uint32_t mask)
1167 {
1168         uint32_t soft_min_level = 0, soft_max_level = 0;
1169         uint32_t min_freq = 0, max_freq = 0;
1170         int ret = 0 ;
1171
1172         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1173         soft_max_level = mask ? (fls(mask) - 1) : 0;
1174
1175         switch (clk_type) {
1176         case SMU_SOCCLK:
1177                 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1178                                                 soft_min_level, &min_freq);
1179                 if (ret)
1180                         return ret;
1181                 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1182                                                 soft_max_level, &max_freq);
1183                 if (ret)
1184                         return ret;
1185                 ret = smu_cmn_send_smc_msg_with_param(smu,
1186                                                                 SMU_MSG_SetSoftMaxSocclkByFreq,
1187                                                                 max_freq, NULL);
1188                 if (ret)
1189                         return ret;
1190                 ret = smu_cmn_send_smc_msg_with_param(smu,
1191                                                                 SMU_MSG_SetHardMinSocclkByFreq,
1192                                                                 min_freq, NULL);
1193                 if (ret)
1194                         return ret;
1195                 break;
1196         case SMU_FCLK:
1197                 ret = vangogh_get_dpm_clk_limited(smu,
1198                                                         clk_type, soft_min_level, &min_freq);
1199                 if (ret)
1200                         return ret;
1201                 ret = vangogh_get_dpm_clk_limited(smu,
1202                                                         clk_type, soft_max_level, &max_freq);
1203                 if (ret)
1204                         return ret;
1205                 ret = smu_cmn_send_smc_msg_with_param(smu,
1206                                                                 SMU_MSG_SetSoftMaxFclkByFreq,
1207                                                                 max_freq, NULL);
1208                 if (ret)
1209                         return ret;
1210                 ret = smu_cmn_send_smc_msg_with_param(smu,
1211                                                                 SMU_MSG_SetHardMinFclkByFreq,
1212                                                                 min_freq, NULL);
1213                 if (ret)
1214                         return ret;
1215                 break;
1216         case SMU_VCLK:
1217                 ret = vangogh_get_dpm_clk_limited(smu,
1218                                                         clk_type, soft_min_level, &min_freq);
1219                 if (ret)
1220                         return ret;
1221
1222                 ret = vangogh_get_dpm_clk_limited(smu,
1223                                                         clk_type, soft_max_level, &max_freq);
1224                 if (ret)
1225                         return ret;
1226
1227
1228                 ret = smu_cmn_send_smc_msg_with_param(smu,
1229                                                                 SMU_MSG_SetHardMinVcn,
1230                                                                 min_freq << 16, NULL);
1231                 if (ret)
1232                         return ret;
1233
1234                 ret = smu_cmn_send_smc_msg_with_param(smu,
1235                                                                 SMU_MSG_SetSoftMaxVcn,
1236                                                                 max_freq << 16, NULL);
1237                 if (ret)
1238                         return ret;
1239
1240                 break;
1241         case SMU_DCLK:
1242                 ret = vangogh_get_dpm_clk_limited(smu,
1243                                                         clk_type, soft_min_level, &min_freq);
1244                 if (ret)
1245                         return ret;
1246
1247                 ret = vangogh_get_dpm_clk_limited(smu,
1248                                                         clk_type, soft_max_level, &max_freq);
1249                 if (ret)
1250                         return ret;
1251
1252                 ret = smu_cmn_send_smc_msg_with_param(smu,
1253                                                         SMU_MSG_SetHardMinVcn,
1254                                                         min_freq, NULL);
1255                 if (ret)
1256                         return ret;
1257
1258                 ret = smu_cmn_send_smc_msg_with_param(smu,
1259                                                         SMU_MSG_SetSoftMaxVcn,
1260                                                         max_freq, NULL);
1261                 if (ret)
1262                         return ret;
1263
1264                 break;
1265         default:
1266                 break;
1267         }
1268
1269         return ret;
1270 }
1271
1272 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1273 {
1274         int ret = 0, i = 0;
1275         uint32_t min_freq, max_freq, force_freq;
1276         enum smu_clk_type clk_type;
1277
1278         enum smu_clk_type clks[] = {
1279                 SMU_SOCCLK,
1280                 SMU_VCLK,
1281                 SMU_DCLK,
1282                 SMU_FCLK,
1283         };
1284
1285         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1286                 clk_type = clks[i];
1287                 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1288                 if (ret)
1289                         return ret;
1290
1291                 force_freq = highest ? max_freq : min_freq;
1292                 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1293                 if (ret)
1294                         return ret;
1295         }
1296
1297         return ret;
1298 }
1299
1300 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1301 {
1302         int ret = 0, i = 0;
1303         uint32_t min_freq, max_freq;
1304         enum smu_clk_type clk_type;
1305
1306         struct clk_feature_map {
1307                 enum smu_clk_type clk_type;
1308                 uint32_t        feature;
1309         } clk_feature_map[] = {
1310                 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1311                 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1312                 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1313                 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1314         };
1315
1316         for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1317
1318                 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1319                     continue;
1320
1321                 clk_type = clk_feature_map[i].clk_type;
1322
1323                 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1324
1325                 if (ret)
1326                         return ret;
1327
1328                 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1329
1330                 if (ret)
1331                         return ret;
1332         }
1333
1334         return ret;
1335 }
1336
1337 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1338 {
1339         int ret = 0;
1340         uint32_t socclk_freq = 0, fclk_freq = 0;
1341         uint32_t vclk_freq = 0, dclk_freq = 0;
1342
1343         ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1344         if (ret)
1345                 return ret;
1346
1347         ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1348         if (ret)
1349                 return ret;
1350
1351         ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1352         if (ret)
1353                 return ret;
1354
1355         ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1356         if (ret)
1357                 return ret;
1358
1359         ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1360         if (ret)
1361                 return ret;
1362
1363         ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1364         if (ret)
1365                 return ret;
1366
1367         ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1368         if (ret)
1369                 return ret;
1370
1371         ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1372         if (ret)
1373                 return ret;
1374
1375         return ret;
1376 }
1377
1378 static int vangogh_set_performance_level(struct smu_context *smu,
1379                                         enum amd_dpm_forced_level level)
1380 {
1381         int ret = 0;
1382         uint32_t soc_mask, mclk_mask, fclk_mask;
1383         uint32_t vclk_mask = 0, dclk_mask = 0;
1384
1385         switch (level) {
1386         case AMD_DPM_FORCED_LEVEL_HIGH:
1387                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1388                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1389
1390                 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1391                 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1392
1393                 ret = vangogh_force_dpm_limit_value(smu, true);
1394                 break;
1395         case AMD_DPM_FORCED_LEVEL_LOW:
1396                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1397                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1398
1399                 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1400                 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1401
1402                 ret = vangogh_force_dpm_limit_value(smu, false);
1403                 break;
1404         case AMD_DPM_FORCED_LEVEL_AUTO:
1405                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1406                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1407
1408                 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1409                 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1410
1411                 ret = vangogh_unforce_dpm_levels(smu);
1412                 break;
1413         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1414                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1415                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1416
1417                 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1418                 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1419
1420                 ret = smu_cmn_send_smc_msg_with_param(smu,
1421                                         SMU_MSG_SetHardMinGfxClk,
1422                                         VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
1423                 if (ret)
1424                         return ret;
1425
1426                 ret = smu_cmn_send_smc_msg_with_param(smu,
1427                                         SMU_MSG_SetSoftMaxGfxClk,
1428                                         VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
1429                 if (ret)
1430                         return ret;
1431
1432                 ret = vangogh_get_profiling_clk_mask(smu, level,
1433                                                         &vclk_mask,
1434                                                         &dclk_mask,
1435                                                         &mclk_mask,
1436                                                         &fclk_mask,
1437                                                         &soc_mask);
1438                 if (ret)
1439                         return ret;
1440
1441                 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1442                 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1443                 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1444                 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1445
1446                 break;
1447         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1448                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1449                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1450
1451                 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1452                 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1453
1454                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn,
1455                                                                 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
1456                 if (ret)
1457                         return ret;
1458
1459                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn,
1460                                                                 VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
1461                 if (ret)
1462                         return ret;
1463                 break;
1464         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1465                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1466                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1467
1468                 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1469                 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1470
1471                 ret = vangogh_get_profiling_clk_mask(smu, level,
1472                                                         NULL,
1473                                                         NULL,
1474                                                         &mclk_mask,
1475                                                         &fclk_mask,
1476                                                         NULL);
1477                 if (ret)
1478                         return ret;
1479
1480                 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1481                 break;
1482         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1483                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1484                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1485
1486                 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1487                 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1488
1489                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1490                                 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
1491                 if (ret)
1492                         return ret;
1493
1494                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1495                                 VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
1496                 if (ret)
1497                         return ret;
1498
1499                 ret = vangogh_set_peak_clock_by_device(smu);
1500                 break;
1501         case AMD_DPM_FORCED_LEVEL_MANUAL:
1502         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1503         default:
1504                 break;
1505         }
1506         return ret;
1507 }
1508
1509 static int vangogh_read_sensor(struct smu_context *smu,
1510                                  enum amd_pp_sensors sensor,
1511                                  void *data, uint32_t *size)
1512 {
1513         int ret = 0;
1514
1515         if (!data || !size)
1516                 return -EINVAL;
1517
1518         mutex_lock(&smu->sensor_lock);
1519         switch (sensor) {
1520         case AMDGPU_PP_SENSOR_GPU_LOAD:
1521                 ret = vangogh_common_get_smu_metrics_data(smu,
1522                                                    METRICS_AVERAGE_GFXACTIVITY,
1523                                                    (uint32_t *)data);
1524                 *size = 4;
1525                 break;
1526         case AMDGPU_PP_SENSOR_GPU_POWER:
1527                 ret = vangogh_common_get_smu_metrics_data(smu,
1528                                                    METRICS_AVERAGE_SOCKETPOWER,
1529                                                    (uint32_t *)data);
1530                 *size = 4;
1531                 break;
1532         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1533                 ret = vangogh_common_get_smu_metrics_data(smu,
1534                                                    METRICS_TEMPERATURE_EDGE,
1535                                                    (uint32_t *)data);
1536                 *size = 4;
1537                 break;
1538         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1539                 ret = vangogh_common_get_smu_metrics_data(smu,
1540                                                    METRICS_TEMPERATURE_HOTSPOT,
1541                                                    (uint32_t *)data);
1542                 *size = 4;
1543                 break;
1544         case AMDGPU_PP_SENSOR_GFX_MCLK:
1545                 ret = vangogh_common_get_smu_metrics_data(smu,
1546                                                    METRICS_CURR_UCLK,
1547                                                    (uint32_t *)data);
1548                 *(uint32_t *)data *= 100;
1549                 *size = 4;
1550                 break;
1551         case AMDGPU_PP_SENSOR_GFX_SCLK:
1552                 ret = vangogh_common_get_smu_metrics_data(smu,
1553                                                    METRICS_CURR_GFXCLK,
1554                                                    (uint32_t *)data);
1555                 *(uint32_t *)data *= 100;
1556                 *size = 4;
1557                 break;
1558         case AMDGPU_PP_SENSOR_VDDGFX:
1559                 ret = vangogh_common_get_smu_metrics_data(smu,
1560                                                    METRICS_VOLTAGE_VDDGFX,
1561                                                    (uint32_t *)data);
1562                 *size = 4;
1563                 break;
1564         case AMDGPU_PP_SENSOR_VDDNB:
1565                 ret = vangogh_common_get_smu_metrics_data(smu,
1566                                                    METRICS_VOLTAGE_VDDSOC,
1567                                                    (uint32_t *)data);
1568                 *size = 4;
1569                 break;
1570         case AMDGPU_PP_SENSOR_CPU_CLK:
1571                 ret = vangogh_common_get_smu_metrics_data(smu,
1572                                                    METRICS_AVERAGE_CPUCLK,
1573                                                    (uint32_t *)data);
1574                 *size = smu->cpu_core_num * sizeof(uint16_t);
1575                 break;
1576         default:
1577                 ret = -EOPNOTSUPP;
1578                 break;
1579         }
1580         mutex_unlock(&smu->sensor_lock);
1581
1582         return ret;
1583 }
1584
1585 static int vangogh_set_watermarks_table(struct smu_context *smu,
1586                                        struct pp_smu_wm_range_sets *clock_ranges)
1587 {
1588         int i;
1589         int ret = 0;
1590         Watermarks_t *table = smu->smu_table.watermarks_table;
1591
1592         if (!table || !clock_ranges)
1593                 return -EINVAL;
1594
1595         if (clock_ranges) {
1596                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1597                         clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1598                         return -EINVAL;
1599
1600                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1601                         table->WatermarkRow[WM_DCFCLK][i].MinClock =
1602                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1603                         table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1604                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1605                         table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1606                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1607                         table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1608                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1609
1610                         table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1611                                 clock_ranges->reader_wm_sets[i].wm_inst;
1612                 }
1613
1614                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1615                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1616                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1617                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1618                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1619                         table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1620                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1621                         table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1622                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1623
1624                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1625                                 clock_ranges->writer_wm_sets[i].wm_inst;
1626                 }
1627
1628                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1629         }
1630
1631         /* pass data to smu controller */
1632         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1633              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1634                 ret = smu_cmn_write_watermarks_table(smu);
1635                 if (ret) {
1636                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1637                         return ret;
1638                 }
1639                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1640         }
1641
1642         return 0;
1643 }
1644
1645 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1646                                       void **table)
1647 {
1648         struct smu_table_context *smu_table = &smu->smu_table;
1649         struct gpu_metrics_v2_2 *gpu_metrics =
1650                 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1651         SmuMetrics_legacy_t metrics;
1652         int ret = 0;
1653
1654         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1655         if (ret)
1656                 return ret;
1657
1658         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1659
1660         gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1661         gpu_metrics->temperature_soc = metrics.SocTemperature;
1662         memcpy(&gpu_metrics->temperature_core[0],
1663                 &metrics.CoreTemperature[0],
1664                 sizeof(uint16_t) * 4);
1665         gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1666
1667         gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1668         gpu_metrics->average_mm_activity = metrics.UvdActivity;
1669
1670         gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1671         gpu_metrics->average_cpu_power = metrics.Power[0];
1672         gpu_metrics->average_soc_power = metrics.Power[1];
1673         gpu_metrics->average_gfx_power = metrics.Power[2];
1674         memcpy(&gpu_metrics->average_core_power[0],
1675                 &metrics.CorePower[0],
1676                 sizeof(uint16_t) * 4);
1677
1678         gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1679         gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1680         gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1681         gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1682         gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1683         gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1684
1685         memcpy(&gpu_metrics->current_coreclk[0],
1686                 &metrics.CoreFrequency[0],
1687                 sizeof(uint16_t) * 4);
1688         gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1689
1690         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1691         gpu_metrics->indep_throttle_status =
1692                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1693                                                            vangogh_throttler_map);
1694
1695         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1696
1697         *table = (void *)gpu_metrics;
1698
1699         return sizeof(struct gpu_metrics_v2_2);
1700 }
1701
1702 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1703                                       void **table)
1704 {
1705         struct smu_table_context *smu_table = &smu->smu_table;
1706         struct gpu_metrics_v2_2 *gpu_metrics =
1707                 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1708         SmuMetrics_t metrics;
1709         int ret = 0;
1710
1711         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1712         if (ret)
1713                 return ret;
1714
1715         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1716
1717         gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1718         gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1719         memcpy(&gpu_metrics->temperature_core[0],
1720                 &metrics.Current.CoreTemperature[0],
1721                 sizeof(uint16_t) * 4);
1722         gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1723
1724         gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1725         gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1726
1727         gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1728         gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1729         gpu_metrics->average_soc_power = metrics.Current.Power[1];
1730         gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1731         memcpy(&gpu_metrics->average_core_power[0],
1732                 &metrics.Average.CorePower[0],
1733                 sizeof(uint16_t) * 4);
1734
1735         gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1736         gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1737         gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1738         gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1739         gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1740         gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1741
1742         gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1743         gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1744         gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1745         gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1746         gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1747         gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1748
1749         memcpy(&gpu_metrics->current_coreclk[0],
1750                 &metrics.Current.CoreFrequency[0],
1751                 sizeof(uint16_t) * 4);
1752         gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1753
1754         gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1755         gpu_metrics->indep_throttle_status =
1756                         smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1757                                                            vangogh_throttler_map);
1758
1759         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1760
1761         *table = (void *)gpu_metrics;
1762
1763         return sizeof(struct gpu_metrics_v2_2);
1764 }
1765
1766 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1767                                       void **table)
1768 {
1769         struct amdgpu_device *adev = smu->adev;
1770         uint32_t if_version;
1771         int ret = 0;
1772
1773         ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
1774         if (ret) {
1775                 dev_err(adev->dev, "Failed to get smu if version!\n");
1776                 return ret;
1777         }
1778
1779         if (if_version < 0x3)
1780                 ret = vangogh_get_legacy_gpu_metrics(smu, table);
1781         else
1782                 ret = vangogh_get_gpu_metrics(smu, table);
1783
1784         return ret;
1785 }
1786
1787 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1788                                         long input[], uint32_t size)
1789 {
1790         int ret = 0;
1791         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1792
1793         if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
1794                 dev_warn(smu->adev->dev,
1795                         "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
1796                 return -EINVAL;
1797         }
1798
1799         switch (type) {
1800         case PP_OD_EDIT_CCLK_VDDC_TABLE:
1801                 if (size != 3) {
1802                         dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
1803                         return -EINVAL;
1804                 }
1805                 if (input[0] >= smu->cpu_core_num) {
1806                         dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
1807                                 smu->cpu_core_num);
1808                 }
1809                 smu->cpu_core_id_select = input[0];
1810                 if (input[1] == 0) {
1811                         if (input[2] < smu->cpu_default_soft_min_freq) {
1812                                 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1813                                         input[2], smu->cpu_default_soft_min_freq);
1814                                 return -EINVAL;
1815                         }
1816                         smu->cpu_actual_soft_min_freq = input[2];
1817                 } else if (input[1] == 1) {
1818                         if (input[2] > smu->cpu_default_soft_max_freq) {
1819                                 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1820                                         input[2], smu->cpu_default_soft_max_freq);
1821                                 return -EINVAL;
1822                         }
1823                         smu->cpu_actual_soft_max_freq = input[2];
1824                 } else {
1825                         return -EINVAL;
1826                 }
1827                 break;
1828         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1829                 if (size != 2) {
1830                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1831                         return -EINVAL;
1832                 }
1833
1834                 if (input[0] == 0) {
1835                         if (input[1] < smu->gfx_default_hard_min_freq) {
1836                                 dev_warn(smu->adev->dev,
1837                                         "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1838                                         input[1], smu->gfx_default_hard_min_freq);
1839                                 return -EINVAL;
1840                         }
1841                         smu->gfx_actual_hard_min_freq = input[1];
1842                 } else if (input[0] == 1) {
1843                         if (input[1] > smu->gfx_default_soft_max_freq) {
1844                                 dev_warn(smu->adev->dev,
1845                                         "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1846                                         input[1], smu->gfx_default_soft_max_freq);
1847                                 return -EINVAL;
1848                         }
1849                         smu->gfx_actual_soft_max_freq = input[1];
1850                 } else {
1851                         return -EINVAL;
1852                 }
1853                 break;
1854         case PP_OD_RESTORE_DEFAULT_TABLE:
1855                 if (size != 0) {
1856                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1857                         return -EINVAL;
1858                 } else {
1859                         smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1860                         smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1861                         smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1862                         smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1863                 }
1864                 break;
1865         case PP_OD_COMMIT_DPM_TABLE:
1866                 if (size != 0) {
1867                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1868                         return -EINVAL;
1869                 } else {
1870                         if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1871                                 dev_err(smu->adev->dev,
1872                                         "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1873                                         smu->gfx_actual_hard_min_freq,
1874                                         smu->gfx_actual_soft_max_freq);
1875                                 return -EINVAL;
1876                         }
1877
1878                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1879                                                                         smu->gfx_actual_hard_min_freq, NULL);
1880                         if (ret) {
1881                                 dev_err(smu->adev->dev, "Set hard min sclk failed!");
1882                                 return ret;
1883                         }
1884
1885                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1886                                                                         smu->gfx_actual_soft_max_freq, NULL);
1887                         if (ret) {
1888                                 dev_err(smu->adev->dev, "Set soft max sclk failed!");
1889                                 return ret;
1890                         }
1891
1892                         if (smu->adev->pm.fw_version < 0x43f1b00) {
1893                                 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
1894                                 break;
1895                         }
1896
1897                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1898                                                               ((smu->cpu_core_id_select << 20)
1899                                                                | smu->cpu_actual_soft_min_freq),
1900                                                               NULL);
1901                         if (ret) {
1902                                 dev_err(smu->adev->dev, "Set hard min cclk failed!");
1903                                 return ret;
1904                         }
1905
1906                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1907                                                               ((smu->cpu_core_id_select << 20)
1908                                                                | smu->cpu_actual_soft_max_freq),
1909                                                               NULL);
1910                         if (ret) {
1911                                 dev_err(smu->adev->dev, "Set soft max cclk failed!");
1912                                 return ret;
1913                         }
1914                 }
1915                 break;
1916         default:
1917                 return -ENOSYS;
1918         }
1919
1920         return ret;
1921 }
1922
1923 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
1924 {
1925         struct smu_table_context *smu_table = &smu->smu_table;
1926
1927         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
1928 }
1929
1930 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1931 {
1932         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1933
1934         smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1935         smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1936         smu->gfx_actual_hard_min_freq = 0;
1937         smu->gfx_actual_soft_max_freq = 0;
1938
1939         smu->cpu_default_soft_min_freq = 1400;
1940         smu->cpu_default_soft_max_freq = 3500;
1941         smu->cpu_actual_soft_min_freq = 0;
1942         smu->cpu_actual_soft_max_freq = 0;
1943
1944         return 0;
1945 }
1946
1947 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
1948 {
1949         DpmClocks_t *table = smu->smu_table.clocks_table;
1950         int i;
1951
1952         if (!clock_table || !table)
1953                 return -EINVAL;
1954
1955         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
1956                 clock_table->SocClocks[i].Freq = table->SocClocks[i];
1957                 clock_table->SocClocks[i].Vol = table->SocVoltage[i];
1958         }
1959
1960         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1961                 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
1962                 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
1963         }
1964
1965         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1966                 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
1967                 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
1968         }
1969
1970         return 0;
1971 }
1972
1973
1974 static int vangogh_system_features_control(struct smu_context *smu, bool en)
1975 {
1976         struct amdgpu_device *adev = smu->adev;
1977         struct smu_feature *feature = &smu->smu_feature;
1978         uint32_t feature_mask[2];
1979         int ret = 0;
1980
1981         if (adev->pm.fw_version >= 0x43f1700 && !en)
1982                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
1983                                                       RLC_STATUS_OFF, NULL);
1984
1985         bitmap_zero(feature->enabled, feature->feature_num);
1986         bitmap_zero(feature->supported, feature->feature_num);
1987
1988         if (!en)
1989                 return ret;
1990
1991         ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
1992         if (ret)
1993                 return ret;
1994
1995         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
1996                     feature->feature_num);
1997         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
1998                     feature->feature_num);
1999
2000         return 0;
2001 }
2002
2003 static int vangogh_post_smu_init(struct smu_context *smu)
2004 {
2005         struct amdgpu_device *adev = smu->adev;
2006         uint32_t tmp;
2007         int ret = 0;
2008         uint8_t aon_bits = 0;
2009         /* Two CUs in one WGP */
2010         uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2011         uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2012                 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2013
2014         /* allow message will be sent after enable message on Vangogh*/
2015         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2016                         (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2017                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2018                 if (ret) {
2019                         dev_err(adev->dev, "Failed to Enable GfxOff!\n");
2020                         return ret;
2021                 }
2022         } else {
2023                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2024                 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2025         }
2026
2027         /* if all CUs are active, no need to power off any WGPs */
2028         if (total_cu == adev->gfx.cu_info.number)
2029                 return 0;
2030
2031         /*
2032          * Calculate the total bits number of always on WGPs for all SA/SEs in
2033          * RLC_PG_ALWAYS_ON_WGP_MASK.
2034          */
2035         tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2036         tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2037
2038         aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2039
2040         /* Do not request any WGPs less than set in the AON_WGP_MASK */
2041         if (aon_bits > req_active_wgps) {
2042                 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2043                 return 0;
2044         } else {
2045                 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2046         }
2047 }
2048
2049 static int vangogh_mode_reset(struct smu_context *smu, int type)
2050 {
2051         int ret = 0, index = 0;
2052
2053         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2054                                                SMU_MSG_GfxDeviceDriverReset);
2055         if (index < 0)
2056                 return index == -EACCES ? 0 : index;
2057
2058         mutex_lock(&smu->message_lock);
2059
2060         ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
2061
2062         mutex_unlock(&smu->message_lock);
2063
2064         mdelay(10);
2065
2066         return ret;
2067 }
2068
2069 static int vangogh_mode2_reset(struct smu_context *smu)
2070 {
2071         return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2072 }
2073
2074 static int vangogh_get_power_limit(struct smu_context *smu,
2075                                    uint32_t *current_power_limit,
2076                                    uint32_t *default_power_limit,
2077                                    uint32_t *max_power_limit)
2078 {
2079         struct smu_11_5_power_context *power_context =
2080                                                                 smu->smu_power.power_context;
2081         uint32_t ppt_limit;
2082         int ret = 0;
2083
2084         if (smu->adev->pm.fw_version < 0x43f1e00)
2085                 return ret;
2086
2087         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2088         if (ret) {
2089                 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2090                 return ret;
2091         }
2092         /* convert from milliwatt to watt */
2093         if (current_power_limit)
2094                 *current_power_limit = ppt_limit / 1000;
2095         if (default_power_limit)
2096                 *default_power_limit = ppt_limit / 1000;
2097         if (max_power_limit)
2098                 *max_power_limit = 29;
2099
2100         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2101         if (ret) {
2102                 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2103                 return ret;
2104         }
2105         /* convert from milliwatt to watt */
2106         power_context->current_fast_ppt_limit =
2107                         power_context->default_fast_ppt_limit = ppt_limit / 1000;
2108         power_context->max_fast_ppt_limit = 30;
2109
2110         return ret;
2111 }
2112
2113 static int vangogh_get_ppt_limit(struct smu_context *smu,
2114                                                                 uint32_t *ppt_limit,
2115                                                                 enum smu_ppt_limit_type type,
2116                                                                 enum smu_ppt_limit_level level)
2117 {
2118         struct smu_11_5_power_context *power_context =
2119                                                         smu->smu_power.power_context;
2120
2121         if (!power_context)
2122                 return -EOPNOTSUPP;
2123
2124         if (type == SMU_FAST_PPT_LIMIT) {
2125                 switch (level) {
2126                 case SMU_PPT_LIMIT_MAX:
2127                         *ppt_limit = power_context->max_fast_ppt_limit;
2128                         break;
2129                 case SMU_PPT_LIMIT_CURRENT:
2130                         *ppt_limit = power_context->current_fast_ppt_limit;
2131                         break;
2132                 case SMU_PPT_LIMIT_DEFAULT:
2133                         *ppt_limit = power_context->default_fast_ppt_limit;
2134                         break;
2135                 default:
2136                         break;
2137                 }
2138         }
2139
2140         return 0;
2141 }
2142
2143 static int vangogh_set_power_limit(struct smu_context *smu, uint32_t ppt_limit)
2144 {
2145         struct smu_11_5_power_context *power_context =
2146                                                         smu->smu_power.power_context;
2147         uint32_t limit_type = ppt_limit >> 24;
2148         int ret = 0;
2149
2150         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2151                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2152                 return -EOPNOTSUPP;
2153         }
2154
2155         switch (limit_type) {
2156         case SMU_DEFAULT_PPT_LIMIT:
2157                 ret = smu_cmn_send_smc_msg_with_param(smu,
2158                                 SMU_MSG_SetSlowPPTLimit,
2159                                 ppt_limit * 1000, /* convert from watt to milliwatt */
2160                                 NULL);
2161                 if (ret)
2162                         return ret;
2163
2164                 smu->current_power_limit = ppt_limit;
2165                 break;
2166         case SMU_FAST_PPT_LIMIT:
2167                 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2168                 if (ppt_limit > power_context->max_fast_ppt_limit) {
2169                         dev_err(smu->adev->dev,
2170                                 "New power limit (%d) is over the max allowed %d\n",
2171                                 ppt_limit, power_context->max_fast_ppt_limit);
2172                         return ret;
2173                 }
2174
2175                 ret = smu_cmn_send_smc_msg_with_param(smu,
2176                                 SMU_MSG_SetFastPPTLimit,
2177                                 ppt_limit * 1000, /* convert from watt to milliwatt */
2178                                 NULL);
2179                 if (ret)
2180                         return ret;
2181
2182                 power_context->current_fast_ppt_limit = ppt_limit;
2183                 break;
2184         default:
2185                 return -EINVAL;
2186         }
2187
2188         return ret;
2189 }
2190
2191 static const struct pptable_funcs vangogh_ppt_funcs = {
2192
2193         .check_fw_status = smu_v11_0_check_fw_status,
2194         .check_fw_version = smu_v11_0_check_fw_version,
2195         .init_smc_tables = vangogh_init_smc_tables,
2196         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2197         .init_power = smu_v11_0_init_power,
2198         .fini_power = smu_v11_0_fini_power,
2199         .register_irq_handler = smu_v11_0_register_irq_handler,
2200         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2201         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2202         .send_smc_msg = smu_cmn_send_smc_msg,
2203         .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2204         .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2205         .is_dpm_running = vangogh_is_dpm_running,
2206         .read_sensor = vangogh_read_sensor,
2207         .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
2208         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2209         .set_watermarks_table = vangogh_set_watermarks_table,
2210         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2211         .interrupt_work = smu_v11_0_interrupt_work,
2212         .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2213         .od_edit_dpm_table = vangogh_od_edit_dpm_table,
2214         .print_clk_levels = vangogh_common_print_clk_levels,
2215         .set_default_dpm_table = vangogh_set_default_dpm_tables,
2216         .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2217         .system_features_control = vangogh_system_features_control,
2218         .feature_is_enabled = smu_cmn_feature_is_enabled,
2219         .set_power_profile_mode = vangogh_set_power_profile_mode,
2220         .get_power_profile_mode = vangogh_get_power_profile_mode,
2221         .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2222         .force_clk_levels = vangogh_force_clk_levels,
2223         .set_performance_level = vangogh_set_performance_level,
2224         .post_init = vangogh_post_smu_init,
2225         .mode2_reset = vangogh_mode2_reset,
2226         .gfx_off_control = smu_v11_0_gfx_off_control,
2227         .get_ppt_limit = vangogh_get_ppt_limit,
2228         .get_power_limit = vangogh_get_power_limit,
2229         .set_power_limit = vangogh_set_power_limit,
2230         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2231 };
2232
2233 void vangogh_set_ppt_funcs(struct smu_context *smu)
2234 {
2235         smu->ppt_funcs = &vangogh_ppt_funcs;
2236         smu->message_map = vangogh_message_map;
2237         smu->feature_map = vangogh_feature_mask_map;
2238         smu->table_map = vangogh_table_map;
2239         smu->workload_map = vangogh_workload_map;
2240         smu->is_apu = true;
2241 }