drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "soc15_common.h"
  35 #include "smu_v11_0.h"
  36 #include "smu11_driver_if_navi10.h"
  37 #include "atom.h"
  38 #include "navi10_ppt.h"
  39 #include "smu_v11_0_pptable.h"
  40 #include "smu_v11_0_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45
  46 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  47 #include "smu_cmn.h"
  48 #include "smu_11_0_cdr_table.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define FEATURE_MASK(feature) (1ULL << feature)
  63 #define SMC_DPM_FEATURE ( \
  64         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  65         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  66         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  69         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  72
  73 #define SMU_11_0_GFX_BUSY_THRESHOLD 15
  74
  75 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  76         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  77         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  78         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  79         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,    0),
  80         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,   0),
  81         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,         0),
  82         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,        0),
  83         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,         0),
  84         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,        0),
  85         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,        0),
  86         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,       0),
  87         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow,     1),
  88         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh,    1),
  89         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,              1),
  90         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                  0),
  91         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        0),
  92         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         0),
  93         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,         0),
  94         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,          0),
  95         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        0),
  96         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        0),
  97         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,            0),
  98         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable,             0),
  99         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc,                       0),
 100         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                    0),
 101         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,             0),
 102         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,             0),
 103         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,             1),
 104         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,             0),
 105         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,                1),
 106         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,                1),
 107         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,            1),
 108         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig,       0),
 109         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,                0),
 110         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,        0),
 111         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,         0),
 112         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,       0),
 113         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk,       0),
 114         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,        0),
 115         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,            0),
 116         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,            0),
 117         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                  0),
 118         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,          1),
 119         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,       0),
 120         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,        0),
 121         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,           0),
 122         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt,             0),
 123         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays,                0),
 124         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
 125         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow,  0),
 126         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                  0),
 127         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,               0),
 128         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                  0),
 129         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,          1),
 130         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData,                 0),
 131         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                     0),
 132         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset,           0),
 133         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown,        0),
 134         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   0),
 135         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 0),
 136         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  0),
 137         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                0),
 138         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,               0),
 139         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                        0),
 140         MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange,  0),
 141         MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange,   0),
 142         MSG_MAP(GetVoltageByDpm,                PPSMC_MSG_GetVoltageByDpm,              0),
 143         MSG_MAP(GetVoltageByDpmOverdrive,       PPSMC_MSG_GetVoltageByDpmOverdrive,     0),
 144         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,      0),
 145         MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
 146         MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
 147         MSG_MAP(GET_UMC_FW_WA,                  PPSMC_MSG_GetUMCFWWA,                   0),
 148 };
 149
 150 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 151         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 152         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 153         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 154         CLK_MAP(FCLK, PPCLK_SOCCLK),
 155         CLK_MAP(UCLK, PPCLK_UCLK),
 156         CLK_MAP(MCLK, PPCLK_UCLK),
 157         CLK_MAP(DCLK, PPCLK_DCLK),
 158         CLK_MAP(VCLK, PPCLK_VCLK),
 159         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 160         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 161         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 162         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 163 };
 164
 165 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 166         FEA_MAP(DPM_PREFETCHER),
 167         FEA_MAP(DPM_GFXCLK),
 168         FEA_MAP(DPM_GFX_PACE),
 169         FEA_MAP(DPM_UCLK),
 170         FEA_MAP(DPM_SOCCLK),
 171         FEA_MAP(DPM_MP0CLK),
 172         FEA_MAP(DPM_LINK),
 173         FEA_MAP(DPM_DCEFCLK),
 174         FEA_MAP(MEM_VDDCI_SCALING),
 175         FEA_MAP(MEM_MVDD_SCALING),
 176         FEA_MAP(DS_GFXCLK),
 177         FEA_MAP(DS_SOCCLK),
 178         FEA_MAP(DS_LCLK),
 179         FEA_MAP(DS_DCEFCLK),
 180         FEA_MAP(DS_UCLK),
 181         FEA_MAP(GFX_ULV),
 182         FEA_MAP(FW_DSTATE),
 183         FEA_MAP(GFXOFF),
 184         FEA_MAP(BACO),
 185         FEA_MAP(VCN_PG),
 186         FEA_MAP(JPEG_PG),
 187         FEA_MAP(USB_PG),
 188         FEA_MAP(RSMU_SMN_CG),
 189         FEA_MAP(PPT),
 190         FEA_MAP(TDC),
 191         FEA_MAP(GFX_EDC),
 192         FEA_MAP(APCC_PLUS),
 193         FEA_MAP(GTHR),
 194         FEA_MAP(ACDC),
 195         FEA_MAP(VR0HOT),
 196         FEA_MAP(VR1HOT),
 197         FEA_MAP(FW_CTF),
 198         FEA_MAP(FAN_CONTROL),
 199         FEA_MAP(THERMAL),
 200         FEA_MAP(GFX_DCS),
 201         FEA_MAP(RM),
 202         FEA_MAP(LED_DISPLAY),
 203         FEA_MAP(GFX_SS),
 204         FEA_MAP(OUT_OF_BAND_MONITOR),
 205         FEA_MAP(TEMP_DEPENDENT_VMIN),
 206         FEA_MAP(MMHUB_PG),
 207         FEA_MAP(ATHUB_PG),
 208         FEA_MAP(APCC_DFLL),
 209 };
 210
 211 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 212         TAB_MAP(PPTABLE),
 213         TAB_MAP(WATERMARKS),
 214         TAB_MAP(AVFS),
 215         TAB_MAP(AVFS_PSM_DEBUG),
 216         TAB_MAP(AVFS_FUSE_OVERRIDE),
 217         TAB_MAP(PMSTATUSLOG),
 218         TAB_MAP(SMU_METRICS),
 219         TAB_MAP(DRIVER_SMU_CONFIG),
 220         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 221         TAB_MAP(OVERDRIVE),
 222         TAB_MAP(I2C_COMMANDS),
 223         TAB_MAP(PACE),
 224 };
 225
 226 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 227         PWR_MAP(AC),
 228         PWR_MAP(DC),
 229 };
 230
 231 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 232         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 233         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 234         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 235         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 236         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 237         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 238         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 239 };
 240
 241 static const uint8_t navi1x_throttler_map[] = {
 242         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 243         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 244         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 245         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 246         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 247         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 248         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 249         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 250         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 251         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 252         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 253         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 254         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 255         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 256         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 257         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 258         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 259         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 260 };
 261
 262
 263 static bool is_asic_secure(struct smu_context *smu)
 264 {
 265         struct amdgpu_device *adev = smu->adev;
 266         bool is_secure = true;
 267         uint32_t mp0_fw_intf;
 268
 269         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 270                                    (smnMP0_FW_INTF & 0xffffffff));
 271
 272         if (!(mp0_fw_intf & (1 << 19)))
 273                 is_secure = false;
 274
 275         return is_secure;
 276 }
 277
 278 static int
 279 navi10_get_allowed_feature_mask(struct smu_context *smu,
 280                                   uint32_t *feature_mask, uint32_t num)
 281 {
 282         struct amdgpu_device *adev = smu->adev;
 283
 284         if (num > 2)
 285                 return -EINVAL;
 286
 287         memset(feature_mask, 0, sizeof(uint32_t) * num);
 288
 289         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 290                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 291                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 292                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 293                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 294                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 295                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 296                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 297                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 298                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 299                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 300                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 301                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 302                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 303                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 304                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 305                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 306                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 307                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 308                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 309
 310         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 311                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 312
 313         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 314                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 315
 316         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 317                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 318
 319         if (adev->pm.pp_feature & PP_ULV_MASK)
 320                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 321
 322         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 323                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 324
 325         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 326                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 327
 328         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 329                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 330
 331         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 332                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 333
 334         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 335                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 336
 337         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 338                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 339
 340         if (smu->dc_controlled_by_gpio)
 341                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 342
 343         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 344                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 345
 346         /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
 347         if (!(is_asic_secure(smu) &&
 348              (adev->asic_type == CHIP_NAVI10) &&
 349              (adev->rev_id == 0)) &&
 350             (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
 351                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 352                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 353                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 354
 355         /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
 356         if (is_asic_secure(smu) &&
 357             (adev->asic_type == CHIP_NAVI10) &&
 358             (adev->rev_id == 0))
 359                 *(uint64_t *)feature_mask &=
 360                                 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 361
 362         return 0;
 363 }
 364
 365 static void navi10_check_bxco_support(struct smu_context *smu)
 366 {
 367         struct smu_table_context *table_context = &smu->smu_table;
 368         struct smu_11_0_powerplay_table *powerplay_table =
 369                 table_context->power_play_table;
 370         struct smu_baco_context *smu_baco = &smu->smu_baco;
 371         struct amdgpu_device *adev = smu->adev;
 372         uint32_t val;
 373
 374         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 375             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
 376                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 377                 smu_baco->platform_support =
 378                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 379                                                                         false;
 380         }
 381 }
 382
 383 static int navi10_check_powerplay_table(struct smu_context *smu)
 384 {
 385         struct smu_table_context *table_context = &smu->smu_table;
 386         struct smu_11_0_powerplay_table *powerplay_table =
 387                 table_context->power_play_table;
 388
 389         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
 390                 smu->dc_controlled_by_gpio = true;
 391
 392         navi10_check_bxco_support(smu);
 393
 394         table_context->thermal_controller_type =
 395                 powerplay_table->thermal_controller_type;
 396
 397         /*
 398          * Instead of having its own buffer space and get overdrive_table copied,
 399          * smu->od_settings just points to the actual overdrive_table
 400          */
 401         smu->od_settings = &powerplay_table->overdrive_table;
 402
 403         return 0;
 404 }
 405
 406 static int navi10_append_powerplay_table(struct smu_context *smu)
 407 {
 408         struct amdgpu_device *adev = smu->adev;
 409         struct smu_table_context *table_context = &smu->smu_table;
 410         PPTable_t *smc_pptable = table_context->driver_pptable;
 411         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 412         struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
 413         int index, ret;
 414
 415         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 416                                            smc_dpm_info);
 417
 418         ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
 419                                       (uint8_t **)&smc_dpm_table);
 420         if (ret)
 421                 return ret;
 422
 423         dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 424                         smc_dpm_table->table_header.format_revision,
 425                         smc_dpm_table->table_header.content_revision);
 426
 427         if (smc_dpm_table->table_header.format_revision != 4) {
 428                 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
 429                 return -EINVAL;
 430         }
 431
 432         switch (smc_dpm_table->table_header.content_revision) {
 433         case 5: /* nv10 and nv14 */
 434                 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
 435                                     smc_dpm_table, I2cControllers);
 436                 break;
 437         case 7: /* nv12 */
 438                 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
 439                                               (uint8_t **)&smc_dpm_table_v4_7);
 440                 if (ret)
 441                         return ret;
 442                 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
 443                                     smc_dpm_table_v4_7, I2cControllers);
 444                 break;
 445         default:
 446                 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
 447                                 smc_dpm_table->table_header.content_revision);
 448                 return -EINVAL;
 449         }
 450
 451         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 452                 /* TODO: remove it once SMU fw fix it */
 453                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 454         }
 455
 456         return 0;
 457 }
 458
 459 static int navi10_store_powerplay_table(struct smu_context *smu)
 460 {
 461         struct smu_table_context *table_context = &smu->smu_table;
 462         struct smu_11_0_powerplay_table *powerplay_table =
 463                 table_context->power_play_table;
 464
 465         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 466                sizeof(PPTable_t));
 467
 468         return 0;
 469 }
 470
 471 static int navi10_setup_pptable(struct smu_context *smu)
 472 {
 473         int ret = 0;
 474
 475         ret = smu_v11_0_setup_pptable(smu);
 476         if (ret)
 477                 return ret;
 478
 479         ret = navi10_store_powerplay_table(smu);
 480         if (ret)
 481                 return ret;
 482
 483         ret = navi10_append_powerplay_table(smu);
 484         if (ret)
 485                 return ret;
 486
 487         ret = navi10_check_powerplay_table(smu);
 488         if (ret)
 489                 return ret;
 490
 491         return ret;
 492 }
 493
 494 static int navi10_tables_init(struct smu_context *smu)
 495 {
 496         struct smu_table_context *smu_table = &smu->smu_table;
 497         struct smu_table *tables = smu_table->tables;
 498
 499         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 500                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 501         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 502                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 503         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t),
 504                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 505         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 506                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 507         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 508                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 509         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 510                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 511         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 512                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 513                        AMDGPU_GEM_DOMAIN_VRAM);
 514
 515         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t),
 516                                            GFP_KERNEL);
 517         if (!smu_table->metrics_table)
 518                 goto err0_out;
 519         smu_table->metrics_time = 0;
 520
 521         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 522         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 523         if (!smu_table->gpu_metrics_table)
 524                 goto err1_out;
 525
 526         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 527         if (!smu_table->watermarks_table)
 528                 goto err2_out;
 529
 530         return 0;
 531
 532 err2_out:
 533         kfree(smu_table->gpu_metrics_table);
 534 err1_out:
 535         kfree(smu_table->metrics_table);
 536 err0_out:
 537         return -ENOMEM;
 538 }
 539
 540 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
 541                                               MetricsMember_t member,
 542                                               uint32_t *value)
 543 {
 544         struct smu_table_context *smu_table= &smu->smu_table;
 545         SmuMetrics_legacy_t *metrics =
 546                 (SmuMetrics_legacy_t *)smu_table->metrics_table;
 547         int ret = 0;
 548
 549         mutex_lock(&smu->metrics_lock);
 550
 551         ret = smu_cmn_get_metrics_table_locked(smu,
 552                                                NULL,
 553                                                false);
 554         if (ret) {
 555                 mutex_unlock(&smu->metrics_lock);
 556                 return ret;
 557         }
 558
 559         switch (member) {
 560         case METRICS_CURR_GFXCLK:
 561                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 562                 break;
 563         case METRICS_CURR_SOCCLK:
 564                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 565                 break;
 566         case METRICS_CURR_UCLK:
 567                 *value = metrics->CurrClock[PPCLK_UCLK];
 568                 break;
 569         case METRICS_CURR_VCLK:
 570                 *value = metrics->CurrClock[PPCLK_VCLK];
 571                 break;
 572         case METRICS_CURR_DCLK:
 573                 *value = metrics->CurrClock[PPCLK_DCLK];
 574                 break;
 575         case METRICS_CURR_DCEFCLK:
 576                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 577                 break;
 578         case METRICS_AVERAGE_GFXCLK:
 579                 *value = metrics->AverageGfxclkFrequency;
 580                 break;
 581         case METRICS_AVERAGE_SOCCLK:
 582                 *value = metrics->AverageSocclkFrequency;
 583                 break;
 584         case METRICS_AVERAGE_UCLK:
 585                 *value = metrics->AverageUclkFrequency;
 586                 break;
 587         case METRICS_AVERAGE_GFXACTIVITY:
 588                 *value = metrics->AverageGfxActivity;
 589                 break;
 590         case METRICS_AVERAGE_MEMACTIVITY:
 591                 *value = metrics->AverageUclkActivity;
 592                 break;
 593         case METRICS_AVERAGE_SOCKETPOWER:
 594                 *value = metrics->AverageSocketPower << 8;
 595                 break;
 596         case METRICS_TEMPERATURE_EDGE:
 597                 *value = metrics->TemperatureEdge *
 598                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 599                 break;
 600         case METRICS_TEMPERATURE_HOTSPOT:
 601                 *value = metrics->TemperatureHotspot *
 602                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 603                 break;
 604         case METRICS_TEMPERATURE_MEM:
 605                 *value = metrics->TemperatureMem *
 606                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 607                 break;
 608         case METRICS_TEMPERATURE_VRGFX:
 609                 *value = metrics->TemperatureVrGfx *
 610                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 611                 break;
 612         case METRICS_TEMPERATURE_VRSOC:
 613                 *value = metrics->TemperatureVrSoc *
 614                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 615                 break;
 616         case METRICS_THROTTLER_STATUS:
 617                 *value = metrics->ThrottlerStatus;
 618                 break;
 619         case METRICS_CURR_FANSPEED:
 620                 *value = metrics->CurrFanSpeed;
 621                 break;
 622         default:
 623                 *value = UINT_MAX;
 624                 break;
 625         }
 626
 627         mutex_unlock(&smu->metrics_lock);
 628
 629         return ret;
 630 }
 631
 632 static int navi10_get_smu_metrics_data(struct smu_context *smu,
 633                                        MetricsMember_t member,
 634                                        uint32_t *value)
 635 {
 636         struct smu_table_context *smu_table= &smu->smu_table;
 637         SmuMetrics_t *metrics =
 638                 (SmuMetrics_t *)smu_table->metrics_table;
 639         int ret = 0;
 640
 641         mutex_lock(&smu->metrics_lock);
 642
 643         ret = smu_cmn_get_metrics_table_locked(smu,
 644                                                NULL,
 645                                                false);
 646         if (ret) {
 647                 mutex_unlock(&smu->metrics_lock);
 648                 return ret;
 649         }
 650
 651         switch (member) {
 652         case METRICS_CURR_GFXCLK:
 653                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 654                 break;
 655         case METRICS_CURR_SOCCLK:
 656                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 657                 break;
 658         case METRICS_CURR_UCLK:
 659                 *value = metrics->CurrClock[PPCLK_UCLK];
 660                 break;
 661         case METRICS_CURR_VCLK:
 662                 *value = metrics->CurrClock[PPCLK_VCLK];
 663                 break;
 664         case METRICS_CURR_DCLK:
 665                 *value = metrics->CurrClock[PPCLK_DCLK];
 666                 break;
 667         case METRICS_CURR_DCEFCLK:
 668                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 669                 break;
 670         case METRICS_AVERAGE_GFXCLK:
 671                 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
 672                         *value = metrics->AverageGfxclkFrequencyPreDs;
 673                 else
 674                         *value = metrics->AverageGfxclkFrequencyPostDs;
 675                 break;
 676         case METRICS_AVERAGE_SOCCLK:
 677                 *value = metrics->AverageSocclkFrequency;
 678                 break;
 679         case METRICS_AVERAGE_UCLK:
 680                 *value = metrics->AverageUclkFrequencyPostDs;
 681                 break;
 682         case METRICS_AVERAGE_GFXACTIVITY:
 683                 *value = metrics->AverageGfxActivity;
 684                 break;
 685         case METRICS_AVERAGE_MEMACTIVITY:
 686                 *value = metrics->AverageUclkActivity;
 687                 break;
 688         case METRICS_AVERAGE_SOCKETPOWER:
 689                 *value = metrics->AverageSocketPower << 8;
 690                 break;
 691         case METRICS_TEMPERATURE_EDGE:
 692                 *value = metrics->TemperatureEdge *
 693                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 694                 break;
 695         case METRICS_TEMPERATURE_HOTSPOT:
 696                 *value = metrics->TemperatureHotspot *
 697                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 698                 break;
 699         case METRICS_TEMPERATURE_MEM:
 700                 *value = metrics->TemperatureMem *
 701                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 702                 break;
 703         case METRICS_TEMPERATURE_VRGFX:
 704                 *value = metrics->TemperatureVrGfx *
 705                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 706                 break;
 707         case METRICS_TEMPERATURE_VRSOC:
 708                 *value = metrics->TemperatureVrSoc *
 709                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 710                 break;
 711         case METRICS_THROTTLER_STATUS:
 712                 *value = metrics->ThrottlerStatus;
 713                 break;
 714         case METRICS_CURR_FANSPEED:
 715                 *value = metrics->CurrFanSpeed;
 716                 break;
 717         default:
 718                 *value = UINT_MAX;
 719                 break;
 720         }
 721
 722         mutex_unlock(&smu->metrics_lock);
 723
 724         return ret;
 725 }
 726
 727 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu,
 728                                               MetricsMember_t member,
 729                                               uint32_t *value)
 730 {
 731         struct smu_table_context *smu_table= &smu->smu_table;
 732         SmuMetrics_NV12_legacy_t *metrics =
 733                 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
 734         int ret = 0;
 735
 736         mutex_lock(&smu->metrics_lock);
 737
 738         ret = smu_cmn_get_metrics_table_locked(smu,
 739                                                NULL,
 740                                                false);
 741         if (ret) {
 742                 mutex_unlock(&smu->metrics_lock);
 743                 return ret;
 744         }
 745
 746         switch (member) {
 747         case METRICS_CURR_GFXCLK:
 748                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 749                 break;
 750         case METRICS_CURR_SOCCLK:
 751                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 752                 break;
 753         case METRICS_CURR_UCLK:
 754                 *value = metrics->CurrClock[PPCLK_UCLK];
 755                 break;
 756         case METRICS_CURR_VCLK:
 757                 *value = metrics->CurrClock[PPCLK_VCLK];
 758                 break;
 759         case METRICS_CURR_DCLK:
 760                 *value = metrics->CurrClock[PPCLK_DCLK];
 761                 break;
 762         case METRICS_CURR_DCEFCLK:
 763                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 764                 break;
 765         case METRICS_AVERAGE_GFXCLK:
 766                 *value = metrics->AverageGfxclkFrequency;
 767                 break;
 768         case METRICS_AVERAGE_SOCCLK:
 769                 *value = metrics->AverageSocclkFrequency;
 770                 break;
 771         case METRICS_AVERAGE_UCLK:
 772                 *value = metrics->AverageUclkFrequency;
 773                 break;
 774         case METRICS_AVERAGE_GFXACTIVITY:
 775                 *value = metrics->AverageGfxActivity;
 776                 break;
 777         case METRICS_AVERAGE_MEMACTIVITY:
 778                 *value = metrics->AverageUclkActivity;
 779                 break;
 780         case METRICS_AVERAGE_SOCKETPOWER:
 781                 *value = metrics->AverageSocketPower << 8;
 782                 break;
 783         case METRICS_TEMPERATURE_EDGE:
 784                 *value = metrics->TemperatureEdge *
 785                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 786                 break;
 787         case METRICS_TEMPERATURE_HOTSPOT:
 788                 *value = metrics->TemperatureHotspot *
 789                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 790                 break;
 791         case METRICS_TEMPERATURE_MEM:
 792                 *value = metrics->TemperatureMem *
 793                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 794                 break;
 795         case METRICS_TEMPERATURE_VRGFX:
 796                 *value = metrics->TemperatureVrGfx *
 797                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 798                 break;
 799         case METRICS_TEMPERATURE_VRSOC:
 800                 *value = metrics->TemperatureVrSoc *
 801                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 802                 break;
 803         case METRICS_THROTTLER_STATUS:
 804                 *value = metrics->ThrottlerStatus;
 805                 break;
 806         case METRICS_CURR_FANSPEED:
 807                 *value = metrics->CurrFanSpeed;
 808                 break;
 809         default:
 810                 *value = UINT_MAX;
 811                 break;
 812         }
 813
 814         mutex_unlock(&smu->metrics_lock);
 815
 816         return ret;
 817 }
 818
 819 static int navi12_get_smu_metrics_data(struct smu_context *smu,
 820                                        MetricsMember_t member,
 821                                        uint32_t *value)
 822 {
 823         struct smu_table_context *smu_table= &smu->smu_table;
 824         SmuMetrics_NV12_t *metrics =
 825                 (SmuMetrics_NV12_t *)smu_table->metrics_table;
 826         int ret = 0;
 827
 828         mutex_lock(&smu->metrics_lock);
 829
 830         ret = smu_cmn_get_metrics_table_locked(smu,
 831                                                NULL,
 832                                                false);
 833         if (ret) {
 834                 mutex_unlock(&smu->metrics_lock);
 835                 return ret;
 836         }
 837
 838         switch (member) {
 839         case METRICS_CURR_GFXCLK:
 840                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 841                 break;
 842         case METRICS_CURR_SOCCLK:
 843                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 844                 break;
 845         case METRICS_CURR_UCLK:
 846                 *value = metrics->CurrClock[PPCLK_UCLK];
 847                 break;
 848         case METRICS_CURR_VCLK:
 849                 *value = metrics->CurrClock[PPCLK_VCLK];
 850                 break;
 851         case METRICS_CURR_DCLK:
 852                 *value = metrics->CurrClock[PPCLK_DCLK];
 853                 break;
 854         case METRICS_CURR_DCEFCLK:
 855                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 856                 break;
 857         case METRICS_AVERAGE_GFXCLK:
 858                 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
 859                         *value = metrics->AverageGfxclkFrequencyPreDs;
 860                 else
 861                         *value = metrics->AverageGfxclkFrequencyPostDs;
 862                 break;
 863         case METRICS_AVERAGE_SOCCLK:
 864                 *value = metrics->AverageSocclkFrequency;
 865                 break;
 866         case METRICS_AVERAGE_UCLK:
 867                 *value = metrics->AverageUclkFrequencyPostDs;
 868                 break;
 869         case METRICS_AVERAGE_GFXACTIVITY:
 870                 *value = metrics->AverageGfxActivity;
 871                 break;
 872         case METRICS_AVERAGE_MEMACTIVITY:
 873                 *value = metrics->AverageUclkActivity;
 874                 break;
 875         case METRICS_AVERAGE_SOCKETPOWER:
 876                 *value = metrics->AverageSocketPower << 8;
 877                 break;
 878         case METRICS_TEMPERATURE_EDGE:
 879                 *value = metrics->TemperatureEdge *
 880                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 881                 break;
 882         case METRICS_TEMPERATURE_HOTSPOT:
 883                 *value = metrics->TemperatureHotspot *
 884                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 885                 break;
 886         case METRICS_TEMPERATURE_MEM:
 887                 *value = metrics->TemperatureMem *
 888                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 889                 break;
 890         case METRICS_TEMPERATURE_VRGFX:
 891                 *value = metrics->TemperatureVrGfx *
 892                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 893                 break;
 894         case METRICS_TEMPERATURE_VRSOC:
 895                 *value = metrics->TemperatureVrSoc *
 896                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 897                 break;
 898         case METRICS_THROTTLER_STATUS:
 899                 *value = metrics->ThrottlerStatus;
 900                 break;
 901         case METRICS_CURR_FANSPEED:
 902                 *value = metrics->CurrFanSpeed;
 903                 break;
 904         default:
 905                 *value = UINT_MAX;
 906                 break;
 907         }
 908
 909         mutex_unlock(&smu->metrics_lock);
 910
 911         return ret;
 912 }
 913
 914 static int navi1x_get_smu_metrics_data(struct smu_context *smu,
 915                                        MetricsMember_t member,
 916                                        uint32_t *value)
 917 {
 918         struct amdgpu_device *adev = smu->adev;
 919         uint32_t smu_version;
 920         int ret = 0;
 921
 922         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 923         if (ret) {
 924                 dev_err(adev->dev, "Failed to get smu version!\n");
 925                 return ret;
 926         }
 927
 928         switch (adev->asic_type) {
 929         case CHIP_NAVI12:
 930                 if (smu_version > 0x00341C00)
 931                         ret = navi12_get_smu_metrics_data(smu, member, value);
 932                 else
 933                         ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
 934                 break;
 935         case CHIP_NAVI10:
 936         case CHIP_NAVI14:
 937         default:
 938                 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
 939                       ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
 940                         ret = navi10_get_smu_metrics_data(smu, member, value);
 941                 else
 942                         ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
 943                 break;
 944         }
 945
 946         return ret;
 947 }
 948
 949 static int navi10_allocate_dpm_context(struct smu_context *smu)
 950 {
 951         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 952
 953         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 954                                        GFP_KERNEL);
 955         if (!smu_dpm->dpm_context)
 956                 return -ENOMEM;
 957
 958         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 959
 960         return 0;
 961 }
 962
 963 static int navi10_init_smc_tables(struct smu_context *smu)
 964 {
 965         int ret = 0;
 966
 967         ret = navi10_tables_init(smu);
 968         if (ret)
 969                 return ret;
 970
 971         ret = navi10_allocate_dpm_context(smu);
 972         if (ret)
 973                 return ret;
 974
 975         return smu_v11_0_init_smc_tables(smu);
 976 }
 977
 978 static int navi10_set_default_dpm_table(struct smu_context *smu)
 979 {
 980         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 981         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 982         struct smu_11_0_dpm_table *dpm_table;
 983         int ret = 0;
 984
 985         /* socclk dpm table setup */
 986         dpm_table = &dpm_context->dpm_tables.soc_table;
 987         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 988                 ret = smu_v11_0_set_single_dpm_table(smu,
 989                                                      SMU_SOCCLK,
 990                                                      dpm_table);
 991                 if (ret)
 992                         return ret;
 993                 dpm_table->is_fine_grained =
 994                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 995         } else {
 996                 dpm_table->count = 1;
 997                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 998                 dpm_table->dpm_levels[0].enabled = true;
 999                 dpm_table->min = dpm_table->dpm_levels[0].value;
1000                 dpm_table->max = dpm_table->dpm_levels[0].value;
1001         }
1002
1003         /* gfxclk dpm table setup */
1004         dpm_table = &dpm_context->dpm_tables.gfx_table;
1005         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1006                 ret = smu_v11_0_set_single_dpm_table(smu,
1007                                                      SMU_GFXCLK,
1008                                                      dpm_table);
1009                 if (ret)
1010                         return ret;
1011                 dpm_table->is_fine_grained =
1012                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
1013         } else {
1014                 dpm_table->count = 1;
1015                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1016                 dpm_table->dpm_levels[0].enabled = true;
1017                 dpm_table->min = dpm_table->dpm_levels[0].value;
1018                 dpm_table->max = dpm_table->dpm_levels[0].value;
1019         }
1020
1021         /* uclk dpm table setup */
1022         dpm_table = &dpm_context->dpm_tables.uclk_table;
1023         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1024                 ret = smu_v11_0_set_single_dpm_table(smu,
1025                                                      SMU_UCLK,
1026                                                      dpm_table);
1027                 if (ret)
1028                         return ret;
1029                 dpm_table->is_fine_grained =
1030                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
1031         } else {
1032                 dpm_table->count = 1;
1033                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1034                 dpm_table->dpm_levels[0].enabled = true;
1035                 dpm_table->min = dpm_table->dpm_levels[0].value;
1036                 dpm_table->max = dpm_table->dpm_levels[0].value;
1037         }
1038
1039         /* vclk dpm table setup */
1040         dpm_table = &dpm_context->dpm_tables.vclk_table;
1041         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1042                 ret = smu_v11_0_set_single_dpm_table(smu,
1043                                                      SMU_VCLK,
1044                                                      dpm_table);
1045                 if (ret)
1046                         return ret;
1047                 dpm_table->is_fine_grained =
1048                         !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
1049         } else {
1050                 dpm_table->count = 1;
1051                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1052                 dpm_table->dpm_levels[0].enabled = true;
1053                 dpm_table->min = dpm_table->dpm_levels[0].value;
1054                 dpm_table->max = dpm_table->dpm_levels[0].value;
1055         }
1056
1057         /* dclk dpm table setup */
1058         dpm_table = &dpm_context->dpm_tables.dclk_table;
1059         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1060                 ret = smu_v11_0_set_single_dpm_table(smu,
1061                                                      SMU_DCLK,
1062                                                      dpm_table);
1063                 if (ret)
1064                         return ret;
1065                 dpm_table->is_fine_grained =
1066                         !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
1067         } else {
1068                 dpm_table->count = 1;
1069                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1070                 dpm_table->dpm_levels[0].enabled = true;
1071                 dpm_table->min = dpm_table->dpm_levels[0].value;
1072                 dpm_table->max = dpm_table->dpm_levels[0].value;
1073         }
1074
1075         /* dcefclk dpm table setup */
1076         dpm_table = &dpm_context->dpm_tables.dcef_table;
1077         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1078                 ret = smu_v11_0_set_single_dpm_table(smu,
1079                                                      SMU_DCEFCLK,
1080                                                      dpm_table);
1081                 if (ret)
1082                         return ret;
1083                 dpm_table->is_fine_grained =
1084                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
1085         } else {
1086                 dpm_table->count = 1;
1087                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1088                 dpm_table->dpm_levels[0].enabled = true;
1089                 dpm_table->min = dpm_table->dpm_levels[0].value;
1090                 dpm_table->max = dpm_table->dpm_levels[0].value;
1091         }
1092
1093         /* pixelclk dpm table setup */
1094         dpm_table = &dpm_context->dpm_tables.pixel_table;
1095         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1096                 ret = smu_v11_0_set_single_dpm_table(smu,
1097                                                      SMU_PIXCLK,
1098                                                      dpm_table);
1099                 if (ret)
1100                         return ret;
1101                 dpm_table->is_fine_grained =
1102                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
1103         } else {
1104                 dpm_table->count = 1;
1105                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1106                 dpm_table->dpm_levels[0].enabled = true;
1107                 dpm_table->min = dpm_table->dpm_levels[0].value;
1108                 dpm_table->max = dpm_table->dpm_levels[0].value;
1109         }
1110
1111         /* displayclk dpm table setup */
1112         dpm_table = &dpm_context->dpm_tables.display_table;
1113         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1114                 ret = smu_v11_0_set_single_dpm_table(smu,
1115                                                      SMU_DISPCLK,
1116                                                      dpm_table);
1117                 if (ret)
1118                         return ret;
1119                 dpm_table->is_fine_grained =
1120                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
1121         } else {
1122                 dpm_table->count = 1;
1123                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1124                 dpm_table->dpm_levels[0].enabled = true;
1125                 dpm_table->min = dpm_table->dpm_levels[0].value;
1126                 dpm_table->max = dpm_table->dpm_levels[0].value;
1127         }
1128
1129         /* phyclk dpm table setup */
1130         dpm_table = &dpm_context->dpm_tables.phy_table;
1131         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1132                 ret = smu_v11_0_set_single_dpm_table(smu,
1133                                                      SMU_PHYCLK,
1134                                                      dpm_table);
1135                 if (ret)
1136                         return ret;
1137                 dpm_table->is_fine_grained =
1138                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
1139         } else {
1140                 dpm_table->count = 1;
1141                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1142                 dpm_table->dpm_levels[0].enabled = true;
1143                 dpm_table->min = dpm_table->dpm_levels[0].value;
1144                 dpm_table->max = dpm_table->dpm_levels[0].value;
1145         }
1146
1147         return 0;
1148 }
1149
1150 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1151 {
1152         int ret = 0;
1153
1154         if (enable) {
1155                 /* vcn dpm on is a prerequisite for vcn power gate messages */
1156                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1157                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
1158                         if (ret)
1159                                 return ret;
1160                 }
1161         } else {
1162                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1163                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
1164                         if (ret)
1165                                 return ret;
1166                 }
1167         }
1168
1169         return ret;
1170 }
1171
1172 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1173 {
1174         int ret = 0;
1175
1176         if (enable) {
1177                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1178                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
1179                         if (ret)
1180                                 return ret;
1181                 }
1182         } else {
1183                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1184                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
1185                         if (ret)
1186                                 return ret;
1187                 }
1188         }
1189
1190         return ret;
1191 }
1192
1193 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
1194                                        enum smu_clk_type clk_type,
1195                                        uint32_t *value)
1196 {
1197         MetricsMember_t member_type;
1198         int clk_id = 0;
1199
1200         clk_id = smu_cmn_to_asic_specific_index(smu,
1201                                                 CMN2ASIC_MAPPING_CLK,
1202                                                 clk_type);
1203         if (clk_id < 0)
1204                 return clk_id;
1205
1206         switch (clk_id) {
1207         case PPCLK_GFXCLK:
1208                 member_type = METRICS_CURR_GFXCLK;
1209                 break;
1210         case PPCLK_UCLK:
1211                 member_type = METRICS_CURR_UCLK;
1212                 break;
1213         case PPCLK_SOCCLK:
1214                 member_type = METRICS_CURR_SOCCLK;
1215                 break;
1216         case PPCLK_VCLK:
1217                 member_type = METRICS_CURR_VCLK;
1218                 break;
1219         case PPCLK_DCLK:
1220                 member_type = METRICS_CURR_DCLK;
1221                 break;
1222         case PPCLK_DCEFCLK:
1223                 member_type = METRICS_CURR_DCEFCLK;
1224                 break;
1225         default:
1226                 return -EINVAL;
1227         }
1228
1229         return navi1x_get_smu_metrics_data(smu,
1230                                            member_type,
1231                                            value);
1232 }
1233
1234 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1235 {
1236         PPTable_t *pptable = smu->smu_table.driver_pptable;
1237         DpmDescriptor_t *dpm_desc = NULL;
1238         uint32_t clk_index = 0;
1239
1240         clk_index = smu_cmn_to_asic_specific_index(smu,
1241                                                    CMN2ASIC_MAPPING_CLK,
1242                                                    clk_type);
1243         dpm_desc = &pptable->DpmDescriptor[clk_index];
1244
1245         /* 0 - Fine grained DPM, 1 - Discrete DPM */
1246         return dpm_desc->SnapToDiscrete == 0;
1247 }
1248
1249 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
1250 {
1251         return od_table->cap[cap];
1252 }
1253
1254 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
1255                                         enum SMU_11_0_ODSETTING_ID setting,
1256                                         uint32_t *min, uint32_t *max)
1257 {
1258         if (min)
1259                 *min = od_table->min[setting];
1260         if (max)
1261                 *max = od_table->max[setting];
1262 }
1263
1264 static int navi10_print_clk_levels(struct smu_context *smu,
1265                         enum smu_clk_type clk_type, char *buf)
1266 {
1267         uint16_t *curve_settings;
1268         int i, size = 0, ret = 0;
1269         uint32_t cur_value = 0, value = 0, count = 0;
1270         uint32_t freq_values[3] = {0};
1271         uint32_t mark_index = 0;
1272         struct smu_table_context *table_context = &smu->smu_table;
1273         uint32_t gen_speed, lane_width;
1274         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1275         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1276         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1277         OverDriveTable_t *od_table =
1278                 (OverDriveTable_t *)table_context->overdrive_table;
1279         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1280         uint32_t min_value, max_value;
1281
1282         switch (clk_type) {
1283         case SMU_GFXCLK:
1284         case SMU_SCLK:
1285         case SMU_SOCCLK:
1286         case SMU_MCLK:
1287         case SMU_UCLK:
1288         case SMU_FCLK:
1289         case SMU_VCLK:
1290         case SMU_DCLK:
1291         case SMU_DCEFCLK:
1292                 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1293                 if (ret)
1294                         return size;
1295
1296                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1297                 if (ret)
1298                         return size;
1299
1300                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1301                         for (i = 0; i < count; i++) {
1302                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1303                                 if (ret)
1304                                         return size;
1305
1306                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1307                                                 cur_value == value ? "*" : "");
1308                         }
1309                 } else {
1310                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1311                         if (ret)
1312                                 return size;
1313                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1314                         if (ret)
1315                                 return size;
1316
1317                         freq_values[1] = cur_value;
1318                         mark_index = cur_value == freq_values[0] ? 0 :
1319                                      cur_value == freq_values[2] ? 2 : 1;
1320                         if (mark_index != 1)
1321                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
1322
1323                         for (i = 0; i < 3; i++) {
1324                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1325                                                 i == mark_index ? "*" : "");
1326                         }
1327
1328                 }
1329                 break;
1330         case SMU_PCIE:
1331                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1332                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1333                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1334                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1335                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1336                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1337                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1338                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1339                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1340                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1341                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1342                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1343                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1344                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1345                                         pptable->LclkFreq[i],
1346                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1347                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1348                                         "*" : "");
1349                 break;
1350         case SMU_OD_SCLK:
1351                 if (!smu->od_enabled || !od_table || !od_settings)
1352                         break;
1353                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1354                         break;
1355                 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1356                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1357                                       od_table->GfxclkFmin, od_table->GfxclkFmax);
1358                 break;
1359         case SMU_OD_MCLK:
1360                 if (!smu->od_enabled || !od_table || !od_settings)
1361                         break;
1362                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1363                         break;
1364                 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1365                 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax);
1366                 break;
1367         case SMU_OD_VDDC_CURVE:
1368                 if (!smu->od_enabled || !od_table || !od_settings)
1369                         break;
1370                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1371                         break;
1372                 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
1373                 for (i = 0; i < 3; i++) {
1374                         switch (i) {
1375                         case 0:
1376                                 curve_settings = &od_table->GfxclkFreq1;
1377                                 break;
1378                         case 1:
1379                                 curve_settings = &od_table->GfxclkFreq2;
1380                                 break;
1381                         case 2:
1382                                 curve_settings = &od_table->GfxclkFreq3;
1383                                 break;
1384                         default:
1385                                 break;
1386                         }
1387                         size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n",
1388                                               i, curve_settings[0],
1389                                         curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1390                 }
1391                 break;
1392         case SMU_OD_RANGE:
1393                 if (!smu->od_enabled || !od_table || !od_settings)
1394                         break;
1395                 size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
1396
1397                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1398                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1399                                                     &min_value, NULL);
1400                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1401                                                     NULL, &max_value);
1402                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1403                                         min_value, max_value);
1404                 }
1405
1406                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1407                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1408                                                     &min_value, &max_value);
1409                         size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1410                                         min_value, max_value);
1411                 }
1412
1413                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1414                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1415                                                     &min_value, &max_value);
1416                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1417                                               min_value, max_value);
1418                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1419                                                     &min_value, &max_value);
1420                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1421                                               min_value, max_value);
1422                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1423                                                     &min_value, &max_value);
1424                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1425                                               min_value, max_value);
1426                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1427                                                     &min_value, &max_value);
1428                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1429                                               min_value, max_value);
1430                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1431                                                     &min_value, &max_value);
1432                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1433                                               min_value, max_value);
1434                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1435                                                     &min_value, &max_value);
1436                         size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1437                                               min_value, max_value);
1438                 }
1439
1440                 break;
1441         default:
1442                 break;
1443         }
1444
1445         return size;
1446 }
1447
1448 static int navi10_force_clk_levels(struct smu_context *smu,
1449                                    enum smu_clk_type clk_type, uint32_t mask)
1450 {
1451
1452         int ret = 0, size = 0;
1453         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1454
1455         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1456         soft_max_level = mask ? (fls(mask) - 1) : 0;
1457
1458         switch (clk_type) {
1459         case SMU_GFXCLK:
1460         case SMU_SCLK:
1461         case SMU_SOCCLK:
1462         case SMU_MCLK:
1463         case SMU_UCLK:
1464         case SMU_FCLK:
1465                 /* There is only 2 levels for fine grained DPM */
1466                 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1467                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1468                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1469                 }
1470
1471                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1472                 if (ret)
1473                         return size;
1474
1475                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1476                 if (ret)
1477                         return size;
1478
1479                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1480                 if (ret)
1481                         return size;
1482                 break;
1483         case SMU_DCEFCLK:
1484                 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1485                 break;
1486
1487         default:
1488                 break;
1489         }
1490
1491         return size;
1492 }
1493
1494 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1495 {
1496         struct smu_11_0_dpm_context *dpm_context =
1497                                 smu->smu_dpm.dpm_context;
1498         struct smu_11_0_dpm_table *gfx_table =
1499                                 &dpm_context->dpm_tables.gfx_table;
1500         struct smu_11_0_dpm_table *mem_table =
1501                                 &dpm_context->dpm_tables.uclk_table;
1502         struct smu_11_0_dpm_table *soc_table =
1503                                 &dpm_context->dpm_tables.soc_table;
1504         struct smu_umd_pstate_table *pstate_table =
1505                                 &smu->pstate_table;
1506         struct amdgpu_device *adev = smu->adev;
1507         uint32_t sclk_freq;
1508
1509         pstate_table->gfxclk_pstate.min = gfx_table->min;
1510         switch (adev->asic_type) {
1511         case CHIP_NAVI10:
1512                 switch (adev->pdev->revision) {
1513                 case 0xf0: /* XTX */
1514                 case 0xc0:
1515                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1516                         break;
1517                 case 0xf1: /* XT */
1518                 case 0xc1:
1519                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1520                         break;
1521                 default: /* XL */
1522                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1523                         break;
1524                 }
1525                 break;
1526         case CHIP_NAVI14:
1527                 switch (adev->pdev->revision) {
1528                 case 0xc7: /* XT */
1529                 case 0xf4:
1530                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1531                         break;
1532                 case 0xc1: /* XTM */
1533                 case 0xf2:
1534                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1535                         break;
1536                 case 0xc3: /* XLM */
1537                 case 0xf3:
1538                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1539                         break;
1540                 case 0xc5: /* XTX */
1541                 case 0xf6:
1542                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1543                         break;
1544                 default: /* XL */
1545                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1546                         break;
1547                 }
1548                 break;
1549         case CHIP_NAVI12:
1550                 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1551                 break;
1552         default:
1553                 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1554                 break;
1555         }
1556         pstate_table->gfxclk_pstate.peak = sclk_freq;
1557
1558         pstate_table->uclk_pstate.min = mem_table->min;
1559         pstate_table->uclk_pstate.peak = mem_table->max;
1560
1561         pstate_table->socclk_pstate.min = soc_table->min;
1562         pstate_table->socclk_pstate.peak = soc_table->max;
1563
1564         if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1565             mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1566             soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1567                 pstate_table->gfxclk_pstate.standard =
1568                         NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1569                 pstate_table->uclk_pstate.standard =
1570                         NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1571                 pstate_table->socclk_pstate.standard =
1572                         NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1573         } else {
1574                 pstate_table->gfxclk_pstate.standard =
1575                         pstate_table->gfxclk_pstate.min;
1576                 pstate_table->uclk_pstate.standard =
1577                         pstate_table->uclk_pstate.min;
1578                 pstate_table->socclk_pstate.standard =
1579                         pstate_table->socclk_pstate.min;
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1586                                                  enum smu_clk_type clk_type,
1587                                                  struct pp_clock_levels_with_latency *clocks)
1588 {
1589         int ret = 0, i = 0;
1590         uint32_t level_count = 0, freq = 0;
1591
1592         switch (clk_type) {
1593         case SMU_GFXCLK:
1594         case SMU_DCEFCLK:
1595         case SMU_SOCCLK:
1596         case SMU_MCLK:
1597         case SMU_UCLK:
1598                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1599                 if (ret)
1600                         return ret;
1601
1602                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1603                 clocks->num_levels = level_count;
1604
1605                 for (i = 0; i < level_count; i++) {
1606                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1607                         if (ret)
1608                                 return ret;
1609
1610                         clocks->data[i].clocks_in_khz = freq * 1000;
1611                         clocks->data[i].latency_in_us = 0;
1612                 }
1613                 break;
1614         default:
1615                 break;
1616         }
1617
1618         return ret;
1619 }
1620
1621 static int navi10_pre_display_config_changed(struct smu_context *smu)
1622 {
1623         int ret = 0;
1624         uint32_t max_freq = 0;
1625
1626         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1627         if (ret)
1628                 return ret;
1629
1630         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1631                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1632                 if (ret)
1633                         return ret;
1634                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1635                 if (ret)
1636                         return ret;
1637         }
1638
1639         return ret;
1640 }
1641
1642 static int navi10_display_config_changed(struct smu_context *smu)
1643 {
1644         int ret = 0;
1645
1646         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1647             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1648             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1649                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1650                                                   smu->display_config->num_display,
1651                                                   NULL);
1652                 if (ret)
1653                         return ret;
1654         }
1655
1656         return ret;
1657 }
1658
1659 static bool navi10_is_dpm_running(struct smu_context *smu)
1660 {
1661         int ret = 0;
1662         uint32_t feature_mask[2];
1663         uint64_t feature_enabled;
1664
1665         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1666         if (ret)
1667                 return false;
1668
1669         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1670
1671         return !!(feature_enabled & SMC_DPM_FEATURE);
1672 }
1673
1674 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1675                                     uint32_t *speed)
1676 {
1677         int ret = 0;
1678
1679         if (!speed)
1680                 return -EINVAL;
1681
1682         switch (smu_v11_0_get_fan_control_mode(smu)) {
1683         case AMD_FAN_CTRL_AUTO:
1684                 ret = navi10_get_smu_metrics_data(smu,
1685                                                   METRICS_CURR_FANSPEED,
1686                                                   speed);
1687                 break;
1688         default:
1689                 ret = smu_v11_0_get_fan_speed_rpm(smu,
1690                                                   speed);
1691                 break;
1692         }
1693
1694         return ret;
1695 }
1696
1697 static int navi10_get_fan_parameters(struct smu_context *smu)
1698 {
1699         PPTable_t *pptable = smu->smu_table.driver_pptable;
1700
1701         smu->fan_max_rpm = pptable->FanMaximumRpm;
1702
1703         return 0;
1704 }
1705
1706 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1707 {
1708         DpmActivityMonitorCoeffInt_t activity_monitor;
1709         uint32_t i, size = 0;
1710         int16_t workload_type = 0;
1711         static const char *profile_name[] = {
1712                                         "BOOTUP_DEFAULT",
1713                                         "3D_FULL_SCREEN",
1714                                         "POWER_SAVING",
1715                                         "VIDEO",
1716                                         "VR",
1717                                         "COMPUTE",
1718                                         "CUSTOM"};
1719         static const char *title[] = {
1720                         "PROFILE_INDEX(NAME)",
1721                         "CLOCK_TYPE(NAME)",
1722                         "FPS",
1723                         "MinFreqType",
1724                         "MinActiveFreqType",
1725                         "MinActiveFreq",
1726                         "BoosterFreqType",
1727                         "BoosterFreq",
1728                         "PD_Data_limit_c",
1729                         "PD_Data_error_coeff",
1730                         "PD_Data_error_rate_coeff"};
1731         int result = 0;
1732
1733         if (!buf)
1734                 return -EINVAL;
1735
1736         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1737                         title[0], title[1], title[2], title[3], title[4], title[5],
1738                         title[6], title[7], title[8], title[9], title[10]);
1739
1740         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1741                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1742                 workload_type = smu_cmn_to_asic_specific_index(smu,
1743                                                                CMN2ASIC_MAPPING_WORKLOAD,
1744                                                                i);
1745                 if (workload_type < 0)
1746                         return -EINVAL;
1747
1748                 result = smu_cmn_update_table(smu,
1749                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1750                                           (void *)(&activity_monitor), false);
1751                 if (result) {
1752                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1753                         return result;
1754                 }
1755
1756                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1757                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1758
1759                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1760                         " ",
1761                         0,
1762                         "GFXCLK",
1763                         activity_monitor.Gfx_FPS,
1764                         activity_monitor.Gfx_MinFreqStep,
1765                         activity_monitor.Gfx_MinActiveFreqType,
1766                         activity_monitor.Gfx_MinActiveFreq,
1767                         activity_monitor.Gfx_BoosterFreqType,
1768                         activity_monitor.Gfx_BoosterFreq,
1769                         activity_monitor.Gfx_PD_Data_limit_c,
1770                         activity_monitor.Gfx_PD_Data_error_coeff,
1771                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1772
1773                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1774                         " ",
1775                         1,
1776                         "SOCCLK",
1777                         activity_monitor.Soc_FPS,
1778                         activity_monitor.Soc_MinFreqStep,
1779                         activity_monitor.Soc_MinActiveFreqType,
1780                         activity_monitor.Soc_MinActiveFreq,
1781                         activity_monitor.Soc_BoosterFreqType,
1782                         activity_monitor.Soc_BoosterFreq,
1783                         activity_monitor.Soc_PD_Data_limit_c,
1784                         activity_monitor.Soc_PD_Data_error_coeff,
1785                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1786
1787                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1788                         " ",
1789                         2,
1790                         "MEMLK",
1791                         activity_monitor.Mem_FPS,
1792                         activity_monitor.Mem_MinFreqStep,
1793                         activity_monitor.Mem_MinActiveFreqType,
1794                         activity_monitor.Mem_MinActiveFreq,
1795                         activity_monitor.Mem_BoosterFreqType,
1796                         activity_monitor.Mem_BoosterFreq,
1797                         activity_monitor.Mem_PD_Data_limit_c,
1798                         activity_monitor.Mem_PD_Data_error_coeff,
1799                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1800         }
1801
1802         return size;
1803 }
1804
1805 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1806 {
1807         DpmActivityMonitorCoeffInt_t activity_monitor;
1808         int workload_type, ret = 0;
1809
1810         smu->power_profile_mode = input[size];
1811
1812         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1813                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1814                 return -EINVAL;
1815         }
1816
1817         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1818
1819                 ret = smu_cmn_update_table(smu,
1820                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1821                                        (void *)(&activity_monitor), false);
1822                 if (ret) {
1823                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1824                         return ret;
1825                 }
1826
1827                 switch (input[0]) {
1828                 case 0: /* Gfxclk */
1829                         activity_monitor.Gfx_FPS = input[1];
1830                         activity_monitor.Gfx_MinFreqStep = input[2];
1831                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1832                         activity_monitor.Gfx_MinActiveFreq = input[4];
1833                         activity_monitor.Gfx_BoosterFreqType = input[5];
1834                         activity_monitor.Gfx_BoosterFreq = input[6];
1835                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1836                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1837                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1838                         break;
1839                 case 1: /* Socclk */
1840                         activity_monitor.Soc_FPS = input[1];
1841                         activity_monitor.Soc_MinFreqStep = input[2];
1842                         activity_monitor.Soc_MinActiveFreqType = input[3];
1843                         activity_monitor.Soc_MinActiveFreq = input[4];
1844                         activity_monitor.Soc_BoosterFreqType = input[5];
1845                         activity_monitor.Soc_BoosterFreq = input[6];
1846                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1847                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1848                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1849                         break;
1850                 case 2: /* Memlk */
1851                         activity_monitor.Mem_FPS = input[1];
1852                         activity_monitor.Mem_MinFreqStep = input[2];
1853                         activity_monitor.Mem_MinActiveFreqType = input[3];
1854                         activity_monitor.Mem_MinActiveFreq = input[4];
1855                         activity_monitor.Mem_BoosterFreqType = input[5];
1856                         activity_monitor.Mem_BoosterFreq = input[6];
1857                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1858                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1859                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1860                         break;
1861                 }
1862
1863                 ret = smu_cmn_update_table(smu,
1864                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1865                                        (void *)(&activity_monitor), true);
1866                 if (ret) {
1867                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1868                         return ret;
1869                 }
1870         }
1871
1872         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1873         workload_type = smu_cmn_to_asic_specific_index(smu,
1874                                                        CMN2ASIC_MAPPING_WORKLOAD,
1875                                                        smu->power_profile_mode);
1876         if (workload_type < 0)
1877                 return -EINVAL;
1878         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1879                                     1 << workload_type, NULL);
1880
1881         return ret;
1882 }
1883
1884 static int navi10_notify_smc_display_config(struct smu_context *smu)
1885 {
1886         struct smu_clocks min_clocks = {0};
1887         struct pp_display_clock_request clock_req;
1888         int ret = 0;
1889
1890         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1891         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1892         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1893
1894         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1895                 clock_req.clock_type = amd_pp_dcef_clock;
1896                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1897
1898                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1899                 if (!ret) {
1900                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1901                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1902                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1903                                                                   min_clocks.dcef_clock_in_sr/100,
1904                                                                   NULL);
1905                                 if (ret) {
1906                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1907                                         return ret;
1908                                 }
1909                         }
1910                 } else {
1911                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1912                 }
1913         }
1914
1915         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1916                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1917                 if (ret) {
1918                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1919                         return ret;
1920                 }
1921         }
1922
1923         return 0;
1924 }
1925
1926 static int navi10_set_watermarks_table(struct smu_context *smu,
1927                                        struct pp_smu_wm_range_sets *clock_ranges)
1928 {
1929         Watermarks_t *table = smu->smu_table.watermarks_table;
1930         int ret = 0;
1931         int i;
1932
1933         if (clock_ranges) {
1934                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1935                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1936                         return -EINVAL;
1937
1938                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1939                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1940                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1941                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1942                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1943                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1944                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1945                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1946                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1947
1948                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1949                                 clock_ranges->reader_wm_sets[i].wm_inst;
1950                 }
1951
1952                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1953                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1954                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1955                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1956                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1957                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1958                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1959                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1960                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1961
1962                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1963                                 clock_ranges->writer_wm_sets[i].wm_inst;
1964                 }
1965
1966                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1967         }
1968
1969         /* pass data to smu controller */
1970         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1971              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1972                 ret = smu_cmn_write_watermarks_table(smu);
1973                 if (ret) {
1974                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1975                         return ret;
1976                 }
1977                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1978         }
1979
1980         return 0;
1981 }
1982
1983 static int navi10_read_sensor(struct smu_context *smu,
1984                                  enum amd_pp_sensors sensor,
1985                                  void *data, uint32_t *size)
1986 {
1987         int ret = 0;
1988         struct smu_table_context *table_context = &smu->smu_table;
1989         PPTable_t *pptable = table_context->driver_pptable;
1990
1991         if(!data || !size)
1992                 return -EINVAL;
1993
1994         mutex_lock(&smu->sensor_lock);
1995         switch (sensor) {
1996         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1997                 *(uint32_t *)data = pptable->FanMaximumRpm;
1998                 *size = 4;
1999                 break;
2000         case AMDGPU_PP_SENSOR_MEM_LOAD:
2001                 ret = navi1x_get_smu_metrics_data(smu,
2002                                                   METRICS_AVERAGE_MEMACTIVITY,
2003                                                   (uint32_t *)data);
2004                 *size = 4;
2005                 break;
2006         case AMDGPU_PP_SENSOR_GPU_LOAD:
2007                 ret = navi1x_get_smu_metrics_data(smu,
2008                                                   METRICS_AVERAGE_GFXACTIVITY,
2009                                                   (uint32_t *)data);
2010                 *size = 4;
2011                 break;
2012         case AMDGPU_PP_SENSOR_GPU_POWER:
2013                 ret = navi1x_get_smu_metrics_data(smu,
2014                                                   METRICS_AVERAGE_SOCKETPOWER,
2015                                                   (uint32_t *)data);
2016                 *size = 4;
2017                 break;
2018         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2019                 ret = navi1x_get_smu_metrics_data(smu,
2020                                                   METRICS_TEMPERATURE_HOTSPOT,
2021                                                   (uint32_t *)data);
2022                 *size = 4;
2023                 break;
2024         case AMDGPU_PP_SENSOR_EDGE_TEMP:
2025                 ret = navi1x_get_smu_metrics_data(smu,
2026                                                   METRICS_TEMPERATURE_EDGE,
2027                                                   (uint32_t *)data);
2028                 *size = 4;
2029                 break;
2030         case AMDGPU_PP_SENSOR_MEM_TEMP:
2031                 ret = navi1x_get_smu_metrics_data(smu,
2032                                                   METRICS_TEMPERATURE_MEM,
2033                                                   (uint32_t *)data);
2034                 *size = 4;
2035                 break;
2036         case AMDGPU_PP_SENSOR_GFX_MCLK:
2037                 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
2038                 *(uint32_t *)data *= 100;
2039                 *size = 4;
2040                 break;
2041         case AMDGPU_PP_SENSOR_GFX_SCLK:
2042                 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
2043                 *(uint32_t *)data *= 100;
2044                 *size = 4;
2045                 break;
2046         case AMDGPU_PP_SENSOR_VDDGFX:
2047                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2048                 *size = 4;
2049                 break;
2050         default:
2051                 ret = -EOPNOTSUPP;
2052                 break;
2053         }
2054         mutex_unlock(&smu->sensor_lock);
2055
2056         return ret;
2057 }
2058
2059 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2060 {
2061         uint32_t num_discrete_levels = 0;
2062         uint16_t *dpm_levels = NULL;
2063         uint16_t i = 0;
2064         struct smu_table_context *table_context = &smu->smu_table;
2065         PPTable_t *driver_ppt = NULL;
2066
2067         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2068                 return -EINVAL;
2069
2070         driver_ppt = table_context->driver_pptable;
2071         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
2072         dpm_levels = driver_ppt->FreqTableUclk;
2073
2074         if (num_discrete_levels == 0 || dpm_levels == NULL)
2075                 return -EINVAL;
2076
2077         *num_states = num_discrete_levels;
2078         for (i = 0; i < num_discrete_levels; i++) {
2079                 /* convert to khz */
2080                 *clocks_in_khz = (*dpm_levels) * 1000;
2081                 clocks_in_khz++;
2082                 dpm_levels++;
2083         }
2084
2085         return 0;
2086 }
2087
2088 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
2089                                                 struct smu_temperature_range *range)
2090 {
2091         struct smu_table_context *table_context = &smu->smu_table;
2092         struct smu_11_0_powerplay_table *powerplay_table =
2093                                 table_context->power_play_table;
2094         PPTable_t *pptable = smu->smu_table.driver_pptable;
2095
2096         if (!range)
2097                 return -EINVAL;
2098
2099         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2100
2101         range->max = pptable->TedgeLimit *
2102                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2103         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
2104                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2105         range->hotspot_crit_max = pptable->ThotspotLimit *
2106                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2107         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2108                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2109         range->mem_crit_max = pptable->TmemLimit *
2110                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2111         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
2112                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2113         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2114
2115         return 0;
2116 }
2117
2118 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
2119                                                 bool disable_memory_clock_switch)
2120 {
2121         int ret = 0;
2122         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2123                 (struct smu_11_0_max_sustainable_clocks *)
2124                         smu->smu_table.max_sustainable_clocks;
2125         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2126         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2127
2128         if(smu->disable_uclk_switch == disable_memory_clock_switch)
2129                 return 0;
2130
2131         if(disable_memory_clock_switch)
2132                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2133         else
2134                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2135
2136         if(!ret)
2137                 smu->disable_uclk_switch = disable_memory_clock_switch;
2138
2139         return ret;
2140 }
2141
2142 static int navi10_get_power_limit(struct smu_context *smu,
2143                                   uint32_t *current_power_limit,
2144                                   uint32_t *default_power_limit,
2145                                   uint32_t *max_power_limit)
2146 {
2147         struct smu_11_0_powerplay_table *powerplay_table =
2148                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
2149         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2150         PPTable_t *pptable = smu->smu_table.driver_pptable;
2151         uint32_t power_limit, od_percent;
2152
2153         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
2154                 /* the last hope to figure out the ppt limit */
2155                 if (!pptable) {
2156                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
2157                         return -EINVAL;
2158                 }
2159                 power_limit =
2160                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2161         }
2162
2163         if (current_power_limit)
2164                 *current_power_limit = power_limit;
2165         if (default_power_limit)
2166                 *default_power_limit = power_limit;
2167
2168         if (max_power_limit) {
2169                 if (smu->od_enabled &&
2170                     navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2171                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2172
2173                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
2174
2175                         power_limit *= (100 + od_percent);
2176                         power_limit /= 100;
2177                 }
2178
2179                 *max_power_limit = power_limit;
2180         }
2181
2182         return 0;
2183 }
2184
2185 static int navi10_update_pcie_parameters(struct smu_context *smu,
2186                                      uint32_t pcie_gen_cap,
2187                                      uint32_t pcie_width_cap)
2188 {
2189         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2190         PPTable_t *pptable = smu->smu_table.driver_pptable;
2191         uint32_t smu_pcie_arg;
2192         int ret, i;
2193
2194         /* lclk dpm table setup */
2195         for (i = 0; i < MAX_PCIE_CONF; i++) {
2196                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2197                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2198         }
2199
2200         for (i = 0; i < NUM_LINK_LEVELS; i++) {
2201                 smu_pcie_arg = (i << 16) |
2202                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
2203                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
2204                                         pptable->PcieLaneCount[i] : pcie_width_cap);
2205                 ret = smu_cmn_send_smc_msg_with_param(smu,
2206                                           SMU_MSG_OverridePcieParameters,
2207                                           smu_pcie_arg,
2208                                           NULL);
2209
2210                 if (ret)
2211                         return ret;
2212
2213                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
2214                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2215                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
2216                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2217         }
2218
2219         return 0;
2220 }
2221
2222 static inline void navi10_dump_od_table(struct smu_context *smu,
2223                                         OverDriveTable_t *od_table)
2224 {
2225         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
2226         dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
2227         dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
2228         dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
2229         dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
2230         dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
2231 }
2232
2233 static int navi10_od_setting_check_range(struct smu_context *smu,
2234                                          struct smu_11_0_overdrive_table *od_table,
2235                                          enum SMU_11_0_ODSETTING_ID setting,
2236                                          uint32_t value)
2237 {
2238         if (value < od_table->min[setting]) {
2239                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2240                 return -EINVAL;
2241         }
2242         if (value > od_table->max[setting]) {
2243                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2244                 return -EINVAL;
2245         }
2246         return 0;
2247 }
2248
2249 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2250                                                      uint16_t *voltage,
2251                                                      uint32_t freq)
2252 {
2253         uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2254         uint32_t value = 0;
2255         int ret;
2256
2257         ret = smu_cmn_send_smc_msg_with_param(smu,
2258                                           SMU_MSG_GetVoltageByDpm,
2259                                           param,
2260                                           &value);
2261         if (ret) {
2262                 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2263                 return ret;
2264         }
2265
2266         *voltage = (uint16_t)value;
2267
2268         return 0;
2269 }
2270
2271 static int navi10_baco_enter(struct smu_context *smu)
2272 {
2273         struct amdgpu_device *adev = smu->adev;
2274
2275         if (adev->in_runpm)
2276                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2277         else
2278                 return smu_v11_0_baco_enter(smu);
2279 }
2280
2281 static int navi10_baco_exit(struct smu_context *smu)
2282 {
2283         struct amdgpu_device *adev = smu->adev;
2284
2285         if (adev->in_runpm) {
2286                 /* Wait for PMFW handling for the Dstate change */
2287                 msleep(10);
2288                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2289         } else {
2290                 return smu_v11_0_baco_exit(smu);
2291         }
2292 }
2293
2294 static int navi10_set_default_od_settings(struct smu_context *smu)
2295 {
2296         OverDriveTable_t *od_table =
2297                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2298         OverDriveTable_t *boot_od_table =
2299                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2300         OverDriveTable_t *user_od_table =
2301                 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2302         int ret = 0;
2303
2304         /*
2305          * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2306          *   - either they already have the default OD settings got during cold bootup
2307          *   - or they have some user customized OD settings which cannot be overwritten
2308          */
2309         if (smu->adev->in_suspend)
2310                 return 0;
2311
2312         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false);
2313         if (ret) {
2314                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2315                 return ret;
2316         }
2317
2318         if (!boot_od_table->GfxclkVolt1) {
2319                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2320                                                                 &boot_od_table->GfxclkVolt1,
2321                                                                 boot_od_table->GfxclkFreq1);
2322                 if (ret)
2323                         return ret;
2324         }
2325
2326         if (!boot_od_table->GfxclkVolt2) {
2327                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2328                                                                 &boot_od_table->GfxclkVolt2,
2329                                                                 boot_od_table->GfxclkFreq2);
2330                 if (ret)
2331                         return ret;
2332         }
2333
2334         if (!boot_od_table->GfxclkVolt3) {
2335                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2336                                                                 &boot_od_table->GfxclkVolt3,
2337                                                                 boot_od_table->GfxclkFreq3);
2338                 if (ret)
2339                         return ret;
2340         }
2341
2342         navi10_dump_od_table(smu, boot_od_table);
2343
2344         memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2345         memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2346
2347         return 0;
2348 }
2349
2350 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2351         int i;
2352         int ret = 0;
2353         struct smu_table_context *table_context = &smu->smu_table;
2354         OverDriveTable_t *od_table;
2355         struct smu_11_0_overdrive_table *od_settings;
2356         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2357         uint16_t *freq_ptr, *voltage_ptr;
2358         od_table = (OverDriveTable_t *)table_context->overdrive_table;
2359
2360         if (!smu->od_enabled) {
2361                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2362                 return -EINVAL;
2363         }
2364
2365         if (!smu->od_settings) {
2366                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2367                 return -ENOENT;
2368         }
2369
2370         od_settings = smu->od_settings;
2371
2372         switch (type) {
2373         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2374                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2375                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2376                         return -ENOTSUPP;
2377                 }
2378                 if (!table_context->overdrive_table) {
2379                         dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2380                         return -EINVAL;
2381                 }
2382                 for (i = 0; i < size; i += 2) {
2383                         if (i + 2 > size) {
2384                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2385                                 return -EINVAL;
2386                         }
2387                         switch (input[i]) {
2388                         case 0:
2389                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2390                                 freq_ptr = &od_table->GfxclkFmin;
2391                                 if (input[i + 1] > od_table->GfxclkFmax) {
2392                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2393                                                 input[i + 1],
2394                                                 od_table->GfxclkFmin);
2395                                         return -EINVAL;
2396                                 }
2397                                 break;
2398                         case 1:
2399                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2400                                 freq_ptr = &od_table->GfxclkFmax;
2401                                 if (input[i + 1] < od_table->GfxclkFmin) {
2402                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2403                                                 input[i + 1],
2404                                                 od_table->GfxclkFmax);
2405                                         return -EINVAL;
2406                                 }
2407                                 break;
2408                         default:
2409                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2410                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2411                                 return -EINVAL;
2412                         }
2413                         ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2414                         if (ret)
2415                                 return ret;
2416                         *freq_ptr = input[i + 1];
2417                 }
2418                 break;
2419         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2420                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2421                         dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2422                         return -ENOTSUPP;
2423                 }
2424                 if (size < 2) {
2425                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2426                         return -EINVAL;
2427                 }
2428                 if (input[0] != 1) {
2429                         dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2430                         dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2431                         return -EINVAL;
2432                 }
2433                 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2434                 if (ret)
2435                         return ret;
2436                 od_table->UclkFmax = input[1];
2437                 break;
2438         case PP_OD_RESTORE_DEFAULT_TABLE:
2439                 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2440                         dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2441                         return -EINVAL;
2442                 }
2443                 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2444                 break;
2445         case PP_OD_COMMIT_DPM_TABLE:
2446                 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2447                         navi10_dump_od_table(smu, od_table);
2448                         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2449                         if (ret) {
2450                                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2451                                 return ret;
2452                         }
2453                         memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2454                         smu->user_dpm_profile.user_od = true;
2455
2456                         if (!memcmp(table_context->user_overdrive_table,
2457                                     table_context->boot_overdrive_table,
2458                                     sizeof(OverDriveTable_t)))
2459                                 smu->user_dpm_profile.user_od = false;
2460                 }
2461                 break;
2462         case PP_OD_EDIT_VDDC_CURVE:
2463                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2464                         dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2465                         return -ENOTSUPP;
2466                 }
2467                 if (size < 3) {
2468                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2469                         return -EINVAL;
2470                 }
2471                 if (!od_table) {
2472                         dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2473                         return -EINVAL;
2474                 }
2475
2476                 switch (input[0]) {
2477                 case 0:
2478                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2479                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2480                         freq_ptr = &od_table->GfxclkFreq1;
2481                         voltage_ptr = &od_table->GfxclkVolt1;
2482                         break;
2483                 case 1:
2484                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2485                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2486                         freq_ptr = &od_table->GfxclkFreq2;
2487                         voltage_ptr = &od_table->GfxclkVolt2;
2488                         break;
2489                 case 2:
2490                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2491                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2492                         freq_ptr = &od_table->GfxclkFreq3;
2493                         voltage_ptr = &od_table->GfxclkVolt3;
2494                         break;
2495                 default:
2496                         dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2497                         dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2498                         return -EINVAL;
2499                 }
2500                 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2501                 if (ret)
2502                         return ret;
2503                 // Allow setting zero to disable the OverDrive VDDC curve
2504                 if (input[2] != 0) {
2505                         ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2506                         if (ret)
2507                                 return ret;
2508                         *freq_ptr = input[1];
2509                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2510                         dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2511                 } else {
2512                         // If setting 0, disable all voltage curve settings
2513                         od_table->GfxclkVolt1 = 0;
2514                         od_table->GfxclkVolt2 = 0;
2515                         od_table->GfxclkVolt3 = 0;
2516                 }
2517                 navi10_dump_od_table(smu, od_table);
2518                 break;
2519         default:
2520                 return -ENOSYS;
2521         }
2522         return ret;
2523 }
2524
2525 static int navi10_run_btc(struct smu_context *smu)
2526 {
2527         int ret = 0;
2528
2529         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2530         if (ret)
2531                 dev_err(smu->adev->dev, "RunBtc failed!\n");
2532
2533         return ret;
2534 }
2535
2536 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
2537 {
2538         struct amdgpu_device *adev = smu->adev;
2539
2540         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2541                 return false;
2542
2543         if (adev->asic_type == CHIP_NAVI10 ||
2544             adev->asic_type == CHIP_NAVI14)
2545                 return true;
2546
2547         return false;
2548 }
2549
2550 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2551 {
2552         uint32_t uclk_count, uclk_min, uclk_max;
2553         int ret = 0;
2554
2555         /* This workaround can be applied only with uclk dpm enabled */
2556         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2557                 return 0;
2558
2559         ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2560         if (ret)
2561                 return ret;
2562
2563         ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2564         if (ret)
2565                 return ret;
2566
2567         /*
2568          * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2569          * This workaround is needed only when the max uclk frequency
2570          * not greater than that.
2571          */
2572         if (uclk_max > 0x2EE)
2573                 return 0;
2574
2575         ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2576         if (ret)
2577                 return ret;
2578
2579         /* Force UCLK out of the highest DPM */
2580         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2581         if (ret)
2582                 return ret;
2583
2584         /* Revert the UCLK Hardmax */
2585         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2586         if (ret)
2587                 return ret;
2588
2589         /*
2590          * In this case, SMU already disabled dummy pstate during enablement
2591          * of UCLK DPM, we have to re-enabled it.
2592          */
2593         return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2594 }
2595
2596 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu)
2597 {
2598         struct smu_table_context *smu_table = &smu->smu_table;
2599         struct smu_table *dummy_read_table =
2600                                 &smu_table->dummy_read_1_table;
2601         char *dummy_table = dummy_read_table->cpu_addr;
2602         int ret = 0;
2603         uint32_t i;
2604
2605         for (i = 0; i < 0x40000; i += 0x1000 * 2) {
2606                 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000);
2607                 dummy_table += 0x1000;
2608                 memcpy(dummy_table, &DbiPrbs7[0], 0x1000);
2609                 dummy_table += 0x1000;
2610         }
2611
2612         amdgpu_asic_flush_hdp(smu->adev, NULL);
2613
2614         ret = smu_cmn_send_smc_msg_with_param(smu,
2615                                               SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
2616                                               upper_32_bits(dummy_read_table->mc_address),
2617                                               NULL);
2618         if (ret)
2619                 return ret;
2620
2621         return smu_cmn_send_smc_msg_with_param(smu,
2622                                                SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
2623                                                lower_32_bits(dummy_read_table->mc_address),
2624                                                NULL);
2625 }
2626
2627 static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
2628 {
2629         struct amdgpu_device *adev = smu->adev;
2630         uint8_t umc_fw_greater_than_v136 = false;
2631         uint8_t umc_fw_disable_cdr = false;
2632         uint32_t pmfw_version;
2633         uint32_t param;
2634         int ret = 0;
2635
2636         if (!navi10_need_umc_cdr_workaround(smu))
2637                 return 0;
2638
2639         ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
2640         if (ret) {
2641                 dev_err(adev->dev, "Failed to get smu version!\n");
2642                 return ret;
2643         }
2644
2645         /*
2646          * The messages below are only supported by Navi10 42.53.0 and later
2647          * PMFWs and Navi14 53.29.0 and later PMFWs.
2648          * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
2649          * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
2650          * - PPSMC_MSG_GetUMCFWWA
2651          */
2652         if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) ||
2653             ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) {
2654                 ret = smu_cmn_send_smc_msg_with_param(smu,
2655                                                       SMU_MSG_GET_UMC_FW_WA,
2656                                                       0,
2657                                                       &param);
2658                 if (ret)
2659                         return ret;
2660
2661                 /* First bit indicates if the UMC f/w is above v137 */
2662                 umc_fw_greater_than_v136 = param & 0x1;
2663
2664                 /* Second bit indicates if hybrid-cdr is disabled */
2665                 umc_fw_disable_cdr = param & 0x2;
2666
2667                 /* w/a only allowed if UMC f/w is <= 136 */
2668                 if (umc_fw_greater_than_v136)
2669                         return 0;
2670
2671                 if (umc_fw_disable_cdr) {
2672                         if (adev->asic_type == CHIP_NAVI10)
2673                                 return navi10_umc_hybrid_cdr_workaround(smu);
2674                 } else {
2675                         return navi10_set_dummy_pstates_table_location(smu);
2676                 }
2677         } else {
2678                 if (adev->asic_type == CHIP_NAVI10)
2679                         return navi10_umc_hybrid_cdr_workaround(smu);
2680         }
2681
2682         return 0;
2683 }
2684
2685 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
2686                                              void **table)
2687 {
2688         struct smu_table_context *smu_table = &smu->smu_table;
2689         struct gpu_metrics_v1_3 *gpu_metrics =
2690                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2691         SmuMetrics_legacy_t metrics;
2692         int ret = 0;
2693
2694         mutex_lock(&smu->metrics_lock);
2695
2696         ret = smu_cmn_get_metrics_table_locked(smu,
2697                                                NULL,
2698                                                true);
2699         if (ret) {
2700                 mutex_unlock(&smu->metrics_lock);
2701                 return ret;
2702         }
2703
2704         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t));
2705
2706         mutex_unlock(&smu->metrics_lock);
2707
2708         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2709
2710         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2711         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2712         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2713         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2714         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2715         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2716
2717         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2718         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2719
2720         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2721
2722         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2723         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2724         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2725
2726         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2727         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2728         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2729         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2730         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2731
2732         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2733         gpu_metrics->indep_throttle_status =
2734                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2735                                                            navi1x_throttler_map);
2736
2737         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2738
2739         gpu_metrics->pcie_link_width =
2740                         smu_v11_0_get_current_pcie_link_width(smu);
2741         gpu_metrics->pcie_link_speed =
2742                         smu_v11_0_get_current_pcie_link_speed(smu);
2743
2744         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2745
2746         if (metrics.CurrGfxVoltageOffset)
2747                 gpu_metrics->voltage_gfx =
2748                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2749         if (metrics.CurrMemVidOffset)
2750                 gpu_metrics->voltage_mem =
2751                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2752         if (metrics.CurrSocVoltageOffset)
2753                 gpu_metrics->voltage_soc =
2754                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2755
2756         *table = (void *)gpu_metrics;
2757
2758         return sizeof(struct gpu_metrics_v1_3);
2759 }
2760
2761 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
2762                            struct i2c_msg *msg, int num_msgs)
2763 {
2764         struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
2765         struct smu_table_context *smu_table = &adev->smu.smu_table;
2766         struct smu_table *table = &smu_table->driver_table;
2767         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2768         int i, j, r, c;
2769         u16 dir;
2770
2771         req = kzalloc(sizeof(*req), GFP_KERNEL);
2772         if (!req)
2773                 return -ENOMEM;
2774
2775         req->I2CcontrollerPort = 0;
2776         req->I2CSpeed = I2C_SPEED_FAST_400K;
2777         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2778         dir = msg[0].flags & I2C_M_RD;
2779
2780         for (c = i = 0; i < num_msgs; i++) {
2781                 for (j = 0; j < msg[i].len; j++, c++) {
2782                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2783
2784                         if (!(msg[i].flags & I2C_M_RD)) {
2785                                 /* write */
2786                                 cmd->Cmd = I2C_CMD_WRITE;
2787                                 cmd->RegisterAddr = msg[i].buf[j];
2788                         }
2789
2790                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
2791                                 /* The direction changes.
2792                                  */
2793                                 dir = msg[i].flags & I2C_M_RD;
2794                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2795                         }
2796
2797                         req->NumCmds++;
2798
2799                         /*
2800                          * Insert STOP if we are at the last byte of either last
2801                          * message for the transaction or the client explicitly
2802                          * requires a STOP at this particular message.
2803                          */
2804                         if ((j == msg[i].len - 1) &&
2805                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2806                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2807                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2808                         }
2809                 }
2810         }
2811         mutex_lock(&adev->smu.mutex);
2812         r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2813         mutex_unlock(&adev->smu.mutex);
2814         if (r)
2815                 goto fail;
2816
2817         for (c = i = 0; i < num_msgs; i++) {
2818                 if (!(msg[i].flags & I2C_M_RD)) {
2819                         c += msg[i].len;
2820                         continue;
2821                 }
2822                 for (j = 0; j < msg[i].len; j++, c++) {
2823                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2824
2825                         msg[i].buf[j] = cmd->Data;
2826                 }
2827         }
2828         r = num_msgs;
2829 fail:
2830         kfree(req);
2831         return r;
2832 }
2833
2834 static u32 navi10_i2c_func(struct i2c_adapter *adap)
2835 {
2836         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2837 }
2838
2839
2840 static const struct i2c_algorithm navi10_i2c_algo = {
2841         .master_xfer = navi10_i2c_xfer,
2842         .functionality = navi10_i2c_func,
2843 };
2844
2845 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = {
2846         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2847         .max_read_len  = MAX_SW_I2C_COMMANDS,
2848         .max_write_len = MAX_SW_I2C_COMMANDS,
2849         .max_comb_1st_msg_len = 2,
2850         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2851 };
2852
2853 static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2854 {
2855         struct amdgpu_device *adev = to_amdgpu_device(control);
2856         int res;
2857
2858         control->owner = THIS_MODULE;
2859         control->class = I2C_CLASS_HWMON;
2860         control->dev.parent = &adev->pdev->dev;
2861         control->algo = &navi10_i2c_algo;
2862         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2863         control->quirks = &navi10_i2c_control_quirks;
2864
2865         res = i2c_add_adapter(control);
2866         if (res)
2867                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2868
2869         return res;
2870 }
2871
2872 static void navi10_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2873 {
2874         i2c_del_adapter(control);
2875 }
2876
2877 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
2878                                       void **table)
2879 {
2880         struct smu_table_context *smu_table = &smu->smu_table;
2881         struct gpu_metrics_v1_3 *gpu_metrics =
2882                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2883         SmuMetrics_t metrics;
2884         int ret = 0;
2885
2886         mutex_lock(&smu->metrics_lock);
2887
2888         ret = smu_cmn_get_metrics_table_locked(smu,
2889                                                NULL,
2890                                                true);
2891         if (ret) {
2892                 mutex_unlock(&smu->metrics_lock);
2893                 return ret;
2894         }
2895
2896         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
2897
2898         mutex_unlock(&smu->metrics_lock);
2899
2900         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2901
2902         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2903         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2904         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2905         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2906         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2907         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2908
2909         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2910         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2911
2912         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2913
2914         if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
2915                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2916         else
2917                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2918
2919         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2920         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2921
2922         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2923         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2924         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2925         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2926         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2927
2928         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2929         gpu_metrics->indep_throttle_status =
2930                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2931                                                            navi1x_throttler_map);
2932
2933         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2934
2935         gpu_metrics->pcie_link_width = metrics.PcieWidth;
2936         gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
2937
2938         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2939
2940         if (metrics.CurrGfxVoltageOffset)
2941                 gpu_metrics->voltage_gfx =
2942                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2943         if (metrics.CurrMemVidOffset)
2944                 gpu_metrics->voltage_mem =
2945                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2946         if (metrics.CurrSocVoltageOffset)
2947                 gpu_metrics->voltage_soc =
2948                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2949
2950         *table = (void *)gpu_metrics;
2951
2952         return sizeof(struct gpu_metrics_v1_3);
2953 }
2954
2955 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
2956                                              void **table)
2957 {
2958         struct smu_table_context *smu_table = &smu->smu_table;
2959         struct gpu_metrics_v1_3 *gpu_metrics =
2960                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2961         SmuMetrics_NV12_legacy_t metrics;
2962         int ret = 0;
2963
2964         mutex_lock(&smu->metrics_lock);
2965
2966         ret = smu_cmn_get_metrics_table_locked(smu,
2967                                                NULL,
2968                                                true);
2969         if (ret) {
2970                 mutex_unlock(&smu->metrics_lock);
2971                 return ret;
2972         }
2973
2974         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t));
2975
2976         mutex_unlock(&smu->metrics_lock);
2977
2978         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2979
2980         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2981         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2982         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2983         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2984         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2985         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2986
2987         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2988         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2989
2990         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2991
2992         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2993         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2994         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2995
2996         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2997         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2998         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2999         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3000
3001         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3002         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3003         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3004         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3005         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3006
3007         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3008         gpu_metrics->indep_throttle_status =
3009                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3010                                                            navi1x_throttler_map);
3011
3012         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3013
3014         gpu_metrics->pcie_link_width =
3015                         smu_v11_0_get_current_pcie_link_width(smu);
3016         gpu_metrics->pcie_link_speed =
3017                         smu_v11_0_get_current_pcie_link_speed(smu);
3018
3019         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3020
3021         if (metrics.CurrGfxVoltageOffset)
3022                 gpu_metrics->voltage_gfx =
3023                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3024         if (metrics.CurrMemVidOffset)
3025                 gpu_metrics->voltage_mem =
3026                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3027         if (metrics.CurrSocVoltageOffset)
3028                 gpu_metrics->voltage_soc =
3029                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3030
3031         *table = (void *)gpu_metrics;
3032
3033         return sizeof(struct gpu_metrics_v1_3);
3034 }
3035
3036 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
3037                                       void **table)
3038 {
3039         struct smu_table_context *smu_table = &smu->smu_table;
3040         struct gpu_metrics_v1_3 *gpu_metrics =
3041                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3042         SmuMetrics_NV12_t metrics;
3043         int ret = 0;
3044
3045         mutex_lock(&smu->metrics_lock);
3046
3047         ret = smu_cmn_get_metrics_table_locked(smu,
3048                                                NULL,
3049                                                true);
3050         if (ret) {
3051                 mutex_unlock(&smu->metrics_lock);
3052                 return ret;
3053         }
3054
3055         memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
3056
3057         mutex_unlock(&smu->metrics_lock);
3058
3059         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3060
3061         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3062         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3063         gpu_metrics->temperature_mem = metrics.TemperatureMem;
3064         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3065         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3066         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3067
3068         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3069         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3070
3071         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3072
3073         if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3074                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3075         else
3076                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3077
3078         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3079         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3080
3081         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3082         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3083         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3084         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3085
3086         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3087         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3088         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3089         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3090         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3091
3092         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3093         gpu_metrics->indep_throttle_status =
3094                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3095                                                            navi1x_throttler_map);
3096
3097         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3098
3099         gpu_metrics->pcie_link_width = metrics.PcieWidth;
3100         gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3101
3102         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3103
3104         if (metrics.CurrGfxVoltageOffset)
3105                 gpu_metrics->voltage_gfx =
3106                         (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3107         if (metrics.CurrMemVidOffset)
3108                 gpu_metrics->voltage_mem =
3109                         (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3110         if (metrics.CurrSocVoltageOffset)
3111                 gpu_metrics->voltage_soc =
3112                         (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3113
3114         *table = (void *)gpu_metrics;
3115
3116         return sizeof(struct gpu_metrics_v1_3);
3117 }
3118
3119 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
3120                                       void **table)
3121 {
3122         struct amdgpu_device *adev = smu->adev;
3123         uint32_t smu_version;
3124         int ret = 0;
3125
3126         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3127         if (ret) {
3128                 dev_err(adev->dev, "Failed to get smu version!\n");
3129                 return ret;
3130         }
3131
3132         switch (adev->asic_type) {
3133         case CHIP_NAVI12:
3134                 if (smu_version > 0x00341C00)
3135                         ret = navi12_get_gpu_metrics(smu, table);
3136                 else
3137                         ret = navi12_get_legacy_gpu_metrics(smu, table);
3138                 break;
3139         case CHIP_NAVI10:
3140         case CHIP_NAVI14:
3141         default:
3142                 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
3143                       ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
3144                         ret = navi10_get_gpu_metrics(smu, table);
3145                 else
3146                         ret =navi10_get_legacy_gpu_metrics(smu, table);
3147                 break;
3148         }
3149
3150         return ret;
3151 }
3152
3153 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
3154 {
3155         struct smu_table_context *table_context = &smu->smu_table;
3156         PPTable_t *smc_pptable = table_context->driver_pptable;
3157         struct amdgpu_device *adev = smu->adev;
3158         uint32_t param = 0;
3159
3160         /* Navi12 does not support this */
3161         if (adev->asic_type == CHIP_NAVI12)
3162                 return 0;
3163
3164         /*
3165          * Skip the MGpuFanBoost setting for those ASICs
3166          * which do not support it
3167          */
3168         if (!smc_pptable->MGpuFanBoostLimitRpm)
3169                 return 0;
3170
3171         /* Workaround for WS SKU */
3172         if (adev->pdev->device == 0x7312 &&
3173             adev->pdev->revision == 0)
3174                 param = 0xD188;
3175
3176         return smu_cmn_send_smc_msg_with_param(smu,
3177                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
3178                                                param,
3179                                                NULL);
3180 }
3181
3182 static int navi10_post_smu_init(struct smu_context *smu)
3183 {
3184         struct amdgpu_device *adev = smu->adev;
3185         int ret = 0;
3186
3187         if (amdgpu_sriov_vf(adev))
3188                 return 0;
3189
3190         ret = navi10_run_umc_cdr_workaround(smu);
3191         if (ret) {
3192                 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
3193                 return ret;
3194         }
3195
3196         if (!smu->dc_controlled_by_gpio) {
3197                 /*
3198                  * For Navi1X, manually switch it to AC mode as PMFW
3199                  * may boot it with DC mode.
3200                  */
3201                 ret = smu_v11_0_set_power_source(smu,
3202                                                  adev->pm.ac_power ?
3203                                                  SMU_POWER_SOURCE_AC :
3204                                                  SMU_POWER_SOURCE_DC);
3205                 if (ret) {
3206                         dev_err(adev->dev, "Failed to switch to %s mode!\n",
3207                                         adev->pm.ac_power ? "AC" : "DC");
3208                         return ret;
3209                 }
3210         }
3211
3212         return ret;
3213 }
3214
3215 static const struct pptable_funcs navi10_ppt_funcs = {
3216         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3217         .set_default_dpm_table = navi10_set_default_dpm_table,
3218         .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
3219         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
3220         .i2c_init = navi10_i2c_control_init,
3221         .i2c_fini = navi10_i2c_control_fini,
3222         .print_clk_levels = navi10_print_clk_levels,
3223         .force_clk_levels = navi10_force_clk_levels,
3224         .populate_umd_state_clk = navi10_populate_umd_state_clk,
3225         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
3226         .pre_display_config_changed = navi10_pre_display_config_changed,
3227         .display_config_changed = navi10_display_config_changed,
3228         .notify_smc_display_config = navi10_notify_smc_display_config,
3229         .is_dpm_running = navi10_is_dpm_running,
3230         .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3231         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
3232         .get_power_profile_mode = navi10_get_power_profile_mode,
3233         .set_power_profile_mode = navi10_set_power_profile_mode,
3234         .set_watermarks_table = navi10_set_watermarks_table,
3235         .read_sensor = navi10_read_sensor,
3236         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
3237         .set_performance_level = smu_v11_0_set_performance_level,
3238         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
3239         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
3240         .get_power_limit = navi10_get_power_limit,
3241         .update_pcie_parameters = navi10_update_pcie_parameters,
3242         .init_microcode = smu_v11_0_init_microcode,
3243         .load_microcode = smu_v11_0_load_microcode,
3244         .fini_microcode = smu_v11_0_fini_microcode,
3245         .init_smc_tables = navi10_init_smc_tables,
3246         .fini_smc_tables = smu_v11_0_fini_smc_tables,
3247         .init_power = smu_v11_0_init_power,
3248         .fini_power = smu_v11_0_fini_power,
3249         .check_fw_status = smu_v11_0_check_fw_status,
3250         .setup_pptable = navi10_setup_pptable,
3251         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3252         .check_fw_version = smu_v11_0_check_fw_version,
3253         .write_pptable = smu_cmn_write_pptable,
3254         .set_driver_table_location = smu_v11_0_set_driver_table_location,
3255         .set_tool_table_location = smu_v11_0_set_tool_table_location,
3256         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3257         .system_features_control = smu_v11_0_system_features_control,
3258         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3259         .send_smc_msg = smu_cmn_send_smc_msg,
3260         .init_display_count = smu_v11_0_init_display_count,
3261         .set_allowed_mask = smu_v11_0_set_allowed_mask,
3262         .get_enabled_mask = smu_cmn_get_enabled_mask,
3263         .feature_is_enabled = smu_cmn_feature_is_enabled,
3264         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3265         .notify_display_change = smu_v11_0_notify_display_change,
3266         .set_power_limit = smu_v11_0_set_power_limit,
3267         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3268         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3269         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3270         .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
3271         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3272         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3273         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3274         .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3275         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3276         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3277         .gfx_off_control = smu_v11_0_gfx_off_control,
3278         .register_irq_handler = smu_v11_0_register_irq_handler,
3279         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3280         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3281         .baco_is_support = smu_v11_0_baco_is_support,
3282         .baco_get_state = smu_v11_0_baco_get_state,
3283         .baco_set_state = smu_v11_0_baco_set_state,
3284         .baco_enter = navi10_baco_enter,
3285         .baco_exit = navi10_baco_exit,
3286         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3287         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3288         .set_default_od_settings = navi10_set_default_od_settings,
3289         .od_edit_dpm_table = navi10_od_edit_dpm_table,
3290         .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3291         .run_btc = navi10_run_btc,
3292         .set_power_source = smu_v11_0_set_power_source,
3293         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3294         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3295         .get_gpu_metrics = navi1x_get_gpu_metrics,
3296         .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
3297         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3298         .deep_sleep_control = smu_v11_0_deep_sleep_control,
3299         .get_fan_parameters = navi10_get_fan_parameters,
3300         .post_init = navi10_post_smu_init,
3301         .interrupt_work = smu_v11_0_interrupt_work,
3302         .set_mp1_state = smu_cmn_set_mp1_state,
3303 };
3304
3305 void navi10_set_ppt_funcs(struct smu_context *smu)
3306 {
3307         smu->ppt_funcs = &navi10_ppt_funcs;
3308         smu->message_map = navi10_message_map;
3309         smu->clock_map = navi10_clk_map;
3310         smu->feature_map = navi10_feature_mask_map;
3311         smu->table_map = navi10_table_map;
3312         smu->pwr_src_map = navi10_pwr_src_map;
3313         smu->workload_map = navi10_workload_map;
3314 }