drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "vangogh_ppt.h"
  37 #include "aldebaran_ppt.h"
  38 #include "yellow_carp_ppt.h"
  39 #include "cyan_skillfish_ppt.h"
  40 #include "amd_pcie.h"
  41
  42 /*
  43  * DO NOT use these for err/warn/info/debug messages.
  44  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  45  * They are more MGPU friendly.
  46  */
  47 #undef pr_err
  48 #undef pr_warn
  49 #undef pr_info
  50 #undef pr_debug
  51
  52 static const struct amd_pm_funcs swsmu_pm_funcs;
  53 static int smu_force_smuclk_levels(struct smu_context *smu,
  54                                    enum smu_clk_type clk_type,
  55                                    uint32_t mask);
  56 static int smu_handle_task(struct smu_context *smu,
  57                            enum amd_dpm_forced_level level,
  58                            enum amd_pp_task task_id,
  59                            bool lock_needed);
  60 static int smu_reset(struct smu_context *smu);
  61 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
  62 static int smu_set_fan_control_mode(struct smu_context *smu, int value);
  63 static int smu_set_power_limit(void *handle, uint32_t limit);
  64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
  65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
  66
  67 static int smu_sys_get_pp_feature_mask(void *handle,
  68                                        char *buf)
  69 {
  70         struct smu_context *smu = handle;
  71         int size = 0;
  72
  73         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  74                 return -EOPNOTSUPP;
  75
  76         mutex_lock(&smu->mutex);
  77
  78         size = smu_get_pp_feature_mask(smu, buf);
  79
  80         mutex_unlock(&smu->mutex);
  81
  82         return size;
  83 }
  84
  85 static int smu_sys_set_pp_feature_mask(void *handle,
  86                                        uint64_t new_mask)
  87 {
  88         struct smu_context *smu = handle;
  89         int ret = 0;
  90
  91         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  92                 return -EOPNOTSUPP;
  93
  94         mutex_lock(&smu->mutex);
  95
  96         ret = smu_set_pp_feature_mask(smu, new_mask);
  97
  98         mutex_unlock(&smu->mutex);
  99
 100         return ret;
 101 }
 102
 103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
 104 {
 105         int ret = 0;
 106         struct smu_context *smu = &adev->smu;
 107
 108         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
 109                 *value = smu_get_gfx_off_status(smu);
 110         else
 111                 ret = -EINVAL;
 112
 113         return ret;
 114 }
 115
 116 int smu_set_soft_freq_range(struct smu_context *smu,
 117                             enum smu_clk_type clk_type,
 118                             uint32_t min,
 119                             uint32_t max)
 120 {
 121         int ret = 0;
 122
 123         mutex_lock(&smu->mutex);
 124
 125         if (smu->ppt_funcs->set_soft_freq_limited_range)
 126                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 127                                                                   clk_type,
 128                                                                   min,
 129                                                                   max);
 130
 131         mutex_unlock(&smu->mutex);
 132
 133         return ret;
 134 }
 135
 136 int smu_get_dpm_freq_range(struct smu_context *smu,
 137                            enum smu_clk_type clk_type,
 138                            uint32_t *min,
 139                            uint32_t *max)
 140 {
 141         int ret = 0;
 142
 143         if (!min && !max)
 144                 return -EINVAL;
 145
 146         mutex_lock(&smu->mutex);
 147
 148         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 149                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 150                                                             clk_type,
 151                                                             min,
 152                                                             max);
 153
 154         mutex_unlock(&smu->mutex);
 155
 156         return ret;
 157 }
 158
 159 static u32 smu_get_mclk(void *handle, bool low)
 160 {
 161         struct smu_context *smu = handle;
 162         uint32_t clk_freq;
 163         int ret = 0;
 164
 165         ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
 166                                      low ? &clk_freq : NULL,
 167                                      !low ? &clk_freq : NULL);
 168         if (ret)
 169                 return 0;
 170         return clk_freq * 100;
 171 }
 172
 173 static u32 smu_get_sclk(void *handle, bool low)
 174 {
 175         struct smu_context *smu = handle;
 176         uint32_t clk_freq;
 177         int ret = 0;
 178
 179         ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
 180                                      low ? &clk_freq : NULL,
 181                                      !low ? &clk_freq : NULL);
 182         if (ret)
 183                 return 0;
 184         return clk_freq * 100;
 185 }
 186
 187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 188                                          bool enable)
 189 {
 190         struct smu_power_context *smu_power = &smu->smu_power;
 191         struct smu_power_gate *power_gate = &smu_power->power_gate;
 192         int ret = 0;
 193
 194         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 195                 return 0;
 196
 197         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 198                 return 0;
 199
 200         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 201         if (!ret)
 202                 atomic_set(&power_gate->vcn_gated, !enable);
 203
 204         return ret;
 205 }
 206
 207 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 208                                   bool enable)
 209 {
 210         struct smu_power_context *smu_power = &smu->smu_power;
 211         struct smu_power_gate *power_gate = &smu_power->power_gate;
 212         int ret = 0;
 213
 214         mutex_lock(&power_gate->vcn_gate_lock);
 215
 216         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 217
 218         mutex_unlock(&power_gate->vcn_gate_lock);
 219
 220         return ret;
 221 }
 222
 223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 224                                           bool enable)
 225 {
 226         struct smu_power_context *smu_power = &smu->smu_power;
 227         struct smu_power_gate *power_gate = &smu_power->power_gate;
 228         int ret = 0;
 229
 230         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 231                 return 0;
 232
 233         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 234                 return 0;
 235
 236         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 237         if (!ret)
 238                 atomic_set(&power_gate->jpeg_gated, !enable);
 239
 240         return ret;
 241 }
 242
 243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 244                                    bool enable)
 245 {
 246         struct smu_power_context *smu_power = &smu->smu_power;
 247         struct smu_power_gate *power_gate = &smu_power->power_gate;
 248         int ret = 0;
 249
 250         mutex_lock(&power_gate->jpeg_gate_lock);
 251
 252         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 253
 254         mutex_unlock(&power_gate->jpeg_gate_lock);
 255
 256         return ret;
 257 }
 258
 259 /**
 260  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 261  *
 262  * @handle:        smu_context pointer
 263  * @block_type: the IP block to power gate/ungate
 264  * @gate:       to power gate if true, ungate otherwise
 265  *
 266  * This API uses no smu->mutex lock protection due to:
 267  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 268  *    This is guarded to be race condition free by the caller.
 269  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 270  *    Under this case, the smu->mutex lock protection is already enforced on
 271  *    the parent API smu_force_performance_level of the call path.
 272  */
 273 static int smu_dpm_set_power_gate(void *handle,
 274                                   uint32_t block_type,
 275                                   bool gate)
 276 {
 277         struct smu_context *smu = handle;
 278         int ret = 0;
 279
 280         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 281                 return -EOPNOTSUPP;
 282
 283         switch (block_type) {
 284         /*
 285          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 286          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 287          */
 288         case AMD_IP_BLOCK_TYPE_UVD:
 289         case AMD_IP_BLOCK_TYPE_VCN:
 290                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 291                 if (ret)
 292                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 293                                 gate ? "gate" : "ungate");
 294                 break;
 295         case AMD_IP_BLOCK_TYPE_GFX:
 296                 ret = smu_gfx_off_control(smu, gate);
 297                 if (ret)
 298                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 299                                 gate ? "enable" : "disable");
 300                 break;
 301         case AMD_IP_BLOCK_TYPE_SDMA:
 302                 ret = smu_powergate_sdma(smu, gate);
 303                 if (ret)
 304                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 305                                 gate ? "gate" : "ungate");
 306                 break;
 307         case AMD_IP_BLOCK_TYPE_JPEG:
 308                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 309                 if (ret)
 310                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 311                                 gate ? "gate" : "ungate");
 312                 break;
 313         default:
 314                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 315                 return -EINVAL;
 316         }
 317
 318         return ret;
 319 }
 320
 321 /**
 322  * smu_set_user_clk_dependencies - set user profile clock dependencies
 323  *
 324  * @smu:        smu_context pointer
 325  * @clk:        enum smu_clk_type type
 326  *
 327  * Enable/Disable the clock dependency for the @clk type.
 328  */
 329 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
 330 {
 331         if (smu->adev->in_suspend)
 332                 return;
 333
 334         if (clk == SMU_MCLK) {
 335                 smu->user_dpm_profile.clk_dependency = 0;
 336                 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
 337         } else if (clk == SMU_FCLK) {
 338                 /* MCLK takes precedence over FCLK */
 339                 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
 340                         return;
 341
 342                 smu->user_dpm_profile.clk_dependency = 0;
 343                 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
 344         } else if (clk == SMU_SOCCLK) {
 345                 /* MCLK takes precedence over SOCCLK */
 346                 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
 347                         return;
 348
 349                 smu->user_dpm_profile.clk_dependency = 0;
 350                 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
 351         } else
 352                 /* Add clk dependencies here, if any */
 353                 return;
 354 }
 355
 356 /**
 357  * smu_restore_dpm_user_profile - reinstate user dpm profile
 358  *
 359  * @smu:        smu_context pointer
 360  *
 361  * Restore the saved user power configurations include power limit,
 362  * clock frequencies, fan control mode and fan speed.
 363  */
 364 static void smu_restore_dpm_user_profile(struct smu_context *smu)
 365 {
 366         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 367         int ret = 0;
 368
 369         if (!smu->adev->in_suspend)
 370                 return;
 371
 372         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 373                 return;
 374
 375         /* Enable restore flag */
 376         smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
 377
 378         /* set the user dpm power limit */
 379         if (smu->user_dpm_profile.power_limit) {
 380                 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
 381                 if (ret)
 382                         dev_err(smu->adev->dev, "Failed to set power limit value\n");
 383         }
 384
 385         /* set the user dpm clock configurations */
 386         if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 387                 enum smu_clk_type clk_type;
 388
 389                 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
 390                         /*
 391                          * Iterate over smu clk type and force the saved user clk
 392                          * configs, skip if clock dependency is enabled
 393                          */
 394                         if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
 395                                         smu->user_dpm_profile.clk_mask[clk_type]) {
 396                                 ret = smu_force_smuclk_levels(smu, clk_type,
 397                                                 smu->user_dpm_profile.clk_mask[clk_type]);
 398                                 if (ret)
 399                                         dev_err(smu->adev->dev,
 400                                                 "Failed to set clock type = %d\n", clk_type);
 401                         }
 402                 }
 403         }
 404
 405         /* set the user dpm fan configurations */
 406         if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
 407             smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
 408                 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
 409                 if (ret) {
 410                         smu->user_dpm_profile.fan_speed_pwm = 0;
 411                         smu->user_dpm_profile.fan_speed_rpm = 0;
 412                         smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
 413                         dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
 414                 }
 415
 416                 if (smu->user_dpm_profile.fan_speed_pwm) {
 417                         ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
 418                         if (ret)
 419                                 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
 420                 }
 421
 422                 if (smu->user_dpm_profile.fan_speed_rpm) {
 423                         ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
 424                         if (ret)
 425                                 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
 426                 }
 427         }
 428
 429         /* Restore user customized OD settings */
 430         if (smu->user_dpm_profile.user_od) {
 431                 if (smu->ppt_funcs->restore_user_od_settings) {
 432                         ret = smu->ppt_funcs->restore_user_od_settings(smu);
 433                         if (ret)
 434                                 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
 435                 }
 436         }
 437
 438         /* Disable restore flag */
 439         smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
 440 }
 441
 442 static int smu_get_power_num_states(void *handle,
 443                                     struct pp_states_info *state_info)
 444 {
 445         if (!state_info)
 446                 return -EINVAL;
 447
 448         /* not support power state */
 449         memset(state_info, 0, sizeof(struct pp_states_info));
 450         state_info->nums = 1;
 451         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 452
 453         return 0;
 454 }
 455
 456 bool is_support_sw_smu(struct amdgpu_device *adev)
 457 {
 458         if (adev->asic_type >= CHIP_ARCTURUS)
 459                 return true;
 460
 461         return false;
 462 }
 463
 464 bool is_support_cclk_dpm(struct amdgpu_device *adev)
 465 {
 466         struct smu_context *smu = &adev->smu;
 467
 468         if (!is_support_sw_smu(adev))
 469                 return false;
 470
 471         if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
 472                 return false;
 473
 474         return true;
 475 }
 476
 477
 478 static int smu_sys_get_pp_table(void *handle,
 479                                 char **table)
 480 {
 481         struct smu_context *smu = handle;
 482         struct smu_table_context *smu_table = &smu->smu_table;
 483         uint32_t powerplay_table_size;
 484
 485         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 486                 return -EOPNOTSUPP;
 487
 488         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 489                 return -EINVAL;
 490
 491         mutex_lock(&smu->mutex);
 492
 493         if (smu_table->hardcode_pptable)
 494                 *table = smu_table->hardcode_pptable;
 495         else
 496                 *table = smu_table->power_play_table;
 497
 498         powerplay_table_size = smu_table->power_play_table_size;
 499
 500         mutex_unlock(&smu->mutex);
 501
 502         return powerplay_table_size;
 503 }
 504
 505 static int smu_sys_set_pp_table(void *handle,
 506                                 const char *buf,
 507                                 size_t size)
 508 {
 509         struct smu_context *smu = handle;
 510         struct smu_table_context *smu_table = &smu->smu_table;
 511         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 512         int ret = 0;
 513
 514         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 515                 return -EOPNOTSUPP;
 516
 517         if (header->usStructureSize != size) {
 518                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 519                 return -EIO;
 520         }
 521
 522         mutex_lock(&smu->mutex);
 523         if (!smu_table->hardcode_pptable)
 524                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 525         if (!smu_table->hardcode_pptable) {
 526                 ret = -ENOMEM;
 527                 goto failed;
 528         }
 529
 530         memcpy(smu_table->hardcode_pptable, buf, size);
 531         smu_table->power_play_table = smu_table->hardcode_pptable;
 532         smu_table->power_play_table_size = size;
 533
 534         /*
 535          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 536          * skipped) may be needed for custom pptable uploading.
 537          */
 538         smu->uploading_custom_pp_table = true;
 539
 540         ret = smu_reset(smu);
 541         if (ret)
 542                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 543
 544         smu->uploading_custom_pp_table = false;
 545
 546 failed:
 547         mutex_unlock(&smu->mutex);
 548         return ret;
 549 }
 550
 551 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 552 {
 553         struct smu_feature *feature = &smu->smu_feature;
 554         int ret = 0;
 555         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 556
 557         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 558
 559         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 560                                              SMU_FEATURE_MAX/32);
 561         if (ret)
 562                 return ret;
 563
 564         bitmap_or(feature->allowed, feature->allowed,
 565                       (unsigned long *)allowed_feature_mask,
 566                       feature->feature_num);
 567
 568         return ret;
 569 }
 570
 571 static int smu_set_funcs(struct amdgpu_device *adev)
 572 {
 573         struct smu_context *smu = &adev->smu;
 574
 575         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 576                 smu->od_enabled = true;
 577
 578         switch (adev->asic_type) {
 579         case CHIP_NAVI10:
 580         case CHIP_NAVI14:
 581         case CHIP_NAVI12:
 582                 navi10_set_ppt_funcs(smu);
 583                 break;
 584         case CHIP_ARCTURUS:
 585                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 586                 arcturus_set_ppt_funcs(smu);
 587                 /* OD is not supported on Arcturus */
 588                 smu->od_enabled =false;
 589                 break;
 590         case CHIP_SIENNA_CICHLID:
 591         case CHIP_NAVY_FLOUNDER:
 592         case CHIP_DIMGREY_CAVEFISH:
 593         case CHIP_BEIGE_GOBY:
 594                 sienna_cichlid_set_ppt_funcs(smu);
 595                 break;
 596         case CHIP_ALDEBARAN:
 597                 aldebaran_set_ppt_funcs(smu);
 598                 /* Enable pp_od_clk_voltage node */
 599                 smu->od_enabled = true;
 600                 break;
 601         case CHIP_RENOIR:
 602                 renoir_set_ppt_funcs(smu);
 603                 break;
 604         case CHIP_VANGOGH:
 605                 vangogh_set_ppt_funcs(smu);
 606                 break;
 607         case CHIP_YELLOW_CARP:
 608                 yellow_carp_set_ppt_funcs(smu);
 609                 break;
 610         case CHIP_CYAN_SKILLFISH:
 611                 cyan_skillfish_set_ppt_funcs(smu);
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         return 0;
 618 }
 619
 620 static int smu_early_init(void *handle)
 621 {
 622         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 623         struct smu_context *smu = &adev->smu;
 624
 625         smu->adev = adev;
 626         smu->pm_enabled = !!amdgpu_dpm;
 627         smu->is_apu = false;
 628         mutex_init(&smu->mutex);
 629         mutex_init(&smu->smu_baco.mutex);
 630         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 631         smu->smu_baco.platform_support = false;
 632         smu->user_dpm_profile.fan_mode = -1;
 633
 634         adev->powerplay.pp_handle = smu;
 635         adev->powerplay.pp_funcs = &swsmu_pm_funcs;
 636
 637         return smu_set_funcs(adev);
 638 }
 639
 640 static int smu_set_default_dpm_table(struct smu_context *smu)
 641 {
 642         struct smu_power_context *smu_power = &smu->smu_power;
 643         struct smu_power_gate *power_gate = &smu_power->power_gate;
 644         int vcn_gate, jpeg_gate;
 645         int ret = 0;
 646
 647         if (!smu->ppt_funcs->set_default_dpm_table)
 648                 return 0;
 649
 650         mutex_lock(&power_gate->vcn_gate_lock);
 651         mutex_lock(&power_gate->jpeg_gate_lock);
 652
 653         vcn_gate = atomic_read(&power_gate->vcn_gated);
 654         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 655
 656         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 657         if (ret)
 658                 goto err0_out;
 659
 660         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 661         if (ret)
 662                 goto err1_out;
 663
 664         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 665         if (ret)
 666                 dev_err(smu->adev->dev,
 667                         "Failed to setup default dpm clock tables!\n");
 668
 669         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 670 err1_out:
 671         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 672 err0_out:
 673         mutex_unlock(&power_gate->jpeg_gate_lock);
 674         mutex_unlock(&power_gate->vcn_gate_lock);
 675
 676         return ret;
 677 }
 678
 679
 680 static int smu_late_init(void *handle)
 681 {
 682         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 683         struct smu_context *smu = &adev->smu;
 684         int ret = 0;
 685
 686         smu_set_fine_grain_gfx_freq_parameters(smu);
 687
 688         if (!smu->pm_enabled)
 689                 return 0;
 690
 691         ret = smu_post_init(smu);
 692         if (ret) {
 693                 dev_err(adev->dev, "Failed to post smu init!\n");
 694                 return ret;
 695         }
 696
 697         if (adev->asic_type == CHIP_YELLOW_CARP)
 698                 return 0;
 699
 700         if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
 701                 ret = smu_set_default_od_settings(smu);
 702                 if (ret) {
 703                         dev_err(adev->dev, "Failed to setup default OD settings!\n");
 704                         return ret;
 705                 }
 706         }
 707
 708         ret = smu_populate_umd_state_clk(smu);
 709         if (ret) {
 710                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 711                 return ret;
 712         }
 713
 714         ret = smu_get_asic_power_limits(smu,
 715                                         &smu->current_power_limit,
 716                                         &smu->default_power_limit,
 717                                         &smu->max_power_limit);
 718         if (ret) {
 719                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 720                 return ret;
 721         }
 722
 723         if (!amdgpu_sriov_vf(adev))
 724                 smu_get_unique_id(smu);
 725
 726         smu_get_fan_parameters(smu);
 727
 728         smu_handle_task(&adev->smu,
 729                         smu->smu_dpm.dpm_level,
 730                         AMD_PP_TASK_COMPLETE_INIT,
 731                         false);
 732
 733         smu_restore_dpm_user_profile(smu);
 734
 735         return 0;
 736 }
 737
 738 static int smu_init_fb_allocations(struct smu_context *smu)
 739 {
 740         struct amdgpu_device *adev = smu->adev;
 741         struct smu_table_context *smu_table = &smu->smu_table;
 742         struct smu_table *tables = smu_table->tables;
 743         struct smu_table *driver_table = &(smu_table->driver_table);
 744         uint32_t max_table_size = 0;
 745         int ret, i;
 746
 747         /* VRAM allocation for tool table */
 748         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 749                 ret = amdgpu_bo_create_kernel(adev,
 750                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 751                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 752                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 753                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 754                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 755                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 756                 if (ret) {
 757                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 758                         return ret;
 759                 }
 760         }
 761
 762         /* VRAM allocation for driver table */
 763         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 764                 if (tables[i].size == 0)
 765                         continue;
 766
 767                 if (i == SMU_TABLE_PMSTATUSLOG)
 768                         continue;
 769
 770                 if (max_table_size < tables[i].size)
 771                         max_table_size = tables[i].size;
 772         }
 773
 774         driver_table->size = max_table_size;
 775         driver_table->align = PAGE_SIZE;
 776         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 777
 778         ret = amdgpu_bo_create_kernel(adev,
 779                                       driver_table->size,
 780                                       driver_table->align,
 781                                       driver_table->domain,
 782                                       &driver_table->bo,
 783                                       &driver_table->mc_address,
 784                                       &driver_table->cpu_addr);
 785         if (ret) {
 786                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 787                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 788                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 789                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 790                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 791         }
 792
 793         return ret;
 794 }
 795
 796 static int smu_fini_fb_allocations(struct smu_context *smu)
 797 {
 798         struct smu_table_context *smu_table = &smu->smu_table;
 799         struct smu_table *tables = smu_table->tables;
 800         struct smu_table *driver_table = &(smu_table->driver_table);
 801
 802         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 803                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 804                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 805                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 806
 807         amdgpu_bo_free_kernel(&driver_table->bo,
 808                               &driver_table->mc_address,
 809                               &driver_table->cpu_addr);
 810
 811         return 0;
 812 }
 813
 814 /**
 815  * smu_alloc_memory_pool - allocate memory pool in the system memory
 816  *
 817  * @smu: amdgpu_device pointer
 818  *
 819  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 820  * and DramLogSetDramAddr can notify it changed.
 821  *
 822  * Returns 0 on success, error on failure.
 823  */
 824 static int smu_alloc_memory_pool(struct smu_context *smu)
 825 {
 826         struct amdgpu_device *adev = smu->adev;
 827         struct smu_table_context *smu_table = &smu->smu_table;
 828         struct smu_table *memory_pool = &smu_table->memory_pool;
 829         uint64_t pool_size = smu->pool_size;
 830         int ret = 0;
 831
 832         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 833                 return ret;
 834
 835         memory_pool->size = pool_size;
 836         memory_pool->align = PAGE_SIZE;
 837         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 838
 839         switch (pool_size) {
 840         case SMU_MEMORY_POOL_SIZE_256_MB:
 841         case SMU_MEMORY_POOL_SIZE_512_MB:
 842         case SMU_MEMORY_POOL_SIZE_1_GB:
 843         case SMU_MEMORY_POOL_SIZE_2_GB:
 844                 ret = amdgpu_bo_create_kernel(adev,
 845                                               memory_pool->size,
 846                                               memory_pool->align,
 847                                               memory_pool->domain,
 848                                               &memory_pool->bo,
 849                                               &memory_pool->mc_address,
 850                                               &memory_pool->cpu_addr);
 851                 if (ret)
 852                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 853                 break;
 854         default:
 855                 break;
 856         }
 857
 858         return ret;
 859 }
 860
 861 static int smu_free_memory_pool(struct smu_context *smu)
 862 {
 863         struct smu_table_context *smu_table = &smu->smu_table;
 864         struct smu_table *memory_pool = &smu_table->memory_pool;
 865
 866         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 867                 return 0;
 868
 869         amdgpu_bo_free_kernel(&memory_pool->bo,
 870                               &memory_pool->mc_address,
 871                               &memory_pool->cpu_addr);
 872
 873         memset(memory_pool, 0, sizeof(struct smu_table));
 874
 875         return 0;
 876 }
 877
 878 static int smu_alloc_dummy_read_table(struct smu_context *smu)
 879 {
 880         struct smu_table_context *smu_table = &smu->smu_table;
 881         struct smu_table *dummy_read_1_table =
 882                         &smu_table->dummy_read_1_table;
 883         struct amdgpu_device *adev = smu->adev;
 884         int ret = 0;
 885
 886         dummy_read_1_table->size = 0x40000;
 887         dummy_read_1_table->align = PAGE_SIZE;
 888         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 889
 890         ret = amdgpu_bo_create_kernel(adev,
 891                                       dummy_read_1_table->size,
 892                                       dummy_read_1_table->align,
 893                                       dummy_read_1_table->domain,
 894                                       &dummy_read_1_table->bo,
 895                                       &dummy_read_1_table->mc_address,
 896                                       &dummy_read_1_table->cpu_addr);
 897         if (ret)
 898                 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
 899
 900         return ret;
 901 }
 902
 903 static void smu_free_dummy_read_table(struct smu_context *smu)
 904 {
 905         struct smu_table_context *smu_table = &smu->smu_table;
 906         struct smu_table *dummy_read_1_table =
 907                         &smu_table->dummy_read_1_table;
 908
 909
 910         amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
 911                               &dummy_read_1_table->mc_address,
 912                               &dummy_read_1_table->cpu_addr);
 913
 914         memset(dummy_read_1_table, 0, sizeof(struct smu_table));
 915 }
 916
 917 static int smu_smc_table_sw_init(struct smu_context *smu)
 918 {
 919         int ret;
 920
 921         /**
 922          * Create smu_table structure, and init smc tables such as
 923          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 924          */
 925         ret = smu_init_smc_tables(smu);
 926         if (ret) {
 927                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 928                 return ret;
 929         }
 930
 931         /**
 932          * Create smu_power_context structure, and allocate smu_dpm_context and
 933          * context size to fill the smu_power_context data.
 934          */
 935         ret = smu_init_power(smu);
 936         if (ret) {
 937                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 938                 return ret;
 939         }
 940
 941         /*
 942          * allocate vram bos to store smc table contents.
 943          */
 944         ret = smu_init_fb_allocations(smu);
 945         if (ret)
 946                 return ret;
 947
 948         ret = smu_alloc_memory_pool(smu);
 949         if (ret)
 950                 return ret;
 951
 952         ret = smu_alloc_dummy_read_table(smu);
 953         if (ret)
 954                 return ret;
 955
 956         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 957         if (ret)
 958                 return ret;
 959
 960         return 0;
 961 }
 962
 963 static int smu_smc_table_sw_fini(struct smu_context *smu)
 964 {
 965         int ret;
 966
 967         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 968
 969         smu_free_dummy_read_table(smu);
 970
 971         ret = smu_free_memory_pool(smu);
 972         if (ret)
 973                 return ret;
 974
 975         ret = smu_fini_fb_allocations(smu);
 976         if (ret)
 977                 return ret;
 978
 979         ret = smu_fini_power(smu);
 980         if (ret) {
 981                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 982                 return ret;
 983         }
 984
 985         ret = smu_fini_smc_tables(smu);
 986         if (ret) {
 987                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 988                 return ret;
 989         }
 990
 991         return 0;
 992 }
 993
 994 static void smu_throttling_logging_work_fn(struct work_struct *work)
 995 {
 996         struct smu_context *smu = container_of(work, struct smu_context,
 997                                                throttling_logging_work);
 998
 999         smu_log_thermal_throttling(smu);
1000 }
1001
1002 static void smu_interrupt_work_fn(struct work_struct *work)
1003 {
1004         struct smu_context *smu = container_of(work, struct smu_context,
1005                                                interrupt_work);
1006
1007         mutex_lock(&smu->mutex);
1008
1009         if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1010                 smu->ppt_funcs->interrupt_work(smu);
1011
1012         mutex_unlock(&smu->mutex);
1013 }
1014
1015 static int smu_sw_init(void *handle)
1016 {
1017         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018         struct smu_context *smu = &adev->smu;
1019         int ret;
1020
1021         smu->pool_size = adev->pm.smu_prv_buffer_size;
1022         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1023         mutex_init(&smu->smu_feature.mutex);
1024         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1025         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
1026         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1027
1028         mutex_init(&smu->sensor_lock);
1029         mutex_init(&smu->metrics_lock);
1030         mutex_init(&smu->message_lock);
1031
1032         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1033         INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1034         atomic64_set(&smu->throttle_int_counter, 0);
1035         smu->watermarks_bitmap = 0;
1036         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1037         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1038
1039         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1040         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1041         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
1042         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
1043
1044         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1045         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1046         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1047         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1048         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1049         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1050         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1051         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1052
1053         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1054         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1055         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1056         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1057         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1058         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1059         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1060         smu->display_config = &adev->pm.pm_display_cfg;
1061
1062         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1063         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1064
1065         ret = smu_init_microcode(smu);
1066         if (ret) {
1067                 dev_err(adev->dev, "Failed to load smu firmware!\n");
1068                 return ret;
1069         }
1070
1071         ret = smu_smc_table_sw_init(smu);
1072         if (ret) {
1073                 dev_err(adev->dev, "Failed to sw init smc table!\n");
1074                 return ret;
1075         }
1076
1077         ret = smu_register_irq_handler(smu);
1078         if (ret) {
1079                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1080                 return ret;
1081         }
1082
1083         /* If there is no way to query fan control mode, fan control is not supported */
1084         if (!smu->ppt_funcs->get_fan_control_mode)
1085                 smu->adev->pm.no_fan = true;
1086
1087         return 0;
1088 }
1089
1090 static int smu_sw_fini(void *handle)
1091 {
1092         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1093         struct smu_context *smu = &adev->smu;
1094         int ret;
1095
1096         ret = smu_smc_table_sw_fini(smu);
1097         if (ret) {
1098                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1099                 return ret;
1100         }
1101
1102         smu_fini_microcode(smu);
1103
1104         return 0;
1105 }
1106
1107 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1108 {
1109         struct amdgpu_device *adev = smu->adev;
1110         struct smu_temperature_range *range =
1111                                 &smu->thermal_range;
1112         int ret = 0;
1113
1114         if (!smu->ppt_funcs->get_thermal_temperature_range)
1115                 return 0;
1116
1117         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1118         if (ret)
1119                 return ret;
1120
1121         adev->pm.dpm.thermal.min_temp = range->min;
1122         adev->pm.dpm.thermal.max_temp = range->max;
1123         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1124         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1125         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1126         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1127         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1128         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1129         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1130
1131         return ret;
1132 }
1133
1134 static int smu_smc_hw_setup(struct smu_context *smu)
1135 {
1136         struct amdgpu_device *adev = smu->adev;
1137         uint32_t pcie_gen = 0, pcie_width = 0;
1138         int ret = 0;
1139
1140         if (adev->in_suspend && smu_is_dpm_running(smu)) {
1141                 dev_info(adev->dev, "dpm has been enabled\n");
1142                 /* this is needed specifically */
1143                 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
1144                     (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
1145                         ret = smu_system_features_control(smu, true);
1146                 return ret;
1147         }
1148
1149         ret = smu_init_display_count(smu, 0);
1150         if (ret) {
1151                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1152                 return ret;
1153         }
1154
1155         ret = smu_set_driver_table_location(smu);
1156         if (ret) {
1157                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1158                 return ret;
1159         }
1160
1161         /*
1162          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1163          */
1164         ret = smu_set_tool_table_location(smu);
1165         if (ret) {
1166                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1167                 return ret;
1168         }
1169
1170         /*
1171          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1172          * pool location.
1173          */
1174         ret = smu_notify_memory_pool_location(smu);
1175         if (ret) {
1176                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1177                 return ret;
1178         }
1179
1180         /* smu_dump_pptable(smu); */
1181         /*
1182          * Copy pptable bo in the vram to smc with SMU MSGs such as
1183          * SetDriverDramAddr and TransferTableDram2Smu.
1184          */
1185         ret = smu_write_pptable(smu);
1186         if (ret) {
1187                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1188                 return ret;
1189         }
1190
1191         /* issue Run*Btc msg */
1192         ret = smu_run_btc(smu);
1193         if (ret)
1194                 return ret;
1195
1196         ret = smu_feature_set_allowed_mask(smu);
1197         if (ret) {
1198                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1199                 return ret;
1200         }
1201
1202         ret = smu_system_features_control(smu, true);
1203         if (ret) {
1204                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1205                 return ret;
1206         }
1207
1208         if (!smu_is_dpm_running(smu))
1209                 dev_info(adev->dev, "dpm has been disabled\n");
1210
1211         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1212                 pcie_gen = 3;
1213         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1214                 pcie_gen = 2;
1215         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1216                 pcie_gen = 1;
1217         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1218                 pcie_gen = 0;
1219
1220         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1221          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1222          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1223          */
1224         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1225                 pcie_width = 6;
1226         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1227                 pcie_width = 5;
1228         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1229                 pcie_width = 4;
1230         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1231                 pcie_width = 3;
1232         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1233                 pcie_width = 2;
1234         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1235                 pcie_width = 1;
1236         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1237         if (ret) {
1238                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1239                 return ret;
1240         }
1241
1242         ret = smu_get_thermal_temperature_range(smu);
1243         if (ret) {
1244                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1245                 return ret;
1246         }
1247
1248         ret = smu_enable_thermal_alert(smu);
1249         if (ret) {
1250                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1251                 return ret;
1252         }
1253
1254         /*
1255          * Set initialized values (get from vbios) to dpm tables context such as
1256          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1257          * type of clks.
1258          */
1259         ret = smu_set_default_dpm_table(smu);
1260         if (ret) {
1261                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1262                 return ret;
1263         }
1264
1265         ret = smu_notify_display_change(smu);
1266         if (ret)
1267                 return ret;
1268
1269         /*
1270          * Set min deep sleep dce fclk with bootup value from vbios via
1271          * SetMinDeepSleepDcefclk MSG.
1272          */
1273         ret = smu_set_min_dcef_deep_sleep(smu,
1274                                           smu->smu_table.boot_values.dcefclk / 100);
1275         if (ret)
1276                 return ret;
1277
1278         return ret;
1279 }
1280
1281 static int smu_start_smc_engine(struct smu_context *smu)
1282 {
1283         struct amdgpu_device *adev = smu->adev;
1284         int ret = 0;
1285
1286         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1287                 if (adev->asic_type < CHIP_NAVI10) {
1288                         if (smu->ppt_funcs->load_microcode) {
1289                                 ret = smu->ppt_funcs->load_microcode(smu);
1290                                 if (ret)
1291                                         return ret;
1292                         }
1293                 }
1294         }
1295
1296         if (smu->ppt_funcs->check_fw_status) {
1297                 ret = smu->ppt_funcs->check_fw_status(smu);
1298                 if (ret) {
1299                         dev_err(adev->dev, "SMC is not ready\n");
1300                         return ret;
1301                 }
1302         }
1303
1304         /*
1305          * Send msg GetDriverIfVersion to check if the return value is equal
1306          * with DRIVER_IF_VERSION of smc header.
1307          */
1308         ret = smu_check_fw_version(smu);
1309         if (ret)
1310                 return ret;
1311
1312         return ret;
1313 }
1314
1315 static int smu_hw_init(void *handle)
1316 {
1317         int ret;
1318         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1319         struct smu_context *smu = &adev->smu;
1320
1321         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1322                 smu->pm_enabled = false;
1323                 return 0;
1324         }
1325
1326         ret = smu_start_smc_engine(smu);
1327         if (ret) {
1328                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1329                 return ret;
1330         }
1331
1332         if (smu->is_apu) {
1333                 smu_powergate_sdma(&adev->smu, false);
1334                 smu_dpm_set_vcn_enable(smu, true);
1335                 smu_dpm_set_jpeg_enable(smu, true);
1336                 smu_set_gfx_cgpg(&adev->smu, true);
1337         }
1338
1339         if (!smu->pm_enabled)
1340                 return 0;
1341
1342         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1343         ret = smu_get_vbios_bootup_values(smu);
1344         if (ret) {
1345                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1346                 return ret;
1347         }
1348
1349         ret = smu_setup_pptable(smu);
1350         if (ret) {
1351                 dev_err(adev->dev, "Failed to setup pptable!\n");
1352                 return ret;
1353         }
1354
1355         ret = smu_get_driver_allowed_feature_mask(smu);
1356         if (ret)
1357                 return ret;
1358
1359         ret = smu_smc_hw_setup(smu);
1360         if (ret) {
1361                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1362                 return ret;
1363         }
1364
1365         /*
1366          * Move maximum sustainable clock retrieving here considering
1367          * 1. It is not needed on resume(from S3).
1368          * 2. DAL settings come between .hw_init and .late_init of SMU.
1369          *    And DAL needs to know the maximum sustainable clocks. Thus
1370          *    it cannot be put in .late_init().
1371          */
1372         ret = smu_init_max_sustainable_clocks(smu);
1373         if (ret) {
1374                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1375                 return ret;
1376         }
1377
1378         adev->pm.dpm_enabled = true;
1379
1380         dev_info(adev->dev, "SMU is initialized successfully!\n");
1381
1382         return 0;
1383 }
1384
1385 static int smu_disable_dpms(struct smu_context *smu)
1386 {
1387         struct amdgpu_device *adev = smu->adev;
1388         int ret = 0;
1389         bool use_baco = !smu->is_apu &&
1390                 ((amdgpu_in_reset(adev) &&
1391                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1392                  ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1393
1394         /*
1395          * For custom pptable uploading, skip the DPM features
1396          * disable process on Navi1x ASICs.
1397          *   - As the gfx related features are under control of
1398          *     RLC on those ASICs. RLC reinitialization will be
1399          *     needed to reenable them. That will cost much more
1400          *     efforts.
1401          *
1402          *   - SMU firmware can handle the DPM reenablement
1403          *     properly.
1404          */
1405         if (smu->uploading_custom_pp_table &&
1406             (adev->asic_type >= CHIP_NAVI10) &&
1407             (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
1408                 return smu_disable_all_features_with_exception(smu,
1409                                                                true,
1410                                                                SMU_FEATURE_COUNT);
1411
1412         /*
1413          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1414          * on BACO in. Driver involvement is unnecessary.
1415          */
1416         if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
1417              ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) &&
1418              use_baco)
1419                 return smu_disable_all_features_with_exception(smu,
1420                                                                true,
1421                                                                SMU_FEATURE_BACO_BIT);
1422
1423         /*
1424          * For gpu reset, runpm and hibernation through BACO,
1425          * BACO feature has to be kept enabled.
1426          */
1427         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1428                 ret = smu_disable_all_features_with_exception(smu,
1429                                                               false,
1430                                                               SMU_FEATURE_BACO_BIT);
1431                 if (ret)
1432                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1433         } else {
1434                 ret = smu_system_features_control(smu, false);
1435                 if (ret)
1436                         dev_err(adev->dev, "Failed to disable smu features.\n");
1437         }
1438
1439         if (adev->asic_type >= CHIP_NAVI10 &&
1440             adev->gfx.rlc.funcs->stop)
1441                 adev->gfx.rlc.funcs->stop(adev);
1442
1443         return ret;
1444 }
1445
1446 static int smu_smc_hw_cleanup(struct smu_context *smu)
1447 {
1448         struct amdgpu_device *adev = smu->adev;
1449         int ret = 0;
1450
1451         cancel_work_sync(&smu->throttling_logging_work);
1452         cancel_work_sync(&smu->interrupt_work);
1453
1454         ret = smu_disable_thermal_alert(smu);
1455         if (ret) {
1456                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1457                 return ret;
1458         }
1459
1460         ret = smu_disable_dpms(smu);
1461         if (ret) {
1462                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1463                 return ret;
1464         }
1465
1466         return 0;
1467 }
1468
1469 static int smu_hw_fini(void *handle)
1470 {
1471         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1472         struct smu_context *smu = &adev->smu;
1473
1474         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1475                 return 0;
1476
1477         if (smu->is_apu) {
1478                 smu_powergate_sdma(&adev->smu, true);
1479         }
1480
1481         smu_dpm_set_vcn_enable(smu, false);
1482         smu_dpm_set_jpeg_enable(smu, false);
1483
1484         adev->vcn.cur_state = AMD_PG_STATE_GATE;
1485         adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1486
1487         if (!smu->pm_enabled)
1488                 return 0;
1489
1490         adev->pm.dpm_enabled = false;
1491
1492         return smu_smc_hw_cleanup(smu);
1493 }
1494
1495 static int smu_reset(struct smu_context *smu)
1496 {
1497         struct amdgpu_device *adev = smu->adev;
1498         int ret;
1499
1500         amdgpu_gfx_off_ctrl(smu->adev, false);
1501
1502         ret = smu_hw_fini(adev);
1503         if (ret)
1504                 return ret;
1505
1506         ret = smu_hw_init(adev);
1507         if (ret)
1508                 return ret;
1509
1510         ret = smu_late_init(adev);
1511         if (ret)
1512                 return ret;
1513
1514         amdgpu_gfx_off_ctrl(smu->adev, true);
1515
1516         return 0;
1517 }
1518
1519 static int smu_suspend(void *handle)
1520 {
1521         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1522         struct smu_context *smu = &adev->smu;
1523         int ret;
1524
1525         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1526                 return 0;
1527
1528         if (!smu->pm_enabled)
1529                 return 0;
1530
1531         adev->pm.dpm_enabled = false;
1532
1533         ret = smu_smc_hw_cleanup(smu);
1534         if (ret)
1535                 return ret;
1536
1537         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1538
1539         /* skip CGPG when in S0ix */
1540         if (smu->is_apu && !adev->in_s0ix)
1541                 smu_set_gfx_cgpg(&adev->smu, false);
1542
1543         return 0;
1544 }
1545
1546 static int smu_resume(void *handle)
1547 {
1548         int ret;
1549         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1550         struct smu_context *smu = &adev->smu;
1551
1552         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1553                 return 0;
1554
1555         if (!smu->pm_enabled)
1556                 return 0;
1557
1558         dev_info(adev->dev, "SMU is resuming...\n");
1559
1560         ret = smu_start_smc_engine(smu);
1561         if (ret) {
1562                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1563                 return ret;
1564         }
1565
1566         ret = smu_smc_hw_setup(smu);
1567         if (ret) {
1568                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1569                 return ret;
1570         }
1571
1572         if (smu->is_apu)
1573                 smu_set_gfx_cgpg(&adev->smu, true);
1574
1575         smu->disable_uclk_switch = 0;
1576
1577         adev->pm.dpm_enabled = true;
1578
1579         dev_info(adev->dev, "SMU is resumed successfully!\n");
1580
1581         return 0;
1582 }
1583
1584 static int smu_display_configuration_change(void *handle,
1585                                             const struct amd_pp_display_configuration *display_config)
1586 {
1587         struct smu_context *smu = handle;
1588         int index = 0;
1589         int num_of_active_display = 0;
1590
1591         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1592                 return -EOPNOTSUPP;
1593
1594         if (!display_config)
1595                 return -EINVAL;
1596
1597         mutex_lock(&smu->mutex);
1598
1599         smu_set_min_dcef_deep_sleep(smu,
1600                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1601
1602         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1603                 if (display_config->displays[index].controller_id != 0)
1604                         num_of_active_display++;
1605         }
1606
1607         mutex_unlock(&smu->mutex);
1608
1609         return 0;
1610 }
1611
1612 static int smu_set_clockgating_state(void *handle,
1613                                      enum amd_clockgating_state state)
1614 {
1615         return 0;
1616 }
1617
1618 static int smu_set_powergating_state(void *handle,
1619                                      enum amd_powergating_state state)
1620 {
1621         return 0;
1622 }
1623
1624 static int smu_enable_umd_pstate(void *handle,
1625                       enum amd_dpm_forced_level *level)
1626 {
1627         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1628                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1629                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1630                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1631
1632         struct smu_context *smu = (struct smu_context*)(handle);
1633         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1634
1635         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1636                 return -EINVAL;
1637
1638         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1639                 /* enter umd pstate, save current level, disable gfx cg*/
1640                 if (*level & profile_mode_mask) {
1641                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1642                         smu_dpm_ctx->enable_umd_pstate = true;
1643                         smu_gpo_control(smu, false);
1644                         amdgpu_device_ip_set_powergating_state(smu->adev,
1645                                                                AMD_IP_BLOCK_TYPE_GFX,
1646                                                                AMD_PG_STATE_UNGATE);
1647                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1648                                                                AMD_IP_BLOCK_TYPE_GFX,
1649                                                                AMD_CG_STATE_UNGATE);
1650                         smu_gfx_ulv_control(smu, false);
1651                         smu_deep_sleep_control(smu, false);
1652                         amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1653                 }
1654         } else {
1655                 /* exit umd pstate, restore level, enable gfx cg*/
1656                 if (!(*level & profile_mode_mask)) {
1657                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1658                                 *level = smu_dpm_ctx->saved_dpm_level;
1659                         smu_dpm_ctx->enable_umd_pstate = false;
1660                         amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1661                         smu_deep_sleep_control(smu, true);
1662                         smu_gfx_ulv_control(smu, true);
1663                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1664                                                                AMD_IP_BLOCK_TYPE_GFX,
1665                                                                AMD_CG_STATE_GATE);
1666                         amdgpu_device_ip_set_powergating_state(smu->adev,
1667                                                                AMD_IP_BLOCK_TYPE_GFX,
1668                                                                AMD_PG_STATE_GATE);
1669                         smu_gpo_control(smu, true);
1670                 }
1671         }
1672
1673         return 0;
1674 }
1675
1676 static int smu_bump_power_profile_mode(struct smu_context *smu,
1677                                            long *param,
1678                                            uint32_t param_size)
1679 {
1680         int ret = 0;
1681
1682         if (smu->ppt_funcs->set_power_profile_mode)
1683                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1684
1685         return ret;
1686 }
1687
1688 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1689                                    enum amd_dpm_forced_level level,
1690                                    bool skip_display_settings)
1691 {
1692         int ret = 0;
1693         int index = 0;
1694         long workload;
1695         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1696
1697         if (!skip_display_settings) {
1698                 ret = smu_display_config_changed(smu);
1699                 if (ret) {
1700                         dev_err(smu->adev->dev, "Failed to change display config!");
1701                         return ret;
1702                 }
1703         }
1704
1705         ret = smu_apply_clocks_adjust_rules(smu);
1706         if (ret) {
1707                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1708                 return ret;
1709         }
1710
1711         if (!skip_display_settings) {
1712                 ret = smu_notify_smc_display_config(smu);
1713                 if (ret) {
1714                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1715                         return ret;
1716                 }
1717         }
1718
1719         if (smu_dpm_ctx->dpm_level != level) {
1720                 ret = smu_asic_set_performance_level(smu, level);
1721                 if (ret) {
1722                         dev_err(smu->adev->dev, "Failed to set performance level!");
1723                         return ret;
1724                 }
1725
1726                 /* update the saved copy */
1727                 smu_dpm_ctx->dpm_level = level;
1728         }
1729
1730         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1731                 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1732                 index = fls(smu->workload_mask);
1733                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1734                 workload = smu->workload_setting[index];
1735
1736                 if (smu->power_profile_mode != workload)
1737                         smu_bump_power_profile_mode(smu, &workload, 0);
1738         }
1739
1740         return ret;
1741 }
1742
1743 static int smu_handle_task(struct smu_context *smu,
1744                            enum amd_dpm_forced_level level,
1745                            enum amd_pp_task task_id,
1746                            bool lock_needed)
1747 {
1748         int ret = 0;
1749
1750         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1751                 return -EOPNOTSUPP;
1752
1753         if (lock_needed)
1754                 mutex_lock(&smu->mutex);
1755
1756         switch (task_id) {
1757         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1758                 ret = smu_pre_display_config_changed(smu);
1759                 if (ret)
1760                         goto out;
1761                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1762                 break;
1763         case AMD_PP_TASK_COMPLETE_INIT:
1764         case AMD_PP_TASK_READJUST_POWER_STATE:
1765                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1766                 break;
1767         default:
1768                 break;
1769         }
1770
1771 out:
1772         if (lock_needed)
1773                 mutex_unlock(&smu->mutex);
1774
1775         return ret;
1776 }
1777
1778 static int smu_handle_dpm_task(void *handle,
1779                                enum amd_pp_task task_id,
1780                                enum amd_pm_state_type *user_state)
1781 {
1782         struct smu_context *smu = handle;
1783         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1784
1785         return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true);
1786
1787 }
1788
1789 static int smu_switch_power_profile(void *handle,
1790                                     enum PP_SMC_POWER_PROFILE type,
1791                                     bool en)
1792 {
1793         struct smu_context *smu = handle;
1794         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1795         long workload;
1796         uint32_t index;
1797
1798         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1799                 return -EOPNOTSUPP;
1800
1801         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1802                 return -EINVAL;
1803
1804         mutex_lock(&smu->mutex);
1805
1806         if (!en) {
1807                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1808                 index = fls(smu->workload_mask);
1809                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1810                 workload = smu->workload_setting[index];
1811         } else {
1812                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1813                 index = fls(smu->workload_mask);
1814                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1815                 workload = smu->workload_setting[index];
1816         }
1817
1818         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1819                 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1820                 smu_bump_power_profile_mode(smu, &workload, 0);
1821
1822         mutex_unlock(&smu->mutex);
1823
1824         return 0;
1825 }
1826
1827 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1828 {
1829         struct smu_context *smu = handle;
1830         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1831         enum amd_dpm_forced_level level;
1832
1833         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1834                 return -EOPNOTSUPP;
1835
1836         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1837                 return -EINVAL;
1838
1839         mutex_lock(&(smu->mutex));
1840         level = smu_dpm_ctx->dpm_level;
1841         mutex_unlock(&(smu->mutex));
1842
1843         return level;
1844 }
1845
1846 static int smu_force_performance_level(void *handle,
1847                                        enum amd_dpm_forced_level level)
1848 {
1849         struct smu_context *smu = handle;
1850         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1851         int ret = 0;
1852
1853         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1854                 return -EOPNOTSUPP;
1855
1856         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1857                 return -EINVAL;
1858
1859         mutex_lock(&smu->mutex);
1860
1861         ret = smu_enable_umd_pstate(smu, &level);
1862         if (ret) {
1863                 mutex_unlock(&smu->mutex);
1864                 return ret;
1865         }
1866
1867         ret = smu_handle_task(smu, level,
1868                               AMD_PP_TASK_READJUST_POWER_STATE,
1869                               false);
1870
1871         mutex_unlock(&smu->mutex);
1872
1873         /* reset user dpm clock state */
1874         if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1875                 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1876                 smu->user_dpm_profile.clk_dependency = 0;
1877         }
1878
1879         return ret;
1880 }
1881
1882 static int smu_set_display_count(void *handle, uint32_t count)
1883 {
1884         struct smu_context *smu = handle;
1885         int ret = 0;
1886
1887         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1888                 return -EOPNOTSUPP;
1889
1890         mutex_lock(&smu->mutex);
1891         ret = smu_init_display_count(smu, count);
1892         mutex_unlock(&smu->mutex);
1893
1894         return ret;
1895 }
1896
1897 static int smu_force_smuclk_levels(struct smu_context *smu,
1898                          enum smu_clk_type clk_type,
1899                          uint32_t mask)
1900 {
1901         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1902         int ret = 0;
1903
1904         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1905                 return -EOPNOTSUPP;
1906
1907         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1908                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1909                 return -EINVAL;
1910         }
1911
1912         mutex_lock(&smu->mutex);
1913
1914         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1915                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1916                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
1917                         smu->user_dpm_profile.clk_mask[clk_type] = mask;
1918                         smu_set_user_clk_dependencies(smu, clk_type);
1919                 }
1920         }
1921
1922         mutex_unlock(&smu->mutex);
1923
1924         return ret;
1925 }
1926
1927 static int smu_force_ppclk_levels(void *handle,
1928                                   enum pp_clock_type type,
1929                                   uint32_t mask)
1930 {
1931         struct smu_context *smu = handle;
1932         enum smu_clk_type clk_type;
1933
1934         switch (type) {
1935         case PP_SCLK:
1936                 clk_type = SMU_SCLK; break;
1937         case PP_MCLK:
1938                 clk_type = SMU_MCLK; break;
1939         case PP_PCIE:
1940                 clk_type = SMU_PCIE; break;
1941         case PP_SOCCLK:
1942                 clk_type = SMU_SOCCLK; break;
1943         case PP_FCLK:
1944                 clk_type = SMU_FCLK; break;
1945         case PP_DCEFCLK:
1946                 clk_type = SMU_DCEFCLK; break;
1947         case PP_VCLK:
1948                 clk_type = SMU_VCLK; break;
1949         case PP_DCLK:
1950                 clk_type = SMU_DCLK; break;
1951         case OD_SCLK:
1952                 clk_type = SMU_OD_SCLK; break;
1953         case OD_MCLK:
1954                 clk_type = SMU_OD_MCLK; break;
1955         case OD_VDDC_CURVE:
1956                 clk_type = SMU_OD_VDDC_CURVE; break;
1957         case OD_RANGE:
1958                 clk_type = SMU_OD_RANGE; break;
1959         default:
1960                 return -EINVAL;
1961         }
1962
1963         return smu_force_smuclk_levels(smu, clk_type, mask);
1964 }
1965
1966 /*
1967  * On system suspending or resetting, the dpm_enabled
1968  * flag will be cleared. So that those SMU services which
1969  * are not supported will be gated.
1970  * However, the mp1 state setting should still be granted
1971  * even if the dpm_enabled cleared.
1972  */
1973 static int smu_set_mp1_state(void *handle,
1974                              enum pp_mp1_state mp1_state)
1975 {
1976         struct smu_context *smu = handle;
1977         int ret = 0;
1978
1979         if (!smu->pm_enabled)
1980                 return -EOPNOTSUPP;
1981
1982         mutex_lock(&smu->mutex);
1983
1984         if (smu->ppt_funcs &&
1985             smu->ppt_funcs->set_mp1_state)
1986                 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
1987
1988         mutex_unlock(&smu->mutex);
1989
1990         return ret;
1991 }
1992
1993 static int smu_set_df_cstate(void *handle,
1994                              enum pp_df_cstate state)
1995 {
1996         struct smu_context *smu = handle;
1997         int ret = 0;
1998
1999         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2000                 return -EOPNOTSUPP;
2001
2002         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2003                 return 0;
2004
2005         mutex_lock(&smu->mutex);
2006
2007         ret = smu->ppt_funcs->set_df_cstate(smu, state);
2008         if (ret)
2009                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2010
2011         mutex_unlock(&smu->mutex);
2012
2013         return ret;
2014 }
2015
2016 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2017 {
2018         int ret = 0;
2019
2020         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2021                 return -EOPNOTSUPP;
2022
2023         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2024                 return 0;
2025
2026         mutex_lock(&smu->mutex);
2027
2028         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2029         if (ret)
2030                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2031
2032         mutex_unlock(&smu->mutex);
2033
2034         return ret;
2035 }
2036
2037 int smu_write_watermarks_table(struct smu_context *smu)
2038 {
2039         int ret = 0;
2040
2041         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2042                 return -EOPNOTSUPP;
2043
2044         mutex_lock(&smu->mutex);
2045
2046         ret = smu_set_watermarks_table(smu, NULL);
2047
2048         mutex_unlock(&smu->mutex);
2049
2050         return ret;
2051 }
2052
2053 static int smu_set_watermarks_for_clock_ranges(void *handle,
2054                                                struct pp_smu_wm_range_sets *clock_ranges)
2055 {
2056         struct smu_context *smu = handle;
2057         int ret = 0;
2058
2059         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2060                 return -EOPNOTSUPP;
2061
2062         if (smu->disable_watermark)
2063                 return 0;
2064
2065         mutex_lock(&smu->mutex);
2066
2067         ret = smu_set_watermarks_table(smu, clock_ranges);
2068
2069         mutex_unlock(&smu->mutex);
2070
2071         return ret;
2072 }
2073
2074 int smu_set_ac_dc(struct smu_context *smu)
2075 {
2076         int ret = 0;
2077
2078         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2079                 return -EOPNOTSUPP;
2080
2081         /* controlled by firmware */
2082         if (smu->dc_controlled_by_gpio)
2083                 return 0;
2084
2085         mutex_lock(&smu->mutex);
2086         ret = smu_set_power_source(smu,
2087                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2088                                    SMU_POWER_SOURCE_DC);
2089         if (ret)
2090                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2091                        smu->adev->pm.ac_power ? "AC" : "DC");
2092         mutex_unlock(&smu->mutex);
2093
2094         return ret;
2095 }
2096
2097 const struct amd_ip_funcs smu_ip_funcs = {
2098         .name = "smu",
2099         .early_init = smu_early_init,
2100         .late_init = smu_late_init,
2101         .sw_init = smu_sw_init,
2102         .sw_fini = smu_sw_fini,
2103         .hw_init = smu_hw_init,
2104         .hw_fini = smu_hw_fini,
2105         .suspend = smu_suspend,
2106         .resume = smu_resume,
2107         .is_idle = NULL,
2108         .check_soft_reset = NULL,
2109         .wait_for_idle = NULL,
2110         .soft_reset = NULL,
2111         .set_clockgating_state = smu_set_clockgating_state,
2112         .set_powergating_state = smu_set_powergating_state,
2113         .enable_umd_pstate = smu_enable_umd_pstate,
2114 };
2115
2116 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2117 {
2118         .type = AMD_IP_BLOCK_TYPE_SMC,
2119         .major = 11,
2120         .minor = 0,
2121         .rev = 0,
2122         .funcs = &smu_ip_funcs,
2123 };
2124
2125 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2126 {
2127         .type = AMD_IP_BLOCK_TYPE_SMC,
2128         .major = 12,
2129         .minor = 0,
2130         .rev = 0,
2131         .funcs = &smu_ip_funcs,
2132 };
2133
2134 const struct amdgpu_ip_block_version smu_v13_0_ip_block =
2135 {
2136         .type = AMD_IP_BLOCK_TYPE_SMC,
2137         .major = 13,
2138         .minor = 0,
2139         .rev = 0,
2140         .funcs = &smu_ip_funcs,
2141 };
2142
2143 static int smu_load_microcode(void *handle)
2144 {
2145         struct smu_context *smu = handle;
2146         struct amdgpu_device *adev = smu->adev;
2147         int ret = 0;
2148
2149         if (!smu->pm_enabled)
2150                 return -EOPNOTSUPP;
2151
2152         /* This should be used for non PSP loading */
2153         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2154                 return 0;
2155
2156         if (smu->ppt_funcs->load_microcode) {
2157                 ret = smu->ppt_funcs->load_microcode(smu);
2158                 if (ret) {
2159                         dev_err(adev->dev, "Load microcode failed\n");
2160                         return ret;
2161                 }
2162         }
2163
2164         if (smu->ppt_funcs->check_fw_status) {
2165                 ret = smu->ppt_funcs->check_fw_status(smu);
2166                 if (ret) {
2167                         dev_err(adev->dev, "SMC is not ready\n");
2168                         return ret;
2169                 }
2170         }
2171
2172         return ret;
2173 }
2174
2175 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2176 {
2177         int ret = 0;
2178
2179         mutex_lock(&smu->mutex);
2180
2181         if (smu->ppt_funcs->set_gfx_cgpg)
2182                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2183
2184         mutex_unlock(&smu->mutex);
2185
2186         return ret;
2187 }
2188
2189 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2190 {
2191         struct smu_context *smu = handle;
2192         int ret = 0;
2193
2194         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2195                 return -EOPNOTSUPP;
2196
2197         mutex_lock(&smu->mutex);
2198
2199         if (smu->ppt_funcs->set_fan_speed_rpm) {
2200                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2201                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2202                         smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2203                         smu->user_dpm_profile.fan_speed_rpm = speed;
2204
2205                         /* Override custom PWM setting as they cannot co-exist */
2206                         smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2207                         smu->user_dpm_profile.fan_speed_pwm = 0;
2208                 }
2209         }
2210
2211         mutex_unlock(&smu->mutex);
2212
2213         return ret;
2214 }
2215
2216 /**
2217  * smu_get_power_limit - Request one of the SMU Power Limits
2218  *
2219  * @handle: pointer to smu context
2220  * @limit: requested limit is written back to this variable
2221  * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2222  * @pp_power_type: &pp_power_type type of power
2223  * Return:  0 on success, <0 on error
2224  *
2225  */
2226 int smu_get_power_limit(void *handle,
2227                         uint32_t *limit,
2228                         enum pp_power_limit_level pp_limit_level,
2229                         enum pp_power_type pp_power_type)
2230 {
2231         struct smu_context *smu = handle;
2232         enum smu_ppt_limit_level limit_level;
2233         uint32_t limit_type;
2234         int ret = 0;
2235
2236         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2237                 return -EOPNOTSUPP;
2238
2239         switch(pp_power_type) {
2240         case PP_PWR_TYPE_SUSTAINED:
2241                 limit_type = SMU_DEFAULT_PPT_LIMIT;
2242                 break;
2243         case PP_PWR_TYPE_FAST:
2244                 limit_type = SMU_FAST_PPT_LIMIT;
2245                 break;
2246         default:
2247                 return -EOPNOTSUPP;
2248                 break;
2249         }
2250
2251         switch(pp_limit_level){
2252         case PP_PWR_LIMIT_CURRENT:
2253                 limit_level = SMU_PPT_LIMIT_CURRENT;
2254                 break;
2255         case PP_PWR_LIMIT_DEFAULT:
2256                 limit_level = SMU_PPT_LIMIT_DEFAULT;
2257                 break;
2258         case PP_PWR_LIMIT_MAX:
2259                 limit_level = SMU_PPT_LIMIT_MAX;
2260                 break;
2261         case PP_PWR_LIMIT_MIN:
2262         default:
2263                 return -EOPNOTSUPP;
2264                 break;
2265         }
2266
2267         mutex_lock(&smu->mutex);
2268
2269         if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2270                 if (smu->ppt_funcs->get_ppt_limit)
2271                         ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2272         } else {
2273                 switch (limit_level) {
2274                 case SMU_PPT_LIMIT_CURRENT:
2275                         if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
2276                              (smu->adev->asic_type == CHIP_SIENNA_CICHLID) ||
2277                              (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) ||
2278                              (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) ||
2279                              (smu->adev->asic_type == CHIP_BEIGE_GOBY))
2280                                 ret = smu_get_asic_power_limits(smu,
2281                                                                 &smu->current_power_limit,
2282                                                                 NULL,
2283                                                                 NULL);
2284                         *limit = smu->current_power_limit;
2285                         break;
2286                 case SMU_PPT_LIMIT_DEFAULT:
2287                         *limit = smu->default_power_limit;
2288                         break;
2289                 case SMU_PPT_LIMIT_MAX:
2290                         *limit = smu->max_power_limit;
2291                         break;
2292                 default:
2293                         break;
2294                 }
2295         }
2296
2297         mutex_unlock(&smu->mutex);
2298
2299         return ret;
2300 }
2301
2302 static int smu_set_power_limit(void *handle, uint32_t limit)
2303 {
2304         struct smu_context *smu = handle;
2305         uint32_t limit_type = limit >> 24;
2306         int ret = 0;
2307
2308         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2309                 return -EOPNOTSUPP;
2310
2311         mutex_lock(&smu->mutex);
2312
2313         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2314                 if (smu->ppt_funcs->set_power_limit) {
2315                         ret = smu->ppt_funcs->set_power_limit(smu, limit);
2316                         goto out;
2317                 }
2318
2319         if (limit > smu->max_power_limit) {
2320                 dev_err(smu->adev->dev,
2321                         "New power limit (%d) is over the max allowed %d\n",
2322                         limit, smu->max_power_limit);
2323                 ret = -EINVAL;
2324                 goto out;
2325         }
2326
2327         if (!limit)
2328                 limit = smu->current_power_limit;
2329
2330         if (smu->ppt_funcs->set_power_limit) {
2331                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2332                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2333                         smu->user_dpm_profile.power_limit = limit;
2334         }
2335
2336 out:
2337         mutex_unlock(&smu->mutex);
2338
2339         return ret;
2340 }
2341
2342 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2343 {
2344         int ret = 0;
2345
2346         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2347                 return -EOPNOTSUPP;
2348
2349         mutex_lock(&smu->mutex);
2350
2351         if (smu->ppt_funcs->print_clk_levels)
2352                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2353
2354         mutex_unlock(&smu->mutex);
2355
2356         return ret;
2357 }
2358
2359 static int smu_print_ppclk_levels(void *handle,
2360                                   enum pp_clock_type type,
2361                                   char *buf)
2362 {
2363         struct smu_context *smu = handle;
2364         enum smu_clk_type clk_type;
2365
2366         switch (type) {
2367         case PP_SCLK:
2368                 clk_type = SMU_SCLK; break;
2369         case PP_MCLK:
2370                 clk_type = SMU_MCLK; break;
2371         case PP_PCIE:
2372                 clk_type = SMU_PCIE; break;
2373         case PP_SOCCLK:
2374                 clk_type = SMU_SOCCLK; break;
2375         case PP_FCLK:
2376                 clk_type = SMU_FCLK; break;
2377         case PP_DCEFCLK:
2378                 clk_type = SMU_DCEFCLK; break;
2379         case PP_VCLK:
2380                 clk_type = SMU_VCLK; break;
2381         case PP_DCLK:
2382                 clk_type = SMU_DCLK; break;
2383         case OD_SCLK:
2384                 clk_type = SMU_OD_SCLK; break;
2385         case OD_MCLK:
2386                 clk_type = SMU_OD_MCLK; break;
2387         case OD_VDDC_CURVE:
2388                 clk_type = SMU_OD_VDDC_CURVE; break;
2389         case OD_RANGE:
2390                 clk_type = SMU_OD_RANGE; break;
2391         case OD_VDDGFX_OFFSET:
2392                 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2393         case OD_CCLK:
2394                 clk_type = SMU_OD_CCLK; break;
2395         default:
2396                 return -EINVAL;
2397         }
2398
2399         return smu_print_smuclk_levels(smu, clk_type, buf);
2400 }
2401
2402 static int smu_od_edit_dpm_table(void *handle,
2403                                  enum PP_OD_DPM_TABLE_COMMAND type,
2404                                  long *input, uint32_t size)
2405 {
2406         struct smu_context *smu = handle;
2407         int ret = 0;
2408
2409         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2410                 return -EOPNOTSUPP;
2411
2412         mutex_lock(&smu->mutex);
2413
2414         if (smu->ppt_funcs->od_edit_dpm_table) {
2415                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2416         }
2417
2418         mutex_unlock(&smu->mutex);
2419
2420         return ret;
2421 }
2422
2423 static int smu_read_sensor(void *handle,
2424                            int sensor,
2425                            void *data,
2426                            int *size_arg)
2427 {
2428         struct smu_context *smu = handle;
2429         struct smu_umd_pstate_table *pstate_table =
2430                                 &smu->pstate_table;
2431         int ret = 0;
2432         uint32_t *size, size_val;
2433
2434         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2435                 return -EOPNOTSUPP;
2436
2437         if (!data || !size_arg)
2438                 return -EINVAL;
2439
2440         size_val = *size_arg;
2441         size = &size_val;
2442
2443         mutex_lock(&smu->mutex);
2444
2445         if (smu->ppt_funcs->read_sensor)
2446                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2447                         goto unlock;
2448
2449         switch (sensor) {
2450         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2451                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2452                 *size = 4;
2453                 break;
2454         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2455                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2456                 *size = 4;
2457                 break;
2458         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2459                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2460                 *size = 8;
2461                 break;
2462         case AMDGPU_PP_SENSOR_UVD_POWER:
2463                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2464                 *size = 4;
2465                 break;
2466         case AMDGPU_PP_SENSOR_VCE_POWER:
2467                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2468                 *size = 4;
2469                 break;
2470         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2471                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2472                 *size = 4;
2473                 break;
2474         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2475                 *(uint32_t *)data = 0;
2476                 *size = 4;
2477                 break;
2478         default:
2479                 *size = 0;
2480                 ret = -EOPNOTSUPP;
2481                 break;
2482         }
2483
2484 unlock:
2485         mutex_unlock(&smu->mutex);
2486
2487         // assign uint32_t to int
2488         *size_arg = size_val;
2489
2490         return ret;
2491 }
2492
2493 static int smu_get_power_profile_mode(void *handle, char *buf)
2494 {
2495         struct smu_context *smu = handle;
2496         int ret = 0;
2497
2498         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2499                 return -EOPNOTSUPP;
2500
2501         mutex_lock(&smu->mutex);
2502
2503         if (smu->ppt_funcs->get_power_profile_mode)
2504                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2505
2506         mutex_unlock(&smu->mutex);
2507
2508         return ret;
2509 }
2510
2511 static int smu_set_power_profile_mode(void *handle,
2512                                       long *param,
2513                                       uint32_t param_size)
2514 {
2515         struct smu_context *smu = handle;
2516         int ret = 0;
2517
2518         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2519                 return -EOPNOTSUPP;
2520
2521         mutex_lock(&smu->mutex);
2522
2523         smu_bump_power_profile_mode(smu, param, param_size);
2524
2525         mutex_unlock(&smu->mutex);
2526
2527         return ret;
2528 }
2529
2530
2531 static u32 smu_get_fan_control_mode(void *handle)
2532 {
2533         struct smu_context *smu = handle;
2534         u32 ret = 0;
2535
2536         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2537                 return AMD_FAN_CTRL_NONE;
2538
2539         mutex_lock(&smu->mutex);
2540
2541         if (smu->ppt_funcs->get_fan_control_mode)
2542                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2543
2544         mutex_unlock(&smu->mutex);
2545
2546         return ret;
2547 }
2548
2549 static int smu_set_fan_control_mode(struct smu_context *smu, int value)
2550 {
2551         int ret = 0;
2552
2553         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2554                 return  -EOPNOTSUPP;
2555
2556         mutex_lock(&smu->mutex);
2557
2558         if (smu->ppt_funcs->set_fan_control_mode) {
2559                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2560                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2561                         smu->user_dpm_profile.fan_mode = value;
2562         }
2563
2564         mutex_unlock(&smu->mutex);
2565
2566         /* reset user dpm fan speed */
2567         if (!ret && value != AMD_FAN_CTRL_MANUAL &&
2568                         !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2569                 smu->user_dpm_profile.fan_speed_pwm = 0;
2570                 smu->user_dpm_profile.fan_speed_rpm = 0;
2571                 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
2572         }
2573
2574         return ret;
2575 }
2576
2577 static void smu_pp_set_fan_control_mode(void *handle, u32 value)
2578 {
2579         struct smu_context *smu = handle;
2580
2581         smu_set_fan_control_mode(smu, value);
2582 }
2583
2584
2585 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
2586 {
2587         struct smu_context *smu = handle;
2588         int ret = 0;
2589
2590         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2591                 return -EOPNOTSUPP;
2592
2593         mutex_lock(&smu->mutex);
2594
2595         if (smu->ppt_funcs->get_fan_speed_pwm)
2596                 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
2597
2598         mutex_unlock(&smu->mutex);
2599
2600         return ret;
2601 }
2602
2603 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
2604 {
2605         struct smu_context *smu = handle;
2606         int ret = 0;
2607
2608         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2609                 return -EOPNOTSUPP;
2610
2611         mutex_lock(&smu->mutex);
2612
2613         if (smu->ppt_funcs->set_fan_speed_pwm) {
2614                 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
2615                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2616                         smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
2617                         smu->user_dpm_profile.fan_speed_pwm = speed;
2618
2619                         /* Override custom RPM setting as they cannot co-exist */
2620                         smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
2621                         smu->user_dpm_profile.fan_speed_rpm = 0;
2622                 }
2623         }
2624
2625         mutex_unlock(&smu->mutex);
2626
2627         return ret;
2628 }
2629
2630 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2631 {
2632         struct smu_context *smu = handle;
2633         int ret = 0;
2634
2635         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2636                 return -EOPNOTSUPP;
2637
2638         mutex_lock(&smu->mutex);
2639
2640         if (smu->ppt_funcs->get_fan_speed_rpm)
2641                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2642
2643         mutex_unlock(&smu->mutex);
2644
2645         return ret;
2646 }
2647
2648 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2649 {
2650         struct smu_context *smu = handle;
2651         int ret = 0;
2652
2653         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2654                 return -EOPNOTSUPP;
2655
2656         mutex_lock(&smu->mutex);
2657
2658         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2659
2660         mutex_unlock(&smu->mutex);
2661
2662         return ret;
2663 }
2664
2665 static int smu_get_clock_by_type_with_latency(void *handle,
2666                                               enum amd_pp_clock_type type,
2667                                               struct pp_clock_levels_with_latency *clocks)
2668 {
2669         struct smu_context *smu = handle;
2670         enum smu_clk_type clk_type;
2671         int ret = 0;
2672
2673         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2674                 return -EOPNOTSUPP;
2675
2676         mutex_lock(&smu->mutex);
2677
2678         if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2679                 switch (type) {
2680                 case amd_pp_sys_clock:
2681                         clk_type = SMU_GFXCLK;
2682                         break;
2683                 case amd_pp_mem_clock:
2684                         clk_type = SMU_MCLK;
2685                         break;
2686                 case amd_pp_dcef_clock:
2687                         clk_type = SMU_DCEFCLK;
2688                         break;
2689                 case amd_pp_disp_clock:
2690                         clk_type = SMU_DISPCLK;
2691                         break;
2692                 default:
2693                         dev_err(smu->adev->dev, "Invalid clock type!\n");
2694                         mutex_unlock(&smu->mutex);
2695                         return -EINVAL;
2696                 }
2697
2698                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2699         }
2700
2701         mutex_unlock(&smu->mutex);
2702
2703         return ret;
2704 }
2705
2706 static int smu_display_clock_voltage_request(void *handle,
2707                                              struct pp_display_clock_request *clock_req)
2708 {
2709         struct smu_context *smu = handle;
2710         int ret = 0;
2711
2712         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2713                 return -EOPNOTSUPP;
2714
2715         mutex_lock(&smu->mutex);
2716
2717         if (smu->ppt_funcs->display_clock_voltage_request)
2718                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2719
2720         mutex_unlock(&smu->mutex);
2721
2722         return ret;
2723 }
2724
2725
2726 static int smu_display_disable_memory_clock_switch(void *handle,
2727                                                    bool disable_memory_clock_switch)
2728 {
2729         struct smu_context *smu = handle;
2730         int ret = -EINVAL;
2731
2732         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2733                 return -EOPNOTSUPP;
2734
2735         mutex_lock(&smu->mutex);
2736
2737         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2738                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2739
2740         mutex_unlock(&smu->mutex);
2741
2742         return ret;
2743 }
2744
2745 static int smu_set_xgmi_pstate(void *handle,
2746                                uint32_t pstate)
2747 {
2748         struct smu_context *smu = handle;
2749         int ret = 0;
2750
2751         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2752                 return -EOPNOTSUPP;
2753
2754         mutex_lock(&smu->mutex);
2755
2756         if (smu->ppt_funcs->set_xgmi_pstate)
2757                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2758
2759         mutex_unlock(&smu->mutex);
2760
2761         if(ret)
2762                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2763
2764         return ret;
2765 }
2766
2767 static int smu_get_baco_capability(void *handle, bool *cap)
2768 {
2769         struct smu_context *smu = handle;
2770         int ret = 0;
2771
2772         *cap = false;
2773
2774         if (!smu->pm_enabled)
2775                 return 0;
2776
2777         mutex_lock(&smu->mutex);
2778
2779         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2780                 *cap = smu->ppt_funcs->baco_is_support(smu);
2781
2782         mutex_unlock(&smu->mutex);
2783
2784         return ret;
2785 }
2786
2787 static int smu_baco_set_state(void *handle, int state)
2788 {
2789         struct smu_context *smu = handle;
2790         int ret = 0;
2791
2792         if (!smu->pm_enabled)
2793                 return -EOPNOTSUPP;
2794
2795         if (state == 0) {
2796                 mutex_lock(&smu->mutex);
2797
2798                 if (smu->ppt_funcs->baco_exit)
2799                         ret = smu->ppt_funcs->baco_exit(smu);
2800
2801                 mutex_unlock(&smu->mutex);
2802         } else if (state == 1) {
2803                 mutex_lock(&smu->mutex);
2804
2805                 if (smu->ppt_funcs->baco_enter)
2806                         ret = smu->ppt_funcs->baco_enter(smu);
2807
2808                 mutex_unlock(&smu->mutex);
2809
2810         } else {
2811                 return -EINVAL;
2812         }
2813
2814         if (ret)
2815                 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2816                                 (state)?"enter":"exit");
2817
2818         return ret;
2819 }
2820
2821 bool smu_mode1_reset_is_support(struct smu_context *smu)
2822 {
2823         bool ret = false;
2824
2825         if (!smu->pm_enabled)
2826                 return false;
2827
2828         mutex_lock(&smu->mutex);
2829
2830         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2831                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2832
2833         mutex_unlock(&smu->mutex);
2834
2835         return ret;
2836 }
2837
2838 bool smu_mode2_reset_is_support(struct smu_context *smu)
2839 {
2840         bool ret = false;
2841
2842         if (!smu->pm_enabled)
2843                 return false;
2844
2845         mutex_lock(&smu->mutex);
2846
2847         if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2848                 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2849
2850         mutex_unlock(&smu->mutex);
2851
2852         return ret;
2853 }
2854
2855 int smu_mode1_reset(struct smu_context *smu)
2856 {
2857         int ret = 0;
2858
2859         if (!smu->pm_enabled)
2860                 return -EOPNOTSUPP;
2861
2862         mutex_lock(&smu->mutex);
2863
2864         if (smu->ppt_funcs->mode1_reset)
2865                 ret = smu->ppt_funcs->mode1_reset(smu);
2866
2867         mutex_unlock(&smu->mutex);
2868
2869         return ret;
2870 }
2871
2872 static int smu_mode2_reset(void *handle)
2873 {
2874         struct smu_context *smu = handle;
2875         int ret = 0;
2876
2877         if (!smu->pm_enabled)
2878                 return -EOPNOTSUPP;
2879
2880         mutex_lock(&smu->mutex);
2881
2882         if (smu->ppt_funcs->mode2_reset)
2883                 ret = smu->ppt_funcs->mode2_reset(smu);
2884
2885         mutex_unlock(&smu->mutex);
2886
2887         if (ret)
2888                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2889
2890         return ret;
2891 }
2892
2893 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2894                                                 struct pp_smu_nv_clock_table *max_clocks)
2895 {
2896         struct smu_context *smu = handle;
2897         int ret = 0;
2898
2899         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2900                 return -EOPNOTSUPP;
2901
2902         mutex_lock(&smu->mutex);
2903
2904         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2905                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2906
2907         mutex_unlock(&smu->mutex);
2908
2909         return ret;
2910 }
2911
2912 static int smu_get_uclk_dpm_states(void *handle,
2913                                    unsigned int *clock_values_in_khz,
2914                                    unsigned int *num_states)
2915 {
2916         struct smu_context *smu = handle;
2917         int ret = 0;
2918
2919         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2920                 return -EOPNOTSUPP;
2921
2922         mutex_lock(&smu->mutex);
2923
2924         if (smu->ppt_funcs->get_uclk_dpm_states)
2925                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2926
2927         mutex_unlock(&smu->mutex);
2928
2929         return ret;
2930 }
2931
2932 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
2933 {
2934         struct smu_context *smu = handle;
2935         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2936
2937         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2938                 return -EOPNOTSUPP;
2939
2940         mutex_lock(&smu->mutex);
2941
2942         if (smu->ppt_funcs->get_current_power_state)
2943                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2944
2945         mutex_unlock(&smu->mutex);
2946
2947         return pm_state;
2948 }
2949
2950 static int smu_get_dpm_clock_table(void *handle,
2951                                    struct dpm_clocks *clock_table)
2952 {
2953         struct smu_context *smu = handle;
2954         int ret = 0;
2955
2956         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2957                 return -EOPNOTSUPP;
2958
2959         mutex_lock(&smu->mutex);
2960
2961         if (smu->ppt_funcs->get_dpm_clock_table)
2962                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2963
2964         mutex_unlock(&smu->mutex);
2965
2966         return ret;
2967 }
2968
2969 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
2970 {
2971         struct smu_context *smu = handle;
2972         ssize_t size;
2973
2974         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2975                 return -EOPNOTSUPP;
2976
2977         if (!smu->ppt_funcs->get_gpu_metrics)
2978                 return -EOPNOTSUPP;
2979
2980         mutex_lock(&smu->mutex);
2981
2982         size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2983
2984         mutex_unlock(&smu->mutex);
2985
2986         return size;
2987 }
2988
2989 static int smu_enable_mgpu_fan_boost(void *handle)
2990 {
2991         struct smu_context *smu = handle;
2992         int ret = 0;
2993
2994         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2995                 return -EOPNOTSUPP;
2996
2997         mutex_lock(&smu->mutex);
2998
2999         if (smu->ppt_funcs->enable_mgpu_fan_boost)
3000                 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
3001
3002         mutex_unlock(&smu->mutex);
3003
3004         return ret;
3005 }
3006
3007 static int smu_gfx_state_change_set(void *handle,
3008                                     uint32_t state)
3009 {
3010         struct smu_context *smu = handle;
3011         int ret = 0;
3012
3013         mutex_lock(&smu->mutex);
3014         if (smu->ppt_funcs->gfx_state_change_set)
3015                 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
3016         mutex_unlock(&smu->mutex);
3017
3018         return ret;
3019 }
3020
3021 int smu_set_light_sbr(struct smu_context *smu, bool enable)
3022 {
3023         int ret = 0;
3024
3025         mutex_lock(&smu->mutex);
3026         if (smu->ppt_funcs->set_light_sbr)
3027                 ret = smu->ppt_funcs->set_light_sbr(smu, enable);
3028         mutex_unlock(&smu->mutex);
3029
3030         return ret;
3031 }
3032
3033 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3034 {
3035         struct smu_context *smu = handle;
3036         struct smu_table_context *smu_table = &smu->smu_table;
3037         struct smu_table *memory_pool = &smu_table->memory_pool;
3038
3039         if (!addr || !size)
3040                 return -EINVAL;
3041
3042         *addr = NULL;
3043         *size = 0;
3044         mutex_lock(&smu->mutex);
3045         if (memory_pool->bo) {
3046                 *addr = memory_pool->cpu_addr;
3047                 *size = memory_pool->size;
3048         }
3049         mutex_unlock(&smu->mutex);
3050
3051         return 0;
3052 }
3053
3054 static const struct amd_pm_funcs swsmu_pm_funcs = {
3055         /* export for sysfs */
3056         .set_fan_control_mode    = smu_pp_set_fan_control_mode,
3057         .get_fan_control_mode    = smu_get_fan_control_mode,
3058         .set_fan_speed_pwm   = smu_set_fan_speed_pwm,
3059         .get_fan_speed_pwm   = smu_get_fan_speed_pwm,
3060         .force_clock_level       = smu_force_ppclk_levels,
3061         .print_clock_levels      = smu_print_ppclk_levels,
3062         .force_performance_level = smu_force_performance_level,
3063         .read_sensor             = smu_read_sensor,
3064         .get_performance_level   = smu_get_performance_level,
3065         .get_current_power_state = smu_get_current_power_state,
3066         .get_fan_speed_rpm       = smu_get_fan_speed_rpm,
3067         .set_fan_speed_rpm       = smu_set_fan_speed_rpm,
3068         .get_pp_num_states       = smu_get_power_num_states,
3069         .get_pp_table            = smu_sys_get_pp_table,
3070         .set_pp_table            = smu_sys_set_pp_table,
3071         .switch_power_profile    = smu_switch_power_profile,
3072         /* export to amdgpu */
3073         .dispatch_tasks          = smu_handle_dpm_task,
3074         .load_firmware           = smu_load_microcode,
3075         .set_powergating_by_smu  = smu_dpm_set_power_gate,
3076         .set_power_limit         = smu_set_power_limit,
3077         .get_power_limit         = smu_get_power_limit,
3078         .get_power_profile_mode  = smu_get_power_profile_mode,
3079         .set_power_profile_mode  = smu_set_power_profile_mode,
3080         .odn_edit_dpm_table      = smu_od_edit_dpm_table,
3081         .set_mp1_state           = smu_set_mp1_state,
3082         .gfx_state_change_set    = smu_gfx_state_change_set,
3083         /* export to DC */
3084         .get_sclk                         = smu_get_sclk,
3085         .get_mclk                         = smu_get_mclk,
3086         .display_configuration_change     = smu_display_configuration_change,
3087         .get_clock_by_type_with_latency   = smu_get_clock_by_type_with_latency,
3088         .display_clock_voltage_request    = smu_display_clock_voltage_request,
3089         .enable_mgpu_fan_boost            = smu_enable_mgpu_fan_boost,
3090         .set_active_display_count         = smu_set_display_count,
3091         .set_min_deep_sleep_dcefclk       = smu_set_deep_sleep_dcefclk,
3092         .get_asic_baco_capability         = smu_get_baco_capability,
3093         .set_asic_baco_state              = smu_baco_set_state,
3094         .get_ppfeature_status             = smu_sys_get_pp_feature_mask,
3095         .set_ppfeature_status             = smu_sys_set_pp_feature_mask,
3096         .asic_reset_mode_2                = smu_mode2_reset,
3097         .set_df_cstate                    = smu_set_df_cstate,
3098         .set_xgmi_pstate                  = smu_set_xgmi_pstate,
3099         .get_gpu_metrics                  = smu_sys_get_gpu_metrics,
3100         .set_watermarks_for_clock_ranges     = smu_set_watermarks_for_clock_ranges,
3101         .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3102         .get_max_sustainable_clocks_by_dc    = smu_get_max_sustainable_clocks_by_dc,
3103         .get_uclk_dpm_states              = smu_get_uclk_dpm_states,
3104         .get_dpm_clock_table              = smu_get_dpm_clock_table,
3105         .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3106 };
3107
3108 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
3109                        uint64_t event_arg)
3110 {
3111         int ret = -EINVAL;
3112         struct smu_context *smu = &adev->smu;
3113
3114         if (smu->ppt_funcs->wait_for_event) {
3115                 mutex_lock(&smu->mutex);
3116                 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3117                 mutex_unlock(&smu->mutex);
3118         }
3119
3120         return ret;
3121 }