2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/gfp.h>
27 #include <linux/slab.h>
28 #include <linux/firmware.h>
29 #include "amd_shared.h"
30 #include "amd_powerplay.h"
31 #include "power_state.h"
36 static const struct amd_pm_funcs pp_dpm_funcs;
38 static int amd_powerplay_create(struct amdgpu_device *adev)
40 struct pp_hwmgr *hwmgr;
45 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
50 hwmgr->not_vf = !amdgpu_sriov_vf(adev);
51 hwmgr->device = amdgpu_cgs_create_device(adev);
52 mutex_init(&hwmgr->smu_lock);
53 mutex_init(&hwmgr->msg_lock);
54 hwmgr->chip_family = adev->family;
55 hwmgr->chip_id = adev->asic_type;
56 hwmgr->feature_mask = adev->pm.pp_feature;
57 hwmgr->display_config = &adev->pm.pm_display_cfg;
58 adev->powerplay.pp_handle = hwmgr;
59 adev->powerplay.pp_funcs = &pp_dpm_funcs;
64 static void amd_powerplay_destroy(struct amdgpu_device *adev)
66 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
68 mutex_destroy(&hwmgr->msg_lock);
70 kfree(hwmgr->hardcode_pp_table);
71 hwmgr->hardcode_pp_table = NULL;
77 static int pp_early_init(void *handle)
80 struct amdgpu_device *adev = handle;
82 ret = amd_powerplay_create(adev);
87 ret = hwmgr_early_init(adev->powerplay.pp_handle);
94 static int pp_sw_init(void *handle)
96 struct amdgpu_device *adev = handle;
97 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
100 ret = hwmgr_sw_init(hwmgr);
102 pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully");
107 static int pp_sw_fini(void *handle)
109 struct amdgpu_device *adev = handle;
110 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
112 hwmgr_sw_fini(hwmgr);
114 release_firmware(adev->pm.fw);
120 static int pp_hw_init(void *handle)
123 struct amdgpu_device *adev = handle;
124 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
126 ret = hwmgr_hw_init(hwmgr);
129 pr_err("powerplay hw init failed\n");
134 static int pp_hw_fini(void *handle)
136 struct amdgpu_device *adev = handle;
137 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
139 hwmgr_hw_fini(hwmgr);
144 static void pp_reserve_vram_for_smu(struct amdgpu_device *adev)
147 void *cpu_ptr = NULL;
149 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
151 if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size,
152 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
153 &adev->pm.smu_prv_buffer,
156 DRM_ERROR("amdgpu: failed to create smu prv buffer\n");
160 if (hwmgr->hwmgr_func->notify_cac_buffer_info)
161 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr,
162 lower_32_bits((unsigned long)cpu_ptr),
163 upper_32_bits((unsigned long)cpu_ptr),
164 lower_32_bits(gpu_addr),
165 upper_32_bits(gpu_addr),
166 adev->pm.smu_prv_buffer_size);
169 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
170 adev->pm.smu_prv_buffer = NULL;
171 DRM_ERROR("amdgpu: failed to notify SMU buffer address\n");
175 static int pp_late_init(void *handle)
177 struct amdgpu_device *adev = handle;
178 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
180 if (hwmgr && hwmgr->pm_en) {
181 mutex_lock(&hwmgr->smu_lock);
182 hwmgr_handle_task(hwmgr,
183 AMD_PP_TASK_COMPLETE_INIT, NULL);
184 mutex_unlock(&hwmgr->smu_lock);
186 if (adev->pm.smu_prv_buffer_size != 0)
187 pp_reserve_vram_for_smu(adev);
192 static void pp_late_fini(void *handle)
194 struct amdgpu_device *adev = handle;
196 if (adev->pm.smu_prv_buffer)
197 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
198 amd_powerplay_destroy(adev);
202 static bool pp_is_idle(void *handle)
207 static int pp_wait_for_idle(void *handle)
212 static int pp_sw_reset(void *handle)
217 static int pp_set_powergating_state(void *handle,
218 enum amd_powergating_state state)
223 static int pp_suspend(void *handle)
225 struct amdgpu_device *adev = handle;
226 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
228 return hwmgr_suspend(hwmgr);
231 static int pp_resume(void *handle)
233 struct amdgpu_device *adev = handle;
234 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
236 return hwmgr_resume(hwmgr);
239 static int pp_set_clockgating_state(void *handle,
240 enum amd_clockgating_state state)
245 static const struct amd_ip_funcs pp_ip_funcs = {
247 .early_init = pp_early_init,
248 .late_init = pp_late_init,
249 .sw_init = pp_sw_init,
250 .sw_fini = pp_sw_fini,
251 .hw_init = pp_hw_init,
252 .hw_fini = pp_hw_fini,
253 .late_fini = pp_late_fini,
254 .suspend = pp_suspend,
256 .is_idle = pp_is_idle,
257 .wait_for_idle = pp_wait_for_idle,
258 .soft_reset = pp_sw_reset,
259 .set_clockgating_state = pp_set_clockgating_state,
260 .set_powergating_state = pp_set_powergating_state,
263 const struct amdgpu_ip_block_version pp_smu_ip_block =
265 .type = AMD_IP_BLOCK_TYPE_SMC,
269 .funcs = &pp_ip_funcs,
272 /* This interface only be supported On Vi,
273 * because only smu7/8 can help to load gfx/sdma fw,
274 * smu need to be enabled before load other ip's fw.
275 * so call start smu to load smu7 fw and other ip's fw
277 static int pp_dpm_load_fw(void *handle)
279 struct pp_hwmgr *hwmgr = handle;
281 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
284 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
285 pr_err("fw load failed\n");
292 static int pp_dpm_fw_loading_complete(void *handle)
297 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
299 struct pp_hwmgr *hwmgr = handle;
301 if (!hwmgr || !hwmgr->pm_en)
304 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
305 pr_info_ratelimited("%s was not implemented.\n", __func__);
309 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
312 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
313 enum amd_dpm_forced_level *level)
315 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
316 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
317 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
318 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
320 if (!(hwmgr->dpm_level & profile_mode_mask)) {
321 /* enter umd pstate, save current level, disable gfx cg*/
322 if (*level & profile_mode_mask) {
323 hwmgr->saved_dpm_level = hwmgr->dpm_level;
324 hwmgr->en_umd_pstate = true;
325 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
326 AMD_IP_BLOCK_TYPE_GFX,
327 AMD_PG_STATE_UNGATE);
328 amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
329 AMD_IP_BLOCK_TYPE_GFX,
330 AMD_CG_STATE_UNGATE);
333 /* exit umd pstate, restore level, enable gfx cg*/
334 if (!(*level & profile_mode_mask)) {
335 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
336 *level = hwmgr->saved_dpm_level;
337 hwmgr->en_umd_pstate = false;
338 amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
339 AMD_IP_BLOCK_TYPE_GFX,
341 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
342 AMD_IP_BLOCK_TYPE_GFX,
348 static int pp_dpm_force_performance_level(void *handle,
349 enum amd_dpm_forced_level level)
351 struct pp_hwmgr *hwmgr = handle;
353 if (!hwmgr || !hwmgr->pm_en)
356 if (level == hwmgr->dpm_level)
359 mutex_lock(&hwmgr->smu_lock);
360 pp_dpm_en_umd_pstate(hwmgr, &level);
361 hwmgr->request_dpm_level = level;
362 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
363 mutex_unlock(&hwmgr->smu_lock);
368 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
371 struct pp_hwmgr *hwmgr = handle;
372 enum amd_dpm_forced_level level;
374 if (!hwmgr || !hwmgr->pm_en)
377 mutex_lock(&hwmgr->smu_lock);
378 level = hwmgr->dpm_level;
379 mutex_unlock(&hwmgr->smu_lock);
383 static uint32_t pp_dpm_get_sclk(void *handle, bool low)
385 struct pp_hwmgr *hwmgr = handle;
388 if (!hwmgr || !hwmgr->pm_en)
391 if (hwmgr->hwmgr_func->get_sclk == NULL) {
392 pr_info_ratelimited("%s was not implemented.\n", __func__);
395 mutex_lock(&hwmgr->smu_lock);
396 clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
397 mutex_unlock(&hwmgr->smu_lock);
401 static uint32_t pp_dpm_get_mclk(void *handle, bool low)
403 struct pp_hwmgr *hwmgr = handle;
406 if (!hwmgr || !hwmgr->pm_en)
409 if (hwmgr->hwmgr_func->get_mclk == NULL) {
410 pr_info_ratelimited("%s was not implemented.\n", __func__);
413 mutex_lock(&hwmgr->smu_lock);
414 clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
415 mutex_unlock(&hwmgr->smu_lock);
419 static void pp_dpm_powergate_vce(void *handle, bool gate)
421 struct pp_hwmgr *hwmgr = handle;
423 if (!hwmgr || !hwmgr->pm_en)
426 if (hwmgr->hwmgr_func->powergate_vce == NULL) {
427 pr_info_ratelimited("%s was not implemented.\n", __func__);
430 mutex_lock(&hwmgr->smu_lock);
431 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
432 mutex_unlock(&hwmgr->smu_lock);
435 static void pp_dpm_powergate_uvd(void *handle, bool gate)
437 struct pp_hwmgr *hwmgr = handle;
439 if (!hwmgr || !hwmgr->pm_en)
442 if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
443 pr_info_ratelimited("%s was not implemented.\n", __func__);
446 mutex_lock(&hwmgr->smu_lock);
447 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
448 mutex_unlock(&hwmgr->smu_lock);
451 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
452 enum amd_pm_state_type *user_state)
455 struct pp_hwmgr *hwmgr = handle;
457 if (!hwmgr || !hwmgr->pm_en)
460 mutex_lock(&hwmgr->smu_lock);
461 ret = hwmgr_handle_task(hwmgr, task_id, user_state);
462 mutex_unlock(&hwmgr->smu_lock);
467 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
469 struct pp_hwmgr *hwmgr = handle;
470 struct pp_power_state *state;
471 enum amd_pm_state_type pm_type;
473 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
476 mutex_lock(&hwmgr->smu_lock);
478 state = hwmgr->current_ps;
480 switch (state->classification.ui_label) {
481 case PP_StateUILabel_Battery:
482 pm_type = POWER_STATE_TYPE_BATTERY;
484 case PP_StateUILabel_Balanced:
485 pm_type = POWER_STATE_TYPE_BALANCED;
487 case PP_StateUILabel_Performance:
488 pm_type = POWER_STATE_TYPE_PERFORMANCE;
491 if (state->classification.flags & PP_StateClassificationFlag_Boot)
492 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
494 pm_type = POWER_STATE_TYPE_DEFAULT;
497 mutex_unlock(&hwmgr->smu_lock);
502 static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
504 struct pp_hwmgr *hwmgr = handle;
506 if (!hwmgr || !hwmgr->pm_en)
509 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
510 pr_info_ratelimited("%s was not implemented.\n", __func__);
513 mutex_lock(&hwmgr->smu_lock);
514 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
515 mutex_unlock(&hwmgr->smu_lock);
518 static uint32_t pp_dpm_get_fan_control_mode(void *handle)
520 struct pp_hwmgr *hwmgr = handle;
523 if (!hwmgr || !hwmgr->pm_en)
526 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
527 pr_info_ratelimited("%s was not implemented.\n", __func__);
530 mutex_lock(&hwmgr->smu_lock);
531 mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
532 mutex_unlock(&hwmgr->smu_lock);
536 static int pp_dpm_set_fan_speed_pwm(void *handle, uint32_t speed)
538 struct pp_hwmgr *hwmgr = handle;
541 if (!hwmgr || !hwmgr->pm_en)
544 if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL) {
545 pr_info_ratelimited("%s was not implemented.\n", __func__);
548 mutex_lock(&hwmgr->smu_lock);
549 ret = hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed);
550 mutex_unlock(&hwmgr->smu_lock);
554 static int pp_dpm_get_fan_speed_pwm(void *handle, uint32_t *speed)
556 struct pp_hwmgr *hwmgr = handle;
559 if (!hwmgr || !hwmgr->pm_en)
562 if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL) {
563 pr_info_ratelimited("%s was not implemented.\n", __func__);
567 mutex_lock(&hwmgr->smu_lock);
568 ret = hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed);
569 mutex_unlock(&hwmgr->smu_lock);
573 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
575 struct pp_hwmgr *hwmgr = handle;
578 if (!hwmgr || !hwmgr->pm_en)
581 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
584 mutex_lock(&hwmgr->smu_lock);
585 ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
586 mutex_unlock(&hwmgr->smu_lock);
590 static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm)
592 struct pp_hwmgr *hwmgr = handle;
595 if (!hwmgr || !hwmgr->pm_en)
598 if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) {
599 pr_info_ratelimited("%s was not implemented.\n", __func__);
602 mutex_lock(&hwmgr->smu_lock);
603 ret = hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm);
604 mutex_unlock(&hwmgr->smu_lock);
608 static int pp_dpm_get_pp_num_states(void *handle,
609 struct pp_states_info *data)
611 struct pp_hwmgr *hwmgr = handle;
614 memset(data, 0, sizeof(*data));
616 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
619 mutex_lock(&hwmgr->smu_lock);
621 data->nums = hwmgr->num_ps;
623 for (i = 0; i < hwmgr->num_ps; i++) {
624 struct pp_power_state *state = (struct pp_power_state *)
625 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
626 switch (state->classification.ui_label) {
627 case PP_StateUILabel_Battery:
628 data->states[i] = POWER_STATE_TYPE_BATTERY;
630 case PP_StateUILabel_Balanced:
631 data->states[i] = POWER_STATE_TYPE_BALANCED;
633 case PP_StateUILabel_Performance:
634 data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
637 if (state->classification.flags & PP_StateClassificationFlag_Boot)
638 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
640 data->states[i] = POWER_STATE_TYPE_DEFAULT;
643 mutex_unlock(&hwmgr->smu_lock);
647 static int pp_dpm_get_pp_table(void *handle, char **table)
649 struct pp_hwmgr *hwmgr = handle;
652 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
655 mutex_lock(&hwmgr->smu_lock);
656 *table = (char *)hwmgr->soft_pp_table;
657 size = hwmgr->soft_pp_table_size;
658 mutex_unlock(&hwmgr->smu_lock);
662 static int amd_powerplay_reset(void *handle)
664 struct pp_hwmgr *hwmgr = handle;
667 ret = hwmgr_hw_fini(hwmgr);
671 ret = hwmgr_hw_init(hwmgr);
675 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
678 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
680 struct pp_hwmgr *hwmgr = handle;
683 if (!hwmgr || !hwmgr->pm_en)
686 mutex_lock(&hwmgr->smu_lock);
687 if (!hwmgr->hardcode_pp_table) {
688 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
689 hwmgr->soft_pp_table_size,
691 if (!hwmgr->hardcode_pp_table)
695 memcpy(hwmgr->hardcode_pp_table, buf, size);
697 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
699 ret = amd_powerplay_reset(handle);
703 if (hwmgr->hwmgr_func->avfs_control) {
704 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
708 mutex_unlock(&hwmgr->smu_lock);
711 mutex_unlock(&hwmgr->smu_lock);
715 static int pp_dpm_force_clock_level(void *handle,
716 enum pp_clock_type type, uint32_t mask)
718 struct pp_hwmgr *hwmgr = handle;
721 if (!hwmgr || !hwmgr->pm_en)
724 if (hwmgr->hwmgr_func->force_clock_level == NULL) {
725 pr_info_ratelimited("%s was not implemented.\n", __func__);
729 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
730 pr_debug("force clock level is for dpm manual mode only.\n");
734 mutex_lock(&hwmgr->smu_lock);
735 ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
736 mutex_unlock(&hwmgr->smu_lock);
740 static int pp_dpm_print_clock_levels(void *handle,
741 enum pp_clock_type type, char *buf)
743 struct pp_hwmgr *hwmgr = handle;
746 if (!hwmgr || !hwmgr->pm_en)
749 if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
750 pr_info_ratelimited("%s was not implemented.\n", __func__);
753 mutex_lock(&hwmgr->smu_lock);
754 ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
755 mutex_unlock(&hwmgr->smu_lock);
759 static int pp_dpm_get_sclk_od(void *handle)
761 struct pp_hwmgr *hwmgr = handle;
764 if (!hwmgr || !hwmgr->pm_en)
767 if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
768 pr_info_ratelimited("%s was not implemented.\n", __func__);
771 mutex_lock(&hwmgr->smu_lock);
772 ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
773 mutex_unlock(&hwmgr->smu_lock);
777 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
779 struct pp_hwmgr *hwmgr = handle;
782 if (!hwmgr || !hwmgr->pm_en)
785 if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
786 pr_info_ratelimited("%s was not implemented.\n", __func__);
790 mutex_lock(&hwmgr->smu_lock);
791 ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
792 mutex_unlock(&hwmgr->smu_lock);
796 static int pp_dpm_get_mclk_od(void *handle)
798 struct pp_hwmgr *hwmgr = handle;
801 if (!hwmgr || !hwmgr->pm_en)
804 if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
805 pr_info_ratelimited("%s was not implemented.\n", __func__);
808 mutex_lock(&hwmgr->smu_lock);
809 ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
810 mutex_unlock(&hwmgr->smu_lock);
814 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
816 struct pp_hwmgr *hwmgr = handle;
819 if (!hwmgr || !hwmgr->pm_en)
822 if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
823 pr_info_ratelimited("%s was not implemented.\n", __func__);
826 mutex_lock(&hwmgr->smu_lock);
827 ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
828 mutex_unlock(&hwmgr->smu_lock);
832 static int pp_dpm_read_sensor(void *handle, int idx,
833 void *value, int *size)
835 struct pp_hwmgr *hwmgr = handle;
838 if (!hwmgr || !hwmgr->pm_en || !value)
842 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
843 *((uint32_t *)value) = hwmgr->pstate_sclk;
845 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
846 *((uint32_t *)value) = hwmgr->pstate_mclk;
848 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
849 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;
851 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
852 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
855 mutex_lock(&hwmgr->smu_lock);
856 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
857 mutex_unlock(&hwmgr->smu_lock);
862 static struct amd_vce_state*
863 pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
865 struct pp_hwmgr *hwmgr = handle;
867 if (!hwmgr || !hwmgr->pm_en)
870 if (idx < hwmgr->num_vce_state_tables)
871 return &hwmgr->vce_states[idx];
875 static int pp_get_power_profile_mode(void *handle, char *buf)
877 struct pp_hwmgr *hwmgr = handle;
879 if (!hwmgr || !hwmgr->pm_en || !buf)
882 if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
883 pr_info_ratelimited("%s was not implemented.\n", __func__);
884 return snprintf(buf, PAGE_SIZE, "\n");
887 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
890 static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
892 struct pp_hwmgr *hwmgr = handle;
895 if (!hwmgr || !hwmgr->pm_en)
898 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
899 pr_info_ratelimited("%s was not implemented.\n", __func__);
903 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
904 pr_debug("power profile setting is for manual dpm mode only.\n");
908 mutex_lock(&hwmgr->smu_lock);
909 ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
910 mutex_unlock(&hwmgr->smu_lock);
914 static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size)
916 struct pp_hwmgr *hwmgr = handle;
918 if (!hwmgr || !hwmgr->pm_en)
921 if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL)
924 return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size);
927 static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
929 struct pp_hwmgr *hwmgr = handle;
931 if (!hwmgr || !hwmgr->pm_en)
934 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
935 pr_info_ratelimited("%s was not implemented.\n", __func__);
939 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
942 static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state)
944 struct pp_hwmgr *hwmgr = handle;
952 if (hwmgr->hwmgr_func->set_mp1_state)
953 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
958 static int pp_dpm_switch_power_profile(void *handle,
959 enum PP_SMC_POWER_PROFILE type, bool en)
961 struct pp_hwmgr *hwmgr = handle;
965 if (!hwmgr || !hwmgr->pm_en)
968 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
969 pr_info_ratelimited("%s was not implemented.\n", __func__);
973 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
976 mutex_lock(&hwmgr->smu_lock);
979 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
980 index = fls(hwmgr->workload_mask);
981 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
982 workload = hwmgr->workload_setting[index];
984 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
985 index = fls(hwmgr->workload_mask);
986 index = index <= Workload_Policy_Max ? index - 1 : 0;
987 workload = hwmgr->workload_setting[index];
990 if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
991 hwmgr->hwmgr_func->disable_power_features_for_compute_performance) {
992 if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) {
993 mutex_unlock(&hwmgr->smu_lock);
998 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
999 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
1000 mutex_unlock(&hwmgr->smu_lock);
1005 static int pp_set_power_limit(void *handle, uint32_t limit)
1007 struct pp_hwmgr *hwmgr = handle;
1008 uint32_t max_power_limit;
1010 if (!hwmgr || !hwmgr->pm_en)
1013 if (hwmgr->hwmgr_func->set_power_limit == NULL) {
1014 pr_info_ratelimited("%s was not implemented.\n", __func__);
1019 limit = hwmgr->default_power_limit;
1021 max_power_limit = hwmgr->default_power_limit;
1022 if (hwmgr->od_enabled) {
1023 max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1024 max_power_limit /= 100;
1027 if (limit > max_power_limit)
1030 mutex_lock(&hwmgr->smu_lock);
1031 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
1032 hwmgr->power_limit = limit;
1033 mutex_unlock(&hwmgr->smu_lock);
1037 static int pp_get_power_limit(void *handle, uint32_t *limit,
1038 enum pp_power_limit_level pp_limit_level,
1039 enum pp_power_type power_type)
1041 struct pp_hwmgr *hwmgr = handle;
1044 if (!hwmgr || !hwmgr->pm_en ||!limit)
1047 if (power_type != PP_PWR_TYPE_SUSTAINED)
1050 mutex_lock(&hwmgr->smu_lock);
1052 switch (pp_limit_level) {
1053 case PP_PWR_LIMIT_CURRENT:
1054 *limit = hwmgr->power_limit;
1056 case PP_PWR_LIMIT_DEFAULT:
1057 *limit = hwmgr->default_power_limit;
1059 case PP_PWR_LIMIT_MAX:
1060 *limit = hwmgr->default_power_limit;
1061 if (hwmgr->od_enabled) {
1062 *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1071 mutex_unlock(&hwmgr->smu_lock);
1076 static int pp_display_configuration_change(void *handle,
1077 const struct amd_pp_display_configuration *display_config)
1079 struct pp_hwmgr *hwmgr = handle;
1081 if (!hwmgr || !hwmgr->pm_en)
1084 mutex_lock(&hwmgr->smu_lock);
1085 phm_store_dal_configuration_data(hwmgr, display_config);
1086 mutex_unlock(&hwmgr->smu_lock);
1090 static int pp_get_display_power_level(void *handle,
1091 struct amd_pp_simple_clock_info *output)
1093 struct pp_hwmgr *hwmgr = handle;
1096 if (!hwmgr || !hwmgr->pm_en ||!output)
1099 mutex_lock(&hwmgr->smu_lock);
1100 ret = phm_get_dal_power_level(hwmgr, output);
1101 mutex_unlock(&hwmgr->smu_lock);
1105 static int pp_get_current_clocks(void *handle,
1106 struct amd_pp_clock_info *clocks)
1108 struct amd_pp_simple_clock_info simple_clocks = { 0 };
1109 struct pp_clock_info hw_clocks;
1110 struct pp_hwmgr *hwmgr = handle;
1113 if (!hwmgr || !hwmgr->pm_en)
1116 mutex_lock(&hwmgr->smu_lock);
1118 phm_get_dal_power_level(hwmgr, &simple_clocks);
1120 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1121 PHM_PlatformCaps_PowerContainment))
1122 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1123 &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment);
1125 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1126 &hw_clocks, PHM_PerformanceLevelDesignation_Activity);
1129 pr_debug("Error in phm_get_clock_info \n");
1130 mutex_unlock(&hwmgr->smu_lock);
1134 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1135 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1136 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1137 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1138 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1139 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1141 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1142 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1144 if (simple_clocks.level == 0)
1145 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1147 clocks->max_clocks_state = simple_clocks.level;
1149 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1150 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1151 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1153 mutex_unlock(&hwmgr->smu_lock);
1157 static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1159 struct pp_hwmgr *hwmgr = handle;
1162 if (!hwmgr || !hwmgr->pm_en)
1168 mutex_lock(&hwmgr->smu_lock);
1169 ret = phm_get_clock_by_type(hwmgr, type, clocks);
1170 mutex_unlock(&hwmgr->smu_lock);
1174 static int pp_get_clock_by_type_with_latency(void *handle,
1175 enum amd_pp_clock_type type,
1176 struct pp_clock_levels_with_latency *clocks)
1178 struct pp_hwmgr *hwmgr = handle;
1181 if (!hwmgr || !hwmgr->pm_en ||!clocks)
1184 mutex_lock(&hwmgr->smu_lock);
1185 ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1186 mutex_unlock(&hwmgr->smu_lock);
1190 static int pp_get_clock_by_type_with_voltage(void *handle,
1191 enum amd_pp_clock_type type,
1192 struct pp_clock_levels_with_voltage *clocks)
1194 struct pp_hwmgr *hwmgr = handle;
1197 if (!hwmgr || !hwmgr->pm_en ||!clocks)
1200 mutex_lock(&hwmgr->smu_lock);
1202 ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1204 mutex_unlock(&hwmgr->smu_lock);
1208 static int pp_set_watermarks_for_clocks_ranges(void *handle,
1211 struct pp_hwmgr *hwmgr = handle;
1214 if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
1217 mutex_lock(&hwmgr->smu_lock);
1218 ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
1220 mutex_unlock(&hwmgr->smu_lock);
1225 static int pp_display_clock_voltage_request(void *handle,
1226 struct pp_display_clock_request *clock)
1228 struct pp_hwmgr *hwmgr = handle;
1231 if (!hwmgr || !hwmgr->pm_en ||!clock)
1234 mutex_lock(&hwmgr->smu_lock);
1235 ret = phm_display_clock_voltage_request(hwmgr, clock);
1236 mutex_unlock(&hwmgr->smu_lock);
1241 static int pp_get_display_mode_validation_clocks(void *handle,
1242 struct amd_pp_simple_clock_info *clocks)
1244 struct pp_hwmgr *hwmgr = handle;
1247 if (!hwmgr || !hwmgr->pm_en ||!clocks)
1250 clocks->level = PP_DAL_POWERLEVEL_7;
1252 mutex_lock(&hwmgr->smu_lock);
1254 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1255 ret = phm_get_max_high_clocks(hwmgr, clocks);
1257 mutex_unlock(&hwmgr->smu_lock);
1261 static int pp_dpm_powergate_mmhub(void *handle)
1263 struct pp_hwmgr *hwmgr = handle;
1265 if (!hwmgr || !hwmgr->pm_en)
1268 if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
1269 pr_info_ratelimited("%s was not implemented.\n", __func__);
1273 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
1276 static int pp_dpm_powergate_gfx(void *handle, bool gate)
1278 struct pp_hwmgr *hwmgr = handle;
1280 if (!hwmgr || !hwmgr->pm_en)
1283 if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
1284 pr_info_ratelimited("%s was not implemented.\n", __func__);
1288 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
1291 static void pp_dpm_powergate_acp(void *handle, bool gate)
1293 struct pp_hwmgr *hwmgr = handle;
1295 if (!hwmgr || !hwmgr->pm_en)
1298 if (hwmgr->hwmgr_func->powergate_acp == NULL) {
1299 pr_info_ratelimited("%s was not implemented.\n", __func__);
1303 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
1306 static void pp_dpm_powergate_sdma(void *handle, bool gate)
1308 struct pp_hwmgr *hwmgr = handle;
1313 if (hwmgr->hwmgr_func->powergate_sdma == NULL) {
1314 pr_info_ratelimited("%s was not implemented.\n", __func__);
1318 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate);
1321 static int pp_set_powergating_by_smu(void *handle,
1322 uint32_t block_type, bool gate)
1326 switch (block_type) {
1327 case AMD_IP_BLOCK_TYPE_UVD:
1328 case AMD_IP_BLOCK_TYPE_VCN:
1329 pp_dpm_powergate_uvd(handle, gate);
1331 case AMD_IP_BLOCK_TYPE_VCE:
1332 pp_dpm_powergate_vce(handle, gate);
1334 case AMD_IP_BLOCK_TYPE_GMC:
1335 pp_dpm_powergate_mmhub(handle);
1337 case AMD_IP_BLOCK_TYPE_GFX:
1338 ret = pp_dpm_powergate_gfx(handle, gate);
1340 case AMD_IP_BLOCK_TYPE_ACP:
1341 pp_dpm_powergate_acp(handle, gate);
1343 case AMD_IP_BLOCK_TYPE_SDMA:
1344 pp_dpm_powergate_sdma(handle, gate);
1352 static int pp_notify_smu_enable_pwe(void *handle)
1354 struct pp_hwmgr *hwmgr = handle;
1356 if (!hwmgr || !hwmgr->pm_en)
1359 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) {
1360 pr_info_ratelimited("%s was not implemented.\n", __func__);
1364 mutex_lock(&hwmgr->smu_lock);
1365 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr);
1366 mutex_unlock(&hwmgr->smu_lock);
1371 static int pp_enable_mgpu_fan_boost(void *handle)
1373 struct pp_hwmgr *hwmgr = handle;
1378 if (!hwmgr->pm_en ||
1379 hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL)
1382 mutex_lock(&hwmgr->smu_lock);
1383 hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr);
1384 mutex_unlock(&hwmgr->smu_lock);
1389 static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock)
1391 struct pp_hwmgr *hwmgr = handle;
1393 if (!hwmgr || !hwmgr->pm_en)
1396 if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) {
1397 pr_debug("%s was not implemented.\n", __func__);
1401 mutex_lock(&hwmgr->smu_lock);
1402 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
1403 mutex_unlock(&hwmgr->smu_lock);
1408 static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock)
1410 struct pp_hwmgr *hwmgr = handle;
1412 if (!hwmgr || !hwmgr->pm_en)
1415 if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) {
1416 pr_debug("%s was not implemented.\n", __func__);
1420 mutex_lock(&hwmgr->smu_lock);
1421 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
1422 mutex_unlock(&hwmgr->smu_lock);
1427 static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock)
1429 struct pp_hwmgr *hwmgr = handle;
1431 if (!hwmgr || !hwmgr->pm_en)
1434 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) {
1435 pr_debug("%s was not implemented.\n", __func__);
1439 mutex_lock(&hwmgr->smu_lock);
1440 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
1441 mutex_unlock(&hwmgr->smu_lock);
1446 static int pp_set_active_display_count(void *handle, uint32_t count)
1448 struct pp_hwmgr *hwmgr = handle;
1451 if (!hwmgr || !hwmgr->pm_en)
1454 mutex_lock(&hwmgr->smu_lock);
1455 ret = phm_set_active_display_count(hwmgr, count);
1456 mutex_unlock(&hwmgr->smu_lock);
1461 static int pp_get_asic_baco_capability(void *handle, bool *cap)
1463 struct pp_hwmgr *hwmgr = handle;
1469 if (!(hwmgr->not_vf && amdgpu_dpm) ||
1470 !hwmgr->hwmgr_func->get_asic_baco_capability)
1473 mutex_lock(&hwmgr->smu_lock);
1474 hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
1475 mutex_unlock(&hwmgr->smu_lock);
1480 static int pp_get_asic_baco_state(void *handle, int *state)
1482 struct pp_hwmgr *hwmgr = handle;
1487 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
1490 mutex_lock(&hwmgr->smu_lock);
1491 hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state);
1492 mutex_unlock(&hwmgr->smu_lock);
1497 static int pp_set_asic_baco_state(void *handle, int state)
1499 struct pp_hwmgr *hwmgr = handle;
1504 if (!(hwmgr->not_vf && amdgpu_dpm) ||
1505 !hwmgr->hwmgr_func->set_asic_baco_state)
1508 mutex_lock(&hwmgr->smu_lock);
1509 hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
1510 mutex_unlock(&hwmgr->smu_lock);
1515 static int pp_get_ppfeature_status(void *handle, char *buf)
1517 struct pp_hwmgr *hwmgr = handle;
1520 if (!hwmgr || !hwmgr->pm_en || !buf)
1523 if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) {
1524 pr_info_ratelimited("%s was not implemented.\n", __func__);
1528 mutex_lock(&hwmgr->smu_lock);
1529 ret = hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf);
1530 mutex_unlock(&hwmgr->smu_lock);
1535 static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
1537 struct pp_hwmgr *hwmgr = handle;
1540 if (!hwmgr || !hwmgr->pm_en)
1543 if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) {
1544 pr_info_ratelimited("%s was not implemented.\n", __func__);
1548 mutex_lock(&hwmgr->smu_lock);
1549 ret = hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks);
1550 mutex_unlock(&hwmgr->smu_lock);
1555 static int pp_asic_reset_mode_2(void *handle)
1557 struct pp_hwmgr *hwmgr = handle;
1560 if (!hwmgr || !hwmgr->pm_en)
1563 if (hwmgr->hwmgr_func->asic_reset == NULL) {
1564 pr_info_ratelimited("%s was not implemented.\n", __func__);
1568 mutex_lock(&hwmgr->smu_lock);
1569 ret = hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
1570 mutex_unlock(&hwmgr->smu_lock);
1575 static int pp_smu_i2c_bus_access(void *handle, bool acquire)
1577 struct pp_hwmgr *hwmgr = handle;
1580 if (!hwmgr || !hwmgr->pm_en)
1583 if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) {
1584 pr_info_ratelimited("%s was not implemented.\n", __func__);
1588 mutex_lock(&hwmgr->smu_lock);
1589 ret = hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
1590 mutex_unlock(&hwmgr->smu_lock);
1595 static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
1597 struct pp_hwmgr *hwmgr = handle;
1602 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate)
1605 mutex_lock(&hwmgr->smu_lock);
1606 hwmgr->hwmgr_func->set_df_cstate(hwmgr, state);
1607 mutex_unlock(&hwmgr->smu_lock);
1612 static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)
1614 struct pp_hwmgr *hwmgr = handle;
1619 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
1622 mutex_lock(&hwmgr->smu_lock);
1623 hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
1624 mutex_unlock(&hwmgr->smu_lock);
1629 static ssize_t pp_get_gpu_metrics(void *handle, void **table)
1631 struct pp_hwmgr *hwmgr = handle;
1637 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics)
1640 mutex_lock(&hwmgr->smu_lock);
1641 size = hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table);
1642 mutex_unlock(&hwmgr->smu_lock);
1647 static int pp_gfx_state_change_set(void *handle, uint32_t state)
1649 struct pp_hwmgr *hwmgr = handle;
1651 if (!hwmgr || !hwmgr->pm_en)
1654 if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
1655 pr_info_ratelimited("%s was not implemented.\n", __func__);
1659 mutex_lock(&hwmgr->smu_lock);
1660 hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
1661 mutex_unlock(&hwmgr->smu_lock);
1665 static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size)
1667 struct pp_hwmgr *hwmgr = handle;
1668 struct amdgpu_device *adev = hwmgr->adev;
1675 mutex_lock(&hwmgr->smu_lock);
1676 if (adev->pm.smu_prv_buffer) {
1677 amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr);
1678 *size = adev->pm.smu_prv_buffer_size;
1680 mutex_unlock(&hwmgr->smu_lock);
1685 static const struct amd_pm_funcs pp_dpm_funcs = {
1686 .load_firmware = pp_dpm_load_fw,
1687 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
1688 .force_performance_level = pp_dpm_force_performance_level,
1689 .get_performance_level = pp_dpm_get_performance_level,
1690 .get_current_power_state = pp_dpm_get_current_power_state,
1691 .dispatch_tasks = pp_dpm_dispatch_tasks,
1692 .set_fan_control_mode = pp_dpm_set_fan_control_mode,
1693 .get_fan_control_mode = pp_dpm_get_fan_control_mode,
1694 .set_fan_speed_pwm = pp_dpm_set_fan_speed_pwm,
1695 .get_fan_speed_pwm = pp_dpm_get_fan_speed_pwm,
1696 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
1697 .set_fan_speed_rpm = pp_dpm_set_fan_speed_rpm,
1698 .get_pp_num_states = pp_dpm_get_pp_num_states,
1699 .get_pp_table = pp_dpm_get_pp_table,
1700 .set_pp_table = pp_dpm_set_pp_table,
1701 .force_clock_level = pp_dpm_force_clock_level,
1702 .print_clock_levels = pp_dpm_print_clock_levels,
1703 .get_sclk_od = pp_dpm_get_sclk_od,
1704 .set_sclk_od = pp_dpm_set_sclk_od,
1705 .get_mclk_od = pp_dpm_get_mclk_od,
1706 .set_mclk_od = pp_dpm_set_mclk_od,
1707 .read_sensor = pp_dpm_read_sensor,
1708 .get_vce_clock_state = pp_dpm_get_vce_clock_state,
1709 .switch_power_profile = pp_dpm_switch_power_profile,
1710 .set_clockgating_by_smu = pp_set_clockgating_by_smu,
1711 .set_powergating_by_smu = pp_set_powergating_by_smu,
1712 .get_power_profile_mode = pp_get_power_profile_mode,
1713 .set_power_profile_mode = pp_set_power_profile_mode,
1714 .set_fine_grain_clk_vol = pp_set_fine_grain_clk_vol,
1715 .odn_edit_dpm_table = pp_odn_edit_dpm_table,
1716 .set_mp1_state = pp_dpm_set_mp1_state,
1717 .set_power_limit = pp_set_power_limit,
1718 .get_power_limit = pp_get_power_limit,
1720 .get_sclk = pp_dpm_get_sclk,
1721 .get_mclk = pp_dpm_get_mclk,
1722 .display_configuration_change = pp_display_configuration_change,
1723 .get_display_power_level = pp_get_display_power_level,
1724 .get_current_clocks = pp_get_current_clocks,
1725 .get_clock_by_type = pp_get_clock_by_type,
1726 .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
1727 .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
1728 .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
1729 .display_clock_voltage_request = pp_display_clock_voltage_request,
1730 .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
1731 .notify_smu_enable_pwe = pp_notify_smu_enable_pwe,
1732 .enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost,
1733 .set_active_display_count = pp_set_active_display_count,
1734 .set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk,
1735 .set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq,
1736 .set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq,
1737 .get_asic_baco_capability = pp_get_asic_baco_capability,
1738 .get_asic_baco_state = pp_get_asic_baco_state,
1739 .set_asic_baco_state = pp_set_asic_baco_state,
1740 .get_ppfeature_status = pp_get_ppfeature_status,
1741 .set_ppfeature_status = pp_set_ppfeature_status,
1742 .asic_reset_mode_2 = pp_asic_reset_mode_2,
1743 .smu_i2c_bus_access = pp_smu_i2c_bus_access,
1744 .set_df_cstate = pp_set_df_cstate,
1745 .set_xgmi_pstate = pp_set_xgmi_pstate,
1746 .get_gpu_metrics = pp_get_gpu_metrics,
1747 .gfx_state_change_set = pp_gfx_state_change_set,
1748 .get_smu_prv_buf_details = pp_get_prv_buffer_details,