drivers/gpu/drm/amd/include/kgd_pp_interface.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __KGD_PP_INTERFACE_H__
  25 #define __KGD_PP_INTERFACE_H__
  26
  27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
  28
  29 struct amd_vce_state {
  30         /* vce clocks */
  31         u32 evclk;
  32         u32 ecclk;
  33         /* gpu clocks */
  34         u32 sclk;
  35         u32 mclk;
  36         u8 clk_idx;
  37         u8 pstate;
  38 };
  39
  40
  41 enum amd_dpm_forced_level {
  42         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  43         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  44         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  45         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  46         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  47         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  48         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  49         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  50         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  51         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
  52 };
  53
  54 enum amd_pm_state_type {
  55         /* not used for dpm */
  56         POWER_STATE_TYPE_DEFAULT,
  57         POWER_STATE_TYPE_POWERSAVE,
  58         /* user selectable states */
  59         POWER_STATE_TYPE_BATTERY,
  60         POWER_STATE_TYPE_BALANCED,
  61         POWER_STATE_TYPE_PERFORMANCE,
  62         /* internal states */
  63         POWER_STATE_TYPE_INTERNAL_UVD,
  64         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  65         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  66         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  67         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  68         POWER_STATE_TYPE_INTERNAL_BOOT,
  69         POWER_STATE_TYPE_INTERNAL_THERMAL,
  70         POWER_STATE_TYPE_INTERNAL_ACPI,
  71         POWER_STATE_TYPE_INTERNAL_ULV,
  72         POWER_STATE_TYPE_INTERNAL_3DPERF,
  73 };
  74
  75 #define AMD_MAX_VCE_LEVELS 6
  76
  77 enum amd_vce_level {
  78         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  79         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  80         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  81         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  82         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  83         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  84 };
  85
  86 enum amd_fan_ctrl_mode {
  87         AMD_FAN_CTRL_NONE = 0,
  88         AMD_FAN_CTRL_MANUAL = 1,
  89         AMD_FAN_CTRL_AUTO = 2,
  90 };
  91
  92 enum pp_clock_type {
  93         PP_SCLK,
  94         PP_MCLK,
  95         PP_PCIE,
  96         PP_SOCCLK,
  97         PP_FCLK,
  98         PP_DCEFCLK,
  99         PP_VCLK,
 100         PP_DCLK,
 101         OD_SCLK,
 102         OD_MCLK,
 103         OD_VDDC_CURVE,
 104         OD_RANGE,
 105         OD_VDDGFX_OFFSET,
 106         OD_CCLK,
 107 };
 108
 109 enum amd_pp_sensors {
 110         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
 111         AMDGPU_PP_SENSOR_CPU_CLK,
 112         AMDGPU_PP_SENSOR_VDDNB,
 113         AMDGPU_PP_SENSOR_VDDGFX,
 114         AMDGPU_PP_SENSOR_UVD_VCLK,
 115         AMDGPU_PP_SENSOR_UVD_DCLK,
 116         AMDGPU_PP_SENSOR_VCE_ECCLK,
 117         AMDGPU_PP_SENSOR_GPU_LOAD,
 118         AMDGPU_PP_SENSOR_MEM_LOAD,
 119         AMDGPU_PP_SENSOR_GFX_MCLK,
 120         AMDGPU_PP_SENSOR_GPU_TEMP,
 121         AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
 122         AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 123         AMDGPU_PP_SENSOR_MEM_TEMP,
 124         AMDGPU_PP_SENSOR_VCE_POWER,
 125         AMDGPU_PP_SENSOR_UVD_POWER,
 126         AMDGPU_PP_SENSOR_GPU_POWER,
 127         AMDGPU_PP_SENSOR_SS_APU_SHARE,
 128         AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 129         AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 130         AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 131         AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 132         AMDGPU_PP_SENSOR_MIN_FAN_RPM,
 133         AMDGPU_PP_SENSOR_MAX_FAN_RPM,
 134         AMDGPU_PP_SENSOR_VCN_POWER_STATE,
 135 };
 136
 137 enum amd_pp_task {
 138         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
 139         AMD_PP_TASK_ENABLE_USER_STATE,
 140         AMD_PP_TASK_READJUST_POWER_STATE,
 141         AMD_PP_TASK_COMPLETE_INIT,
 142         AMD_PP_TASK_MAX
 143 };
 144
 145 enum PP_SMC_POWER_PROFILE {
 146         PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
 147         PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
 148         PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
 149         PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
 150         PP_SMC_POWER_PROFILE_VR           = 0x4,
 151         PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
 152         PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 153         PP_SMC_POWER_PROFILE_COUNT,
 154 };
 155
 156 enum {
 157         PP_GROUP_UNKNOWN = 0,
 158         PP_GROUP_GFX = 1,
 159         PP_GROUP_SYS,
 160         PP_GROUP_MAX
 161 };
 162
 163 enum PP_OD_DPM_TABLE_COMMAND {
 164         PP_OD_EDIT_SCLK_VDDC_TABLE,
 165         PP_OD_EDIT_MCLK_VDDC_TABLE,
 166         PP_OD_EDIT_CCLK_VDDC_TABLE,
 167         PP_OD_EDIT_VDDC_CURVE,
 168         PP_OD_RESTORE_DEFAULT_TABLE,
 169         PP_OD_COMMIT_DPM_TABLE,
 170         PP_OD_EDIT_VDDGFX_OFFSET
 171 };
 172
 173 struct pp_states_info {
 174         uint32_t nums;
 175         uint32_t states[16];
 176 };
 177
 178 enum PP_HWMON_TEMP {
 179         PP_TEMP_EDGE = 0,
 180         PP_TEMP_JUNCTION,
 181         PP_TEMP_MEM,
 182         PP_TEMP_MAX
 183 };
 184
 185 enum pp_mp1_state {
 186         PP_MP1_STATE_NONE,
 187         PP_MP1_STATE_SHUTDOWN,
 188         PP_MP1_STATE_UNLOAD,
 189         PP_MP1_STATE_RESET,
 190 };
 191
 192 enum pp_df_cstate {
 193         DF_CSTATE_DISALLOW = 0,
 194         DF_CSTATE_ALLOW,
 195 };
 196
 197 /**
 198  * DOC: amdgpu_pp_power
 199  *
 200  * APU power is managed to system-level requirements through the PPT
 201  * (package power tracking) feature. PPT is intended to limit power to the
 202  * requirements of the power source and could be dynamically updated to
 203  * maximize APU performance within the system power budget.
 204  *
 205  * Two types of power measurement can be requested, where supported, with
 206  * :c:type:`enum pp_power_type <pp_power_type>`.
 207  */
 208
 209 /**
 210  * enum pp_power_limit_level - Used to query the power limits
 211  *
 212  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
 213  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
 214  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
 215  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
 216  */
 217 enum pp_power_limit_level
 218 {
 219         PP_PWR_LIMIT_MIN = -1,
 220         PP_PWR_LIMIT_CURRENT,
 221         PP_PWR_LIMIT_DEFAULT,
 222         PP_PWR_LIMIT_MAX,
 223 };
 224
 225 /**
 226  * enum pp_power_type - Used to specify the type of the requested power
 227  *
 228  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
 229  * moving average of APU power (default ~5000 ms).
 230  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
 231  * where supported.
 232  */
 233 enum pp_power_type
 234 {
 235         PP_PWR_TYPE_SUSTAINED,
 236         PP_PWR_TYPE_FAST,
 237 };
 238
 239 #define PP_GROUP_MASK        0xF0000000
 240 #define PP_GROUP_SHIFT       28
 241
 242 #define PP_BLOCK_MASK        0x0FFFFF00
 243 #define PP_BLOCK_SHIFT       8
 244
 245 #define PP_BLOCK_GFX_CG         0x01
 246 #define PP_BLOCK_GFX_MG         0x02
 247 #define PP_BLOCK_GFX_3D         0x04
 248 #define PP_BLOCK_GFX_RLC        0x08
 249 #define PP_BLOCK_GFX_CP         0x10
 250 #define PP_BLOCK_SYS_BIF        0x01
 251 #define PP_BLOCK_SYS_MC         0x02
 252 #define PP_BLOCK_SYS_ROM        0x04
 253 #define PP_BLOCK_SYS_DRM        0x08
 254 #define PP_BLOCK_SYS_HDP        0x10
 255 #define PP_BLOCK_SYS_SDMA       0x20
 256
 257 #define PP_STATE_MASK           0x0000000F
 258 #define PP_STATE_SHIFT          0
 259 #define PP_STATE_SUPPORT_MASK   0x000000F0
 260 #define PP_STATE_SUPPORT_SHIFT  0
 261
 262 #define PP_STATE_CG             0x01
 263 #define PP_STATE_LS             0x02
 264 #define PP_STATE_DS             0x04
 265 #define PP_STATE_SD             0x08
 266 #define PP_STATE_SUPPORT_CG     0x10
 267 #define PP_STATE_SUPPORT_LS     0x20
 268 #define PP_STATE_SUPPORT_DS     0x40
 269 #define PP_STATE_SUPPORT_SD     0x80
 270
 271 #define PP_CG_MSG_ID(group, block, support, state) \
 272                 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
 273                 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
 274
 275 #define XGMI_MODE_PSTATE_D3 0
 276 #define XGMI_MODE_PSTATE_D0 1
 277
 278 #define NUM_HBM_INSTANCES 4
 279
 280 struct seq_file;
 281 enum amd_pp_clock_type;
 282 struct amd_pp_simple_clock_info;
 283 struct amd_pp_display_configuration;
 284 struct amd_pp_clock_info;
 285 struct pp_display_clock_request;
 286 struct pp_clock_levels_with_voltage;
 287 struct pp_clock_levels_with_latency;
 288 struct amd_pp_clocks;
 289 struct pp_smu_wm_range_sets;
 290 struct pp_smu_nv_clock_table;
 291 struct dpm_clocks;
 292
 293 struct amd_pm_funcs {
 294 /* export for dpm on ci and si */
 295         int (*pre_set_power_state)(void *handle);
 296         int (*set_power_state)(void *handle);
 297         void (*post_set_power_state)(void *handle);
 298         void (*display_configuration_changed)(void *handle);
 299         void (*print_power_state)(void *handle, void *ps);
 300         bool (*vblank_too_short)(void *handle);
 301         void (*enable_bapm)(void *handle, bool enable);
 302         int (*check_state_equal)(void *handle,
 303                                 void  *cps,
 304                                 void  *rps,
 305                                 bool  *equal);
 306 /* export for sysfs */
 307         void (*set_fan_control_mode)(void *handle, u32 mode);
 308         u32 (*get_fan_control_mode)(void *handle);
 309         int (*set_fan_speed_pwm)(void *handle, u32 speed);
 310         int (*get_fan_speed_pwm)(void *handle, u32 *speed);
 311         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 312         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 313         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 314         int (*get_sclk_od)(void *handle);
 315         int (*set_sclk_od)(void *handle, uint32_t value);
 316         int (*get_mclk_od)(void *handle);
 317         int (*set_mclk_od)(void *handle, uint32_t value);
 318         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 319         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 320         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 321         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 322         int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
 323         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 324         int (*get_pp_table)(void *handle, char **table);
 325         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 326         void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 327         int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 328 /* export to amdgpu */
 329         struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 330         int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 331                         enum amd_pm_state_type *user_state);
 332         int (*load_firmware)(void *handle);
 333         int (*wait_for_fw_loading_complete)(void *handle);
 334         int (*set_powergating_by_smu)(void *handle,
 335                                 uint32_t block_type, bool gate);
 336         int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 337         int (*set_power_limit)(void *handle, uint32_t n);
 338         int (*get_power_limit)(void *handle, uint32_t *limit,
 339                         enum pp_power_limit_level pp_limit_level,
 340                         enum pp_power_type power_type);
 341         int (*get_power_profile_mode)(void *handle, char *buf);
 342         int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 343         int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
 344         int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
 345         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 346         int (*smu_i2c_bus_access)(void *handle, bool acquire);
 347         int (*gfx_state_change_set)(void *handle, uint32_t state);
 348 /* export to DC */
 349         u32 (*get_sclk)(void *handle, bool low);
 350         u32 (*get_mclk)(void *handle, bool low);
 351         int (*display_configuration_change)(void *handle,
 352                 const struct amd_pp_display_configuration *input);
 353         int (*get_display_power_level)(void *handle,
 354                 struct amd_pp_simple_clock_info *output);
 355         int (*get_current_clocks)(void *handle,
 356                 struct amd_pp_clock_info *clocks);
 357         int (*get_clock_by_type)(void *handle,
 358                 enum amd_pp_clock_type type,
 359                 struct amd_pp_clocks *clocks);
 360         int (*get_clock_by_type_with_latency)(void *handle,
 361                 enum amd_pp_clock_type type,
 362                 struct pp_clock_levels_with_latency *clocks);
 363         int (*get_clock_by_type_with_voltage)(void *handle,
 364                 enum amd_pp_clock_type type,
 365                 struct pp_clock_levels_with_voltage *clocks);
 366         int (*set_watermarks_for_clocks_ranges)(void *handle,
 367                                                 void *clock_ranges);
 368         int (*display_clock_voltage_request)(void *handle,
 369                                 struct pp_display_clock_request *clock);
 370         int (*get_display_mode_validation_clocks)(void *handle,
 371                 struct amd_pp_simple_clock_info *clocks);
 372         int (*notify_smu_enable_pwe)(void *handle);
 373         int (*enable_mgpu_fan_boost)(void *handle);
 374         int (*set_active_display_count)(void *handle, uint32_t count);
 375         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 376         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 377         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 378         int (*get_asic_baco_capability)(void *handle, bool *cap);
 379         int (*get_asic_baco_state)(void *handle, int *state);
 380         int (*set_asic_baco_state)(void *handle, int state);
 381         int (*get_ppfeature_status)(void *handle, char *buf);
 382         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 383         int (*asic_reset_mode_2)(void *handle);
 384         int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
 385         int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
 386         ssize_t (*get_gpu_metrics)(void *handle, void **table);
 387         int (*set_watermarks_for_clock_ranges)(void *handle,
 388                                                struct pp_smu_wm_range_sets *ranges);
 389         int (*display_disable_memory_clock_switch)(void *handle,
 390                                                    bool disable_memory_clock_switch);
 391         int (*get_max_sustainable_clocks_by_dc)(void *handle,
 392                                                 struct pp_smu_nv_clock_table *max_clocks);
 393         int (*get_uclk_dpm_states)(void *handle,
 394                                    unsigned int *clock_values_in_khz,
 395                                    unsigned int *num_states);
 396         int (*get_dpm_clock_table)(void *handle,
 397                                    struct dpm_clocks *clock_table);
 398         int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 399 };
 400
 401 struct metrics_table_header {
 402         uint16_t                        structure_size;
 403         uint8_t                         format_revision;
 404         uint8_t                         content_revision;
 405 };
 406
 407 /*
 408  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
 409  * Use gpu_metrics_v1_1 or later instead.
 410  */
 411 struct gpu_metrics_v1_0 {
 412         struct metrics_table_header     common_header;
 413
 414         /* Driver attached timestamp (in ns) */
 415         uint64_t                        system_clock_counter;
 416
 417         /* Temperature */
 418         uint16_t                        temperature_edge;
 419         uint16_t                        temperature_hotspot;
 420         uint16_t                        temperature_mem;
 421         uint16_t                        temperature_vrgfx;
 422         uint16_t                        temperature_vrsoc;
 423         uint16_t                        temperature_vrmem;
 424
 425         /* Utilization */
 426         uint16_t                        average_gfx_activity;
 427         uint16_t                        average_umc_activity; // memory controller
 428         uint16_t                        average_mm_activity; // UVD or VCN
 429
 430         /* Power/Energy */
 431         uint16_t                        average_socket_power;
 432         uint32_t                        energy_accumulator;
 433
 434         /* Average clocks */
 435         uint16_t                        average_gfxclk_frequency;
 436         uint16_t                        average_socclk_frequency;
 437         uint16_t                        average_uclk_frequency;
 438         uint16_t                        average_vclk0_frequency;
 439         uint16_t                        average_dclk0_frequency;
 440         uint16_t                        average_vclk1_frequency;
 441         uint16_t                        average_dclk1_frequency;
 442
 443         /* Current clocks */
 444         uint16_t                        current_gfxclk;
 445         uint16_t                        current_socclk;
 446         uint16_t                        current_uclk;
 447         uint16_t                        current_vclk0;
 448         uint16_t                        current_dclk0;
 449         uint16_t                        current_vclk1;
 450         uint16_t                        current_dclk1;
 451
 452         /* Throttle status */
 453         uint32_t                        throttle_status;
 454
 455         /* Fans */
 456         uint16_t                        current_fan_speed;
 457
 458         /* Link width/speed */
 459         uint8_t                         pcie_link_width;
 460         uint8_t                         pcie_link_speed; // in 0.1 GT/s
 461 };
 462
 463 struct gpu_metrics_v1_1 {
 464         struct metrics_table_header     common_header;
 465
 466         /* Temperature */
 467         uint16_t                        temperature_edge;
 468         uint16_t                        temperature_hotspot;
 469         uint16_t                        temperature_mem;
 470         uint16_t                        temperature_vrgfx;
 471         uint16_t                        temperature_vrsoc;
 472         uint16_t                        temperature_vrmem;
 473
 474         /* Utilization */
 475         uint16_t                        average_gfx_activity;
 476         uint16_t                        average_umc_activity; // memory controller
 477         uint16_t                        average_mm_activity; // UVD or VCN
 478
 479         /* Power/Energy */
 480         uint16_t                        average_socket_power;
 481         uint64_t                        energy_accumulator;
 482
 483         /* Driver attached timestamp (in ns) */
 484         uint64_t                        system_clock_counter;
 485
 486         /* Average clocks */
 487         uint16_t                        average_gfxclk_frequency;
 488         uint16_t                        average_socclk_frequency;
 489         uint16_t                        average_uclk_frequency;
 490         uint16_t                        average_vclk0_frequency;
 491         uint16_t                        average_dclk0_frequency;
 492         uint16_t                        average_vclk1_frequency;
 493         uint16_t                        average_dclk1_frequency;
 494
 495         /* Current clocks */
 496         uint16_t                        current_gfxclk;
 497         uint16_t                        current_socclk;
 498         uint16_t                        current_uclk;
 499         uint16_t                        current_vclk0;
 500         uint16_t                        current_dclk0;
 501         uint16_t                        current_vclk1;
 502         uint16_t                        current_dclk1;
 503
 504         /* Throttle status */
 505         uint32_t                        throttle_status;
 506
 507         /* Fans */
 508         uint16_t                        current_fan_speed;
 509
 510         /* Link width/speed */
 511         uint16_t                        pcie_link_width;
 512         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 513
 514         uint16_t                        padding;
 515
 516         uint32_t                        gfx_activity_acc;
 517         uint32_t                        mem_activity_acc;
 518
 519         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 520 };
 521
 522 struct gpu_metrics_v1_2 {
 523         struct metrics_table_header     common_header;
 524
 525         /* Temperature */
 526         uint16_t                        temperature_edge;
 527         uint16_t                        temperature_hotspot;
 528         uint16_t                        temperature_mem;
 529         uint16_t                        temperature_vrgfx;
 530         uint16_t                        temperature_vrsoc;
 531         uint16_t                        temperature_vrmem;
 532
 533         /* Utilization */
 534         uint16_t                        average_gfx_activity;
 535         uint16_t                        average_umc_activity; // memory controller
 536         uint16_t                        average_mm_activity; // UVD or VCN
 537
 538         /* Power/Energy */
 539         uint16_t                        average_socket_power;
 540         uint64_t                        energy_accumulator;
 541
 542         /* Driver attached timestamp (in ns) */
 543         uint64_t                        system_clock_counter;
 544
 545         /* Average clocks */
 546         uint16_t                        average_gfxclk_frequency;
 547         uint16_t                        average_socclk_frequency;
 548         uint16_t                        average_uclk_frequency;
 549         uint16_t                        average_vclk0_frequency;
 550         uint16_t                        average_dclk0_frequency;
 551         uint16_t                        average_vclk1_frequency;
 552         uint16_t                        average_dclk1_frequency;
 553
 554         /* Current clocks */
 555         uint16_t                        current_gfxclk;
 556         uint16_t                        current_socclk;
 557         uint16_t                        current_uclk;
 558         uint16_t                        current_vclk0;
 559         uint16_t                        current_dclk0;
 560         uint16_t                        current_vclk1;
 561         uint16_t                        current_dclk1;
 562
 563         /* Throttle status (ASIC dependent) */
 564         uint32_t                        throttle_status;
 565
 566         /* Fans */
 567         uint16_t                        current_fan_speed;
 568
 569         /* Link width/speed */
 570         uint16_t                        pcie_link_width;
 571         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 572
 573         uint16_t                        padding;
 574
 575         uint32_t                        gfx_activity_acc;
 576         uint32_t                        mem_activity_acc;
 577
 578         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 579
 580         /* PMFW attached timestamp (10ns resolution) */
 581         uint64_t                        firmware_timestamp;
 582 };
 583
 584 struct gpu_metrics_v1_3 {
 585         struct metrics_table_header     common_header;
 586
 587         /* Temperature */
 588         uint16_t                        temperature_edge;
 589         uint16_t                        temperature_hotspot;
 590         uint16_t                        temperature_mem;
 591         uint16_t                        temperature_vrgfx;
 592         uint16_t                        temperature_vrsoc;
 593         uint16_t                        temperature_vrmem;
 594
 595         /* Utilization */
 596         uint16_t                        average_gfx_activity;
 597         uint16_t                        average_umc_activity; // memory controller
 598         uint16_t                        average_mm_activity; // UVD or VCN
 599
 600         /* Power/Energy */
 601         uint16_t                        average_socket_power;
 602         uint64_t                        energy_accumulator;
 603
 604         /* Driver attached timestamp (in ns) */
 605         uint64_t                        system_clock_counter;
 606
 607         /* Average clocks */
 608         uint16_t                        average_gfxclk_frequency;
 609         uint16_t                        average_socclk_frequency;
 610         uint16_t                        average_uclk_frequency;
 611         uint16_t                        average_vclk0_frequency;
 612         uint16_t                        average_dclk0_frequency;
 613         uint16_t                        average_vclk1_frequency;
 614         uint16_t                        average_dclk1_frequency;
 615
 616         /* Current clocks */
 617         uint16_t                        current_gfxclk;
 618         uint16_t                        current_socclk;
 619         uint16_t                        current_uclk;
 620         uint16_t                        current_vclk0;
 621         uint16_t                        current_dclk0;
 622         uint16_t                        current_vclk1;
 623         uint16_t                        current_dclk1;
 624
 625         /* Throttle status */
 626         uint32_t                        throttle_status;
 627
 628         /* Fans */
 629         uint16_t                        current_fan_speed;
 630
 631         /* Link width/speed */
 632         uint16_t                        pcie_link_width;
 633         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 634
 635         uint16_t                        padding;
 636
 637         uint32_t                        gfx_activity_acc;
 638         uint32_t                        mem_activity_acc;
 639
 640         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 641
 642         /* PMFW attached timestamp (10ns resolution) */
 643         uint64_t                        firmware_timestamp;
 644
 645         /* Voltage (mV) */
 646         uint16_t                        voltage_soc;
 647         uint16_t                        voltage_gfx;
 648         uint16_t                        voltage_mem;
 649
 650         uint16_t                        padding1;
 651
 652         /* Throttle status (ASIC independent) */
 653         uint64_t                        indep_throttle_status;
 654 };
 655
 656 /*
 657  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
 658  * Use gpu_metrics_v2_1 or later instead.
 659  */
 660 struct gpu_metrics_v2_0 {
 661         struct metrics_table_header     common_header;
 662
 663         /* Driver attached timestamp (in ns) */
 664         uint64_t                        system_clock_counter;
 665
 666         /* Temperature */
 667         uint16_t                        temperature_gfx; // gfx temperature on APUs
 668         uint16_t                        temperature_soc; // soc temperature on APUs
 669         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 670         uint16_t                        temperature_l3[2];
 671
 672         /* Utilization */
 673         uint16_t                        average_gfx_activity;
 674         uint16_t                        average_mm_activity; // UVD or VCN
 675
 676         /* Power/Energy */
 677         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 678         uint16_t                        average_cpu_power;
 679         uint16_t                        average_soc_power;
 680         uint16_t                        average_gfx_power;
 681         uint16_t                        average_core_power[8]; // CPU core power on APUs
 682
 683         /* Average clocks */
 684         uint16_t                        average_gfxclk_frequency;
 685         uint16_t                        average_socclk_frequency;
 686         uint16_t                        average_uclk_frequency;
 687         uint16_t                        average_fclk_frequency;
 688         uint16_t                        average_vclk_frequency;
 689         uint16_t                        average_dclk_frequency;
 690
 691         /* Current clocks */
 692         uint16_t                        current_gfxclk;
 693         uint16_t                        current_socclk;
 694         uint16_t                        current_uclk;
 695         uint16_t                        current_fclk;
 696         uint16_t                        current_vclk;
 697         uint16_t                        current_dclk;
 698         uint16_t                        current_coreclk[8]; // CPU core clocks
 699         uint16_t                        current_l3clk[2];
 700
 701         /* Throttle status */
 702         uint32_t                        throttle_status;
 703
 704         /* Fans */
 705         uint16_t                        fan_pwm;
 706
 707         uint16_t                        padding;
 708 };
 709
 710 struct gpu_metrics_v2_1 {
 711         struct metrics_table_header     common_header;
 712
 713         /* Temperature */
 714         uint16_t                        temperature_gfx; // gfx temperature on APUs
 715         uint16_t                        temperature_soc; // soc temperature on APUs
 716         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 717         uint16_t                        temperature_l3[2];
 718
 719         /* Utilization */
 720         uint16_t                        average_gfx_activity;
 721         uint16_t                        average_mm_activity; // UVD or VCN
 722
 723         /* Driver attached timestamp (in ns) */
 724         uint64_t                        system_clock_counter;
 725
 726         /* Power/Energy */
 727         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 728         uint16_t                        average_cpu_power;
 729         uint16_t                        average_soc_power;
 730         uint16_t                        average_gfx_power;
 731         uint16_t                        average_core_power[8]; // CPU core power on APUs
 732
 733         /* Average clocks */
 734         uint16_t                        average_gfxclk_frequency;
 735         uint16_t                        average_socclk_frequency;
 736         uint16_t                        average_uclk_frequency;
 737         uint16_t                        average_fclk_frequency;
 738         uint16_t                        average_vclk_frequency;
 739         uint16_t                        average_dclk_frequency;
 740
 741         /* Current clocks */
 742         uint16_t                        current_gfxclk;
 743         uint16_t                        current_socclk;
 744         uint16_t                        current_uclk;
 745         uint16_t                        current_fclk;
 746         uint16_t                        current_vclk;
 747         uint16_t                        current_dclk;
 748         uint16_t                        current_coreclk[8]; // CPU core clocks
 749         uint16_t                        current_l3clk[2];
 750
 751         /* Throttle status */
 752         uint32_t                        throttle_status;
 753
 754         /* Fans */
 755         uint16_t                        fan_pwm;
 756
 757         uint16_t                        padding[3];
 758 };
 759
 760 struct gpu_metrics_v2_2 {
 761         struct metrics_table_header     common_header;
 762
 763         /* Temperature */
 764         uint16_t                        temperature_gfx; // gfx temperature on APUs
 765         uint16_t                        temperature_soc; // soc temperature on APUs
 766         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 767         uint16_t                        temperature_l3[2];
 768
 769         /* Utilization */
 770         uint16_t                        average_gfx_activity;
 771         uint16_t                        average_mm_activity; // UVD or VCN
 772
 773         /* Driver attached timestamp (in ns) */
 774         uint64_t                        system_clock_counter;
 775
 776         /* Power/Energy */
 777         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 778         uint16_t                        average_cpu_power;
 779         uint16_t                        average_soc_power;
 780         uint16_t                        average_gfx_power;
 781         uint16_t                        average_core_power[8]; // CPU core power on APUs
 782
 783         /* Average clocks */
 784         uint16_t                        average_gfxclk_frequency;
 785         uint16_t                        average_socclk_frequency;
 786         uint16_t                        average_uclk_frequency;
 787         uint16_t                        average_fclk_frequency;
 788         uint16_t                        average_vclk_frequency;
 789         uint16_t                        average_dclk_frequency;
 790
 791         /* Current clocks */
 792         uint16_t                        current_gfxclk;
 793         uint16_t                        current_socclk;
 794         uint16_t                        current_uclk;
 795         uint16_t                        current_fclk;
 796         uint16_t                        current_vclk;
 797         uint16_t                        current_dclk;
 798         uint16_t                        current_coreclk[8]; // CPU core clocks
 799         uint16_t                        current_l3clk[2];
 800
 801         /* Throttle status (ASIC dependent) */
 802         uint32_t                        throttle_status;
 803
 804         /* Fans */
 805         uint16_t                        fan_pwm;
 806
 807         uint16_t                        padding[3];
 808
 809         /* Throttle status (ASIC independent) */
 810         uint64_t                        indep_throttle_status;
 811 };
 812
 813 #endif