2 * Copyright (C) 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef _thm_11_0_2_SH_MASK_HEADER
23 #define _thm_11_0_2_SH_MASK_HEADER
26 //CG_MULT_THERMAL_STATUS
27 #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
28 #define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
29 #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL
30 #define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L
31 #define CG_FDO_CTRL2__TMIN__SHIFT 0x0
32 #define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL
33 #define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
34 #define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L
35 #define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
36 #define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL
37 #define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
38 #define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL
39 #define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
40 #define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L
43 #define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
44 #define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
45 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
46 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
47 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
48 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
49 #define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L
50 #define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L
51 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L
52 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L
53 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L
54 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L
55 //THM_THERMAL_INT_CTRL
56 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
57 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
58 #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10
59 #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
60 #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
61 #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
62 #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b
63 #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c
64 #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d
65 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL
66 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L
67 #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L
68 #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L
69 #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L
70 #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L
71 #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L
72 #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L
73 #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L
76 #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0
77 #define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1
78 #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2
79 #define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3
80 #define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4
81 #define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5
82 #define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6
83 #define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe
84 #define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f
85 #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L
86 #define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L
87 #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L
88 #define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L
89 #define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L
90 #define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L
91 #define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L
92 #define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L
93 #define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L
95 #define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
96 #define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L