drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15 #include "dc_dmub_srv.h"
  16 #include "dce/dmub_hw_lock_mgr.h"
  17 #include "inc/link_enc_cfg.h"
  18
  19 /*Travis*/
  20 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  21 /*Nutmeg*/
  22 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  23
  24 #define DC_LOGGER \
  25         link->ctx->logger
  26 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  27
  28 #include "link_dpcd.h"
  29
  30         /* maximum pre emphasis level allowed for each voltage swing level*/
  31         static const enum dc_pre_emphasis
  32         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  33                                             PRE_EMPHASIS_LEVEL2,
  34                                             PRE_EMPHASIS_LEVEL1,
  35                                             PRE_EMPHASIS_DISABLED };
  36
  37 enum {
  38         POST_LT_ADJ_REQ_LIMIT = 6,
  39         POST_LT_ADJ_REQ_TIMEOUT = 200
  40 };
  41
  42 static bool decide_fallback_link_setting(
  43                 struct dc_link_settings initial_link_settings,
  44                 struct dc_link_settings *current_link_setting,
  45                 enum link_training_result training_result);
  46 static struct dc_link_settings get_common_supported_link_settings(
  47                 struct dc_link_settings link_setting_a,
  48                 struct dc_link_settings link_setting_b);
  49
  50 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  51                 const struct dc_link_settings *link_settings)
  52 {
  53         union training_aux_rd_interval training_rd_interval;
  54         uint32_t wait_in_micro_secs = 100;
  55
  56         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  57         core_link_read_dpcd(
  58                         link,
  59                         DP_TRAINING_AUX_RD_INTERVAL,
  60                         (uint8_t *)&training_rd_interval,
  61                         sizeof(training_rd_interval));
  62         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  63                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  64         return wait_in_micro_secs;
  65 }
  66
  67 static uint32_t get_eq_training_aux_rd_interval(
  68         struct dc_link *link,
  69         const struct dc_link_settings *link_settings)
  70 {
  71         union training_aux_rd_interval training_rd_interval;
  72         uint32_t wait_in_micro_secs = 400;
  73
  74         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  75         /* overwrite the delay if rev > 1.1*/
  76         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  77                 /* DP 1.2 or later - retrieve delay through
  78                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  79                 core_link_read_dpcd(
  80                         link,
  81                         DP_TRAINING_AUX_RD_INTERVAL,
  82                         (uint8_t *)&training_rd_interval,
  83                         sizeof(training_rd_interval));
  84
  85                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  86                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  87         }
  88
  89         return wait_in_micro_secs;
  90 }
  91
  92 void dp_wait_for_training_aux_rd_interval(
  93         struct dc_link *link,
  94         uint32_t wait_in_micro_secs)
  95 {
  96         udelay(wait_in_micro_secs);
  97
  98         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
  99                 __func__,
 100                 wait_in_micro_secs);
 101 }
 102
 103 enum dpcd_training_patterns
 104         dc_dp_training_pattern_to_dpcd_training_pattern(
 105         struct dc_link *link,
 106         enum dc_dp_training_pattern pattern)
 107 {
 108         enum dpcd_training_patterns dpcd_tr_pattern =
 109         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 110
 111         switch (pattern) {
 112         case DP_TRAINING_PATTERN_SEQUENCE_1:
 113                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 114                 break;
 115         case DP_TRAINING_PATTERN_SEQUENCE_2:
 116                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 117                 break;
 118         case DP_TRAINING_PATTERN_SEQUENCE_3:
 119                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 120                 break;
 121         case DP_TRAINING_PATTERN_SEQUENCE_4:
 122                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 123                 break;
 124         case DP_TRAINING_PATTERN_VIDEOIDLE:
 125                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 126                 break;
 127         default:
 128                 ASSERT(0);
 129                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 130                         __func__, pattern);
 131                 break;
 132         }
 133
 134         return dpcd_tr_pattern;
 135 }
 136
 137 static void dpcd_set_training_pattern(
 138         struct dc_link *link,
 139         enum dc_dp_training_pattern training_pattern)
 140 {
 141         union dpcd_training_pattern dpcd_pattern = { {0} };
 142
 143         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 144                         dc_dp_training_pattern_to_dpcd_training_pattern(
 145                                         link, training_pattern);
 146
 147         core_link_write_dpcd(
 148                 link,
 149                 DP_TRAINING_PATTERN_SET,
 150                 &dpcd_pattern.raw,
 151                 1);
 152
 153         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 154                 __func__,
 155                 DP_TRAINING_PATTERN_SET,
 156                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 157 }
 158
 159 static enum dc_dp_training_pattern decide_cr_training_pattern(
 160                 const struct dc_link_settings *link_settings)
 161 {
 162         return DP_TRAINING_PATTERN_SEQUENCE_1;
 163 }
 164
 165 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 166                 const struct dc_link_settings *link_settings)
 167 {
 168         struct link_encoder *link_enc;
 169         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 170         struct encoder_feature_support *features;
 171         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 172
 173         /* Access link encoder capability based on whether it is statically
 174          * or dynamically assigned to a link.
 175          */
 176         if (link->is_dig_mapping_flexible &&
 177                         link->dc->res_pool->funcs->link_encs_assign)
 178                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
 179         else
 180                 link_enc = link->link_enc;
 181         ASSERT(link_enc);
 182         features = &link_enc->features;
 183
 184         if (features->flags.bits.IS_TPS3_CAPABLE)
 185                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 186
 187         if (features->flags.bits.IS_TPS4_CAPABLE)
 188                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 189
 190         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 191                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 192                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 193
 194         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 195                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 196                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 197
 198         return DP_TRAINING_PATTERN_SEQUENCE_2;
 199 }
 200
 201 enum dc_status dpcd_set_link_settings(
 202         struct dc_link *link,
 203         const struct link_training_settings *lt_settings)
 204 {
 205         uint8_t rate;
 206         enum dc_status status;
 207
 208         union down_spread_ctrl downspread = { {0} };
 209         union lane_count_set lane_count_set = { {0} };
 210
 211         downspread.raw = (uint8_t)
 212         (lt_settings->link_settings.link_spread);
 213
 214         lane_count_set.bits.LANE_COUNT_SET =
 215         lt_settings->link_settings.lane_count;
 216
 217         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 218         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 219
 220
 221         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 222                         lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 223                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 224                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 225         }
 226
 227         status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 228                 &downspread.raw, sizeof(downspread));
 229
 230         status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 231                 &lane_count_set.raw, 1);
 232
 233         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 234                         lt_settings->link_settings.use_link_rate_set == true) {
 235                 rate = 0;
 236                 /* WA for some MUX chips that will power down with eDP and lose supported
 237                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 238                  * MUX chip gets link rate set back before link training.
 239                  */
 240                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 241                         uint8_t supported_link_rates[16];
 242
 243                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 244                                         supported_link_rates, sizeof(supported_link_rates));
 245                 }
 246                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 247                 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
 248                                 &lt_settings->link_settings.link_rate_set, 1);
 249         } else {
 250                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 251                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 252         }
 253
 254         if (rate) {
 255                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 256                         __func__,
 257                         DP_LINK_BW_SET,
 258                         lt_settings->link_settings.link_rate,
 259                         DP_LANE_COUNT_SET,
 260                         lt_settings->link_settings.lane_count,
 261                         lt_settings->enhanced_framing,
 262                         DP_DOWNSPREAD_CTRL,
 263                         lt_settings->link_settings.link_spread);
 264         } else {
 265                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 266                         __func__,
 267                         DP_LINK_RATE_SET,
 268                         lt_settings->link_settings.link_rate_set,
 269                         DP_LANE_COUNT_SET,
 270                         lt_settings->link_settings.lane_count,
 271                         lt_settings->enhanced_framing,
 272                         DP_DOWNSPREAD_CTRL,
 273                         lt_settings->link_settings.link_spread);
 274         }
 275
 276         return status;
 277 }
 278
 279 uint8_t dc_dp_initialize_scrambling_data_symbols(
 280         struct dc_link *link,
 281         enum dc_dp_training_pattern pattern)
 282 {
 283         uint8_t disable_scrabled_data_symbols = 0;
 284
 285         switch (pattern) {
 286         case DP_TRAINING_PATTERN_SEQUENCE_1:
 287         case DP_TRAINING_PATTERN_SEQUENCE_2:
 288         case DP_TRAINING_PATTERN_SEQUENCE_3:
 289                 disable_scrabled_data_symbols = 1;
 290                 break;
 291         case DP_TRAINING_PATTERN_SEQUENCE_4:
 292                 disable_scrabled_data_symbols = 0;
 293                 break;
 294         default:
 295                 ASSERT(0);
 296                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 297                         __func__, pattern);
 298                 break;
 299         }
 300         return disable_scrabled_data_symbols;
 301 }
 302
 303 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 304 {
 305         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 306 }
 307
 308 static void dpcd_set_lt_pattern_and_lane_settings(
 309         struct dc_link *link,
 310         const struct link_training_settings *lt_settings,
 311         enum dc_dp_training_pattern pattern,
 312         uint32_t offset)
 313 {
 314         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 315
 316         uint32_t dpcd_base_lt_offset;
 317
 318         uint8_t dpcd_lt_buffer[5] = {0};
 319         union dpcd_training_pattern dpcd_pattern = { {0} };
 320         uint32_t lane;
 321         uint32_t size_in_bytes;
 322         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 323         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 324
 325         if (is_repeater(link, offset))
 326                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 327                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 328
 329         /*****************************************************************
 330         * DpcdAddress_TrainingPatternSet
 331         *****************************************************************/
 332         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 333                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 334
 335         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 336                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 337
 338         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 339                 = dpcd_pattern.raw;
 340
 341         if (is_repeater(link, offset)) {
 342                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 343                         __func__,
 344                         offset,
 345                         dpcd_base_lt_offset,
 346                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 347         } else {
 348                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 349                         __func__,
 350                         dpcd_base_lt_offset,
 351                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 352         }
 353         /*****************************************************************
 354         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 355         *****************************************************************/
 356         for (lane = 0; lane <
 357                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 358
 359                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 360                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 361                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 362                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 363
 364                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 365                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 366                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 367                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 368                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 369                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 370         }
 371
 372         /* concatenate everything into one buffer*/
 373
 374         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 375
 376          // 0x00103 - 0x00102
 377         memmove(
 378                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 379                 dpcd_lane,
 380                 size_in_bytes);
 381
 382         if (is_repeater(link, offset)) {
 383                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 384                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 385                         __func__,
 386                         offset,
 387                         dpcd_base_lt_offset,
 388                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 389                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 390                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 391                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 392         } else {
 393                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 394                         __func__,
 395                         dpcd_base_lt_offset,
 396                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 397                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 398                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 399                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 400         }
 401         if (edp_workaround) {
 402                 /* for eDP write in 2 parts because the 5-byte burst is
 403                 * causing issues on some eDP panels (EPR#366724)
 404                 */
 405                 core_link_write_dpcd(
 406                         link,
 407                         DP_TRAINING_PATTERN_SET,
 408                         &dpcd_pattern.raw,
 409                         sizeof(dpcd_pattern.raw));
 410
 411                 core_link_write_dpcd(
 412                         link,
 413                         DP_TRAINING_LANE0_SET,
 414                         (uint8_t *)(dpcd_lane),
 415                         size_in_bytes);
 416
 417                 } else
 418                 /* write it all in (1 + number-of-lanes)-byte burst*/
 419                         core_link_write_dpcd(
 420                                 link,
 421                                 dpcd_base_lt_offset,
 422                                 dpcd_lt_buffer,
 423                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 424
 425         link->cur_lane_setting = lt_settings->lane_settings[0];
 426 }
 427
 428 bool dp_is_cr_done(enum dc_lane_count ln_count,
 429         union lane_status *dpcd_lane_status)
 430 {
 431         uint32_t lane;
 432         /*LANEx_CR_DONE bits All 1's?*/
 433         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 434                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 435                         return false;
 436         }
 437         return true;
 438 }
 439
 440 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
 441                 union lane_status *dpcd_lane_status)
 442 {
 443         bool done = true;
 444         uint32_t lane;
 445         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 446                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 447                         done = false;
 448         return done;
 449 }
 450
 451 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
 452                 union lane_status *dpcd_lane_status)
 453 {
 454         bool locked = true;
 455         uint32_t lane;
 456         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 457                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
 458                         locked = false;
 459         return locked;
 460 }
 461
 462 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
 463 {
 464         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 465 }
 466
 467 void dp_update_drive_settings(
 468                 struct link_training_settings *dest,
 469                 struct link_training_settings src)
 470 {
 471         uint32_t lane;
 472         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 473                 if (dest->voltage_swing == NULL)
 474                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 475                 else
 476                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 477
 478                 if (dest->pre_emphasis == NULL)
 479                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 480                 else
 481                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 482
 483                 if (dest->post_cursor2 == NULL)
 484                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 485                 else
 486                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 487         }
 488 }
 489
 490 static uint8_t get_nibble_at_index(const uint8_t *buf,
 491         uint32_t index)
 492 {
 493         uint8_t nibble;
 494         nibble = buf[index / 2];
 495
 496         if (index % 2)
 497                 nibble >>= 4;
 498         else
 499                 nibble &= 0x0F;
 500
 501         return nibble;
 502 }
 503
 504 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 505         enum dc_voltage_swing voltage)
 506 {
 507         enum dc_pre_emphasis pre_emphasis;
 508         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 509
 510         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 511                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 512
 513         return pre_emphasis;
 514
 515 }
 516
 517 static void find_max_drive_settings(
 518         const struct link_training_settings *link_training_setting,
 519         struct link_training_settings *max_lt_setting)
 520 {
 521         uint32_t lane;
 522         struct dc_lane_settings max_requested;
 523
 524         max_requested.VOLTAGE_SWING =
 525                 link_training_setting->
 526                 lane_settings[0].VOLTAGE_SWING;
 527         max_requested.PRE_EMPHASIS =
 528                 link_training_setting->
 529                 lane_settings[0].PRE_EMPHASIS;
 530         /*max_requested.postCursor2 =
 531          * link_training_setting->laneSettings[0].postCursor2;*/
 532
 533         /* Determine what the maximum of the requested settings are*/
 534         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 535                         lane++) {
 536                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 537                         max_requested.VOLTAGE_SWING)
 538
 539                         max_requested.VOLTAGE_SWING =
 540                         link_training_setting->
 541                         lane_settings[lane].VOLTAGE_SWING;
 542
 543                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 544                                 max_requested.PRE_EMPHASIS)
 545                         max_requested.PRE_EMPHASIS =
 546                         link_training_setting->
 547                         lane_settings[lane].PRE_EMPHASIS;
 548
 549                 /*
 550                 if (link_training_setting->laneSettings[lane].postCursor2 >
 551                  max_requested.postCursor2)
 552                 {
 553                 max_requested.postCursor2 =
 554                 link_training_setting->laneSettings[lane].postCursor2;
 555                 }
 556                 */
 557         }
 558
 559         /* make sure the requested settings are
 560          * not higher than maximum settings*/
 561         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 562                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 563
 564         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 565                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 566         /*
 567         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 568         max_requested.postCursor2 = PostCursor2_MaxLevel;
 569         */
 570
 571         /* make sure the pre-emphasis matches the voltage swing*/
 572         if (max_requested.PRE_EMPHASIS >
 573                 get_max_pre_emphasis_for_voltage_swing(
 574                         max_requested.VOLTAGE_SWING))
 575                 max_requested.PRE_EMPHASIS =
 576                 get_max_pre_emphasis_for_voltage_swing(
 577                         max_requested.VOLTAGE_SWING);
 578
 579         /*
 580          * Post Cursor2 levels are completely independent from
 581          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 582          * can only be applied to each allowable combination of voltage
 583          * swing and pre-emphasis levels */
 584          /* if ( max_requested.postCursor2 >
 585           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 586           *  max_requested.postCursor2 =
 587           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 588           */
 589
 590         max_lt_setting->link_settings.link_rate =
 591                 link_training_setting->link_settings.link_rate;
 592         max_lt_setting->link_settings.lane_count =
 593         link_training_setting->link_settings.lane_count;
 594         max_lt_setting->link_settings.link_spread =
 595                 link_training_setting->link_settings.link_spread;
 596
 597         for (lane = 0; lane <
 598                 link_training_setting->link_settings.lane_count;
 599                 lane++) {
 600                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 601                         max_requested.VOLTAGE_SWING;
 602                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 603                         max_requested.PRE_EMPHASIS;
 604                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 605                  * max_requested.postCursor2;
 606                  */
 607         }
 608
 609 }
 610
 611 enum dc_status dp_get_lane_status_and_drive_settings(
 612         struct dc_link *link,
 613         const struct link_training_settings *link_training_setting,
 614         union lane_status *ln_status,
 615         union lane_align_status_updated *ln_status_updated,
 616         struct link_training_settings *req_settings,
 617         uint32_t offset)
 618 {
 619         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 620         uint8_t lane_adjust_offset = 4;
 621         unsigned int lane01_adjust_address;
 622         uint8_t dpcd_buf[6] = {0};
 623         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 624         struct link_training_settings request_settings = { {0} };
 625         uint32_t lane;
 626         enum dc_status status;
 627
 628         memset(req_settings, '\0', sizeof(struct link_training_settings));
 629
 630         if (is_repeater(link, offset)) {
 631                 lane01_status_address =
 632                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 633                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 634                 lane_adjust_offset = 3;
 635         }
 636
 637         status = core_link_read_dpcd(
 638                 link,
 639                 lane01_status_address,
 640                 (uint8_t *)(dpcd_buf),
 641                 sizeof(dpcd_buf));
 642
 643         for (lane = 0; lane <
 644                 (uint32_t)(link_training_setting->link_settings.lane_count);
 645                 lane++) {
 646
 647                 ln_status[lane].raw =
 648                         get_nibble_at_index(&dpcd_buf[0], lane);
 649                 dpcd_lane_adjust[lane].raw =
 650                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 651         }
 652
 653         ln_status_updated->raw = dpcd_buf[2];
 654
 655         if (is_repeater(link, offset)) {
 656                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 657                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 658                         __func__,
 659                         offset,
 660                         lane01_status_address, dpcd_buf[0],
 661                         lane01_status_address + 1, dpcd_buf[1]);
 662         } else {
 663                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 664                         __func__,
 665                         lane01_status_address, dpcd_buf[0],
 666                         lane01_status_address + 1, dpcd_buf[1]);
 667         }
 668         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 669
 670         if (is_repeater(link, offset))
 671                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 672                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 673
 674         if (is_repeater(link, offset)) {
 675                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 676                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 677                                         __func__,
 678                                         offset,
 679                                         lane01_adjust_address,
 680                                         dpcd_buf[lane_adjust_offset],
 681                                         lane01_adjust_address + 1,
 682                                         dpcd_buf[lane_adjust_offset + 1]);
 683         } else {
 684                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 685                         __func__,
 686                         lane01_adjust_address,
 687                         dpcd_buf[lane_adjust_offset],
 688                         lane01_adjust_address + 1,
 689                         dpcd_buf[lane_adjust_offset + 1]);
 690         }
 691
 692         /*copy to req_settings*/
 693         request_settings.link_settings.lane_count =
 694                 link_training_setting->link_settings.lane_count;
 695         request_settings.link_settings.link_rate =
 696                 link_training_setting->link_settings.link_rate;
 697         request_settings.link_settings.link_spread =
 698                 link_training_setting->link_settings.link_spread;
 699
 700         for (lane = 0; lane <
 701                 (uint32_t)(link_training_setting->link_settings.lane_count);
 702                 lane++) {
 703
 704                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 705                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 706                                 VOLTAGE_SWING_LANE);
 707                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 708                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 709                                 PRE_EMPHASIS_LANE);
 710         }
 711
 712         /*Note: for postcursor2, read adjusted
 713          * postcursor2 settings from*/
 714         /*DpcdAddress_AdjustRequestPostCursor2 =
 715          *0x020C (not implemented yet)*/
 716
 717         /* we find the maximum of the requested settings across all lanes*/
 718         /* and set this maximum for all lanes*/
 719         find_max_drive_settings(&request_settings, req_settings);
 720
 721         /* if post cursor 2 is needed in the future,
 722          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 723          */
 724
 725         return status;
 726 }
 727
 728 enum dc_status dpcd_set_lane_settings(
 729         struct dc_link *link,
 730         const struct link_training_settings *link_training_setting,
 731         uint32_t offset)
 732 {
 733         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 734         uint32_t lane;
 735         unsigned int lane0_set_address;
 736         enum dc_status status;
 737
 738         lane0_set_address = DP_TRAINING_LANE0_SET;
 739
 740         if (is_repeater(link, offset))
 741                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 742                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 743
 744         for (lane = 0; lane <
 745                 (uint32_t)(link_training_setting->
 746                 link_settings.lane_count);
 747                 lane++) {
 748                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 749                         (uint8_t)(link_training_setting->
 750                         lane_settings[lane].VOLTAGE_SWING);
 751                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 752                         (uint8_t)(link_training_setting->
 753                         lane_settings[lane].PRE_EMPHASIS);
 754                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 755                         (link_training_setting->
 756                         lane_settings[lane].VOLTAGE_SWING ==
 757                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 758                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 759                         (link_training_setting->
 760                         lane_settings[lane].PRE_EMPHASIS ==
 761                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 762         }
 763
 764         status = core_link_write_dpcd(link,
 765                 lane0_set_address,
 766                 (uint8_t *)(dpcd_lane),
 767                 link_training_setting->link_settings.lane_count);
 768
 769         /*
 770         if (LTSettings.link.rate == LinkRate_High2)
 771         {
 772                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 773                 for ( uint32_t lane = 0;
 774                 lane < lane_count_DPMax; lane++)
 775                 {
 776                         dpcd_lane2[lane].bits.post_cursor2_set =
 777                         static_cast<unsigned char>(
 778                         LTSettings.laneSettings[lane].postCursor2);
 779                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 780                 }
 781                 m_pDpcdAccessSrv->WriteDpcdData(
 782                 DpcdAddress_Lane0Set2,
 783                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 784                 LTSettings.link.lanes);
 785         }
 786         */
 787
 788         if (is_repeater(link, offset)) {
 789                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 790                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 791                         __func__,
 792                         offset,
 793                         lane0_set_address,
 794                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 795                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 796                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 797                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 798
 799         } else {
 800                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 801                         __func__,
 802                         lane0_set_address,
 803                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 804                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 805                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 806                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 807         }
 808         link->cur_lane_setting = link_training_setting->lane_settings[0];
 809
 810         return status;
 811 }
 812
 813 bool dp_is_max_vs_reached(
 814         const struct link_training_settings *lt_settings)
 815 {
 816         uint32_t lane;
 817         for (lane = 0; lane <
 818                 (uint32_t)(lt_settings->link_settings.lane_count);
 819                 lane++) {
 820                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 821                         == VOLTAGE_SWING_MAX_LEVEL)
 822                         return true;
 823         }
 824         return false;
 825
 826 }
 827
 828 static bool perform_post_lt_adj_req_sequence(
 829         struct dc_link *link,
 830         struct link_training_settings *lt_settings)
 831 {
 832         enum dc_lane_count lane_count =
 833         lt_settings->link_settings.lane_count;
 834
 835         uint32_t adj_req_count;
 836         uint32_t adj_req_timer;
 837         bool req_drv_setting_changed;
 838         uint32_t lane;
 839
 840         req_drv_setting_changed = false;
 841         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 842         adj_req_count++) {
 843
 844                 req_drv_setting_changed = false;
 845
 846                 for (adj_req_timer = 0;
 847                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 848                         adj_req_timer++) {
 849
 850                         struct link_training_settings req_settings;
 851                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 852                         union lane_align_status_updated
 853                                 dpcd_lane_status_updated;
 854
 855                         dp_get_lane_status_and_drive_settings(
 856                                 link,
 857                                 lt_settings,
 858                                 dpcd_lane_status,
 859                                 &dpcd_lane_status_updated,
 860                                 &req_settings,
 861                                 DPRX);
 862
 863                         if (dpcd_lane_status_updated.bits.
 864                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 865                                 return true;
 866
 867                         if (!dp_is_cr_done(lane_count, dpcd_lane_status))
 868                                 return false;
 869
 870                         if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
 871                                         !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
 872                                         !dp_is_interlane_aligned(dpcd_lane_status_updated))
 873                                 return false;
 874
 875                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 876
 877                                 if (lt_settings->
 878                                 lane_settings[lane].VOLTAGE_SWING !=
 879                                 req_settings.lane_settings[lane].
 880                                 VOLTAGE_SWING ||
 881                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 882                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 883
 884                                         req_drv_setting_changed = true;
 885                                         break;
 886                                 }
 887                         }
 888
 889                         if (req_drv_setting_changed) {
 890                                 dp_update_drive_settings(
 891                                         lt_settings, req_settings);
 892
 893                                 dc_link_dp_set_drive_settings(link,
 894                                                 lt_settings);
 895                                 break;
 896                         }
 897
 898                         msleep(1);
 899                 }
 900
 901                 if (!req_drv_setting_changed) {
 902                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 903                                 __func__);
 904
 905                         ASSERT(0);
 906                         return true;
 907                 }
 908         }
 909         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 910                 __func__);
 911
 912         ASSERT(0);
 913         return true;
 914
 915 }
 916
 917 /* Only used for channel equalization */
 918 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 919 {
 920         unsigned int aux_rd_interval_us = 400;
 921
 922         switch (dpcd_aux_read_interval) {
 923         case 0x01:
 924                 aux_rd_interval_us = 4000;
 925                 break;
 926         case 0x02:
 927                 aux_rd_interval_us = 8000;
 928                 break;
 929         case 0x03:
 930                 aux_rd_interval_us = 12000;
 931                 break;
 932         case 0x04:
 933                 aux_rd_interval_us = 16000;
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939         return aux_rd_interval_us;
 940 }
 941
 942 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
 943                                         union lane_status *dpcd_lane_status)
 944 {
 945         enum link_training_result result = LINK_TRAINING_SUCCESS;
 946
 947         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 948                 result = LINK_TRAINING_CR_FAIL_LANE0;
 949         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 950                 result = LINK_TRAINING_CR_FAIL_LANE1;
 951         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 952                 result = LINK_TRAINING_CR_FAIL_LANE23;
 953         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 954                 result = LINK_TRAINING_CR_FAIL_LANE23;
 955         return result;
 956 }
 957
 958 static enum link_training_result perform_channel_equalization_sequence(
 959         struct dc_link *link,
 960         struct link_training_settings *lt_settings,
 961         uint32_t offset)
 962 {
 963         struct link_training_settings req_settings;
 964         enum dc_dp_training_pattern tr_pattern;
 965         uint32_t retries_ch_eq;
 966         uint32_t wait_time_microsec;
 967         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 968         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 969         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 970
 971         /* Note: also check that TPS4 is a supported feature*/
 972
 973         tr_pattern = lt_settings->pattern_for_eq;
 974
 975         if (is_repeater(link, offset))
 976                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 977
 978         dp_set_hw_training_pattern(link, tr_pattern, offset);
 979
 980         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 981                 retries_ch_eq++) {
 982
 983                 dp_set_hw_lane_settings(link, lt_settings, offset);
 984
 985                 /* 2. update DPCD*/
 986                 if (!retries_ch_eq)
 987                         /* EPR #361076 - write as a 5-byte burst,
 988                          * but only for the 1-st iteration
 989                          */
 990
 991                         dpcd_set_lt_pattern_and_lane_settings(
 992                                 link,
 993                                 lt_settings,
 994                                 tr_pattern, offset);
 995                 else
 996                         dpcd_set_lane_settings(link, lt_settings, offset);
 997
 998                 /* 3. wait for receiver to lock-on*/
 999                 wait_time_microsec = lt_settings->eq_pattern_time;
1000
1001                 if (is_repeater(link, offset))
1002                         wait_time_microsec =
1003                                         dp_translate_training_aux_read_interval(
1004                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1005
1006                 dp_wait_for_training_aux_rd_interval(
1007                                 link,
1008                                 wait_time_microsec);
1009
1010                 /* 4. Read lane status and requested
1011                  * drive settings as set by the sink*/
1012
1013                 dp_get_lane_status_and_drive_settings(
1014                         link,
1015                         lt_settings,
1016                         dpcd_lane_status,
1017                         &dpcd_lane_status_updated,
1018                         &req_settings,
1019                         offset);
1020
1021                 /* 5. check CR done*/
1022                 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1023                         return LINK_TRAINING_EQ_FAIL_CR;
1024
1025                 /* 6. check CHEQ done*/
1026                 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1027                                 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1028                                 dp_is_interlane_aligned(dpcd_lane_status_updated))
1029                         return LINK_TRAINING_SUCCESS;
1030
1031                 /* 7. update VS/PE/PC2 in lt_settings*/
1032                 dp_update_drive_settings(lt_settings, req_settings);
1033         }
1034
1035         return LINK_TRAINING_EQ_FAIL_EQ;
1036
1037 }
1038
1039 static void start_clock_recovery_pattern_early(struct dc_link *link,
1040                 struct link_training_settings *lt_settings,
1041                 uint32_t offset)
1042 {
1043         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1044                         __func__);
1045         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1046         dp_set_hw_lane_settings(link, lt_settings, offset);
1047         udelay(400);
1048 }
1049
1050 static enum link_training_result perform_clock_recovery_sequence(
1051         struct dc_link *link,
1052         struct link_training_settings *lt_settings,
1053         uint32_t offset)
1054 {
1055         uint32_t retries_cr;
1056         uint32_t retry_count;
1057         uint32_t wait_time_microsec;
1058         struct link_training_settings req_settings;
1059         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1060         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1061         union lane_align_status_updated dpcd_lane_status_updated;
1062
1063         retries_cr = 0;
1064         retry_count = 0;
1065
1066         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1067                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1068
1069         /* najeeb - The synaptics MST hub can put the LT in
1070         * infinite loop by switching the VS
1071         */
1072         /* between level 0 and level 1 continuously, here
1073         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1074         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1075                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1076
1077                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1078                 memset(&dpcd_lane_status_updated, '\0',
1079                 sizeof(dpcd_lane_status_updated));
1080
1081                 /* 1. call HWSS to set lane settings*/
1082                 dp_set_hw_lane_settings(
1083                                 link,
1084                                 lt_settings,
1085                                 offset);
1086
1087                 /* 2. update DPCD of the receiver*/
1088                 if (!retry_count)
1089                         /* EPR #361076 - write as a 5-byte burst,
1090                          * but only for the 1-st iteration.*/
1091                         dpcd_set_lt_pattern_and_lane_settings(
1092                                         link,
1093                                         lt_settings,
1094                                         lt_settings->pattern_for_cr,
1095                                         offset);
1096                 else
1097                         dpcd_set_lane_settings(
1098                                         link,
1099                                         lt_settings,
1100                                         offset);
1101
1102                 /* 3. wait receiver to lock-on*/
1103                 wait_time_microsec = lt_settings->cr_pattern_time;
1104
1105                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1106                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1107
1108                 dp_wait_for_training_aux_rd_interval(
1109                                 link,
1110                                 wait_time_microsec);
1111
1112                 /* 4. Read lane status and requested drive
1113                 * settings as set by the sink
1114                 */
1115                 dp_get_lane_status_and_drive_settings(
1116                                 link,
1117                                 lt_settings,
1118                                 dpcd_lane_status,
1119                                 &dpcd_lane_status_updated,
1120                                 &req_settings,
1121                                 offset);
1122
1123                 /* 5. check CR done*/
1124                 if (dp_is_cr_done(lane_count, dpcd_lane_status))
1125                         return LINK_TRAINING_SUCCESS;
1126
1127                 /* 6. max VS reached*/
1128                 if (dp_is_max_vs_reached(lt_settings))
1129                         break;
1130
1131                 /* 7. same lane settings*/
1132                 /* Note: settings are the same for all lanes,
1133                  * so comparing first lane is sufficient*/
1134                 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1135                         req_settings.lane_settings[0].VOLTAGE_SWING)
1136                         && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1137                                 req_settings.lane_settings[0].PRE_EMPHASIS))
1138                         retries_cr++;
1139                 else
1140                         retries_cr = 0;
1141
1142                 /* 8. update VS/PE/PC2 in lt_settings*/
1143                 dp_update_drive_settings(lt_settings, req_settings);
1144
1145                 retry_count++;
1146         }
1147
1148         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1149                 ASSERT(0);
1150                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1151                         __func__,
1152                         LINK_TRAINING_MAX_CR_RETRY);
1153
1154         }
1155
1156         return dp_get_cr_failure(lane_count, dpcd_lane_status);
1157 }
1158
1159 static inline enum link_training_result dp_transition_to_video_idle(
1160         struct dc_link *link,
1161         struct link_training_settings *lt_settings,
1162         enum link_training_result status)
1163 {
1164         union lane_count_set lane_count_set = { {0} };
1165
1166         /* 4. mainlink output idle pattern*/
1167         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1168
1169         /*
1170          * 5. post training adjust if required
1171          * If the upstream DPTX and downstream DPRX both support TPS4,
1172          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1173          */
1174         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1175                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1176                 /* delay 5ms after Main Link output idle pattern and then check
1177                  * DPCD 0202h.
1178                  */
1179                 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1180                         msleep(5);
1181                         status = dp_check_link_loss_status(link, lt_settings);
1182                 }
1183                 return status;
1184         }
1185
1186         if (status == LINK_TRAINING_SUCCESS &&
1187                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1188                 status = LINK_TRAINING_LQA_FAIL;
1189
1190         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1191         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1192         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1193
1194         core_link_write_dpcd(
1195                 link,
1196                 DP_LANE_COUNT_SET,
1197                 &lane_count_set.raw,
1198                 sizeof(lane_count_set));
1199
1200         return status;
1201 }
1202
1203 enum link_training_result dp_check_link_loss_status(
1204         struct dc_link *link,
1205         const struct link_training_settings *link_training_setting)
1206 {
1207         enum link_training_result status = LINK_TRAINING_SUCCESS;
1208         union lane_status lane_status;
1209         uint8_t dpcd_buf[6] = {0};
1210         uint32_t lane;
1211
1212         core_link_read_dpcd(
1213                         link,
1214                         DP_SINK_COUNT,
1215                         (uint8_t *)(dpcd_buf),
1216                         sizeof(dpcd_buf));
1217
1218         /*parse lane status*/
1219         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1220                 /*
1221                  * check lanes status
1222                  */
1223                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1224
1225                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1226                         !lane_status.bits.CR_DONE_0 ||
1227                         !lane_status.bits.SYMBOL_LOCKED_0) {
1228                         /* if one of the channel equalization, clock
1229                          * recovery or symbol lock is dropped
1230                          * consider it as (link has been
1231                          * dropped) dp sink status has changed
1232                          */
1233                         status = LINK_TRAINING_LINK_LOSS;
1234                         break;
1235                 }
1236         }
1237
1238         return status;
1239 }
1240
1241 static inline void decide_8b_10b_training_settings(
1242          struct dc_link *link,
1243         const struct dc_link_settings *link_setting,
1244         struct link_training_settings *lt_settings)
1245 {
1246         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1247
1248         /* Initialize link settings */
1249         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1250         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1251         lt_settings->link_settings.link_rate = link_setting->link_rate;
1252         lt_settings->link_settings.lane_count = link_setting->lane_count;
1253         /* TODO hard coded to SS for now
1254          * lt_settings.link_settings.link_spread =
1255          * dal_display_path_is_ss_supported(
1256          * path_mode->display_path) ?
1257          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1258          * LINK_SPREAD_DISABLED;
1259          */
1260         lt_settings->link_settings.link_spread = link->dp_ss_off ?
1261                         LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1262         lt_settings->lttpr_mode = link->lttpr_mode;
1263         lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1264         lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1265         lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1266         lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1267         lt_settings->enhanced_framing = 1;
1268         lt_settings->should_set_fec_ready = true;
1269 }
1270
1271 void dp_decide_training_settings(
1272                 struct dc_link *link,
1273                 const struct dc_link_settings *link_settings,
1274                 struct link_training_settings *lt_settings)
1275 {
1276         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1277                 decide_8b_10b_training_settings(link, link_settings, lt_settings);
1278 }
1279
1280 static void override_training_settings(
1281                 struct dc_link *link,
1282                 const struct dc_link_training_overrides *overrides,
1283                 struct link_training_settings *lt_settings)
1284 {
1285         uint32_t lane;
1286
1287         /* Override link settings */
1288         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1289                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1290         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1291                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1292
1293         /* Override link spread */
1294         if (!link->dp_ss_off && overrides->downspread != NULL)
1295                 lt_settings->link_settings.link_spread = *overrides->downspread ?
1296                                 LINK_SPREAD_05_DOWNSPREAD_30KHZ
1297                                 : LINK_SPREAD_DISABLED;
1298
1299         /* Override lane settings */
1300         if (overrides->voltage_swing != NULL)
1301                 lt_settings->voltage_swing = overrides->voltage_swing;
1302         if (overrides->pre_emphasis != NULL)
1303                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1304         if (overrides->post_cursor2 != NULL)
1305                 lt_settings->post_cursor2 = overrides->post_cursor2;
1306         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1307                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1308                         lt_settings->voltage_swing != NULL ?
1309                         *lt_settings->voltage_swing :
1310                         VOLTAGE_SWING_LEVEL0;
1311                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1312                         lt_settings->pre_emphasis != NULL ?
1313                         *lt_settings->pre_emphasis
1314                         : PRE_EMPHASIS_DISABLED;
1315                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1316                         lt_settings->post_cursor2 != NULL ?
1317                         *lt_settings->post_cursor2
1318                         : POST_CURSOR2_DISABLED;
1319         }
1320
1321         /* Initialize training timings */
1322         if (overrides->cr_pattern_time != NULL)
1323                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1324
1325         if (overrides->eq_pattern_time != NULL)
1326                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1327
1328         if (overrides->pattern_for_cr != NULL)
1329                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1330         if (overrides->pattern_for_eq != NULL)
1331                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1332
1333         if (overrides->enhanced_framing != NULL)
1334                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1335
1336         if (link->preferred_training_settings.fec_enable != NULL)
1337                 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1338 }
1339
1340 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1341 {
1342         switch (lttpr_repeater_count) {
1343         case 0x80: // 1 lttpr repeater
1344                 return 1;
1345         case 0x40: // 2 lttpr repeaters
1346                 return 2;
1347         case 0x20: // 3 lttpr repeaters
1348                 return 3;
1349         case 0x10: // 4 lttpr repeaters
1350                 return 4;
1351         case 0x08: // 5 lttpr repeaters
1352                 return 5;
1353         case 0x04: // 6 lttpr repeaters
1354                 return 6;
1355         case 0x02: // 7 lttpr repeaters
1356                 return 7;
1357         case 0x01: // 8 lttpr repeaters
1358                 return 8;
1359         default:
1360                 break;
1361         }
1362         return 0; // invalid value
1363 }
1364
1365 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
1366 {
1367         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1368
1369         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1370         return core_link_write_dpcd(link,
1371                         DP_PHY_REPEATER_MODE,
1372                         (uint8_t *)&repeater_mode,
1373                         sizeof(repeater_mode));
1374 }
1375
1376 enum dc_status configure_lttpr_mode_non_transparent(
1377                 struct dc_link *link,
1378                 const struct link_training_settings *lt_settings)
1379 {
1380         /* aux timeout is already set to extended */
1381         /* RESET/SET lttpr mode to enable non transparent mode */
1382         uint8_t repeater_cnt;
1383         uint32_t aux_interval_address;
1384         uint8_t repeater_id;
1385         enum dc_status result = DC_ERROR_UNEXPECTED;
1386         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1387
1388         enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
1389
1390         if (encoding == DP_8b_10b_ENCODING) {
1391                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1392                 result = core_link_write_dpcd(link,
1393                                 DP_PHY_REPEATER_MODE,
1394                                 (uint8_t *)&repeater_mode,
1395                                 sizeof(repeater_mode));
1396
1397         }
1398
1399         if (result == DC_OK) {
1400                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1401         }
1402
1403         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1404
1405                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1406
1407                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1408                 result = core_link_write_dpcd(link,
1409                                 DP_PHY_REPEATER_MODE,
1410                                 (uint8_t *)&repeater_mode,
1411                                 sizeof(repeater_mode));
1412
1413                 if (result == DC_OK) {
1414                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1415                 }
1416
1417                 if (encoding == DP_8b_10b_ENCODING) {
1418                         repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1419                         for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1420                                 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1421                                                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1422                                 core_link_read_dpcd(
1423                                         link,
1424                                         aux_interval_address,
1425                                         (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1426                                         sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1427                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1428                         }
1429                 }
1430         }
1431
1432         return result;
1433 }
1434
1435 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1436 {
1437         union dpcd_training_pattern dpcd_pattern = { {0} };
1438
1439         const uint32_t dpcd_base_lt_offset =
1440                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1441                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1442         /* Set training not in progress*/
1443         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1444
1445         core_link_write_dpcd(
1446                 link,
1447                 dpcd_base_lt_offset,
1448                 &dpcd_pattern.raw,
1449                 1);
1450
1451         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1452                 __func__,
1453                 offset,
1454                 dpcd_base_lt_offset,
1455                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1456 }
1457
1458 static void print_status_message(
1459         struct dc_link *link,
1460         const struct link_training_settings *lt_settings,
1461         enum link_training_result status)
1462 {
1463         char *link_rate = "Unknown";
1464         char *lt_result = "Unknown";
1465         char *lt_spread = "Disabled";
1466
1467         switch (lt_settings->link_settings.link_rate) {
1468         case LINK_RATE_LOW:
1469                 link_rate = "RBR";
1470                 break;
1471         case LINK_RATE_RATE_2:
1472                 link_rate = "R2";
1473                 break;
1474         case LINK_RATE_RATE_3:
1475                 link_rate = "R3";
1476                 break;
1477         case LINK_RATE_HIGH:
1478                 link_rate = "HBR";
1479                 break;
1480         case LINK_RATE_RBR2:
1481                 link_rate = "RBR2";
1482                 break;
1483         case LINK_RATE_RATE_6:
1484                 link_rate = "R6";
1485                 break;
1486         case LINK_RATE_HIGH2:
1487                 link_rate = "HBR2";
1488                 break;
1489         case LINK_RATE_HIGH3:
1490                 link_rate = "HBR3";
1491                 break;
1492         default:
1493                 break;
1494         }
1495
1496         switch (status) {
1497         case LINK_TRAINING_SUCCESS:
1498                 lt_result = "pass";
1499                 break;
1500         case LINK_TRAINING_CR_FAIL_LANE0:
1501                 lt_result = "CR failed lane0";
1502                 break;
1503         case LINK_TRAINING_CR_FAIL_LANE1:
1504                 lt_result = "CR failed lane1";
1505                 break;
1506         case LINK_TRAINING_CR_FAIL_LANE23:
1507                 lt_result = "CR failed lane23";
1508                 break;
1509         case LINK_TRAINING_EQ_FAIL_CR:
1510                 lt_result = "CR failed in EQ";
1511                 break;
1512         case LINK_TRAINING_EQ_FAIL_EQ:
1513                 lt_result = "EQ failed";
1514                 break;
1515         case LINK_TRAINING_LQA_FAIL:
1516                 lt_result = "LQA failed";
1517                 break;
1518         case LINK_TRAINING_LINK_LOSS:
1519                 lt_result = "Link loss";
1520                 break;
1521         default:
1522                 break;
1523         }
1524
1525         switch (lt_settings->link_settings.link_spread) {
1526         case LINK_SPREAD_DISABLED:
1527                 lt_spread = "Disabled";
1528                 break;
1529         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1530                 lt_spread = "0.5% 30KHz";
1531                 break;
1532         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1533                 lt_spread = "0.5% 33KHz";
1534                 break;
1535         default:
1536                 break;
1537         }
1538
1539         /* Connectivity log: link training */
1540         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1541                                 link_rate,
1542                                 lt_settings->link_settings.lane_count,
1543                                 lt_result,
1544                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1545                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1546                                 lt_spread);
1547 }
1548
1549 void dc_link_dp_set_drive_settings(
1550         struct dc_link *link,
1551         struct link_training_settings *lt_settings)
1552 {
1553         /* program ASIC PHY settings*/
1554         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1555
1556         /* Notify DP sink the PHY settings from source */
1557         dpcd_set_lane_settings(link, lt_settings, DPRX);
1558 }
1559
1560 bool dc_link_dp_perform_link_training_skip_aux(
1561         struct dc_link *link,
1562         const struct dc_link_settings *link_setting)
1563 {
1564         struct link_training_settings lt_settings;
1565
1566         dp_decide_training_settings(
1567                         link,
1568                         link_setting,
1569                         &lt_settings);
1570         override_training_settings(
1571                         link,
1572                         &link->preferred_training_settings,
1573                         &lt_settings);
1574
1575         /* 1. Perform_clock_recovery_sequence. */
1576
1577         /* transmit training pattern for clock recovery */
1578         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1579
1580         /* call HWSS to set lane settings*/
1581         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1582
1583         /* wait receiver to lock-on*/
1584         dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1585
1586         /* 2. Perform_channel_equalization_sequence. */
1587
1588         /* transmit training pattern for channel equalization. */
1589         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1590
1591         /* call HWSS to set lane settings*/
1592         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1593
1594         /* wait receiver to lock-on. */
1595         dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1596
1597         /* 3. Perform_link_training_int. */
1598
1599         /* Mainlink output idle pattern. */
1600         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1601
1602         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1603
1604         return true;
1605 }
1606
1607 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
1608 {
1609         enum dc_status status = DC_OK;
1610
1611         if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1612                 status = configure_lttpr_mode_transparent(link);
1613
1614         else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1615                 status = configure_lttpr_mode_non_transparent(link, lt_settings);
1616
1617         return status;
1618 }
1619
1620 static void dpcd_exit_training_mode(struct dc_link *link)
1621 {
1622
1623         /* clear training pattern set */
1624         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1625 }
1626
1627 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1628                 struct link_training_settings *lt_settings)
1629 {
1630         enum dp_link_encoding encoding =
1631                         dp_get_link_encoding_format(
1632                                         &lt_settings->link_settings);
1633         enum dc_status status;
1634
1635         status = core_link_write_dpcd(
1636                         link,
1637                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1638                         (uint8_t *) &encoding,
1639                         1);
1640         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1641                                         __func__,
1642                                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1643                                         encoding);
1644
1645         return status;
1646 }
1647
1648 static enum link_training_result dp_perform_8b_10b_link_training(
1649                 struct dc_link *link,
1650                 struct link_training_settings *lt_settings)
1651 {
1652         enum link_training_result status = LINK_TRAINING_SUCCESS;
1653
1654         uint8_t repeater_cnt;
1655         uint8_t repeater_id;
1656         uint8_t lane = 0;
1657
1658         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1659                 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
1660
1661         /* 1. set link rate, lane count and spread. */
1662         dpcd_set_link_settings(link, lt_settings);
1663
1664         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1665
1666                 /* 2. perform link training (set link training done
1667                  *  to false is done as well)
1668                  */
1669                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1670
1671                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1672                                 repeater_id--) {
1673                         status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
1674
1675                         if (status != LINK_TRAINING_SUCCESS)
1676                                 break;
1677
1678                         status = perform_channel_equalization_sequence(link,
1679                                         lt_settings,
1680                                         repeater_id);
1681
1682                         if (status != LINK_TRAINING_SUCCESS)
1683                                 break;
1684
1685                         repeater_training_done(link, repeater_id);
1686                 }
1687
1688                 for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
1689                         lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
1690         }
1691
1692         if (status == LINK_TRAINING_SUCCESS) {
1693                 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
1694         if (status == LINK_TRAINING_SUCCESS) {
1695                 status = perform_channel_equalization_sequence(link,
1696                                         lt_settings,
1697                                         DPRX);
1698                 }
1699         }
1700
1701         return status;
1702 }
1703
1704 enum link_training_result dc_link_dp_perform_link_training(
1705         struct dc_link *link,
1706         const struct dc_link_settings *link_settings,
1707         bool skip_video_pattern)
1708 {
1709         enum link_training_result status = LINK_TRAINING_SUCCESS;
1710         struct link_training_settings lt_settings;
1711         enum dp_link_encoding encoding =
1712                         dp_get_link_encoding_format(link_settings);
1713
1714         /* decide training settings */
1715         dp_decide_training_settings(
1716                         link,
1717                         link_settings,
1718                         &lt_settings);
1719         override_training_settings(
1720                         link,
1721                         &link->preferred_training_settings,
1722                         &lt_settings);
1723
1724         /* reset previous training states */
1725         dpcd_exit_training_mode(link);
1726
1727         /* configure link prior to entering training mode */
1728         dpcd_configure_lttpr_mode(link, &lt_settings);
1729         dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
1730         dpcd_configure_channel_coding(link, &lt_settings);
1731
1732         /* enter training mode:
1733          * Per DP specs starting from here, DPTX device shall not issue
1734          * Non-LT AUX transactions inside training mode.
1735          */
1736         if (encoding == DP_8b_10b_ENCODING)
1737                 status = dp_perform_8b_10b_link_training(link, &lt_settings);
1738         else
1739                 ASSERT(0);
1740
1741         /* exit training mode and switch to video idle */
1742         dpcd_exit_training_mode(link);
1743         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1744                 status = dp_transition_to_video_idle(link,
1745                                 &lt_settings,
1746                                 status);
1747
1748         /* dump debug data */
1749         print_status_message(link, &lt_settings, status);
1750         if (status != LINK_TRAINING_SUCCESS)
1751                 link->ctx->dc->debug_data.ltFailCount++;
1752         return status;
1753 }
1754
1755 bool perform_link_training_with_retries(
1756         const struct dc_link_settings *link_setting,
1757         bool skip_video_pattern,
1758         int attempts,
1759         struct pipe_ctx *pipe_ctx,
1760         enum signal_type signal,
1761         bool do_fallback)
1762 {
1763         int j;
1764         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1765         struct dc_stream_state *stream = pipe_ctx->stream;
1766         struct dc_link *link = stream->link;
1767         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1768         struct link_encoder *link_enc;
1769         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1770         struct dc_link_settings current_setting = *link_setting;
1771
1772         /* Dynamically assigned link encoders associated with stream rather than
1773          * link.
1774          */
1775         if (link->dc->res_pool->funcs->link_encs_assign)
1776                 link_enc = stream->link_enc;
1777         else
1778                 link_enc = link->link_enc;
1779
1780         /* We need to do this before the link training to ensure the idle pattern in SST
1781          * mode will be sent right after the link training
1782          */
1783         link_enc->funcs->connect_dig_be_to_fe(link_enc,
1784                                                         pipe_ctx->stream_res.stream_enc->id, true);
1785
1786         for (j = 0; j < attempts; ++j) {
1787
1788                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1789                         __func__, (unsigned int)j + 1, attempts);
1790
1791                 dp_enable_link_phy(
1792                         link,
1793                         signal,
1794                         pipe_ctx->clock_source->id,
1795                         &current_setting);
1796
1797                 if (stream->sink_patches.dppowerup_delay > 0) {
1798                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1799
1800                         msleep(delay_dp_power_up_in_ms);
1801                 }
1802
1803 #ifdef CONFIG_DRM_AMD_DC_HDCP
1804                 if (panel_mode == DP_PANEL_MODE_EDP) {
1805                         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1806
1807                         if (cp_psp && cp_psp->funcs.enable_assr) {
1808                                 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1809                                         /* since eDP implies ASSR on, change panel
1810                                          * mode to disable ASSR
1811                                          */
1812                                         panel_mode = DP_PANEL_MODE_DEFAULT;
1813                                 }
1814                         }
1815                 }
1816 #endif
1817
1818                 dp_set_panel_mode(link, panel_mode);
1819
1820                 if (link->aux_access_disabled) {
1821                         dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
1822                         return true;
1823                 } else {
1824                                 status = dc_link_dp_perform_link_training(
1825                                                                                 link,
1826                                                                                 &current_setting,
1827                                                                                 skip_video_pattern);
1828                         if (status == LINK_TRAINING_SUCCESS)
1829                                 return true;
1830                 }
1831
1832                 /* latest link training still fail, skip delay and keep PHY on
1833                  */
1834                 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1835                         break;
1836
1837                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1838                         __func__, (unsigned int)j + 1, attempts);
1839
1840                 dp_disable_link_phy(link, signal);
1841
1842                 /* Abort link training if failure due to sink being unplugged. */
1843                 if (status == LINK_TRAINING_ABORT)
1844                         break;
1845                 else if (do_fallback) {
1846                         decide_fallback_link_setting(*link_setting, &current_setting, status);
1847                         /* Fail link training if reduced link bandwidth no longer meets
1848                          * stream requirements.
1849                          */
1850                         if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1851                                         dc_link_bandwidth_kbps(link, &current_setting))
1852                                 break;
1853                 }
1854
1855                 msleep(delay_between_attempts);
1856
1857                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1858         }
1859
1860         return false;
1861 }
1862
1863 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1864 {
1865         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1866         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1867
1868         if (dp_cs != NULL) {
1869                 dp_cs_id = dp_cs->id;
1870         } else {
1871                 /*
1872                  * dp clock source is not initialized for some reason.
1873                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1874                  */
1875                 ASSERT(dp_cs);
1876         }
1877
1878         return dp_cs_id;
1879 }
1880
1881 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1882 {
1883         if (mst_enable == false &&
1884                 link->type == dc_connection_mst_branch) {
1885                 /* Disable MST on link. Use only local sink. */
1886                 dp_disable_link_phy_mst(link, link->connector_signal);
1887
1888                 link->type = dc_connection_single;
1889                 link->local_sink = link->remote_sinks[0];
1890                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1891                 dc_sink_retain(link->local_sink);
1892                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1893         } else if (mst_enable == true &&
1894                         link->type == dc_connection_single &&
1895                         link->remote_sinks[0] != NULL) {
1896                 /* Re-enable MST on link. */
1897                 dp_disable_link_phy(link, link->connector_signal);
1898                 dp_enable_mst_on_sink(link, true);
1899
1900                 link->type = dc_connection_mst_branch;
1901                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1902         }
1903 }
1904
1905 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1906 {
1907         /* Begin Sync LT. During this time,
1908          * DPCD:600h must not be powered down.
1909          */
1910         link->sync_lt_in_progress = true;
1911
1912         /*Clear any existing preferred settings.*/
1913         memset(&link->preferred_training_settings, 0,
1914                 sizeof(struct dc_link_training_overrides));
1915         memset(&link->preferred_link_setting, 0,
1916                 sizeof(struct dc_link_settings));
1917
1918         return true;
1919 }
1920
1921 enum link_training_result dc_link_dp_sync_lt_attempt(
1922     struct dc_link *link,
1923     struct dc_link_settings *link_settings,
1924     struct dc_link_training_overrides *lt_overrides)
1925 {
1926         struct link_training_settings lt_settings;
1927         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1928         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1929         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1930         bool fec_enable = false;
1931
1932         dp_decide_training_settings(
1933                         link,
1934                         link_settings,
1935                         &lt_settings);
1936         override_training_settings(
1937                         link,
1938                         lt_overrides,
1939                         &lt_settings);
1940         /* Setup MST Mode */
1941         if (lt_overrides->mst_enable)
1942                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1943
1944         /* Disable link */
1945         dp_disable_link_phy(link, link->connector_signal);
1946
1947         /* Enable link */
1948         dp_cs_id = get_clock_source_id(link);
1949         dp_enable_link_phy(link, link->connector_signal,
1950                 dp_cs_id, link_settings);
1951
1952         /* Set FEC enable */
1953         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1954         dp_set_fec_ready(link, fec_enable);
1955
1956         if (lt_overrides->alternate_scrambler_reset) {
1957                 if (*lt_overrides->alternate_scrambler_reset)
1958                         panel_mode = DP_PANEL_MODE_EDP;
1959                 else
1960                         panel_mode = DP_PANEL_MODE_DEFAULT;
1961         } else
1962                 panel_mode = dp_get_panel_mode(link);
1963
1964         dp_set_panel_mode(link, panel_mode);
1965
1966         /* Attempt to train with given link training settings */
1967         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1968                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1969
1970         /* Set link rate, lane count and spread. */
1971         dpcd_set_link_settings(link, &lt_settings);
1972
1973         /* 2. perform link training (set link training done
1974          *  to false is done as well)
1975          */
1976         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1977         if (lt_status == LINK_TRAINING_SUCCESS) {
1978                 lt_status = perform_channel_equalization_sequence(link,
1979                                                 &lt_settings,
1980                                                 DPRX);
1981         }
1982
1983         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1984         /* 4. print status message*/
1985         print_status_message(link, &lt_settings, lt_status);
1986
1987         return lt_status;
1988 }
1989
1990 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1991 {
1992         /* If input parameter is set, shut down phy.
1993          * Still shouldn't turn off dp_receiver (DPCD:600h)
1994          */
1995         if (link_down == true) {
1996                 dp_disable_link_phy(link, link->connector_signal);
1997                 dp_set_fec_ready(link, false);
1998         }
1999
2000         link->sync_lt_in_progress = false;
2001         return true;
2002 }
2003
2004 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2005 {
2006         if (!max_link_enc_cap) {
2007                 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2008                 return false;
2009         }
2010
2011         if (link->link_enc->funcs->get_max_link_cap) {
2012                 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
2013                 return true;
2014         }
2015
2016         DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2017         max_link_enc_cap->lane_count = 1;
2018         max_link_enc_cap->link_rate = 6;
2019         return false;
2020 }
2021
2022 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
2023 {
2024         struct dc_link_settings max_link_cap = {0};
2025
2026         /* get max link encoder capability */
2027         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
2028
2029         /* Lower link settings based on sink's link cap */
2030         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2031                 max_link_cap.lane_count =
2032                                 link->reported_link_cap.lane_count;
2033         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2034                 max_link_cap.link_rate =
2035                                 link->reported_link_cap.link_rate;
2036         if (link->reported_link_cap.link_spread <
2037                         max_link_cap.link_spread)
2038                 max_link_cap.link_spread =
2039                                 link->reported_link_cap.link_spread;
2040         /*
2041          * account for lttpr repeaters cap
2042          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2043          */
2044         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2045                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2046                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2047
2048                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2049                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2050
2051                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2052                                                 __func__,
2053                                                 max_link_cap.lane_count,
2054                                                 max_link_cap.link_rate);
2055         }
2056         return max_link_cap;
2057 }
2058
2059 enum dc_status read_hpd_rx_irq_data(
2060         struct dc_link *link,
2061         union hpd_irq_data *irq_data)
2062 {
2063         static enum dc_status retval;
2064
2065         /* The HW reads 16 bytes from 200h on HPD,
2066          * but if we get an AUX_DEFER, the HW cannot retry
2067          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2068          * fail, so we now explicitly read 6 bytes which is
2069          * the req from the above mentioned test cases.
2070          *
2071          * For DP 1.4 we need to read those from 2002h range.
2072          */
2073         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2074                 retval = core_link_read_dpcd(
2075                         link,
2076                         DP_SINK_COUNT,
2077                         irq_data->raw,
2078                         sizeof(union hpd_irq_data));
2079         else {
2080                 /* Read 14 bytes in a single read and then copy only the required fields.
2081                  * This is more efficient than doing it in two separate AUX reads. */
2082
2083                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2084
2085                 retval = core_link_read_dpcd(
2086                         link,
2087                         DP_SINK_COUNT_ESI,
2088                         tmp,
2089                         sizeof(tmp));
2090
2091                 if (retval != DC_OK)
2092                         return retval;
2093
2094                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2095                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2096                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2097                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2098                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2099                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2100         }
2101
2102         return retval;
2103 }
2104
2105 bool hpd_rx_irq_check_link_loss_status(
2106         struct dc_link *link,
2107         union hpd_irq_data *hpd_irq_dpcd_data)
2108 {
2109         uint8_t irq_reg_rx_power_state = 0;
2110         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2111         union lane_status lane_status;
2112         uint32_t lane;
2113         bool sink_status_changed;
2114         bool return_code;
2115
2116         sink_status_changed = false;
2117         return_code = false;
2118
2119         if (link->cur_link_settings.lane_count == 0)
2120                 return return_code;
2121
2122         /*1. Check that Link Status changed, before re-training.*/
2123
2124         /*parse lane status*/
2125         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2126                 /* check status of lanes 0,1
2127                  * changed DpcdAddress_Lane01Status (0x202)
2128                  */
2129                 lane_status.raw = get_nibble_at_index(
2130                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2131                         lane);
2132
2133                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2134                         !lane_status.bits.CR_DONE_0 ||
2135                         !lane_status.bits.SYMBOL_LOCKED_0) {
2136                         /* if one of the channel equalization, clock
2137                          * recovery or symbol lock is dropped
2138                          * consider it as (link has been
2139                          * dropped) dp sink status has changed
2140                          */
2141                         sink_status_changed = true;
2142                         break;
2143                 }
2144         }
2145
2146         /* Check interlane align.*/
2147         if (sink_status_changed ||
2148                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2149
2150                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2151
2152                 return_code = true;
2153
2154                 /*2. Check that we can handle interrupt: Not in FS DOS,
2155                  *  Not in "Display Timeout" state, Link is trained.
2156                  */
2157                 dpcd_result = core_link_read_dpcd(link,
2158                         DP_SET_POWER,
2159                         &irq_reg_rx_power_state,
2160                         sizeof(irq_reg_rx_power_state));
2161
2162                 if (dpcd_result != DC_OK) {
2163                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2164                                 __func__);
2165                 } else {
2166                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2167                                 return_code = false;
2168                 }
2169         }
2170
2171         return return_code;
2172 }
2173
2174 bool dp_verify_link_cap(
2175         struct dc_link *link,
2176         struct dc_link_settings *known_limit_link_setting,
2177         int *fail_count)
2178 {
2179         struct dc_link_settings max_link_cap = {0};
2180         struct dc_link_settings cur_link_setting = {0};
2181         struct dc_link_settings *cur = &cur_link_setting;
2182         struct dc_link_settings initial_link_settings = {0};
2183         bool success;
2184         bool skip_link_training;
2185         bool skip_video_pattern;
2186         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2187         enum link_training_result status;
2188         union hpd_irq_data irq_data;
2189
2190         if (link->dc->debug.skip_detection_link_training) {
2191                 link->verified_link_cap = *known_limit_link_setting;
2192                 return true;
2193         }
2194
2195         memset(&irq_data, 0, sizeof(irq_data));
2196         success = false;
2197         skip_link_training = false;
2198
2199         max_link_cap = get_max_link_cap(link);
2200
2201         /* Grant extended timeout request */
2202         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2203                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2204
2205                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2206         }
2207
2208         /* TODO implement override and monitor patch later */
2209
2210         /* try to train the link from high to low to
2211          * find the physical link capability
2212          */
2213         /* disable PHY done possible by BIOS, will be done by driver itself */
2214         dp_disable_link_phy(link, link->connector_signal);
2215
2216         dp_cs_id = get_clock_source_id(link);
2217
2218         /* link training starts with the maximum common settings
2219          * supported by both sink and ASIC.
2220          */
2221         initial_link_settings = get_common_supported_link_settings(
2222                         *known_limit_link_setting,
2223                         max_link_cap);
2224         cur_link_setting = initial_link_settings;
2225
2226         /* Temporary Renoir-specific workaround for SWDEV-215184;
2227          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2228          * so add extra cycle of enabling and disabling the PHY before first link training.
2229          */
2230         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2231                         link->dc->debug.usbc_combo_phy_reset_wa) {
2232                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2233                 dp_disable_link_phy(link, link->connector_signal);
2234         }
2235
2236         do {
2237                 skip_video_pattern = true;
2238
2239                 if (cur->link_rate == LINK_RATE_LOW)
2240                         skip_video_pattern = false;
2241
2242                 dp_enable_link_phy(
2243                                 link,
2244                                 link->connector_signal,
2245                                 dp_cs_id,
2246                                 cur);
2247
2248
2249                 if (skip_link_training)
2250                         success = true;
2251                 else {
2252                         status = dc_link_dp_perform_link_training(
2253                                                         link,
2254                                                         cur,
2255                                                         skip_video_pattern);
2256                         if (status == LINK_TRAINING_SUCCESS)
2257                                 success = true;
2258                         else
2259                                 (*fail_count)++;
2260                 }
2261
2262                 if (success) {
2263                         link->verified_link_cap = *cur;
2264                         udelay(1000);
2265                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2266                                 if (hpd_rx_irq_check_link_loss_status(
2267                                                 link,
2268                                                 &irq_data))
2269                                         (*fail_count)++;
2270                 }
2271                 /* always disable the link before trying another
2272                  * setting or before returning we'll enable it later
2273                  * based on the actual mode we're driving
2274                  */
2275                 dp_disable_link_phy(link, link->connector_signal);
2276         } while (!success && decide_fallback_link_setting(
2277                         initial_link_settings, cur, status));
2278
2279         /* Link Training failed for all Link Settings
2280          *  (Lane Count is still unknown)
2281          */
2282         if (!success) {
2283                 /* If all LT fails for all settings,
2284                  * set verified = failed safe (1 lane low)
2285                  */
2286                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2287                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2288
2289                 link->verified_link_cap.link_spread =
2290                 LINK_SPREAD_DISABLED;
2291         }
2292
2293
2294         return success;
2295 }
2296
2297 bool dp_verify_link_cap_with_retries(
2298         struct dc_link *link,
2299         struct dc_link_settings *known_limit_link_setting,
2300         int attempts)
2301 {
2302         int i = 0;
2303         bool success = false;
2304
2305         for (i = 0; i < attempts; i++) {
2306                 int fail_count = 0;
2307                 enum dc_connection_type type = dc_connection_none;
2308
2309                 memset(&link->verified_link_cap, 0,
2310                                 sizeof(struct dc_link_settings));
2311                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2312                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2313                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2314                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2315                         break;
2316                 } else if (dp_verify_link_cap(link,
2317                                 &link->reported_link_cap,
2318                                 &fail_count) && fail_count == 0) {
2319                         success = true;
2320                         break;
2321                 }
2322                 msleep(10);
2323         }
2324         return success;
2325 }
2326
2327 bool dp_verify_mst_link_cap(
2328         struct dc_link *link)
2329 {
2330         struct dc_link_settings max_link_cap = {0};
2331
2332         max_link_cap = get_max_link_cap(link);
2333         link->verified_link_cap = get_common_supported_link_settings(
2334                 link->reported_link_cap,
2335                 max_link_cap);
2336
2337         return true;
2338 }
2339
2340 static struct dc_link_settings get_common_supported_link_settings(
2341                 struct dc_link_settings link_setting_a,
2342                 struct dc_link_settings link_setting_b)
2343 {
2344         struct dc_link_settings link_settings = {0};
2345
2346         link_settings.lane_count =
2347                 (link_setting_a.lane_count <=
2348                         link_setting_b.lane_count) ?
2349                         link_setting_a.lane_count :
2350                         link_setting_b.lane_count;
2351         link_settings.link_rate =
2352                 (link_setting_a.link_rate <=
2353                         link_setting_b.link_rate) ?
2354                         link_setting_a.link_rate :
2355                         link_setting_b.link_rate;
2356         link_settings.link_spread = LINK_SPREAD_DISABLED;
2357
2358         /* in DP compliance test, DPR-120 may have
2359          * a random value in its MAX_LINK_BW dpcd field.
2360          * We map it to the maximum supported link rate that
2361          * is smaller than MAX_LINK_BW in this case.
2362          */
2363         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2364                 link_settings.link_rate = LINK_RATE_HIGH3;
2365         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2366                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2367                 link_settings.link_rate = LINK_RATE_HIGH2;
2368         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2369                         && link_settings.link_rate > LINK_RATE_HIGH) {
2370                 link_settings.link_rate = LINK_RATE_HIGH;
2371         } else if (link_settings.link_rate < LINK_RATE_HIGH
2372                         && link_settings.link_rate > LINK_RATE_LOW) {
2373                 link_settings.link_rate = LINK_RATE_LOW;
2374         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2375                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2376         }
2377
2378         return link_settings;
2379 }
2380
2381 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2382 {
2383         return lane_count <= LANE_COUNT_ONE;
2384 }
2385
2386 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2387 {
2388         return link_rate <= LINK_RATE_LOW;
2389 }
2390
2391 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2392 {
2393         switch (lane_count) {
2394         case LANE_COUNT_FOUR:
2395                 return LANE_COUNT_TWO;
2396         case LANE_COUNT_TWO:
2397                 return LANE_COUNT_ONE;
2398         case LANE_COUNT_ONE:
2399                 return LANE_COUNT_UNKNOWN;
2400         default:
2401                 return LANE_COUNT_UNKNOWN;
2402         }
2403 }
2404
2405 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2406 {
2407         switch (link_rate) {
2408         case LINK_RATE_HIGH3:
2409                 return LINK_RATE_HIGH2;
2410         case LINK_RATE_HIGH2:
2411                 return LINK_RATE_HIGH;
2412         case LINK_RATE_HIGH:
2413                 return LINK_RATE_LOW;
2414         case LINK_RATE_LOW:
2415                 return LINK_RATE_UNKNOWN;
2416         default:
2417                 return LINK_RATE_UNKNOWN;
2418         }
2419 }
2420
2421 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2422 {
2423         switch (lane_count) {
2424         case LANE_COUNT_ONE:
2425                 return LANE_COUNT_TWO;
2426         case LANE_COUNT_TWO:
2427                 return LANE_COUNT_FOUR;
2428         default:
2429                 return LANE_COUNT_UNKNOWN;
2430         }
2431 }
2432
2433 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2434 {
2435         switch (link_rate) {
2436         case LINK_RATE_LOW:
2437                 return LINK_RATE_HIGH;
2438         case LINK_RATE_HIGH:
2439                 return LINK_RATE_HIGH2;
2440         case LINK_RATE_HIGH2:
2441                 return LINK_RATE_HIGH3;
2442         default:
2443                 return LINK_RATE_UNKNOWN;
2444         }
2445 }
2446
2447 /*
2448  * function: set link rate and lane count fallback based
2449  * on current link setting and last link training result
2450  * return value:
2451  *                      true - link setting could be set
2452  *                      false - has reached minimum setting
2453  *                                      and no further fallback could be done
2454  */
2455 static bool decide_fallback_link_setting(
2456                 struct dc_link_settings initial_link_settings,
2457                 struct dc_link_settings *current_link_setting,
2458                 enum link_training_result training_result)
2459 {
2460         if (!current_link_setting)
2461                 return false;
2462
2463         switch (training_result) {
2464         case LINK_TRAINING_CR_FAIL_LANE0:
2465         case LINK_TRAINING_CR_FAIL_LANE1:
2466         case LINK_TRAINING_CR_FAIL_LANE23:
2467         case LINK_TRAINING_LQA_FAIL:
2468         {
2469                 if (!reached_minimum_link_rate
2470                                 (current_link_setting->link_rate)) {
2471                         current_link_setting->link_rate =
2472                                 reduce_link_rate(
2473                                         current_link_setting->link_rate);
2474                 } else if (!reached_minimum_lane_count
2475                                 (current_link_setting->lane_count)) {
2476                         current_link_setting->link_rate =
2477                                 initial_link_settings.link_rate;
2478                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2479                                 return false;
2480                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2481                                 current_link_setting->lane_count =
2482                                                 LANE_COUNT_ONE;
2483                         else if (training_result ==
2484                                         LINK_TRAINING_CR_FAIL_LANE23)
2485                                 current_link_setting->lane_count =
2486                                                 LANE_COUNT_TWO;
2487                         else
2488                                 current_link_setting->lane_count =
2489                                         reduce_lane_count(
2490                                         current_link_setting->lane_count);
2491                 } else {
2492                         return false;
2493                 }
2494                 break;
2495         }
2496         case LINK_TRAINING_EQ_FAIL_EQ:
2497         {
2498                 if (!reached_minimum_lane_count
2499                                 (current_link_setting->lane_count)) {
2500                         current_link_setting->lane_count =
2501                                 reduce_lane_count(
2502                                         current_link_setting->lane_count);
2503                 } else if (!reached_minimum_link_rate
2504                                 (current_link_setting->link_rate)) {
2505                         current_link_setting->link_rate =
2506                                 reduce_link_rate(
2507                                         current_link_setting->link_rate);
2508                 } else {
2509                         return false;
2510                 }
2511                 break;
2512         }
2513         case LINK_TRAINING_EQ_FAIL_CR:
2514         {
2515                 if (!reached_minimum_link_rate
2516                                 (current_link_setting->link_rate)) {
2517                         current_link_setting->link_rate =
2518                                 reduce_link_rate(
2519                                         current_link_setting->link_rate);
2520                 } else {
2521                         return false;
2522                 }
2523                 break;
2524         }
2525         default:
2526                 return false;
2527         }
2528         return true;
2529 }
2530
2531 bool dp_validate_mode_timing(
2532         struct dc_link *link,
2533         const struct dc_crtc_timing *timing)
2534 {
2535         uint32_t req_bw;
2536         uint32_t max_bw;
2537
2538         const struct dc_link_settings *link_setting;
2539
2540         /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2541         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2542                         !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2543                         dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2544                 return false;
2545
2546         /*always DP fail safe mode*/
2547         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2548                 timing->h_addressable == (uint32_t) 640 &&
2549                 timing->v_addressable == (uint32_t) 480)
2550                 return true;
2551
2552         link_setting = dc_link_get_link_cap(link);
2553
2554         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2555         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2556                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2557                 link_setting = &link->verified_link_cap;
2558         */
2559
2560         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2561         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2562
2563         if (req_bw <= max_bw) {
2564                 /* remember the biggest mode here, during
2565                  * initial link training (to get
2566                  * verified_link_cap), LS sends event about
2567                  * cannot train at reported cap to upper
2568                  * layer and upper layer will re-enumerate modes.
2569                  * this is not necessary if the lower
2570                  * verified_link_cap is enough to drive
2571                  * all the modes */
2572
2573                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2574                 /* if (flags.DYNAMIC_VALIDATION == 1)
2575                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2576                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2577                 return true;
2578         } else
2579                 return false;
2580 }
2581
2582 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2583 {
2584         struct dc_link_settings initial_link_setting = {
2585                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2586         struct dc_link_settings current_link_setting =
2587                         initial_link_setting;
2588         uint32_t link_bw;
2589
2590         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2591                 return false;
2592
2593         /* search for the minimum link setting that:
2594          * 1. is supported according to the link training result
2595          * 2. could support the b/w requested by the timing
2596          */
2597         while (current_link_setting.link_rate <=
2598                         link->verified_link_cap.link_rate) {
2599                 link_bw = dc_link_bandwidth_kbps(
2600                                 link,
2601                                 &current_link_setting);
2602                 if (req_bw <= link_bw) {
2603                         *link_setting = current_link_setting;
2604                         return true;
2605                 }
2606
2607                 if (current_link_setting.lane_count <
2608                                 link->verified_link_cap.lane_count) {
2609                         current_link_setting.lane_count =
2610                                         increase_lane_count(
2611                                                         current_link_setting.lane_count);
2612                 } else {
2613                         current_link_setting.link_rate =
2614                                         increase_link_rate(
2615                                                         current_link_setting.link_rate);
2616                         current_link_setting.lane_count =
2617                                         initial_link_setting.lane_count;
2618                 }
2619         }
2620
2621         return false;
2622 }
2623
2624 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2625 {
2626         struct dc_link_settings initial_link_setting;
2627         struct dc_link_settings current_link_setting;
2628         uint32_t link_bw;
2629
2630         /*
2631          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2632          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2633          */
2634         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
2635                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2636                 *link_setting = link->verified_link_cap;
2637                 return true;
2638         }
2639
2640         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2641         initial_link_setting.lane_count = LANE_COUNT_ONE;
2642         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2643         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2644         initial_link_setting.use_link_rate_set = true;
2645         initial_link_setting.link_rate_set = 0;
2646         current_link_setting = initial_link_setting;
2647
2648         /* search for the minimum link setting that:
2649          * 1. is supported according to the link training result
2650          * 2. could support the b/w requested by the timing
2651          */
2652         while (current_link_setting.link_rate <=
2653                         link->verified_link_cap.link_rate) {
2654                 link_bw = dc_link_bandwidth_kbps(
2655                                 link,
2656                                 &current_link_setting);
2657                 if (req_bw <= link_bw) {
2658                         *link_setting = current_link_setting;
2659                         return true;
2660                 }
2661
2662                 if (current_link_setting.lane_count <
2663                                 link->verified_link_cap.lane_count) {
2664                         current_link_setting.lane_count =
2665                                         increase_lane_count(
2666                                                         current_link_setting.lane_count);
2667                 } else {
2668                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2669                                 current_link_setting.link_rate_set++;
2670                                 current_link_setting.link_rate =
2671                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2672                                 current_link_setting.lane_count =
2673                                                                         initial_link_setting.lane_count;
2674                         } else
2675                                 break;
2676                 }
2677         }
2678         return false;
2679 }
2680
2681 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2682 {
2683         *link_setting = link->verified_link_cap;
2684         return true;
2685 }
2686
2687 void decide_link_settings(struct dc_stream_state *stream,
2688         struct dc_link_settings *link_setting)
2689 {
2690         struct dc_link *link;
2691         uint32_t req_bw;
2692
2693         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2694
2695         link = stream->link;
2696
2697         /* if preferred is specified through AMDDP, use it, if it's enough
2698          * to drive the mode
2699          */
2700         if (link->preferred_link_setting.lane_count !=
2701                         LANE_COUNT_UNKNOWN &&
2702                         link->preferred_link_setting.link_rate !=
2703                                         LINK_RATE_UNKNOWN) {
2704                 *link_setting =  link->preferred_link_setting;
2705                 return;
2706         }
2707
2708         /* MST doesn't perform link training for now
2709          * TODO: add MST specific link training routine
2710          */
2711         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2712                 if (decide_mst_link_settings(link, link_setting))
2713                         return;
2714         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2715                 if (decide_edp_link_settings(link, link_setting, req_bw))
2716                         return;
2717         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2718                 return;
2719
2720         BREAK_TO_DEBUGGER();
2721         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2722
2723         *link_setting = link->verified_link_cap;
2724 }
2725
2726 /*************************Short Pulse IRQ***************************/
2727 static bool allow_hpd_rx_irq(const struct dc_link *link)
2728 {
2729         /*
2730          * Don't handle RX IRQ unless one of following is met:
2731          * 1) The link is established (cur_link_settings != unknown)
2732          * 2) We know we're dealing with a branch device, SST or MST
2733          */
2734
2735         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2736                 is_dp_branch_device(link))
2737                 return true;
2738
2739         return false;
2740 }
2741
2742 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2743 {
2744         union dpcd_psr_configuration psr_configuration;
2745
2746         if (!link->psr_settings.psr_feature_enabled)
2747                 return false;
2748
2749         dm_helpers_dp_read_dpcd(
2750                 link->ctx,
2751                 link,
2752                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2753                 &psr_configuration.raw,
2754                 sizeof(psr_configuration.raw));
2755
2756
2757         if (psr_configuration.bits.ENABLE) {
2758                 unsigned char dpcdbuf[3] = {0};
2759                 union psr_error_status psr_error_status;
2760                 union psr_sink_psr_status psr_sink_psr_status;
2761
2762                 dm_helpers_dp_read_dpcd(
2763                         link->ctx,
2764                         link,
2765                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2766                         (unsigned char *) dpcdbuf,
2767                         sizeof(dpcdbuf));
2768
2769                 /*DPCD 2006h   ERROR STATUS*/
2770                 psr_error_status.raw = dpcdbuf[0];
2771                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2772                 psr_sink_psr_status.raw = dpcdbuf[2];
2773
2774                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2775                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2776                                 psr_error_status.bits.VSC_SDP_ERROR) {
2777                         /* Acknowledge and clear error bits */
2778                         dm_helpers_dp_write_dpcd(
2779                                 link->ctx,
2780                                 link,
2781                                 8198,/*DpcdAddress_PSR_Error_Status*/
2782                                 &psr_error_status.raw,
2783                                 sizeof(psr_error_status.raw));
2784
2785                         /* PSR error, disable and re-enable PSR */
2786                         dc_link_set_psr_allow_active(link, false, true, false);
2787                         dc_link_set_psr_allow_active(link, true, true, false);
2788
2789                         return true;
2790                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2791                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2792                         /* No error is detect, PSR is active.
2793                          * We should return with IRQ_HPD handled without
2794                          * checking for loss of sync since PSR would have
2795                          * powered down main link.
2796                          */
2797                         return true;
2798                 }
2799         }
2800         return false;
2801 }
2802
2803 static void dp_test_send_link_training(struct dc_link *link)
2804 {
2805         struct dc_link_settings link_settings = {0};
2806
2807         core_link_read_dpcd(
2808                         link,
2809                         DP_TEST_LANE_COUNT,
2810                         (unsigned char *)(&link_settings.lane_count),
2811                         1);
2812         core_link_read_dpcd(
2813                         link,
2814                         DP_TEST_LINK_RATE,
2815                         (unsigned char *)(&link_settings.link_rate),
2816                         1);
2817
2818         /* Set preferred link settings */
2819         link->verified_link_cap.lane_count = link_settings.lane_count;
2820         link->verified_link_cap.link_rate = link_settings.link_rate;
2821
2822         dp_retrain_link_dp_test(link, &link_settings, false);
2823 }
2824
2825 /* TODO Raven hbr2 compliance eye output is unstable
2826  * (toggling on and off) with debugger break
2827  * This caueses intermittent PHY automation failure
2828  * Need to look into the root cause */
2829 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2830 {
2831         union phy_test_pattern dpcd_test_pattern;
2832         union lane_adjust dpcd_lane_adjustment[2];
2833         unsigned char dpcd_post_cursor_2_adjustment = 0;
2834         unsigned char test_pattern_buffer[
2835                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2836                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2837         unsigned int test_pattern_size = 0;
2838         enum dp_test_pattern test_pattern;
2839         struct dc_link_training_settings link_settings;
2840         union lane_adjust dpcd_lane_adjust;
2841         unsigned int lane;
2842         struct link_training_settings link_training_settings;
2843         int i = 0;
2844
2845         dpcd_test_pattern.raw = 0;
2846         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2847         memset(&link_settings, 0, sizeof(link_settings));
2848
2849         /* get phy test pattern and pattern parameters from DP receiver */
2850         core_link_read_dpcd(
2851                         link,
2852                         DP_PHY_TEST_PATTERN,
2853                         &dpcd_test_pattern.raw,
2854                         sizeof(dpcd_test_pattern));
2855         core_link_read_dpcd(
2856                         link,
2857                         DP_ADJUST_REQUEST_LANE0_1,
2858                         &dpcd_lane_adjustment[0].raw,
2859                         sizeof(dpcd_lane_adjustment));
2860
2861         /*get post cursor 2 parameters
2862          * For DP 1.1a or eariler, this DPCD register's value is 0
2863          * For DP 1.2 or later:
2864          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2865          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2866          */
2867         core_link_read_dpcd(
2868                         link,
2869                         DP_ADJUST_REQUEST_POST_CURSOR2,
2870                         &dpcd_post_cursor_2_adjustment,
2871                         sizeof(dpcd_post_cursor_2_adjustment));
2872
2873         /* translate request */
2874         switch (dpcd_test_pattern.bits.PATTERN) {
2875         case PHY_TEST_PATTERN_D10_2:
2876                 test_pattern = DP_TEST_PATTERN_D102;
2877                 break;
2878         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2879                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2880                 break;
2881         case PHY_TEST_PATTERN_PRBS7:
2882                 test_pattern = DP_TEST_PATTERN_PRBS7;
2883                 break;
2884         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2885                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2886                 break;
2887         case PHY_TEST_PATTERN_CP2520_1:
2888                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2889                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2890                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2891                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2892                 break;
2893         case PHY_TEST_PATTERN_CP2520_2:
2894                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2895                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2896                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2897                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2898                 break;
2899         case PHY_TEST_PATTERN_CP2520_3:
2900                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2901                 break;
2902         default:
2903                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2904         break;
2905         }
2906
2907         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2908                 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2909                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
2910                 core_link_read_dpcd(
2911                                 link,
2912                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2913                                 test_pattern_buffer,
2914                                 test_pattern_size);
2915         }
2916
2917         /* prepare link training settings */
2918         link_settings.link = link->cur_link_settings;
2919
2920         for (lane = 0; lane <
2921                 (unsigned int)(link->cur_link_settings.lane_count);
2922                 lane++) {
2923                 dpcd_lane_adjust.raw =
2924                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2925                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2926                         (enum dc_voltage_swing)
2927                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2928                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2929                         (enum dc_pre_emphasis)
2930                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2931                 link_settings.lane_settings[lane].POST_CURSOR2 =
2932                         (enum dc_post_cursor2)
2933                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2934         }
2935
2936         for (i = 0; i < 4; i++)
2937                 link_training_settings.lane_settings[i] =
2938                                 link_settings.lane_settings[i];
2939         link_training_settings.link_settings = link_settings.link;
2940         link_training_settings.allow_invalid_msa_timing_param = false;
2941         /*Usage: Measure DP physical lane signal
2942          * by DP SI test equipment automatically.
2943          * PHY test pattern request is generated by equipment via HPD interrupt.
2944          * HPD needs to be active all the time. HPD should be active
2945          * all the time. Do not touch it.
2946          * forward request to DS
2947          */
2948         dc_link_dp_set_test_pattern(
2949                 link,
2950                 test_pattern,
2951                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2952                 &link_training_settings,
2953                 test_pattern_buffer,
2954                 test_pattern_size);
2955 }
2956
2957 static void dp_test_send_link_test_pattern(struct dc_link *link)
2958 {
2959         union link_test_pattern dpcd_test_pattern;
2960         union test_misc dpcd_test_params;
2961         enum dp_test_pattern test_pattern;
2962         enum dp_test_pattern_color_space test_pattern_color_space =
2963                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2964         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2965         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2966         struct pipe_ctx *pipe_ctx = NULL;
2967         int i;
2968
2969         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2970         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2971
2972         for (i = 0; i < MAX_PIPES; i++) {
2973                 if (pipes[i].stream == NULL)
2974                         continue;
2975
2976                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
2977                         pipe_ctx = &pipes[i];
2978                         break;
2979                 }
2980         }
2981
2982         if (pipe_ctx == NULL)
2983                 return;
2984
2985         /* get link test pattern and pattern parameters */
2986         core_link_read_dpcd(
2987                         link,
2988                         DP_TEST_PATTERN,
2989                         &dpcd_test_pattern.raw,
2990                         sizeof(dpcd_test_pattern));
2991         core_link_read_dpcd(
2992                         link,
2993                         DP_TEST_MISC0,
2994                         &dpcd_test_params.raw,
2995                         sizeof(dpcd_test_params));
2996
2997         switch (dpcd_test_pattern.bits.PATTERN) {
2998         case LINK_TEST_PATTERN_COLOR_RAMP:
2999                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
3000         break;
3001         case LINK_TEST_PATTERN_VERTICAL_BARS:
3002                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
3003         break; /* black and white */
3004         case LINK_TEST_PATTERN_COLOR_SQUARES:
3005                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
3006                                 TEST_DYN_RANGE_VESA ?
3007                                 DP_TEST_PATTERN_COLOR_SQUARES :
3008                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
3009         break;
3010         default:
3011                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3012         break;
3013         }
3014
3015         if (dpcd_test_params.bits.CLR_FORMAT == 0)
3016                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
3017         else
3018                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
3019                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
3020                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
3021
3022         switch (dpcd_test_params.bits.BPC) {
3023         case 0: // 6 bits
3024                 requestColorDepth = COLOR_DEPTH_666;
3025                 break;
3026         case 1: // 8 bits
3027                 requestColorDepth = COLOR_DEPTH_888;
3028                 break;
3029         case 2: // 10 bits
3030                 requestColorDepth = COLOR_DEPTH_101010;
3031                 break;
3032         case 3: // 12 bits
3033                 requestColorDepth = COLOR_DEPTH_121212;
3034                 break;
3035         default:
3036                 break;
3037         }
3038
3039         switch (dpcd_test_params.bits.CLR_FORMAT) {
3040         case 0:
3041                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3042                 break;
3043         case 1:
3044                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3045                 break;
3046         case 2:
3047                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3048                 break;
3049         default:
3050                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3051                 break;
3052         }
3053
3054
3055         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3056                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
3057                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3058                                 __func__,
3059                                 pipe_ctx->stream->timing.display_color_depth,
3060                                 requestColorDepth);
3061                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
3062         }
3063
3064         dp_update_dsc_config(pipe_ctx);
3065
3066         dc_link_dp_set_test_pattern(
3067                         link,
3068                         test_pattern,
3069                         test_pattern_color_space,
3070                         NULL,
3071                         NULL,
3072                         0);
3073 }
3074
3075 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3076 {
3077         union audio_test_mode            dpcd_test_mode = {0};
3078         struct audio_test_pattern_type   dpcd_pattern_type = {0};
3079         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3080         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3081
3082         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3083         struct pipe_ctx *pipe_ctx = &pipes[0];
3084         unsigned int channel_count;
3085         unsigned int channel = 0;
3086         unsigned int modes = 0;
3087         unsigned int sampling_rate_in_hz = 0;
3088
3089         // get audio test mode and test pattern parameters
3090         core_link_read_dpcd(
3091                 link,
3092                 DP_TEST_AUDIO_MODE,
3093                 &dpcd_test_mode.raw,
3094                 sizeof(dpcd_test_mode));
3095
3096         core_link_read_dpcd(
3097                 link,
3098                 DP_TEST_AUDIO_PATTERN_TYPE,
3099                 &dpcd_pattern_type.value,
3100                 sizeof(dpcd_pattern_type));
3101
3102         channel_count = dpcd_test_mode.bits.channel_count + 1;
3103
3104         // read pattern periods for requested channels when sawTooth pattern is requested
3105         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3106                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3107
3108                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3109                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3110                 // read period for each channel
3111                 for (channel = 0; channel < channel_count; channel++) {
3112                         core_link_read_dpcd(
3113                                                         link,
3114                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
3115                                                         &dpcd_pattern_period[channel].raw,
3116                                                         sizeof(dpcd_pattern_period[channel]));
3117                 }
3118         }
3119
3120         // translate sampling rate
3121         switch (dpcd_test_mode.bits.sampling_rate) {
3122         case AUDIO_SAMPLING_RATE_32KHZ:
3123                 sampling_rate_in_hz = 32000;
3124                 break;
3125         case AUDIO_SAMPLING_RATE_44_1KHZ:
3126                 sampling_rate_in_hz = 44100;
3127                 break;
3128         case AUDIO_SAMPLING_RATE_48KHZ:
3129                 sampling_rate_in_hz = 48000;
3130                 break;
3131         case AUDIO_SAMPLING_RATE_88_2KHZ:
3132                 sampling_rate_in_hz = 88200;
3133                 break;
3134         case AUDIO_SAMPLING_RATE_96KHZ:
3135                 sampling_rate_in_hz = 96000;
3136                 break;
3137         case AUDIO_SAMPLING_RATE_176_4KHZ:
3138                 sampling_rate_in_hz = 176400;
3139                 break;
3140         case AUDIO_SAMPLING_RATE_192KHZ:
3141                 sampling_rate_in_hz = 192000;
3142                 break;
3143         default:
3144                 sampling_rate_in_hz = 0;
3145                 break;
3146         }
3147
3148         link->audio_test_data.flags.test_requested = 1;
3149         link->audio_test_data.flags.disable_video = disable_video;
3150         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3151         link->audio_test_data.channel_count = channel_count;
3152         link->audio_test_data.pattern_type = test_pattern;
3153
3154         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3155                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3156                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3157                 }
3158         }
3159 }
3160
3161 static void handle_automated_test(struct dc_link *link)
3162 {
3163         union test_request test_request;
3164         union test_response test_response;
3165
3166         memset(&test_request, 0, sizeof(test_request));
3167         memset(&test_response, 0, sizeof(test_response));
3168
3169         core_link_read_dpcd(
3170                 link,
3171                 DP_TEST_REQUEST,
3172                 &test_request.raw,
3173                 sizeof(union test_request));
3174         if (test_request.bits.LINK_TRAINING) {
3175                 /* ACK first to let DP RX test box monitor LT sequence */
3176                 test_response.bits.ACK = 1;
3177                 core_link_write_dpcd(
3178                         link,
3179                         DP_TEST_RESPONSE,
3180                         &test_response.raw,
3181                         sizeof(test_response));
3182                 dp_test_send_link_training(link);
3183                 /* no acknowledge request is needed again */
3184                 test_response.bits.ACK = 0;
3185         }
3186         if (test_request.bits.LINK_TEST_PATTRN) {
3187                 dp_test_send_link_test_pattern(link);
3188                 test_response.bits.ACK = 1;
3189         }
3190
3191         if (test_request.bits.AUDIO_TEST_PATTERN) {
3192                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3193                 test_response.bits.ACK = 1;
3194         }
3195
3196         if (test_request.bits.PHY_TEST_PATTERN) {
3197                 dp_test_send_phy_test_pattern(link);
3198                 test_response.bits.ACK = 1;
3199         }
3200
3201         /* send request acknowledgment */
3202         if (test_response.bits.ACK)
3203                 core_link_write_dpcd(
3204                         link,
3205                         DP_TEST_RESPONSE,
3206                         &test_response.raw,
3207                         sizeof(test_response));
3208 }
3209
3210 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3211 {
3212         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3213         union device_service_irq device_service_clear = { { 0 } };
3214         enum dc_status result;
3215         bool status = false;
3216         struct pipe_ctx *pipe_ctx;
3217         int i;
3218
3219         if (out_link_loss)
3220                 *out_link_loss = false;
3221         /* For use cases related to down stream connection status change,
3222          * PSR and device auto test, refer to function handle_sst_hpd_irq
3223          * in DAL2.1*/
3224
3225         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3226                 __func__, link->link_index);
3227
3228
3229          /* All the "handle_hpd_irq_xxx()" methods
3230                  * should be called only after
3231                  * dal_dpsst_ls_read_hpd_irq_data
3232                  * Order of calls is important too
3233                  */
3234         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3235         if (out_hpd_irq_dpcd_data)
3236                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3237
3238         if (result != DC_OK) {
3239                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3240                         __func__);
3241                 return false;
3242         }
3243
3244         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3245                 device_service_clear.bits.AUTOMATED_TEST = 1;
3246                 core_link_write_dpcd(
3247                         link,
3248                         DP_DEVICE_SERVICE_IRQ_VECTOR,
3249                         &device_service_clear.raw,
3250                         sizeof(device_service_clear.raw));
3251                 device_service_clear.raw = 0;
3252                 handle_automated_test(link);
3253                 return false;
3254         }
3255
3256         if (!allow_hpd_rx_irq(link)) {
3257                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3258                         __func__, link->link_index);
3259                 return false;
3260         }
3261
3262         if (handle_hpd_irq_psr_sink(link))
3263                 /* PSR-related error was detected and handled */
3264                 return true;
3265
3266         /* If PSR-related error handled, Main link may be off,
3267          * so do not handle as a normal sink status change interrupt.
3268          */
3269
3270         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3271                 return true;
3272
3273         /* check if we have MST msg and return since we poll for it */
3274         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3275                 return false;
3276
3277         /* For now we only handle 'Downstream port status' case.
3278          * If we got sink count changed it means
3279          * Downstream port status changed,
3280          * then DM should call DC to do the detection.
3281          * NOTE: Do not handle link loss on eDP since it is internal link*/
3282         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3283                 hpd_rx_irq_check_link_loss_status(
3284                         link,
3285                         &hpd_irq_dpcd_data)) {
3286                 /* Connectivity log: link loss */
3287                 CONN_DATA_LINK_LOSS(link,
3288                                         hpd_irq_dpcd_data.raw,
3289                                         sizeof(hpd_irq_dpcd_data),
3290                                         "Status: ");
3291
3292                 for (i = 0; i < MAX_PIPES; i++) {
3293                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3294                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3295                                 break;
3296                 }
3297
3298                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3299                         return false;
3300
3301
3302                 for (i = 0; i < MAX_PIPES; i++) {
3303                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3304                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3305                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3306                                 core_link_disable_stream(pipe_ctx);
3307                 }
3308
3309                 for (i = 0; i < MAX_PIPES; i++) {
3310                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3311                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3312                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3313                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3314                 }
3315
3316                 status = false;
3317                 if (out_link_loss)
3318                         *out_link_loss = true;
3319         }
3320
3321         if (link->type == dc_connection_sst_branch &&
3322                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3323                         != link->dpcd_sink_count)
3324                 status = true;
3325
3326         /* reasons for HPD RX:
3327          * 1. Link Loss - ie Re-train the Link
3328          * 2. MST sideband message
3329          * 3. Automated Test - ie. Internal Commit
3330          * 4. CP (copy protection) - (not interesting for DM???)
3331          * 5. DRR
3332          * 6. Downstream Port status changed
3333          * -ie. Detect - this the only one
3334          * which is interesting for DM because
3335          * it must call dc_link_detect.
3336          */
3337         return status;
3338 }
3339
3340 /*query dpcd for version and mst cap addresses*/
3341 bool is_mst_supported(struct dc_link *link)
3342 {
3343         bool mst          = false;
3344         enum dc_status st = DC_OK;
3345         union dpcd_rev rev;
3346         union mstm_cap cap;
3347
3348         if (link->preferred_training_settings.mst_enable &&
3349                 *link->preferred_training_settings.mst_enable == false) {
3350                 return false;
3351         }
3352
3353         rev.raw  = 0;
3354         cap.raw  = 0;
3355
3356         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3357                         sizeof(rev));
3358
3359         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3360
3361                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3362                                 &cap.raw, sizeof(cap));
3363                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3364                         mst = true;
3365         }
3366         return mst;
3367
3368 }
3369
3370 bool is_dp_active_dongle(const struct dc_link *link)
3371 {
3372         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3373                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3374 }
3375
3376 bool is_dp_branch_device(const struct dc_link *link)
3377 {
3378         return link->dpcd_caps.is_branch_dev;
3379 }
3380
3381 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3382 {
3383         switch (bpc) {
3384         case DOWN_STREAM_MAX_8BPC:
3385                 return 8;
3386         case DOWN_STREAM_MAX_10BPC:
3387                 return 10;
3388         case DOWN_STREAM_MAX_12BPC:
3389                 return 12;
3390         case DOWN_STREAM_MAX_16BPC:
3391                 return 16;
3392         default:
3393                 break;
3394         }
3395
3396         return -1;
3397 }
3398
3399 static void read_dp_device_vendor_id(struct dc_link *link)
3400 {
3401         struct dp_device_vendor_id dp_id;
3402
3403         /* read IEEE branch device id */
3404         core_link_read_dpcd(
3405                 link,
3406                 DP_BRANCH_OUI,
3407                 (uint8_t *)&dp_id,
3408                 sizeof(dp_id));
3409
3410         link->dpcd_caps.branch_dev_id =
3411                 (dp_id.ieee_oui[0] << 16) +
3412                 (dp_id.ieee_oui[1] << 8) +
3413                 dp_id.ieee_oui[2];
3414
3415         memmove(
3416                 link->dpcd_caps.branch_dev_name,
3417                 dp_id.ieee_device_id,
3418                 sizeof(dp_id.ieee_device_id));
3419 }
3420
3421
3422
3423 static void get_active_converter_info(
3424         uint8_t data, struct dc_link *link)
3425 {
3426         union dp_downstream_port_present ds_port = { .byte = data };
3427         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3428
3429         /* decode converter info*/
3430         if (!ds_port.fields.PORT_PRESENT) {
3431                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3432                 ddc_service_set_dongle_type(link->ddc,
3433                                 link->dpcd_caps.dongle_type);
3434                 link->dpcd_caps.is_branch_dev = false;
3435                 return;
3436         }
3437
3438         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3439         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3440
3441         switch (ds_port.fields.PORT_TYPE) {
3442         case DOWNSTREAM_VGA:
3443                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3444                 break;
3445         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3446                 /* At this point we don't know is it DVI or HDMI or DP++,
3447                  * assume DVI.*/
3448                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3449                 break;
3450         default:
3451                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3452                 break;
3453         }
3454
3455         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3456                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3457                 union dwnstream_port_caps_byte0 *port_caps =
3458                         (union dwnstream_port_caps_byte0 *)det_caps;
3459                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3460                                 det_caps, sizeof(det_caps)) == DC_OK) {
3461
3462                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3463                         /*Handle DP case as DONGLE_NONE*/
3464                         case DOWN_STREAM_DETAILED_DP:
3465                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3466                                 break;
3467                         case DOWN_STREAM_DETAILED_VGA:
3468                                 link->dpcd_caps.dongle_type =
3469                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3470                                 break;
3471                         case DOWN_STREAM_DETAILED_DVI:
3472                                 link->dpcd_caps.dongle_type =
3473                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3474                                 break;
3475                         case DOWN_STREAM_DETAILED_HDMI:
3476                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3477                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3478                                 link->dpcd_caps.dongle_type =
3479                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3480
3481                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3482                                 if (ds_port.fields.DETAILED_CAPS) {
3483
3484                                         union dwnstream_port_caps_byte3_hdmi
3485                                                 hdmi_caps = {.raw = det_caps[3] };
3486                                         union dwnstream_port_caps_byte2
3487                                                 hdmi_color_caps = {.raw = det_caps[2] };
3488                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3489                                                 det_caps[1] * 2500;
3490
3491                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3492                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3493                                         /*YCBCR capability only for HDMI case*/
3494                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3495                                                         == DOWN_STREAM_DETAILED_HDMI) {
3496                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3497                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3498                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3499                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3500                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3501                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3502                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3503                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3504                                         }
3505
3506                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3507                                                 translate_dpcd_max_bpc(
3508                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3509
3510                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3511                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3512                                 }
3513
3514                                 break;
3515                         }
3516                 }
3517         }
3518
3519         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3520
3521         {
3522                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3523
3524                 core_link_read_dpcd(
3525                         link,
3526                         DP_BRANCH_REVISION_START,
3527                         (uint8_t *)&dp_hw_fw_revision,
3528                         sizeof(dp_hw_fw_revision));
3529
3530                 link->dpcd_caps.branch_hw_revision =
3531                         dp_hw_fw_revision.ieee_hw_rev;
3532
3533                 memmove(
3534                         link->dpcd_caps.branch_fw_revision,
3535                         dp_hw_fw_revision.ieee_fw_rev,
3536                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3537         }
3538 }
3539
3540 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3541                 int length)
3542 {
3543         int retry = 0;
3544
3545         if (!link->dpcd_caps.dpcd_rev.raw) {
3546                 do {
3547                         dp_receiver_power_ctrl(link, true);
3548                         core_link_read_dpcd(link, DP_DPCD_REV,
3549                                                         dpcd_data, length);
3550                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3551                                 DP_DPCD_REV -
3552                                 DP_DPCD_REV];
3553                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3554         }
3555
3556         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3557                 switch (link->dpcd_caps.branch_dev_id) {
3558                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3559                  * all internal circuits including AUX communication preventing
3560                  * reading DPCD table and EDID (spec violation).
3561                  * Encoder will skip DP RX power down on disable_output to
3562                  * keep receiver powered all the time.*/
3563                 case DP_BRANCH_DEVICE_ID_0010FA:
3564                 case DP_BRANCH_DEVICE_ID_0080E1:
3565                 case DP_BRANCH_DEVICE_ID_00E04C:
3566                         link->wa_flags.dp_keep_receiver_powered = true;
3567                         break;
3568
3569                 /* TODO: May need work around for other dongles. */
3570                 default:
3571                         link->wa_flags.dp_keep_receiver_powered = false;
3572                         break;
3573                 }
3574         } else
3575                 link->wa_flags.dp_keep_receiver_powered = false;
3576 }
3577
3578 /* Read additional sink caps defined in source specific DPCD area
3579  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3580  */
3581 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3582 {
3583         uint8_t dpcd_data;
3584
3585         if (!link)
3586                 return false;
3587
3588         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3589                 return false;
3590
3591         link->dpcd_sink_ext_caps.raw = dpcd_data;
3592         return true;
3593 }
3594
3595 bool dp_retrieve_lttpr_cap(struct dc_link *link)
3596 {
3597         uint8_t lttpr_dpcd_data[6];
3598         bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
3599         bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
3600         enum dc_status status = DC_ERROR_UNEXPECTED;
3601         bool is_lttpr_present = false;
3602
3603         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3604
3605         /*
3606          * Logic to determine LTTPR mode
3607          */
3608         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3609         if (vbios_lttpr_enable && vbios_lttpr_interop)
3610                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3611         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3612                 if (link->dc->config.allow_lttpr_non_transparent_mode)
3613                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3614                 else
3615                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3616         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3617                 if (!link->dc->config.allow_lttpr_non_transparent_mode
3618                         || !link->dc->caps.extended_aux_timeout_support)
3619                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3620                 else
3621                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3622         }
3623
3624         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3625                 /* By reading LTTPR capability, RX assumes that we will enable
3626                  * LTTPR extended aux timeout if LTTPR is present.
3627                  */
3628                 status = core_link_read_dpcd(
3629                                 link,
3630                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3631                                 lttpr_dpcd_data,
3632                                 sizeof(lttpr_dpcd_data));
3633                 if (status != DC_OK) {
3634                         dm_error("%s: Read LTTPR caps data failed.\n", __func__);
3635                         return false;
3636                 }
3637
3638                 link->dpcd_caps.lttpr_caps.revision.raw =
3639                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3640                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3641
3642                 link->dpcd_caps.lttpr_caps.max_link_rate =
3643                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3644                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3645
3646                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3647                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3648                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3649
3650                 link->dpcd_caps.lttpr_caps.max_lane_count =
3651                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3652                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3653
3654                 link->dpcd_caps.lttpr_caps.mode =
3655                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3656                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3657
3658                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3659                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3660                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3661
3662                 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3663                 is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
3664                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3665                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3666                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3667                 if (is_lttpr_present) {
3668                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3669                         configure_lttpr_mode_transparent(link);
3670                 } else
3671                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3672         }
3673         return is_lttpr_present;
3674 }
3675
3676 static bool retrieve_link_cap(struct dc_link *link)
3677 {
3678         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3679          * which means size 16 will be good for both of those DPCD register block reads
3680          */
3681         uint8_t dpcd_data[16];
3682         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3683          */
3684         uint8_t dpcd_dprx_data = '\0';
3685         uint8_t dpcd_power_state = '\0';
3686
3687         struct dp_device_vendor_id sink_id;
3688         union down_stream_port_count down_strm_port_count;
3689         union edp_configuration_cap edp_config_cap;
3690         union dp_downstream_port_present ds_port = { 0 };
3691         enum dc_status status = DC_ERROR_UNEXPECTED;
3692         uint32_t read_dpcd_retry_cnt = 3;
3693         int i;
3694         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3695         const uint32_t post_oui_delay = 30; // 30ms
3696         bool is_lttpr_present = false;
3697
3698         memset(dpcd_data, '\0', sizeof(dpcd_data));
3699         memset(&down_strm_port_count,
3700                 '\0', sizeof(union down_stream_port_count));
3701         memset(&edp_config_cap, '\0',
3702                 sizeof(union edp_configuration_cap));
3703
3704         /* if extended timeout is supported in hardware,
3705          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3706          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3707          */
3708         dc_link_aux_try_to_configure_timeout(link->ddc,
3709                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3710
3711         is_lttpr_present = dp_retrieve_lttpr_cap(link);
3712
3713         status = core_link_read_dpcd(link, DP_SET_POWER,
3714                         &dpcd_power_state, sizeof(dpcd_power_state));
3715
3716         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3717          * section 2.3.1.2, if AUX CH may be powered down due to
3718          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3719          * signal and may need up to 1 ms before being able to reply.
3720          */
3721         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3722                 udelay(1000);
3723
3724         dpcd_set_source_specific_data(link);
3725         /* Sink may need to configure internals based on vendor, so allow some
3726          * time before proceeding with possibly vendor specific transactions
3727          */
3728         msleep(post_oui_delay);
3729
3730         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3731                 status = core_link_read_dpcd(
3732                                 link,
3733                                 DP_DPCD_REV,
3734                                 dpcd_data,
3735                                 sizeof(dpcd_data));
3736                 if (status == DC_OK)
3737                         break;
3738         }
3739
3740         if (status != DC_OK) {
3741                 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
3742                 return false;
3743         }
3744
3745         if (!is_lttpr_present)
3746                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3747
3748         {
3749                 union training_aux_rd_interval aux_rd_interval;
3750
3751                 aux_rd_interval.raw =
3752                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3753
3754                 link->dpcd_caps.ext_receiver_cap_field_present =
3755                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3756
3757                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3758                         uint8_t ext_cap_data[16];
3759
3760                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3761                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3762                                 status = core_link_read_dpcd(
3763                                 link,
3764                                 DP_DP13_DPCD_REV,
3765                                 ext_cap_data,
3766                                 sizeof(ext_cap_data));
3767                                 if (status == DC_OK) {
3768                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3769                                         break;
3770                                 }
3771                         }
3772                         if (status != DC_OK)
3773                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3774                 }
3775         }
3776
3777         link->dpcd_caps.dpcd_rev.raw =
3778                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3779
3780         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3781                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3782                         status = core_link_read_dpcd(
3783                                         link,
3784                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3785                                         &dpcd_dprx_data,
3786                                         sizeof(dpcd_dprx_data));
3787                         if (status == DC_OK)
3788                                 break;
3789                 }
3790
3791                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3792
3793                 if (status != DC_OK)
3794                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3795         }
3796
3797         else {
3798                 link->dpcd_caps.dprx_feature.raw = 0;
3799         }
3800
3801
3802         /* Error condition checking...
3803          * It is impossible for Sink to report Max Lane Count = 0.
3804          * It is possible for Sink to report Max Link Rate = 0, if it is
3805          * an eDP device that is reporting specialized link rates in the
3806          * SUPPORTED_LINK_RATE table.
3807          */
3808         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3809                 return false;
3810
3811         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3812                                  DP_DPCD_REV];
3813
3814         read_dp_device_vendor_id(link);
3815
3816         get_active_converter_info(ds_port.byte, link);
3817
3818         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3819
3820         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3821                                  DP_DPCD_REV];
3822
3823         link->dpcd_caps.allow_invalid_MSA_timing_param =
3824                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3825
3826         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3827                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3828
3829         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3830                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3831
3832         link->reported_link_cap.lane_count =
3833                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3834         link->reported_link_cap.link_rate = dpcd_data[
3835                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3836         link->reported_link_cap.link_spread =
3837                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3838                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3839
3840         edp_config_cap.raw = dpcd_data[
3841                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3842         link->dpcd_caps.panel_mode_edp =
3843                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3844         link->dpcd_caps.dpcd_display_control_capable =
3845                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3846
3847         link->test_pattern_enabled = false;
3848         link->compliance_test_state.raw = 0;
3849
3850         /* read sink count */
3851         core_link_read_dpcd(link,
3852                         DP_SINK_COUNT,
3853                         &link->dpcd_caps.sink_count.raw,
3854                         sizeof(link->dpcd_caps.sink_count.raw));
3855
3856         /* read sink ieee oui */
3857         core_link_read_dpcd(link,
3858                         DP_SINK_OUI,
3859                         (uint8_t *)(&sink_id),
3860                         sizeof(sink_id));
3861
3862         link->dpcd_caps.sink_dev_id =
3863                         (sink_id.ieee_oui[0] << 16) +
3864                         (sink_id.ieee_oui[1] << 8) +
3865                         (sink_id.ieee_oui[2]);
3866
3867         memmove(
3868                 link->dpcd_caps.sink_dev_id_str,
3869                 sink_id.ieee_device_id,
3870                 sizeof(sink_id.ieee_device_id));
3871
3872         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3873         {
3874                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3875
3876                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3877                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3878                             sizeof(str_mbp_2017))) {
3879                         link->reported_link_cap.link_rate = 0x0c;
3880                 }
3881         }
3882
3883         core_link_read_dpcd(
3884                 link,
3885                 DP_SINK_HW_REVISION_START,
3886                 (uint8_t *)&dp_hw_fw_revision,
3887                 sizeof(dp_hw_fw_revision));
3888
3889         link->dpcd_caps.sink_hw_revision =
3890                 dp_hw_fw_revision.ieee_hw_rev;
3891
3892         memmove(
3893                 link->dpcd_caps.sink_fw_revision,
3894                 dp_hw_fw_revision.ieee_fw_rev,
3895                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3896
3897         memset(&link->dpcd_caps.dsc_caps, '\0',
3898                         sizeof(link->dpcd_caps.dsc_caps));
3899         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3900         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3901         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3902                 status = core_link_read_dpcd(
3903                                 link,
3904                                 DP_FEC_CAPABILITY,
3905                                 &link->dpcd_caps.fec_cap.raw,
3906                                 sizeof(link->dpcd_caps.fec_cap.raw));
3907                 status = core_link_read_dpcd(
3908                                 link,
3909                                 DP_DSC_SUPPORT,
3910                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3911                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3912                 status = core_link_read_dpcd(
3913                                 link,
3914                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3915                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3916                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3917         }
3918
3919         if (!dpcd_read_sink_ext_caps(link))
3920                 link->dpcd_sink_ext_caps.raw = 0;
3921
3922         /* Connectivity log: detection */
3923         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3924
3925         return true;
3926 }
3927
3928 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3929 {
3930         uint8_t dpcd_data[16];
3931         uint32_t read_dpcd_retry_cnt = 3;
3932         enum dc_status status = DC_ERROR_UNEXPECTED;
3933         union dp_downstream_port_present ds_port = { 0 };
3934         union down_stream_port_count down_strm_port_count;
3935         union edp_configuration_cap edp_config_cap;
3936
3937         int i;
3938
3939         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3940                 status = core_link_read_dpcd(
3941                                 link,
3942                                 DP_DPCD_REV,
3943                                 dpcd_data,
3944                                 sizeof(dpcd_data));
3945                 if (status == DC_OK)
3946                         break;
3947         }
3948
3949         link->dpcd_caps.dpcd_rev.raw =
3950                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3951
3952         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3953                 return false;
3954
3955         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3956                         DP_DPCD_REV];
3957
3958         get_active_converter_info(ds_port.byte, link);
3959
3960         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3961                         DP_DPCD_REV];
3962
3963         link->dpcd_caps.allow_invalid_MSA_timing_param =
3964                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3965
3966         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3967                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3968
3969         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3970                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3971
3972         link->reported_link_cap.lane_count =
3973                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3974         link->reported_link_cap.link_rate = dpcd_data[
3975                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3976         link->reported_link_cap.link_spread =
3977                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3978                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3979
3980         edp_config_cap.raw = dpcd_data[
3981                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3982         link->dpcd_caps.panel_mode_edp =
3983                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3984         link->dpcd_caps.dpcd_display_control_capable =
3985                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3986
3987         return true;
3988 }
3989
3990 bool detect_dp_sink_caps(struct dc_link *link)
3991 {
3992         return retrieve_link_cap(link);
3993
3994         /* dc init_hw has power encoder using default
3995          * signal for connector. For native DP, no
3996          * need to power up encoder again. If not native
3997          * DP, hw_init may need check signal or power up
3998          * encoder here.
3999          */
4000         /* TODO save sink caps in link->sink */
4001 }
4002
4003 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
4004 {
4005         enum dc_link_rate link_rate;
4006         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
4007         switch (link_rate_in_khz) {
4008         case 1620000:
4009                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
4010                 break;
4011         case 2160000:
4012                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
4013                 break;
4014         case 2430000:
4015                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
4016                 break;
4017         case 2700000:
4018                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
4019                 break;
4020         case 3240000:
4021                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
4022                 break;
4023         case 4320000:
4024                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
4025                 break;
4026         case 5400000:
4027                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
4028                 break;
4029         case 8100000:
4030                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
4031                 break;
4032         default:
4033                 link_rate = LINK_RATE_UNKNOWN;
4034                 break;
4035         }
4036         return link_rate;
4037 }
4038
4039 void detect_edp_sink_caps(struct dc_link *link)
4040 {
4041         uint8_t supported_link_rates[16];
4042         uint32_t entry;
4043         uint32_t link_rate_in_khz;
4044         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
4045         uint8_t backlight_adj_cap;
4046
4047         retrieve_link_cap(link);
4048         link->dpcd_caps.edp_supported_link_rates_count = 0;
4049         memset(supported_link_rates, 0, sizeof(supported_link_rates));
4050
4051         /*
4052          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4053          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4054          */
4055         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
4056                         (link->dc->debug.optimize_edp_link_rate ||
4057                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
4058                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4059                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4060                                                         supported_link_rates, sizeof(supported_link_rates));
4061
4062                 for (entry = 0; entry < 16; entry += 2) {
4063                         // DPCD register reports per-lane link rate = 16-bit link rate capability
4064                         // value X 200 kHz. Need multiplier to find link rate in kHz.
4065                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4066                                                                                 supported_link_rates[entry]) * 200;
4067
4068                         if (link_rate_in_khz != 0) {
4069                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4070                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4071                                 link->dpcd_caps.edp_supported_link_rates_count++;
4072
4073                                 if (link->reported_link_cap.link_rate < link_rate)
4074                                         link->reported_link_cap.link_rate = link_rate;
4075                         }
4076                 }
4077         }
4078         link->verified_link_cap = link->reported_link_cap;
4079
4080         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4081                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
4082
4083         link->dpcd_caps.dynamic_backlight_capable_edp =
4084                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4085
4086         dc_link_set_default_brightness_aux(link);
4087 }
4088
4089 void dc_link_dp_enable_hpd(const struct dc_link *link)
4090 {
4091         struct link_encoder *encoder = link->link_enc;
4092
4093         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4094                 encoder->funcs->enable_hpd(encoder);
4095 }
4096
4097 void dc_link_dp_disable_hpd(const struct dc_link *link)
4098 {
4099         struct link_encoder *encoder = link->link_enc;
4100
4101         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4102                 encoder->funcs->disable_hpd(encoder);
4103 }
4104
4105 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4106 {
4107         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4108                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4109                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4110                 return true;
4111         else
4112                 return false;
4113 }
4114
4115 static void set_crtc_test_pattern(struct dc_link *link,
4116                                 struct pipe_ctx *pipe_ctx,
4117                                 enum dp_test_pattern test_pattern,
4118                                 enum dp_test_pattern_color_space test_pattern_color_space)
4119 {
4120         enum controller_dp_test_pattern controller_test_pattern;
4121         enum dc_color_depth color_depth = pipe_ctx->
4122                 stream->timing.display_color_depth;
4123         struct bit_depth_reduction_params params;
4124         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4125         int width = pipe_ctx->stream->timing.h_addressable +
4126                 pipe_ctx->stream->timing.h_border_left +
4127                 pipe_ctx->stream->timing.h_border_right;
4128         int height = pipe_ctx->stream->timing.v_addressable +
4129                 pipe_ctx->stream->timing.v_border_bottom +
4130                 pipe_ctx->stream->timing.v_border_top;
4131
4132         memset(&params, 0, sizeof(params));
4133
4134         switch (test_pattern) {
4135         case DP_TEST_PATTERN_COLOR_SQUARES:
4136                 controller_test_pattern =
4137                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4138         break;
4139         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4140                 controller_test_pattern =
4141                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4142         break;
4143         case DP_TEST_PATTERN_VERTICAL_BARS:
4144                 controller_test_pattern =
4145                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4146         break;
4147         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4148                 controller_test_pattern =
4149                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4150         break;
4151         case DP_TEST_PATTERN_COLOR_RAMP:
4152                 controller_test_pattern =
4153                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4154         break;
4155         default:
4156                 controller_test_pattern =
4157                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4158         break;
4159         }
4160
4161         switch (test_pattern) {
4162         case DP_TEST_PATTERN_COLOR_SQUARES:
4163         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4164         case DP_TEST_PATTERN_VERTICAL_BARS:
4165         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4166         case DP_TEST_PATTERN_COLOR_RAMP:
4167         {
4168                 /* disable bit depth reduction */
4169                 pipe_ctx->stream->bit_depth_params = params;
4170                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4171                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4172                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4173                                 controller_test_pattern, color_depth);
4174                 else if (link->dc->hwss.set_disp_pattern_generator) {
4175                         struct pipe_ctx *odm_pipe;
4176                         enum controller_dp_color_space controller_color_space;
4177                         int opp_cnt = 1;
4178                         int offset = 0;
4179                         int dpg_width = width;
4180
4181                         switch (test_pattern_color_space) {
4182                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4183                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4184                                 break;
4185                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4186                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4187                                 break;
4188                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4189                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4190                                 break;
4191                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4192                         default:
4193                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4194                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4195                                 ASSERT(0);
4196                                 break;
4197                         }
4198
4199                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4200                                 opp_cnt++;
4201                         dpg_width = width / opp_cnt;
4202                         offset = dpg_width;
4203
4204                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4205                                         pipe_ctx,
4206                                         controller_test_pattern,
4207                                         controller_color_space,
4208                                         color_depth,
4209                                         NULL,
4210                                         dpg_width,
4211                                         height,
4212                                         0);
4213
4214                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4215                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4216
4217                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4218                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4219                                                 odm_pipe,
4220                                                 controller_test_pattern,
4221                                                 controller_color_space,
4222                                                 color_depth,
4223                                                 NULL,
4224                                                 dpg_width,
4225                                                 height,
4226                                                 offset);
4227                                 offset += offset;
4228                         }
4229                 }
4230         }
4231         break;
4232         case DP_TEST_PATTERN_VIDEO_MODE:
4233         {
4234                 /* restore bitdepth reduction */
4235                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4236                 pipe_ctx->stream->bit_depth_params = params;
4237                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4238                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4239                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4240                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4241                                 color_depth);
4242                 else if (link->dc->hwss.set_disp_pattern_generator) {
4243                         struct pipe_ctx *odm_pipe;
4244                         int opp_cnt = 1;
4245                         int dpg_width = width;
4246
4247                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4248                                 opp_cnt++;
4249
4250                         dpg_width = width / opp_cnt;
4251                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4252                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4253
4254                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4255                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4256                                                 odm_pipe,
4257                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4258                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4259                                                 color_depth,
4260                                                 NULL,
4261                                                 dpg_width,
4262                                                 height,
4263                                                 0);
4264                         }
4265                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4266                                         pipe_ctx,
4267                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4268                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4269                                         color_depth,
4270                                         NULL,
4271                                         dpg_width,
4272                                         height,
4273                                         0);
4274                 }
4275         }
4276         break;
4277
4278         default:
4279         break;
4280         }
4281 }
4282
4283 bool dc_link_dp_set_test_pattern(
4284         struct dc_link *link,
4285         enum dp_test_pattern test_pattern,
4286         enum dp_test_pattern_color_space test_pattern_color_space,
4287         const struct link_training_settings *p_link_settings,
4288         const unsigned char *p_custom_pattern,
4289         unsigned int cust_pattern_size)
4290 {
4291         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4292         struct pipe_ctx *pipe_ctx = NULL;
4293         unsigned int lane;
4294         unsigned int i;
4295         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4296         union dpcd_training_pattern training_pattern;
4297         enum dpcd_phy_test_patterns pattern;
4298
4299         memset(&training_pattern, 0, sizeof(training_pattern));
4300
4301         for (i = 0; i < MAX_PIPES; i++) {
4302                 if (pipes[i].stream == NULL)
4303                         continue;
4304
4305                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4306                         pipe_ctx = &pipes[i];
4307                         break;
4308                 }
4309         }
4310
4311         if (pipe_ctx == NULL)
4312                 return false;
4313
4314         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4315         if (link->test_pattern_enabled && test_pattern ==
4316                         DP_TEST_PATTERN_VIDEO_MODE) {
4317                 /* Set CRTC Test Pattern */
4318                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4319                 dp_set_hw_test_pattern(link, test_pattern,
4320                                 (uint8_t *)p_custom_pattern,
4321                                 (uint32_t)cust_pattern_size);
4322
4323                 /* Unblank Stream */
4324                 link->dc->hwss.unblank_stream(
4325                         pipe_ctx,
4326                         &link->verified_link_cap);
4327                 /* TODO:m_pHwss->MuteAudioEndpoint
4328                  * (pPathMode->pDisplayPath, false);
4329                  */
4330
4331                 /* Reset Test Pattern state */
4332                 link->test_pattern_enabled = false;
4333
4334                 return true;
4335         }
4336
4337         /* Check for PHY Test Patterns */
4338         if (is_dp_phy_pattern(test_pattern)) {
4339                 /* Set DPCD Lane Settings before running test pattern */
4340                 if (p_link_settings != NULL) {
4341                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4342                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4343                 }
4344
4345                 /* Blank stream if running test pattern */
4346                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4347                         /*TODO:
4348                          * m_pHwss->
4349                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4350                          */
4351                         /* Blank stream */
4352                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4353                 }
4354
4355                 dp_set_hw_test_pattern(link, test_pattern,
4356                                 (uint8_t *)p_custom_pattern,
4357                                 (uint32_t)cust_pattern_size);
4358
4359                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4360                         /* Set Test Pattern state */
4361                         link->test_pattern_enabled = true;
4362                         if (p_link_settings != NULL)
4363                                 dpcd_set_link_settings(link,
4364                                                 p_link_settings);
4365                 }
4366
4367                 switch (test_pattern) {
4368                 case DP_TEST_PATTERN_VIDEO_MODE:
4369                         pattern = PHY_TEST_PATTERN_NONE;
4370                         break;
4371                 case DP_TEST_PATTERN_D102:
4372                         pattern = PHY_TEST_PATTERN_D10_2;
4373                         break;
4374                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4375                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4376                         break;
4377                 case DP_TEST_PATTERN_PRBS7:
4378                         pattern = PHY_TEST_PATTERN_PRBS7;
4379                         break;
4380                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4381                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4382                         break;
4383                 case DP_TEST_PATTERN_CP2520_1:
4384                         pattern = PHY_TEST_PATTERN_CP2520_1;
4385                         break;
4386                 case DP_TEST_PATTERN_CP2520_2:
4387                         pattern = PHY_TEST_PATTERN_CP2520_2;
4388                         break;
4389                 case DP_TEST_PATTERN_CP2520_3:
4390                         pattern = PHY_TEST_PATTERN_CP2520_3;
4391                         break;
4392                 default:
4393                         return false;
4394                 }
4395
4396                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4397                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4398                         return false;
4399
4400                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4401                         /* tell receiver that we are sending qualification
4402                          * pattern DP 1.2 or later - DP receiver's link quality
4403                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4404                          * register (0x10B~0x10E)\
4405                          */
4406                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4407                                 link_qual_pattern[lane] =
4408                                                 (unsigned char)(pattern);
4409
4410                         core_link_write_dpcd(link,
4411                                         DP_LINK_QUAL_LANE0_SET,
4412                                         link_qual_pattern,
4413                                         sizeof(link_qual_pattern));
4414                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4415                            link->dpcd_caps.dpcd_rev.raw == 0) {
4416                         /* tell receiver that we are sending qualification
4417                          * pattern DP 1.1a or earlier - DP receiver's link
4418                          * quality pattern is set using
4419                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4420                          * register (0x102). We will use v_1.3 when we are
4421                          * setting test pattern for DP 1.1.
4422                          */
4423                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4424                                             &training_pattern.raw,
4425                                             sizeof(training_pattern));
4426                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4427                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4428                                              &training_pattern.raw,
4429                                              sizeof(training_pattern));
4430                 }
4431         } else {
4432                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4433
4434                 switch (test_pattern_color_space) {
4435                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4436                         color_space = COLOR_SPACE_SRGB;
4437                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4438                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4439                         break;
4440
4441                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4442                         color_space = COLOR_SPACE_YCBCR601;
4443                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4444                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4445                         break;
4446                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4447                         color_space = COLOR_SPACE_YCBCR709;
4448                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4449                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4450                         break;
4451                 default:
4452                         break;
4453                 }
4454
4455                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4456                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4457                                 union dmub_hw_lock_flags hw_locks = { 0 };
4458                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4459
4460                                 hw_locks.bits.lock_dig = 1;
4461                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4462
4463                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4464                                                         true,
4465                                                         &hw_locks,
4466                                                         &inst_flags);
4467                         } else
4468                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4469                                                 pipe_ctx->stream_res.tg);
4470                 }
4471
4472                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4473                 /* update MSA to requested color space */
4474                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4475                                 &pipe_ctx->stream->timing,
4476                                 color_space,
4477                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4478                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4479
4480                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4481                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4482                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4483                         else
4484                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4485                         resource_build_info_frame(pipe_ctx);
4486                         link->dc->hwss.update_info_frame(pipe_ctx);
4487                 }
4488
4489                 /* CRTC Patterns */
4490                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4491                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4492                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4493                                 CRTC_STATE_VACTIVE);
4494                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4495                                 CRTC_STATE_VBLANK);
4496                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4497                                 CRTC_STATE_VACTIVE);
4498
4499                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4500                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4501                                 union dmub_hw_lock_flags hw_locks = { 0 };
4502                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4503
4504                                 hw_locks.bits.lock_dig = 1;
4505                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4506
4507                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4508                                                         false,
4509                                                         &hw_locks,
4510                                                         &inst_flags);
4511                         } else
4512                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4513                                                 pipe_ctx->stream_res.tg);
4514                 }
4515
4516                 /* Set Test Pattern state */
4517                 link->test_pattern_enabled = true;
4518         }
4519
4520         return true;
4521 }
4522
4523 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4524 {
4525         unsigned char mstmCntl;
4526
4527         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4528         if (enable)
4529                 mstmCntl |= DP_MST_EN;
4530         else
4531                 mstmCntl &= (~DP_MST_EN);
4532
4533         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4534 }
4535
4536 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4537 {
4538         union dpcd_edp_config edp_config_set;
4539         bool panel_mode_edp = false;
4540
4541         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4542
4543         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4544
4545                 switch (panel_mode) {
4546                 case DP_PANEL_MODE_EDP:
4547                 case DP_PANEL_MODE_SPECIAL:
4548                         panel_mode_edp = true;
4549                         break;
4550
4551                 default:
4552                                 break;
4553                 }
4554
4555                 /*set edp panel mode in receiver*/
4556                 core_link_read_dpcd(
4557                         link,
4558                         DP_EDP_CONFIGURATION_SET,
4559                         &edp_config_set.raw,
4560                         sizeof(edp_config_set.raw));
4561
4562                 if (edp_config_set.bits.PANEL_MODE_EDP
4563                         != panel_mode_edp) {
4564                         enum dc_status result;
4565
4566                         edp_config_set.bits.PANEL_MODE_EDP =
4567                         panel_mode_edp;
4568                         result = core_link_write_dpcd(
4569                                 link,
4570                                 DP_EDP_CONFIGURATION_SET,
4571                                 &edp_config_set.raw,
4572                                 sizeof(edp_config_set.raw));
4573
4574                         ASSERT(result == DC_OK);
4575                 }
4576         }
4577         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4578                  "eDP panel mode enabled: %d \n",
4579                  link->link_index,
4580                  link->dpcd_caps.panel_mode_edp,
4581                  panel_mode_edp);
4582 }
4583
4584 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4585 {
4586         /* We need to explicitly check that connector
4587          * is not DP. Some Travis_VGA get reported
4588          * by video bios as DP.
4589          */
4590         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4591
4592                 switch (link->dpcd_caps.branch_dev_id) {
4593                 case DP_BRANCH_DEVICE_ID_0022B9:
4594                         /* alternate scrambler reset is required for Travis
4595                          * for the case when external chip does not
4596                          * provide sink device id, alternate scrambler
4597                          * scheme will  be overriden later by querying
4598                          * Encoder features
4599                          */
4600                         if (strncmp(
4601                                 link->dpcd_caps.branch_dev_name,
4602                                 DP_VGA_LVDS_CONVERTER_ID_2,
4603                                 sizeof(
4604                                 link->dpcd_caps.
4605                                 branch_dev_name)) == 0) {
4606                                         return DP_PANEL_MODE_SPECIAL;
4607                         }
4608                         break;
4609                 case DP_BRANCH_DEVICE_ID_00001A:
4610                         /* alternate scrambler reset is required for Travis
4611                          * for the case when external chip does not provide
4612                          * sink device id, alternate scrambler scheme will
4613                          * be overriden later by querying Encoder feature
4614                          */
4615                         if (strncmp(link->dpcd_caps.branch_dev_name,
4616                                 DP_VGA_LVDS_CONVERTER_ID_3,
4617                                 sizeof(
4618                                 link->dpcd_caps.
4619                                 branch_dev_name)) == 0) {
4620                                         return DP_PANEL_MODE_SPECIAL;
4621                         }
4622                         break;
4623                 default:
4624                         break;
4625                 }
4626         }
4627
4628         if (link->dpcd_caps.panel_mode_edp &&
4629                 (link->connector_signal == SIGNAL_TYPE_EDP ||
4630                  (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
4631                   link->is_internal_display))) {
4632                 return DP_PANEL_MODE_EDP;
4633         }
4634
4635         return DP_PANEL_MODE_DEFAULT;
4636 }
4637
4638 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
4639 {
4640         /* FEC has to be "set ready" before the link training.
4641          * The policy is to always train with FEC
4642          * if the sink supports it and leave it enabled on link.
4643          * If FEC is not supported, disable it.
4644          */
4645         struct link_encoder *link_enc = NULL;
4646         enum dc_status status = DC_OK;
4647         uint8_t fec_config = 0;
4648
4649         /* Access link encoder based on whether it is statically
4650          * or dynamically assigned to a link.
4651          */
4652         if (link->is_dig_mapping_flexible &&
4653                         link->dc->res_pool->funcs->link_encs_assign)
4654                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
4655         else
4656                 link_enc = link->link_enc;
4657         ASSERT(link_enc);
4658
4659         if (!dc_link_should_enable_fec(link))
4660                 return status;
4661
4662         if (link_enc->funcs->fec_set_ready &&
4663                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4664                 if (ready) {
4665                         fec_config = 1;
4666                         status = core_link_write_dpcd(link,
4667                                         DP_FEC_CONFIGURATION,
4668                                         &fec_config,
4669                                         sizeof(fec_config));
4670                         if (status == DC_OK) {
4671                                 link_enc->funcs->fec_set_ready(link_enc, true);
4672                                 link->fec_state = dc_link_fec_ready;
4673                         } else {
4674                                 link_enc->funcs->fec_set_ready(link->link_enc, false);
4675                                 link->fec_state = dc_link_fec_not_ready;
4676                                 dm_error("dpcd write failed to set fec_ready");
4677                         }
4678                 } else if (link->fec_state == dc_link_fec_ready) {
4679                         fec_config = 0;
4680                         status = core_link_write_dpcd(link,
4681                                         DP_FEC_CONFIGURATION,
4682                                         &fec_config,
4683                                         sizeof(fec_config));
4684                         link_enc->funcs->fec_set_ready(link_enc, false);
4685                         link->fec_state = dc_link_fec_not_ready;
4686                 }
4687         }
4688
4689         return status;
4690 }
4691
4692 void dp_set_fec_enable(struct dc_link *link, bool enable)
4693 {
4694         struct link_encoder *link_enc = NULL;
4695
4696         /* Access link encoder based on whether it is statically
4697          * or dynamically assigned to a link.
4698          */
4699         if (link->is_dig_mapping_flexible &&
4700                         link->dc->res_pool->funcs->link_encs_assign)
4701                 link_enc = link_enc_cfg_get_link_enc_used_by_link(
4702                                 link->dc->current_state, link);
4703         else
4704                 link_enc = link->link_enc;
4705         ASSERT(link_enc);
4706
4707         if (!dc_link_should_enable_fec(link))
4708                 return;
4709
4710         if (link_enc->funcs->fec_set_enable &&
4711                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4712                 if (link->fec_state == dc_link_fec_ready && enable) {
4713                         /* Accord to DP spec, FEC enable sequence can first
4714                          * be transmitted anytime after 1000 LL codes have
4715                          * been transmitted on the link after link training
4716                          * completion. Using 1 lane RBR should have the maximum
4717                          * time for transmitting 1000 LL codes which is 6.173 us.
4718                          * So use 7 microseconds delay instead.
4719                          */
4720                         udelay(7);
4721                         link_enc->funcs->fec_set_enable(link_enc, true);
4722                         link->fec_state = dc_link_fec_enabled;
4723                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4724                         link_enc->funcs->fec_set_enable(link_enc, false);
4725                         link->fec_state = dc_link_fec_ready;
4726                 }
4727         }
4728 }
4729
4730 void dpcd_set_source_specific_data(struct dc_link *link)
4731 {
4732         if (!link->dc->vendor_signature.is_valid) {
4733                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4734                 struct dpcd_amd_signature amd_signature = {0};
4735                 struct dpcd_amd_device_id amd_device_id = {0};
4736
4737                 amd_device_id.device_id_byte1 =
4738                                 (uint8_t)(link->ctx->asic_id.chip_id);
4739                 amd_device_id.device_id_byte2 =
4740                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4741                 amd_device_id.dce_version =
4742                                 (uint8_t)(link->ctx->dce_version);
4743                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4744                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4745
4746                 core_link_read_dpcd(link, DP_SOURCE_OUI,
4747                                 (uint8_t *)(&amd_signature),
4748                                 sizeof(amd_signature));
4749
4750                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4751                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4752                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4753
4754                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4755                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4756                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4757
4758                         core_link_write_dpcd(link, DP_SOURCE_OUI,
4759                                 (uint8_t *)(&amd_signature),
4760                                 sizeof(amd_signature));
4761                 }
4762
4763                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4764                                 (uint8_t *)(&amd_device_id),
4765                                 sizeof(amd_device_id));
4766
4767                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4768                         link->dc->caps.min_horizontal_blanking_period != 0) {
4769
4770                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4771
4772                         if (link->preferred_link_setting.dpcd_source_device_specific_field_support) {
4773                                 result_write_min_hblank = core_link_write_dpcd(link,
4774                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4775                                         sizeof(hblank_size));
4776
4777                                 if (result_write_min_hblank == DC_ERROR_UNEXPECTED)
4778                                         link->preferred_link_setting.dpcd_source_device_specific_field_support = false;
4779                         } else {
4780                                 DC_LOG_DC("Sink device does not support 00340h DPCD write. Skipping on purpose.\n");
4781                         }
4782                 }
4783
4784                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4785                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4786                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4787                                                         result_write_min_hblank,
4788                                                         link->link_index,
4789                                                         link->ctx->dce_version,
4790                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4791                                                         link->dc->caps.min_horizontal_blanking_period,
4792                                                         link->dpcd_caps.branch_dev_id,
4793                                                         link->dpcd_caps.branch_dev_name[0],
4794                                                         link->dpcd_caps.branch_dev_name[1],
4795                                                         link->dpcd_caps.branch_dev_name[2],
4796                                                         link->dpcd_caps.branch_dev_name[3],
4797                                                         link->dpcd_caps.branch_dev_name[4],
4798                                                         link->dpcd_caps.branch_dev_name[5]);
4799         } else {
4800                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4801                                 link->dc->vendor_signature.data.raw,
4802                                 sizeof(link->dc->vendor_signature.data.raw));
4803         }
4804 }
4805
4806 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4807                 bool isHDR,
4808                 uint32_t backlight_millinits,
4809                 uint32_t transition_time_in_ms)
4810 {
4811         struct dpcd_source_backlight_set dpcd_backlight_set;
4812         uint8_t backlight_control = isHDR ? 1 : 0;
4813
4814         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4815                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4816                 return false;
4817
4818         // OLEDs have no PWM, they can only use AUX
4819         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4820                 backlight_control = 1;
4821
4822         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4823         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4824
4825
4826         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4827                         (uint8_t *)(&dpcd_backlight_set),
4828                         sizeof(dpcd_backlight_set)) != DC_OK)
4829                 return false;
4830
4831         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4832                         &backlight_control, 1) != DC_OK)
4833                 return false;
4834
4835         return true;
4836 }
4837
4838 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4839                 uint32_t *backlight_millinits_avg,
4840                 uint32_t *backlight_millinits_peak)
4841 {
4842         union dpcd_source_backlight_get dpcd_backlight_get;
4843
4844         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4845
4846         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4847                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4848                 return false;
4849
4850         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4851                         dpcd_backlight_get.raw,
4852                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4853                 return false;
4854
4855         *backlight_millinits_avg =
4856                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4857         *backlight_millinits_peak =
4858                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4859
4860         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4861         if (*backlight_millinits_avg == 0 ||
4862                         *backlight_millinits_avg > *backlight_millinits_peak)
4863                 return false;
4864
4865         return true;
4866 }
4867
4868 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4869 {
4870         uint8_t backlight_enable = enable ? 1 : 0;
4871
4872         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4873                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4874                 return false;
4875
4876         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4877                 &backlight_enable, 1) != DC_OK)
4878                 return false;
4879
4880         return true;
4881 }
4882
4883 // we read default from 0x320 because we expect BIOS wrote it there
4884 // regular get_backlight_nit reads from panel set at 0x326
4885 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4886 {
4887         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4888                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4889                 return false;
4890
4891         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4892                 (uint8_t *) backlight_millinits,
4893                 sizeof(uint32_t)) != DC_OK)
4894                 return false;
4895
4896         return true;
4897 }
4898
4899 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4900 {
4901         uint32_t default_backlight;
4902
4903         if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
4904                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4905                         default_backlight = 150000;
4906                 // if < 5 nits or > 5000, it might be wrong readback
4907                 if (default_backlight < 5000 || default_backlight > 5000000)
4908                         default_backlight = 150000; //
4909
4910                 return dc_link_set_backlight_level_nits(link, true,
4911                                 default_backlight, 0);
4912         }
4913         return false;
4914 }
4915
4916 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4917 {
4918         struct dc_link_settings link_setting;
4919         uint8_t link_bw_set;
4920         uint8_t link_rate_set;
4921         uint32_t req_bw;
4922         union lane_count_set lane_count_set = { {0} };
4923
4924         ASSERT(link || crtc_timing); // invalid input
4925
4926         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4927                         !link->dc->debug.optimize_edp_link_rate)
4928                 return false;
4929
4930
4931         // Read DPCD 00100h to find if standard link rates are set
4932         core_link_read_dpcd(link, DP_LINK_BW_SET,
4933                                 &link_bw_set, sizeof(link_bw_set));
4934
4935         if (link_bw_set) {
4936                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4937                 return true;
4938         }
4939
4940         // Read DPCD 00115h to find the edp link rate set used
4941         core_link_read_dpcd(link, DP_LINK_RATE_SET,
4942                             &link_rate_set, sizeof(link_rate_set));
4943
4944         // Read DPCD 00101h to find out the number of lanes currently set
4945         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4946                                 &lane_count_set.raw, sizeof(lane_count_set));
4947
4948         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4949
4950         decide_edp_link_settings(link, &link_setting, req_bw);
4951
4952         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4953                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4954                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4955                 return true;
4956         }
4957
4958         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4959         return false;
4960 }
4961
4962 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4963 {
4964         if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4965                         (link_settings->link_rate <= LINK_RATE_HIGH3))
4966                 return DP_8b_10b_ENCODING;
4967         return DP_UNKNOWN_ENCODING;
4968 }
4969