1 /* Copyright 2015 Advanced Micro Devices, Inc. */
2 #include "dm_services.h"
4 #include "dc_link_dp.h"
5 #include "dm_helpers.h"
10 #include "inc/core_types.h"
11 #include "link_hwss.h"
12 #include "dc_link_ddc.h"
13 #include "core_status.h"
14 #include "dpcd_defs.h"
15 #include "dc_dmub_srv.h"
16 #include "dce/dmub_hw_lock_mgr.h"
19 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
21 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
25 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
27 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
29 /* maximum pre emphasis level allowed for each voltage swing level*/
30 static const enum dc_pre_emphasis
31 voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
34 PRE_EMPHASIS_DISABLED };
37 POST_LT_ADJ_REQ_LIMIT = 6,
38 POST_LT_ADJ_REQ_TIMEOUT = 200
42 LINK_TRAINING_MAX_RETRY_COUNT = 5,
43 /* to avoid infinite loop where-in the receiver
44 * switches between different VS
46 LINK_TRAINING_MAX_CR_RETRY = 100
49 static bool decide_fallback_link_setting(
50 struct dc_link_settings initial_link_settings,
51 struct dc_link_settings *current_link_setting,
52 enum link_training_result training_result);
53 static struct dc_link_settings get_common_supported_link_settings(
54 struct dc_link_settings link_setting_a,
55 struct dc_link_settings link_setting_b);
57 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
58 const struct dc_link_settings *link_settings)
60 union training_aux_rd_interval training_rd_interval;
61 uint32_t wait_in_micro_secs = 100;
63 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
66 DP_TRAINING_AUX_RD_INTERVAL,
67 (uint8_t *)&training_rd_interval,
68 sizeof(training_rd_interval));
69 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
70 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
71 return wait_in_micro_secs;
74 static uint32_t get_eq_training_aux_rd_interval(
76 const struct dc_link_settings *link_settings)
78 union training_aux_rd_interval training_rd_interval;
79 uint32_t wait_in_micro_secs = 400;
81 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
82 /* overwrite the delay if rev > 1.1*/
83 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
84 /* DP 1.2 or later - retrieve delay through
85 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
88 DP_TRAINING_AUX_RD_INTERVAL,
89 (uint8_t *)&training_rd_interval,
90 sizeof(training_rd_interval));
92 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
93 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
96 return wait_in_micro_secs;
99 static void wait_for_training_aux_rd_interval(
100 struct dc_link *link,
101 uint32_t wait_in_micro_secs)
103 udelay(wait_in_micro_secs);
105 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
110 static void dpcd_set_training_pattern(
111 struct dc_link *link,
112 union dpcd_training_pattern dpcd_pattern)
114 core_link_write_dpcd(
116 DP_TRAINING_PATTERN_SET,
120 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
122 DP_TRAINING_PATTERN_SET,
123 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
126 static enum dc_dp_training_pattern decide_cr_training_pattern(
127 const struct dc_link_settings *link_settings)
129 enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
134 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
135 const struct dc_link_settings *link_settings)
137 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
138 struct encoder_feature_support *features = &link->link_enc->features;
139 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
141 if (features->flags.bits.IS_TPS3_CAPABLE)
142 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
144 if (features->flags.bits.IS_TPS4_CAPABLE)
145 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
147 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
148 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
149 return DP_TRAINING_PATTERN_SEQUENCE_4;
151 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
152 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
153 return DP_TRAINING_PATTERN_SEQUENCE_3;
155 return DP_TRAINING_PATTERN_SEQUENCE_2;
158 static void dpcd_set_link_settings(
159 struct dc_link *link,
160 const struct link_training_settings *lt_settings)
164 union down_spread_ctrl downspread = { {0} };
165 union lane_count_set lane_count_set = { {0} };
167 downspread.raw = (uint8_t)
168 (lt_settings->link_settings.link_spread);
170 lane_count_set.bits.LANE_COUNT_SET =
171 lt_settings->link_settings.lane_count;
173 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
174 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
177 if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
178 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
179 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
182 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
183 &downspread.raw, sizeof(downspread));
185 core_link_write_dpcd(link, DP_LANE_COUNT_SET,
186 &lane_count_set.raw, 1);
188 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
189 lt_settings->link_settings.use_link_rate_set == true) {
191 /* WA for some MUX chips that will power down with eDP and lose supported
192 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
193 * MUX chip gets link rate set back before link training.
195 if (link->connector_signal == SIGNAL_TYPE_EDP) {
196 uint8_t supported_link_rates[16];
198 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
199 supported_link_rates, sizeof(supported_link_rates));
201 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
202 core_link_write_dpcd(link, DP_LINK_RATE_SET,
203 <_settings->link_settings.link_rate_set, 1);
205 rate = (uint8_t) (lt_settings->link_settings.link_rate);
206 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
210 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
213 lt_settings->link_settings.link_rate,
215 lt_settings->link_settings.lane_count,
216 lt_settings->enhanced_framing,
218 lt_settings->link_settings.link_spread);
220 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
223 lt_settings->link_settings.link_rate_set,
225 lt_settings->link_settings.lane_count,
226 lt_settings->enhanced_framing,
228 lt_settings->link_settings.link_spread);
232 static enum dpcd_training_patterns
233 dc_dp_training_pattern_to_dpcd_training_pattern(
234 struct dc_link *link,
235 enum dc_dp_training_pattern pattern)
237 enum dpcd_training_patterns dpcd_tr_pattern =
238 DPCD_TRAINING_PATTERN_VIDEOIDLE;
241 case DP_TRAINING_PATTERN_SEQUENCE_1:
242 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
244 case DP_TRAINING_PATTERN_SEQUENCE_2:
245 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
247 case DP_TRAINING_PATTERN_SEQUENCE_3:
248 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
250 case DP_TRAINING_PATTERN_SEQUENCE_4:
251 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
255 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
260 return dpcd_tr_pattern;
263 static uint8_t dc_dp_initialize_scrambling_data_symbols(
264 struct dc_link *link,
265 enum dc_dp_training_pattern pattern)
267 uint8_t disable_scrabled_data_symbols = 0;
270 case DP_TRAINING_PATTERN_SEQUENCE_1:
271 case DP_TRAINING_PATTERN_SEQUENCE_2:
272 case DP_TRAINING_PATTERN_SEQUENCE_3:
273 disable_scrabled_data_symbols = 1;
275 case DP_TRAINING_PATTERN_SEQUENCE_4:
276 disable_scrabled_data_symbols = 0;
280 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
284 return disable_scrabled_data_symbols;
287 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
289 return (link->lttpr_non_transparent_mode && offset != 0);
292 static void dpcd_set_lt_pattern_and_lane_settings(
293 struct dc_link *link,
294 const struct link_training_settings *lt_settings,
295 enum dc_dp_training_pattern pattern,
298 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
300 uint32_t dpcd_base_lt_offset;
302 uint8_t dpcd_lt_buffer[5] = {0};
303 union dpcd_training_pattern dpcd_pattern = { {0} };
305 uint32_t size_in_bytes;
306 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
307 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
309 if (is_repeater(link, offset))
310 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
311 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
313 /*****************************************************************
314 * DpcdAddress_TrainingPatternSet
315 *****************************************************************/
316 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
317 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
319 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
320 dc_dp_initialize_scrambling_data_symbols(link, pattern);
322 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
325 if (is_repeater(link, offset)) {
326 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
330 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
332 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
335 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
337 /*****************************************************************
338 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
339 *****************************************************************/
340 for (lane = 0; lane <
341 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
343 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
344 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
345 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
346 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
348 dpcd_lane[lane].bits.MAX_SWING_REACHED =
349 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
350 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
351 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
352 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
353 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
356 /* concatenate everything into one buffer*/
358 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
362 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
366 if (is_repeater(link, offset)) {
367 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
368 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
372 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
373 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
374 dpcd_lane[0].bits.MAX_SWING_REACHED,
375 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
377 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
380 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
381 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
382 dpcd_lane[0].bits.MAX_SWING_REACHED,
383 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
385 if (edp_workaround) {
386 /* for eDP write in 2 parts because the 5-byte burst is
387 * causing issues on some eDP panels (EPR#366724)
389 core_link_write_dpcd(
391 DP_TRAINING_PATTERN_SET,
393 sizeof(dpcd_pattern.raw));
395 core_link_write_dpcd(
397 DP_TRAINING_LANE0_SET,
398 (uint8_t *)(dpcd_lane),
402 /* write it all in (1 + number-of-lanes)-byte burst*/
403 core_link_write_dpcd(
407 size_in_bytes + sizeof(dpcd_pattern.raw));
409 link->cur_lane_setting = lt_settings->lane_settings[0];
412 static bool is_cr_done(enum dc_lane_count ln_count,
413 union lane_status *dpcd_lane_status)
416 /*LANEx_CR_DONE bits All 1's?*/
417 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
418 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
424 static bool is_ch_eq_done(enum dc_lane_count ln_count,
425 union lane_status *dpcd_lane_status,
426 union lane_align_status_updated *lane_status_updated)
429 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
432 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
433 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
434 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
441 static void update_drive_settings(
442 struct link_training_settings *dest,
443 struct link_training_settings src)
446 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
447 if (dest->voltage_swing == NULL)
448 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
450 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
452 if (dest->pre_emphasis == NULL)
453 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
455 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
457 if (dest->post_cursor2 == NULL)
458 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
460 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
464 static uint8_t get_nibble_at_index(const uint8_t *buf,
468 nibble = buf[index / 2];
478 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
479 enum dc_voltage_swing voltage)
481 enum dc_pre_emphasis pre_emphasis;
482 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
484 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
485 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
491 static void find_max_drive_settings(
492 const struct link_training_settings *link_training_setting,
493 struct link_training_settings *max_lt_setting)
496 struct dc_lane_settings max_requested;
498 max_requested.VOLTAGE_SWING =
499 link_training_setting->
500 lane_settings[0].VOLTAGE_SWING;
501 max_requested.PRE_EMPHASIS =
502 link_training_setting->
503 lane_settings[0].PRE_EMPHASIS;
504 /*max_requested.postCursor2 =
505 * link_training_setting->laneSettings[0].postCursor2;*/
507 /* Determine what the maximum of the requested settings are*/
508 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
510 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
511 max_requested.VOLTAGE_SWING)
513 max_requested.VOLTAGE_SWING =
514 link_training_setting->
515 lane_settings[lane].VOLTAGE_SWING;
517 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
518 max_requested.PRE_EMPHASIS)
519 max_requested.PRE_EMPHASIS =
520 link_training_setting->
521 lane_settings[lane].PRE_EMPHASIS;
524 if (link_training_setting->laneSettings[lane].postCursor2 >
525 max_requested.postCursor2)
527 max_requested.postCursor2 =
528 link_training_setting->laneSettings[lane].postCursor2;
533 /* make sure the requested settings are
534 * not higher than maximum settings*/
535 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
536 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
538 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
539 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
541 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
542 max_requested.postCursor2 = PostCursor2_MaxLevel;
545 /* make sure the pre-emphasis matches the voltage swing*/
546 if (max_requested.PRE_EMPHASIS >
547 get_max_pre_emphasis_for_voltage_swing(
548 max_requested.VOLTAGE_SWING))
549 max_requested.PRE_EMPHASIS =
550 get_max_pre_emphasis_for_voltage_swing(
551 max_requested.VOLTAGE_SWING);
554 * Post Cursor2 levels are completely independent from
555 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
556 * can only be applied to each allowable combination of voltage
557 * swing and pre-emphasis levels */
558 /* if ( max_requested.postCursor2 >
559 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
560 * max_requested.postCursor2 =
561 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
564 max_lt_setting->link_settings.link_rate =
565 link_training_setting->link_settings.link_rate;
566 max_lt_setting->link_settings.lane_count =
567 link_training_setting->link_settings.lane_count;
568 max_lt_setting->link_settings.link_spread =
569 link_training_setting->link_settings.link_spread;
571 for (lane = 0; lane <
572 link_training_setting->link_settings.lane_count;
574 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
575 max_requested.VOLTAGE_SWING;
576 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
577 max_requested.PRE_EMPHASIS;
578 /*max_lt_setting->laneSettings[lane].postCursor2 =
579 * max_requested.postCursor2;
585 static void get_lane_status_and_drive_settings(
586 struct dc_link *link,
587 const struct link_training_settings *link_training_setting,
588 union lane_status *ln_status,
589 union lane_align_status_updated *ln_status_updated,
590 struct link_training_settings *req_settings,
593 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
594 uint8_t lane_adjust_offset = 4;
595 unsigned int lane01_adjust_address;
596 uint8_t dpcd_buf[6] = {0};
597 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
598 struct link_training_settings request_settings = { {0} };
601 memset(req_settings, '\0', sizeof(struct link_training_settings));
603 if (is_repeater(link, offset)) {
604 lane01_status_address =
605 DP_LANE0_1_STATUS_PHY_REPEATER1 +
606 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
607 lane_adjust_offset = 3;
612 lane01_status_address,
613 (uint8_t *)(dpcd_buf),
616 for (lane = 0; lane <
617 (uint32_t)(link_training_setting->link_settings.lane_count);
620 ln_status[lane].raw =
621 get_nibble_at_index(&dpcd_buf[0], lane);
622 dpcd_lane_adjust[lane].raw =
623 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
626 ln_status_updated->raw = dpcd_buf[2];
628 if (is_repeater(link, offset)) {
629 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
630 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
633 lane01_status_address, dpcd_buf[0],
634 lane01_status_address + 1, dpcd_buf[1]);
636 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
638 lane01_status_address, dpcd_buf[0],
639 lane01_status_address + 1, dpcd_buf[1]);
641 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
643 if (is_repeater(link, offset))
644 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
645 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
647 if (is_repeater(link, offset)) {
648 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
649 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
652 lane01_adjust_address,
653 dpcd_buf[lane_adjust_offset],
654 lane01_adjust_address + 1,
655 dpcd_buf[lane_adjust_offset + 1]);
657 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
659 lane01_adjust_address,
660 dpcd_buf[lane_adjust_offset],
661 lane01_adjust_address + 1,
662 dpcd_buf[lane_adjust_offset + 1]);
665 /*copy to req_settings*/
666 request_settings.link_settings.lane_count =
667 link_training_setting->link_settings.lane_count;
668 request_settings.link_settings.link_rate =
669 link_training_setting->link_settings.link_rate;
670 request_settings.link_settings.link_spread =
671 link_training_setting->link_settings.link_spread;
673 for (lane = 0; lane <
674 (uint32_t)(link_training_setting->link_settings.lane_count);
677 request_settings.lane_settings[lane].VOLTAGE_SWING =
678 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
680 request_settings.lane_settings[lane].PRE_EMPHASIS =
681 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
685 /*Note: for postcursor2, read adjusted
686 * postcursor2 settings from*/
687 /*DpcdAddress_AdjustRequestPostCursor2 =
688 *0x020C (not implemented yet)*/
690 /* we find the maximum of the requested settings across all lanes*/
691 /* and set this maximum for all lanes*/
692 find_max_drive_settings(&request_settings, req_settings);
694 /* if post cursor 2 is needed in the future,
695 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
700 static void dpcd_set_lane_settings(
701 struct dc_link *link,
702 const struct link_training_settings *link_training_setting,
705 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
707 unsigned int lane0_set_address;
709 lane0_set_address = DP_TRAINING_LANE0_SET;
711 if (is_repeater(link, offset))
712 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
713 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
715 for (lane = 0; lane <
716 (uint32_t)(link_training_setting->
717 link_settings.lane_count);
719 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
720 (uint8_t)(link_training_setting->
721 lane_settings[lane].VOLTAGE_SWING);
722 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
723 (uint8_t)(link_training_setting->
724 lane_settings[lane].PRE_EMPHASIS);
725 dpcd_lane[lane].bits.MAX_SWING_REACHED =
726 (link_training_setting->
727 lane_settings[lane].VOLTAGE_SWING ==
728 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
729 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
730 (link_training_setting->
731 lane_settings[lane].PRE_EMPHASIS ==
732 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
735 core_link_write_dpcd(link,
737 (uint8_t *)(dpcd_lane),
738 link_training_setting->link_settings.lane_count);
741 if (LTSettings.link.rate == LinkRate_High2)
743 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
744 for ( uint32_t lane = 0;
745 lane < lane_count_DPMax; lane++)
747 dpcd_lane2[lane].bits.post_cursor2_set =
748 static_cast<unsigned char>(
749 LTSettings.laneSettings[lane].postCursor2);
750 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
752 m_pDpcdAccessSrv->WriteDpcdData(
753 DpcdAddress_Lane0Set2,
754 reinterpret_cast<unsigned char*>(dpcd_lane2),
755 LTSettings.link.lanes);
759 if (is_repeater(link, offset)) {
760 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
761 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
765 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
766 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
767 dpcd_lane[0].bits.MAX_SWING_REACHED,
768 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
771 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
774 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
775 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
776 dpcd_lane[0].bits.MAX_SWING_REACHED,
777 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
779 link->cur_lane_setting = link_training_setting->lane_settings[0];
783 static bool is_max_vs_reached(
784 const struct link_training_settings *lt_settings)
787 for (lane = 0; lane <
788 (uint32_t)(lt_settings->link_settings.lane_count);
790 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
791 == VOLTAGE_SWING_MAX_LEVEL)
798 static bool perform_post_lt_adj_req_sequence(
799 struct dc_link *link,
800 struct link_training_settings *lt_settings)
802 enum dc_lane_count lane_count =
803 lt_settings->link_settings.lane_count;
805 uint32_t adj_req_count;
806 uint32_t adj_req_timer;
807 bool req_drv_setting_changed;
810 req_drv_setting_changed = false;
811 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
814 req_drv_setting_changed = false;
816 for (adj_req_timer = 0;
817 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
820 struct link_training_settings req_settings;
821 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
822 union lane_align_status_updated
823 dpcd_lane_status_updated;
825 get_lane_status_and_drive_settings(
829 &dpcd_lane_status_updated,
833 if (dpcd_lane_status_updated.bits.
834 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
837 if (!is_cr_done(lane_count, dpcd_lane_status))
843 &dpcd_lane_status_updated))
846 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
849 lane_settings[lane].VOLTAGE_SWING !=
850 req_settings.lane_settings[lane].
852 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
853 req_settings.lane_settings[lane].PRE_EMPHASIS) {
855 req_drv_setting_changed = true;
860 if (req_drv_setting_changed) {
861 update_drive_settings(
862 lt_settings, req_settings);
864 dc_link_dp_set_drive_settings(link,
872 if (!req_drv_setting_changed) {
873 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
880 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
888 /* Only used for channel equalization */
889 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
891 unsigned int aux_rd_interval_us = 400;
893 switch (dpcd_aux_read_interval) {
895 aux_rd_interval_us = 400;
898 aux_rd_interval_us = 4000;
901 aux_rd_interval_us = 8000;
904 aux_rd_interval_us = 16000;
910 return aux_rd_interval_us;
913 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
914 union lane_status *dpcd_lane_status)
916 enum link_training_result result = LINK_TRAINING_SUCCESS;
918 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
919 result = LINK_TRAINING_CR_FAIL_LANE0;
920 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
921 result = LINK_TRAINING_CR_FAIL_LANE1;
922 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
923 result = LINK_TRAINING_CR_FAIL_LANE23;
924 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
925 result = LINK_TRAINING_CR_FAIL_LANE23;
929 static enum link_training_result perform_channel_equalization_sequence(
930 struct dc_link *link,
931 struct link_training_settings *lt_settings,
934 struct link_training_settings req_settings;
935 enum dc_dp_training_pattern tr_pattern;
936 uint32_t retries_ch_eq;
937 uint32_t wait_time_microsec;
938 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
939 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
940 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
942 /* Note: also check that TPS4 is a supported feature*/
944 tr_pattern = lt_settings->pattern_for_eq;
946 if (is_repeater(link, offset))
947 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
949 dp_set_hw_training_pattern(link, tr_pattern, offset);
951 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
954 dp_set_hw_lane_settings(link, lt_settings, offset);
958 /* EPR #361076 - write as a 5-byte burst,
959 * but only for the 1-st iteration
962 dpcd_set_lt_pattern_and_lane_settings(
967 dpcd_set_lane_settings(link, lt_settings, offset);
969 /* 3. wait for receiver to lock-on*/
970 wait_time_microsec = lt_settings->eq_pattern_time;
972 if (is_repeater(link, offset))
974 translate_training_aux_read_interval(
975 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
977 wait_for_training_aux_rd_interval(
981 /* 4. Read lane status and requested
982 * drive settings as set by the sink*/
984 get_lane_status_and_drive_settings(
988 &dpcd_lane_status_updated,
992 /* 5. check CR done*/
993 if (!is_cr_done(lane_count, dpcd_lane_status))
994 return LINK_TRAINING_EQ_FAIL_CR;
996 /* 6. check CHEQ done*/
997 if (is_ch_eq_done(lane_count,
999 &dpcd_lane_status_updated))
1000 return LINK_TRAINING_SUCCESS;
1002 /* 7. update VS/PE/PC2 in lt_settings*/
1003 update_drive_settings(lt_settings, req_settings);
1006 return LINK_TRAINING_EQ_FAIL_EQ;
1009 #define TRAINING_AUX_RD_INTERVAL 100 //us
1011 static void start_clock_recovery_pattern_early(struct dc_link *link,
1012 struct link_training_settings *lt_settings,
1015 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1017 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1018 dp_set_hw_lane_settings(link, lt_settings, offset);
1022 static enum link_training_result perform_clock_recovery_sequence(
1023 struct dc_link *link,
1024 struct link_training_settings *lt_settings,
1027 uint32_t retries_cr;
1028 uint32_t retry_count;
1029 uint32_t wait_time_microsec;
1030 struct link_training_settings req_settings;
1031 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1032 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1033 union lane_align_status_updated dpcd_lane_status_updated;
1038 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1039 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1041 /* najeeb - The synaptics MST hub can put the LT in
1042 * infinite loop by switching the VS
1044 /* between level 0 and level 1 continuously, here
1045 * we try for CR lock for LinkTrainingMaxCRRetry count*/
1046 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1047 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1049 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1050 memset(&dpcd_lane_status_updated, '\0',
1051 sizeof(dpcd_lane_status_updated));
1053 /* 1. call HWSS to set lane settings*/
1054 dp_set_hw_lane_settings(
1059 /* 2. update DPCD of the receiver*/
1061 /* EPR #361076 - write as a 5-byte burst,
1062 * but only for the 1-st iteration.*/
1063 dpcd_set_lt_pattern_and_lane_settings(
1066 lt_settings->pattern_for_cr,
1069 dpcd_set_lane_settings(
1074 /* 3. wait receiver to lock-on*/
1075 wait_time_microsec = lt_settings->cr_pattern_time;
1077 if (link->lttpr_non_transparent_mode)
1078 wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1080 wait_for_training_aux_rd_interval(
1082 wait_time_microsec);
1084 /* 4. Read lane status and requested drive
1085 * settings as set by the sink
1087 get_lane_status_and_drive_settings(
1091 &dpcd_lane_status_updated,
1095 /* 5. check CR done*/
1096 if (is_cr_done(lane_count, dpcd_lane_status))
1097 return LINK_TRAINING_SUCCESS;
1099 /* 6. max VS reached*/
1100 if (is_max_vs_reached(lt_settings))
1103 /* 7. same voltage*/
1104 /* Note: VS same for all lanes,
1105 * so comparing first lane is sufficient*/
1106 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
1107 req_settings.lane_settings[0].VOLTAGE_SWING)
1112 /* 8. update VS/PE/PC2 in lt_settings*/
1113 update_drive_settings(lt_settings, req_settings);
1118 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1120 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1122 LINK_TRAINING_MAX_CR_RETRY);
1126 return get_cr_failure(lane_count, dpcd_lane_status);
1129 static inline enum link_training_result perform_link_training_int(
1130 struct dc_link *link,
1131 struct link_training_settings *lt_settings,
1132 enum link_training_result status)
1134 union lane_count_set lane_count_set = { {0} };
1135 union dpcd_training_pattern dpcd_pattern = { {0} };
1137 /* 3. set training not in progress*/
1138 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1139 dpcd_set_training_pattern(link, dpcd_pattern);
1141 /* 4. mainlink output idle pattern*/
1142 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1145 * 5. post training adjust if required
1146 * If the upstream DPTX and downstream DPRX both support TPS4,
1147 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1149 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1150 lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)
1153 if (status == LINK_TRAINING_SUCCESS &&
1154 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1155 status = LINK_TRAINING_LQA_FAIL;
1157 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1158 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1159 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1161 core_link_write_dpcd(
1164 &lane_count_set.raw,
1165 sizeof(lane_count_set));
1170 static enum link_training_result check_link_loss_status(
1171 struct dc_link *link,
1172 const struct link_training_settings *link_training_setting)
1174 enum link_training_result status = LINK_TRAINING_SUCCESS;
1175 union lane_status lane_status;
1176 uint8_t dpcd_buf[6] = {0};
1179 core_link_read_dpcd(
1182 (uint8_t *)(dpcd_buf),
1185 /*parse lane status*/
1186 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1188 * check lanes status
1190 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1192 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1193 !lane_status.bits.CR_DONE_0 ||
1194 !lane_status.bits.SYMBOL_LOCKED_0) {
1195 /* if one of the channel equalization, clock
1196 * recovery or symbol lock is dropped
1197 * consider it as (link has been
1198 * dropped) dp sink status has changed
1200 status = LINK_TRAINING_LINK_LOSS;
1208 static void initialize_training_settings(
1209 struct dc_link *link,
1210 const struct dc_link_settings *link_setting,
1211 const struct dc_link_training_overrides *overrides,
1212 struct link_training_settings *lt_settings)
1216 memset(lt_settings, '\0', sizeof(struct link_training_settings));
1218 /* Initialize link settings */
1219 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1220 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1222 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1223 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1225 lt_settings->link_settings.link_rate = link_setting->link_rate;
1227 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1228 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1230 lt_settings->link_settings.lane_count = link_setting->lane_count;
1232 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1234 /* TODO hard coded to SS for now
1235 * lt_settings.link_settings.link_spread =
1236 * dal_display_path_is_ss_supported(
1237 * path_mode->display_path) ?
1238 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1239 * LINK_SPREAD_DISABLED;
1241 /* Initialize link spread */
1242 if (link->dp_ss_off)
1243 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1244 else if (overrides->downspread != NULL)
1245 lt_settings->link_settings.link_spread
1246 = *overrides->downspread
1247 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1248 : LINK_SPREAD_DISABLED;
1250 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1252 /* Initialize lane settings overrides */
1253 if (overrides->voltage_swing != NULL)
1254 lt_settings->voltage_swing = overrides->voltage_swing;
1256 if (overrides->pre_emphasis != NULL)
1257 lt_settings->pre_emphasis = overrides->pre_emphasis;
1259 if (overrides->post_cursor2 != NULL)
1260 lt_settings->post_cursor2 = overrides->post_cursor2;
1262 /* Initialize lane settings (VS/PE/PC2) */
1263 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1264 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1265 lt_settings->voltage_swing != NULL ?
1266 *lt_settings->voltage_swing :
1267 VOLTAGE_SWING_LEVEL0;
1268 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1269 lt_settings->pre_emphasis != NULL ?
1270 *lt_settings->pre_emphasis
1271 : PRE_EMPHASIS_DISABLED;
1272 lt_settings->lane_settings[lane].POST_CURSOR2 =
1273 lt_settings->post_cursor2 != NULL ?
1274 *lt_settings->post_cursor2
1275 : POST_CURSOR2_DISABLED;
1278 /* Initialize training timings */
1279 if (overrides->cr_pattern_time != NULL)
1280 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1282 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1284 if (overrides->eq_pattern_time != NULL)
1285 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1287 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1289 if (overrides->pattern_for_cr != NULL)
1290 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1292 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1293 if (overrides->pattern_for_eq != NULL)
1294 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1296 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1298 if (overrides->enhanced_framing != NULL)
1299 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1301 lt_settings->enhanced_framing = 1;
1304 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
1306 switch (lttpr_repeater_count) {
1307 case 0x80: // 1 lttpr repeater
1309 case 0x40: // 2 lttpr repeaters
1311 case 0x20: // 3 lttpr repeaters
1313 case 0x10: // 4 lttpr repeaters
1315 case 0x08: // 5 lttpr repeaters
1317 case 0x04: // 6 lttpr repeaters
1319 case 0x02: // 7 lttpr repeaters
1321 case 0x01: // 8 lttpr repeaters
1326 return 0; // invalid value
1329 static void configure_lttpr_mode(struct dc_link *link)
1331 /* aux timeout is already set to extended */
1332 /* RESET/SET lttpr mode to enable non transparent mode */
1333 uint8_t repeater_cnt;
1334 uint32_t aux_interval_address;
1335 uint8_t repeater_id;
1336 enum dc_status result = DC_ERROR_UNEXPECTED;
1337 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1339 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1340 result = core_link_write_dpcd(link,
1341 DP_PHY_REPEATER_MODE,
1342 (uint8_t *)&repeater_mode,
1343 sizeof(repeater_mode));
1345 if (result == DC_OK) {
1346 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1349 if (link->lttpr_non_transparent_mode) {
1351 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1353 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1354 result = core_link_write_dpcd(link,
1355 DP_PHY_REPEATER_MODE,
1356 (uint8_t *)&repeater_mode,
1357 sizeof(repeater_mode));
1359 if (result == DC_OK) {
1360 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1363 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1364 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1365 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1366 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1367 core_link_read_dpcd(
1369 aux_interval_address,
1370 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1371 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1372 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1377 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1379 union dpcd_training_pattern dpcd_pattern = { {0} };
1381 const uint32_t dpcd_base_lt_offset =
1382 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1383 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1384 /* Set training not in progress*/
1385 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1387 core_link_write_dpcd(
1389 dpcd_base_lt_offset,
1393 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1396 dpcd_base_lt_offset,
1397 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1400 static void print_status_message(
1401 struct dc_link *link,
1402 const struct link_training_settings *lt_settings,
1403 enum link_training_result status)
1405 char *link_rate = "Unknown";
1406 char *lt_result = "Unknown";
1407 char *lt_spread = "Disabled";
1409 switch (lt_settings->link_settings.link_rate) {
1413 case LINK_RATE_RATE_2:
1416 case LINK_RATE_RATE_3:
1419 case LINK_RATE_HIGH:
1422 case LINK_RATE_RBR2:
1425 case LINK_RATE_RATE_6:
1428 case LINK_RATE_HIGH2:
1431 case LINK_RATE_HIGH3:
1439 case LINK_TRAINING_SUCCESS:
1442 case LINK_TRAINING_CR_FAIL_LANE0:
1443 lt_result = "CR failed lane0";
1445 case LINK_TRAINING_CR_FAIL_LANE1:
1446 lt_result = "CR failed lane1";
1448 case LINK_TRAINING_CR_FAIL_LANE23:
1449 lt_result = "CR failed lane23";
1451 case LINK_TRAINING_EQ_FAIL_CR:
1452 lt_result = "CR failed in EQ";
1454 case LINK_TRAINING_EQ_FAIL_EQ:
1455 lt_result = "EQ failed";
1457 case LINK_TRAINING_LQA_FAIL:
1458 lt_result = "LQA failed";
1460 case LINK_TRAINING_LINK_LOSS:
1461 lt_result = "Link loss";
1467 switch (lt_settings->link_settings.link_spread) {
1468 case LINK_SPREAD_DISABLED:
1469 lt_spread = "Disabled";
1471 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1472 lt_spread = "0.5% 30KHz";
1474 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1475 lt_spread = "0.5% 33KHz";
1481 /* Connectivity log: link training */
1482 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1484 lt_settings->link_settings.lane_count,
1486 lt_settings->lane_settings[0].VOLTAGE_SWING,
1487 lt_settings->lane_settings[0].PRE_EMPHASIS,
1491 void dc_link_dp_set_drive_settings(
1492 struct dc_link *link,
1493 struct link_training_settings *lt_settings)
1495 /* program ASIC PHY settings*/
1496 dp_set_hw_lane_settings(link, lt_settings, DPRX);
1498 /* Notify DP sink the PHY settings from source */
1499 dpcd_set_lane_settings(link, lt_settings, DPRX);
1502 bool dc_link_dp_perform_link_training_skip_aux(
1503 struct dc_link *link,
1504 const struct dc_link_settings *link_setting)
1506 struct link_training_settings lt_settings;
1508 initialize_training_settings(
1511 &link->preferred_training_settings,
1514 /* 1. Perform_clock_recovery_sequence. */
1516 /* transmit training pattern for clock recovery */
1517 dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1519 /* call HWSS to set lane settings*/
1520 dp_set_hw_lane_settings(link, <_settings, DPRX);
1522 /* wait receiver to lock-on*/
1523 wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1525 /* 2. Perform_channel_equalization_sequence. */
1527 /* transmit training pattern for channel equalization. */
1528 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1530 /* call HWSS to set lane settings*/
1531 dp_set_hw_lane_settings(link, <_settings, DPRX);
1533 /* wait receiver to lock-on. */
1534 wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1536 /* 3. Perform_link_training_int. */
1538 /* Mainlink output idle pattern. */
1539 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1541 print_status_message(link, <_settings, LINK_TRAINING_SUCCESS);
1546 enum link_training_result dc_link_dp_perform_link_training(
1547 struct dc_link *link,
1548 const struct dc_link_settings *link_setting,
1549 bool skip_video_pattern)
1551 enum link_training_result status = LINK_TRAINING_SUCCESS;
1552 struct link_training_settings lt_settings;
1555 uint8_t repeater_cnt;
1556 uint8_t repeater_id;
1558 initialize_training_settings(
1561 &link->preferred_training_settings,
1564 /* Configure lttpr mode */
1565 if (link->lttpr_non_transparent_mode)
1566 configure_lttpr_mode(link);
1568 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1569 start_clock_recovery_pattern_early(link, <_settings, DPRX);
1571 /* 1. set link rate, lane count and spread. */
1572 dpcd_set_link_settings(link, <_settings);
1574 if (link->preferred_training_settings.fec_enable != NULL)
1575 fec_enable = *link->preferred_training_settings.fec_enable;
1579 dp_set_fec_ready(link, fec_enable);
1581 if (link->lttpr_non_transparent_mode) {
1583 /* 2. perform link training (set link training done
1584 * to false is done as well)
1586 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1588 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1590 status = perform_clock_recovery_sequence(link, <_settings, repeater_id);
1592 if (status != LINK_TRAINING_SUCCESS)
1595 status = perform_channel_equalization_sequence(link,
1599 if (status != LINK_TRAINING_SUCCESS)
1602 repeater_training_done(link, repeater_id);
1606 if (status == LINK_TRAINING_SUCCESS) {
1607 status = perform_clock_recovery_sequence(link, <_settings, DPRX);
1608 if (status == LINK_TRAINING_SUCCESS) {
1609 status = perform_channel_equalization_sequence(link,
1615 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1616 status = perform_link_training_int(link,
1621 /* delay 5ms after Main Link output idle pattern and then check
1624 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1626 status = check_link_loss_status(link, <_settings);
1629 /* 6. print status message*/
1630 print_status_message(link, <_settings, status);
1632 if (status != LINK_TRAINING_SUCCESS)
1633 link->ctx->dc->debug_data.ltFailCount++;
1638 bool perform_link_training_with_retries(
1639 const struct dc_link_settings *link_setting,
1640 bool skip_video_pattern,
1642 struct pipe_ctx *pipe_ctx,
1643 enum signal_type signal)
1646 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1647 struct dc_stream_state *stream = pipe_ctx->stream;
1648 struct dc_link *link = stream->link;
1649 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1651 /* We need to do this before the link training to ensure the idle pattern in SST
1652 * mode will be sent right after the link training
1654 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1655 pipe_ctx->stream_res.stream_enc->id, true);
1657 for (j = 0; j < attempts; ++j) {
1659 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1660 __func__, (unsigned int)j + 1, attempts);
1665 pipe_ctx->clock_source->id,
1668 if (stream->sink_patches.dppowerup_delay > 0) {
1669 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1671 msleep(delay_dp_power_up_in_ms);
1674 dp_set_panel_mode(link, panel_mode);
1676 if (link->aux_access_disabled) {
1677 dc_link_dp_perform_link_training_skip_aux(link, link_setting);
1679 } else if (dc_link_dp_perform_link_training(
1682 skip_video_pattern) == LINK_TRAINING_SUCCESS)
1685 /* latest link training still fail, skip delay and keep PHY on
1687 if (j == (attempts - 1))
1690 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1691 __func__, (unsigned int)j + 1, attempts);
1693 dp_disable_link_phy(link, signal);
1695 msleep(delay_between_attempts);
1697 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1703 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1705 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1706 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1708 if (dp_cs != NULL) {
1709 dp_cs_id = dp_cs->id;
1712 * dp clock source is not initialized for some reason.
1713 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1721 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1723 if (mst_enable == false &&
1724 link->type == dc_connection_mst_branch) {
1725 /* Disable MST on link. Use only local sink. */
1726 dp_disable_link_phy_mst(link, link->connector_signal);
1728 link->type = dc_connection_single;
1729 link->local_sink = link->remote_sinks[0];
1730 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1731 } else if (mst_enable == true &&
1732 link->type == dc_connection_single &&
1733 link->remote_sinks[0] != NULL) {
1734 /* Re-enable MST on link. */
1735 dp_disable_link_phy(link, link->connector_signal);
1736 dp_enable_mst_on_sink(link, true);
1738 link->type = dc_connection_mst_branch;
1739 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1743 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1745 /* Begin Sync LT. During this time,
1746 * DPCD:600h must not be powered down.
1748 link->sync_lt_in_progress = true;
1750 /*Clear any existing preferred settings.*/
1751 memset(&link->preferred_training_settings, 0,
1752 sizeof(struct dc_link_training_overrides));
1753 memset(&link->preferred_link_setting, 0,
1754 sizeof(struct dc_link_settings));
1759 enum link_training_result dc_link_dp_sync_lt_attempt(
1760 struct dc_link *link,
1761 struct dc_link_settings *link_settings,
1762 struct dc_link_training_overrides *lt_overrides)
1764 struct link_training_settings lt_settings;
1765 enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1766 enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1767 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1768 bool fec_enable = false;
1770 initialize_training_settings(
1776 /* Setup MST Mode */
1777 if (lt_overrides->mst_enable)
1778 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1781 dp_disable_link_phy(link, link->connector_signal);
1784 dp_cs_id = get_clock_source_id(link);
1785 dp_enable_link_phy(link, link->connector_signal,
1786 dp_cs_id, link_settings);
1788 /* Set FEC enable */
1789 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1790 dp_set_fec_ready(link, fec_enable);
1792 if (lt_overrides->alternate_scrambler_reset) {
1793 if (*lt_overrides->alternate_scrambler_reset)
1794 panel_mode = DP_PANEL_MODE_EDP;
1796 panel_mode = DP_PANEL_MODE_DEFAULT;
1798 panel_mode = dp_get_panel_mode(link);
1800 dp_set_panel_mode(link, panel_mode);
1802 /* Attempt to train with given link training settings */
1803 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1804 start_clock_recovery_pattern_early(link, <_settings, DPRX);
1806 /* Set link rate, lane count and spread. */
1807 dpcd_set_link_settings(link, <_settings);
1809 /* 2. perform link training (set link training done
1810 * to false is done as well)
1812 lt_status = perform_clock_recovery_sequence(link, <_settings, DPRX);
1813 if (lt_status == LINK_TRAINING_SUCCESS) {
1814 lt_status = perform_channel_equalization_sequence(link,
1819 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1820 /* 4. print status message*/
1821 print_status_message(link, <_settings, lt_status);
1826 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1828 /* If input parameter is set, shut down phy.
1829 * Still shouldn't turn off dp_receiver (DPCD:600h)
1831 if (link_down == true) {
1832 dp_disable_link_phy(link, link->connector_signal);
1833 dp_set_fec_ready(link, false);
1836 link->sync_lt_in_progress = false;
1840 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1842 struct dc_link_settings max_link_cap = {0};
1844 /* get max link encoder capability */
1845 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1847 /* Lower link settings based on sink's link cap */
1848 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1849 max_link_cap.lane_count =
1850 link->reported_link_cap.lane_count;
1851 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1852 max_link_cap.link_rate =
1853 link->reported_link_cap.link_rate;
1854 if (link->reported_link_cap.link_spread <
1855 max_link_cap.link_spread)
1856 max_link_cap.link_spread =
1857 link->reported_link_cap.link_spread;
1859 * account for lttpr repeaters cap
1860 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1862 if (link->lttpr_non_transparent_mode) {
1863 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1864 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1866 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1867 max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
1869 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
1871 max_link_cap.lane_count,
1872 max_link_cap.link_rate);
1874 return max_link_cap;
1877 enum dc_status read_hpd_rx_irq_data(
1878 struct dc_link *link,
1879 union hpd_irq_data *irq_data)
1881 static enum dc_status retval;
1883 /* The HW reads 16 bytes from 200h on HPD,
1884 * but if we get an AUX_DEFER, the HW cannot retry
1885 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1886 * fail, so we now explicitly read 6 bytes which is
1887 * the req from the above mentioned test cases.
1889 * For DP 1.4 we need to read those from 2002h range.
1891 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1892 retval = core_link_read_dpcd(
1896 sizeof(union hpd_irq_data));
1898 /* Read 14 bytes in a single read and then copy only the required fields.
1899 * This is more efficient than doing it in two separate AUX reads. */
1901 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1903 retval = core_link_read_dpcd(
1909 if (retval != DC_OK)
1912 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1913 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1914 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1915 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1916 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1917 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1923 static bool hpd_rx_irq_check_link_loss_status(
1924 struct dc_link *link,
1925 union hpd_irq_data *hpd_irq_dpcd_data)
1927 uint8_t irq_reg_rx_power_state = 0;
1928 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1929 union lane_status lane_status;
1931 bool sink_status_changed;
1934 sink_status_changed = false;
1935 return_code = false;
1937 if (link->cur_link_settings.lane_count == 0)
1940 /*1. Check that Link Status changed, before re-training.*/
1942 /*parse lane status*/
1943 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1944 /* check status of lanes 0,1
1945 * changed DpcdAddress_Lane01Status (0x202)
1947 lane_status.raw = get_nibble_at_index(
1948 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1951 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1952 !lane_status.bits.CR_DONE_0 ||
1953 !lane_status.bits.SYMBOL_LOCKED_0) {
1954 /* if one of the channel equalization, clock
1955 * recovery or symbol lock is dropped
1956 * consider it as (link has been
1957 * dropped) dp sink status has changed
1959 sink_status_changed = true;
1964 /* Check interlane align.*/
1965 if (sink_status_changed ||
1966 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1968 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1972 /*2. Check that we can handle interrupt: Not in FS DOS,
1973 * Not in "Display Timeout" state, Link is trained.
1975 dpcd_result = core_link_read_dpcd(link,
1977 &irq_reg_rx_power_state,
1978 sizeof(irq_reg_rx_power_state));
1980 if (dpcd_result != DC_OK) {
1981 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1984 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1985 return_code = false;
1992 bool dp_verify_link_cap(
1993 struct dc_link *link,
1994 struct dc_link_settings *known_limit_link_setting,
1997 struct dc_link_settings max_link_cap = {0};
1998 struct dc_link_settings cur_link_setting = {0};
1999 struct dc_link_settings *cur = &cur_link_setting;
2000 struct dc_link_settings initial_link_settings = {0};
2002 bool skip_link_training;
2003 bool skip_video_pattern;
2004 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2005 enum link_training_result status;
2006 union hpd_irq_data irq_data;
2008 if (link->dc->debug.skip_detection_link_training) {
2009 link->verified_link_cap = *known_limit_link_setting;
2013 memset(&irq_data, 0, sizeof(irq_data));
2015 skip_link_training = false;
2017 max_link_cap = get_max_link_cap(link);
2019 /* Grant extended timeout request */
2020 if (link->lttpr_non_transparent_mode && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
2021 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2023 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2026 /* TODO implement override and monitor patch later */
2028 /* try to train the link from high to low to
2029 * find the physical link capability
2031 /* disable PHY done possible by BIOS, will be done by driver itself */
2032 dp_disable_link_phy(link, link->connector_signal);
2034 dp_cs_id = get_clock_source_id(link);
2036 /* link training starts with the maximum common settings
2037 * supported by both sink and ASIC.
2039 initial_link_settings = get_common_supported_link_settings(
2040 *known_limit_link_setting,
2042 cur_link_setting = initial_link_settings;
2044 /* Temporary Renoir-specific workaround for SWDEV-215184;
2045 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2046 * so add extra cycle of enabling and disabling the PHY before first link training.
2048 if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2049 link->dc->debug.usbc_combo_phy_reset_wa) {
2050 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2051 dp_disable_link_phy(link, link->connector_signal);
2055 skip_video_pattern = true;
2057 if (cur->link_rate == LINK_RATE_LOW)
2058 skip_video_pattern = false;
2062 link->connector_signal,
2067 if (skip_link_training)
2070 status = dc_link_dp_perform_link_training(
2073 skip_video_pattern);
2074 if (status == LINK_TRAINING_SUCCESS)
2081 link->verified_link_cap = *cur;
2083 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2084 if (hpd_rx_irq_check_link_loss_status(
2089 /* always disable the link before trying another
2090 * setting or before returning we'll enable it later
2091 * based on the actual mode we're driving
2093 dp_disable_link_phy(link, link->connector_signal);
2094 } while (!success && decide_fallback_link_setting(
2095 initial_link_settings, cur, status));
2097 /* Link Training failed for all Link Settings
2098 * (Lane Count is still unknown)
2101 /* If all LT fails for all settings,
2102 * set verified = failed safe (1 lane low)
2104 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2105 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2107 link->verified_link_cap.link_spread =
2108 LINK_SPREAD_DISABLED;
2115 bool dp_verify_link_cap_with_retries(
2116 struct dc_link *link,
2117 struct dc_link_settings *known_limit_link_setting,
2121 bool success = false;
2123 for (i = 0; i < attempts; i++) {
2125 enum dc_connection_type type = dc_connection_none;
2127 memset(&link->verified_link_cap, 0,
2128 sizeof(struct dc_link_settings));
2129 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2130 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2131 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2132 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2134 } else if (dp_verify_link_cap(link,
2135 &link->reported_link_cap,
2136 &fail_count) && fail_count == 0) {
2145 bool dp_verify_mst_link_cap(
2146 struct dc_link *link)
2148 struct dc_link_settings max_link_cap = {0};
2150 max_link_cap = get_max_link_cap(link);
2151 link->verified_link_cap = get_common_supported_link_settings(
2152 link->reported_link_cap,
2158 static struct dc_link_settings get_common_supported_link_settings(
2159 struct dc_link_settings link_setting_a,
2160 struct dc_link_settings link_setting_b)
2162 struct dc_link_settings link_settings = {0};
2164 link_settings.lane_count =
2165 (link_setting_a.lane_count <=
2166 link_setting_b.lane_count) ?
2167 link_setting_a.lane_count :
2168 link_setting_b.lane_count;
2169 link_settings.link_rate =
2170 (link_setting_a.link_rate <=
2171 link_setting_b.link_rate) ?
2172 link_setting_a.link_rate :
2173 link_setting_b.link_rate;
2174 link_settings.link_spread = LINK_SPREAD_DISABLED;
2176 /* in DP compliance test, DPR-120 may have
2177 * a random value in its MAX_LINK_BW dpcd field.
2178 * We map it to the maximum supported link rate that
2179 * is smaller than MAX_LINK_BW in this case.
2181 if (link_settings.link_rate > LINK_RATE_HIGH3) {
2182 link_settings.link_rate = LINK_RATE_HIGH3;
2183 } else if (link_settings.link_rate < LINK_RATE_HIGH3
2184 && link_settings.link_rate > LINK_RATE_HIGH2) {
2185 link_settings.link_rate = LINK_RATE_HIGH2;
2186 } else if (link_settings.link_rate < LINK_RATE_HIGH2
2187 && link_settings.link_rate > LINK_RATE_HIGH) {
2188 link_settings.link_rate = LINK_RATE_HIGH;
2189 } else if (link_settings.link_rate < LINK_RATE_HIGH
2190 && link_settings.link_rate > LINK_RATE_LOW) {
2191 link_settings.link_rate = LINK_RATE_LOW;
2192 } else if (link_settings.link_rate < LINK_RATE_LOW) {
2193 link_settings.link_rate = LINK_RATE_UNKNOWN;
2196 return link_settings;
2199 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2201 return lane_count <= LANE_COUNT_ONE;
2204 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2206 return link_rate <= LINK_RATE_LOW;
2209 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2211 switch (lane_count) {
2212 case LANE_COUNT_FOUR:
2213 return LANE_COUNT_TWO;
2214 case LANE_COUNT_TWO:
2215 return LANE_COUNT_ONE;
2216 case LANE_COUNT_ONE:
2217 return LANE_COUNT_UNKNOWN;
2219 return LANE_COUNT_UNKNOWN;
2223 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2225 switch (link_rate) {
2226 case LINK_RATE_HIGH3:
2227 return LINK_RATE_HIGH2;
2228 case LINK_RATE_HIGH2:
2229 return LINK_RATE_HIGH;
2230 case LINK_RATE_HIGH:
2231 return LINK_RATE_LOW;
2233 return LINK_RATE_UNKNOWN;
2235 return LINK_RATE_UNKNOWN;
2239 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2241 switch (lane_count) {
2242 case LANE_COUNT_ONE:
2243 return LANE_COUNT_TWO;
2244 case LANE_COUNT_TWO:
2245 return LANE_COUNT_FOUR;
2247 return LANE_COUNT_UNKNOWN;
2251 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2253 switch (link_rate) {
2255 return LINK_RATE_HIGH;
2256 case LINK_RATE_HIGH:
2257 return LINK_RATE_HIGH2;
2258 case LINK_RATE_HIGH2:
2259 return LINK_RATE_HIGH3;
2261 return LINK_RATE_UNKNOWN;
2266 * function: set link rate and lane count fallback based
2267 * on current link setting and last link training result
2269 * true - link setting could be set
2270 * false - has reached minimum setting
2271 * and no further fallback could be done
2273 static bool decide_fallback_link_setting(
2274 struct dc_link_settings initial_link_settings,
2275 struct dc_link_settings *current_link_setting,
2276 enum link_training_result training_result)
2278 if (!current_link_setting)
2281 switch (training_result) {
2282 case LINK_TRAINING_CR_FAIL_LANE0:
2283 case LINK_TRAINING_CR_FAIL_LANE1:
2284 case LINK_TRAINING_CR_FAIL_LANE23:
2285 case LINK_TRAINING_LQA_FAIL:
2287 if (!reached_minimum_link_rate
2288 (current_link_setting->link_rate)) {
2289 current_link_setting->link_rate =
2291 current_link_setting->link_rate);
2292 } else if (!reached_minimum_lane_count
2293 (current_link_setting->lane_count)) {
2294 current_link_setting->link_rate =
2295 initial_link_settings.link_rate;
2296 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2298 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2299 current_link_setting->lane_count =
2301 else if (training_result ==
2302 LINK_TRAINING_CR_FAIL_LANE23)
2303 current_link_setting->lane_count =
2306 current_link_setting->lane_count =
2308 current_link_setting->lane_count);
2314 case LINK_TRAINING_EQ_FAIL_EQ:
2316 if (!reached_minimum_lane_count
2317 (current_link_setting->lane_count)) {
2318 current_link_setting->lane_count =
2320 current_link_setting->lane_count);
2321 } else if (!reached_minimum_link_rate
2322 (current_link_setting->link_rate)) {
2323 current_link_setting->link_rate =
2325 current_link_setting->link_rate);
2331 case LINK_TRAINING_EQ_FAIL_CR:
2333 if (!reached_minimum_link_rate
2334 (current_link_setting->link_rate)) {
2335 current_link_setting->link_rate =
2337 current_link_setting->link_rate);
2349 bool dp_validate_mode_timing(
2350 struct dc_link *link,
2351 const struct dc_crtc_timing *timing)
2356 const struct dc_link_settings *link_setting;
2358 /*always DP fail safe mode*/
2359 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2360 timing->h_addressable == (uint32_t) 640 &&
2361 timing->v_addressable == (uint32_t) 480)
2364 link_setting = dc_link_get_link_cap(link);
2366 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2367 /*if (flags.DYNAMIC_VALIDATION == 1 &&
2368 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2369 link_setting = &link->verified_link_cap;
2372 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2373 max_bw = dc_link_bandwidth_kbps(link, link_setting);
2375 if (req_bw <= max_bw) {
2376 /* remember the biggest mode here, during
2377 * initial link training (to get
2378 * verified_link_cap), LS sends event about
2379 * cannot train at reported cap to upper
2380 * layer and upper layer will re-enumerate modes.
2381 * this is not necessary if the lower
2382 * verified_link_cap is enough to drive
2385 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2386 /* if (flags.DYNAMIC_VALIDATION == 1)
2387 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2388 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2394 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2396 struct dc_link_settings initial_link_setting = {
2397 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2398 struct dc_link_settings current_link_setting =
2399 initial_link_setting;
2402 /* search for the minimum link setting that:
2403 * 1. is supported according to the link training result
2404 * 2. could support the b/w requested by the timing
2406 while (current_link_setting.link_rate <=
2407 link->verified_link_cap.link_rate) {
2408 link_bw = dc_link_bandwidth_kbps(
2410 ¤t_link_setting);
2411 if (req_bw <= link_bw) {
2412 *link_setting = current_link_setting;
2416 if (current_link_setting.lane_count <
2417 link->verified_link_cap.lane_count) {
2418 current_link_setting.lane_count =
2419 increase_lane_count(
2420 current_link_setting.lane_count);
2422 current_link_setting.link_rate =
2424 current_link_setting.link_rate);
2425 current_link_setting.lane_count =
2426 initial_link_setting.lane_count;
2433 static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2435 struct dc_link_settings initial_link_setting;
2436 struct dc_link_settings current_link_setting;
2439 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
2440 link->dpcd_caps.edp_supported_link_rates_count == 0) {
2441 *link_setting = link->verified_link_cap;
2445 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2446 initial_link_setting.lane_count = LANE_COUNT_ONE;
2447 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2448 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2449 initial_link_setting.use_link_rate_set = true;
2450 initial_link_setting.link_rate_set = 0;
2451 current_link_setting = initial_link_setting;
2453 /* search for the minimum link setting that:
2454 * 1. is supported according to the link training result
2455 * 2. could support the b/w requested by the timing
2457 while (current_link_setting.link_rate <=
2458 link->verified_link_cap.link_rate) {
2459 link_bw = dc_link_bandwidth_kbps(
2461 ¤t_link_setting);
2462 if (req_bw <= link_bw) {
2463 *link_setting = current_link_setting;
2467 if (current_link_setting.lane_count <
2468 link->verified_link_cap.lane_count) {
2469 current_link_setting.lane_count =
2470 increase_lane_count(
2471 current_link_setting.lane_count);
2473 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2474 current_link_setting.link_rate_set++;
2475 current_link_setting.link_rate =
2476 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2477 current_link_setting.lane_count =
2478 initial_link_setting.lane_count;
2486 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2488 *link_setting = link->verified_link_cap;
2492 void decide_link_settings(struct dc_stream_state *stream,
2493 struct dc_link_settings *link_setting)
2495 struct dc_link *link;
2498 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2500 link = stream->link;
2502 /* if preferred is specified through AMDDP, use it, if it's enough
2505 if (link->preferred_link_setting.lane_count !=
2506 LANE_COUNT_UNKNOWN &&
2507 link->preferred_link_setting.link_rate !=
2508 LINK_RATE_UNKNOWN) {
2509 *link_setting = link->preferred_link_setting;
2513 /* MST doesn't perform link training for now
2514 * TODO: add MST specific link training routine
2516 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2517 if (decide_mst_link_settings(link, link_setting))
2519 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2520 if (decide_edp_link_settings(link, link_setting, req_bw))
2522 } else if (decide_dp_link_settings(link, link_setting, req_bw))
2525 BREAK_TO_DEBUGGER();
2526 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2528 *link_setting = link->verified_link_cap;
2531 /*************************Short Pulse IRQ***************************/
2532 static bool allow_hpd_rx_irq(const struct dc_link *link)
2535 * Don't handle RX IRQ unless one of following is met:
2536 * 1) The link is established (cur_link_settings != unknown)
2537 * 2) We kicked off MST detection
2538 * 3) We know we're dealing with an active dongle
2541 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2542 (link->type == dc_connection_mst_branch) ||
2543 is_dp_active_dongle(link))
2549 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2551 union dpcd_psr_configuration psr_configuration;
2553 if (!link->psr_settings.psr_feature_enabled)
2556 dm_helpers_dp_read_dpcd(
2559 368,/*DpcdAddress_PSR_Enable_Cfg*/
2560 &psr_configuration.raw,
2561 sizeof(psr_configuration.raw));
2564 if (psr_configuration.bits.ENABLE) {
2565 unsigned char dpcdbuf[3] = {0};
2566 union psr_error_status psr_error_status;
2567 union psr_sink_psr_status psr_sink_psr_status;
2569 dm_helpers_dp_read_dpcd(
2572 0x2006, /*DpcdAddress_PSR_Error_Status*/
2573 (unsigned char *) dpcdbuf,
2576 /*DPCD 2006h ERROR STATUS*/
2577 psr_error_status.raw = dpcdbuf[0];
2578 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2579 psr_sink_psr_status.raw = dpcdbuf[2];
2581 if (psr_error_status.bits.LINK_CRC_ERROR ||
2582 psr_error_status.bits.RFB_STORAGE_ERROR ||
2583 psr_error_status.bits.VSC_SDP_ERROR) {
2584 /* Acknowledge and clear error bits */
2585 dm_helpers_dp_write_dpcd(
2588 8198,/*DpcdAddress_PSR_Error_Status*/
2589 &psr_error_status.raw,
2590 sizeof(psr_error_status.raw));
2592 /* PSR error, disable and re-enable PSR */
2593 dc_link_set_psr_allow_active(link, false, true, false);
2594 dc_link_set_psr_allow_active(link, true, true, false);
2597 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2598 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2599 /* No error is detect, PSR is active.
2600 * We should return with IRQ_HPD handled without
2601 * checking for loss of sync since PSR would have
2602 * powered down main link.
2610 static void dp_test_send_link_training(struct dc_link *link)
2612 struct dc_link_settings link_settings = {0};
2614 core_link_read_dpcd(
2617 (unsigned char *)(&link_settings.lane_count),
2619 core_link_read_dpcd(
2622 (unsigned char *)(&link_settings.link_rate),
2625 /* Set preferred link settings */
2626 link->verified_link_cap.lane_count = link_settings.lane_count;
2627 link->verified_link_cap.link_rate = link_settings.link_rate;
2629 dp_retrain_link_dp_test(link, &link_settings, false);
2632 /* TODO Raven hbr2 compliance eye output is unstable
2633 * (toggling on and off) with debugger break
2634 * This caueses intermittent PHY automation failure
2635 * Need to look into the root cause */
2636 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2638 union phy_test_pattern dpcd_test_pattern;
2639 union lane_adjust dpcd_lane_adjustment[2];
2640 unsigned char dpcd_post_cursor_2_adjustment = 0;
2641 unsigned char test_80_bit_pattern[
2642 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2643 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2644 enum dp_test_pattern test_pattern;
2645 struct dc_link_training_settings link_settings;
2646 union lane_adjust dpcd_lane_adjust;
2648 struct link_training_settings link_training_settings;
2651 dpcd_test_pattern.raw = 0;
2652 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2653 memset(&link_settings, 0, sizeof(link_settings));
2655 /* get phy test pattern and pattern parameters from DP receiver */
2656 core_link_read_dpcd(
2658 DP_PHY_TEST_PATTERN,
2659 &dpcd_test_pattern.raw,
2660 sizeof(dpcd_test_pattern));
2661 core_link_read_dpcd(
2663 DP_ADJUST_REQUEST_LANE0_1,
2664 &dpcd_lane_adjustment[0].raw,
2665 sizeof(dpcd_lane_adjustment));
2667 /*get post cursor 2 parameters
2668 * For DP 1.1a or eariler, this DPCD register's value is 0
2669 * For DP 1.2 or later:
2670 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2671 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2673 core_link_read_dpcd(
2675 DP_ADJUST_REQUEST_POST_CURSOR2,
2676 &dpcd_post_cursor_2_adjustment,
2677 sizeof(dpcd_post_cursor_2_adjustment));
2679 /* translate request */
2680 switch (dpcd_test_pattern.bits.PATTERN) {
2681 case PHY_TEST_PATTERN_D10_2:
2682 test_pattern = DP_TEST_PATTERN_D102;
2684 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2685 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2687 case PHY_TEST_PATTERN_PRBS7:
2688 test_pattern = DP_TEST_PATTERN_PRBS7;
2690 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2691 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2693 case PHY_TEST_PATTERN_CP2520_1:
2694 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2695 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2696 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2697 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2699 case PHY_TEST_PATTERN_CP2520_2:
2700 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2701 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2702 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2703 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2705 case PHY_TEST_PATTERN_CP2520_3:
2706 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2709 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2713 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2714 core_link_read_dpcd(
2716 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2717 test_80_bit_pattern,
2718 sizeof(test_80_bit_pattern));
2720 /* prepare link training settings */
2721 link_settings.link = link->cur_link_settings;
2723 for (lane = 0; lane <
2724 (unsigned int)(link->cur_link_settings.lane_count);
2726 dpcd_lane_adjust.raw =
2727 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2728 link_settings.lane_settings[lane].VOLTAGE_SWING =
2729 (enum dc_voltage_swing)
2730 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2731 link_settings.lane_settings[lane].PRE_EMPHASIS =
2732 (enum dc_pre_emphasis)
2733 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2734 link_settings.lane_settings[lane].POST_CURSOR2 =
2735 (enum dc_post_cursor2)
2736 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2739 for (i = 0; i < 4; i++)
2740 link_training_settings.lane_settings[i] =
2741 link_settings.lane_settings[i];
2742 link_training_settings.link_settings = link_settings.link;
2743 link_training_settings.allow_invalid_msa_timing_param = false;
2744 /*Usage: Measure DP physical lane signal
2745 * by DP SI test equipment automatically.
2746 * PHY test pattern request is generated by equipment via HPD interrupt.
2747 * HPD needs to be active all the time. HPD should be active
2748 * all the time. Do not touch it.
2749 * forward request to DS
2751 dc_link_dp_set_test_pattern(
2754 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2755 &link_training_settings,
2756 test_80_bit_pattern,
2757 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2758 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
2761 static void dp_test_send_link_test_pattern(struct dc_link *link)
2763 union link_test_pattern dpcd_test_pattern;
2764 union test_misc dpcd_test_params;
2765 enum dp_test_pattern test_pattern;
2766 enum dp_test_pattern_color_space test_pattern_color_space =
2767 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2769 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2770 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2772 /* get link test pattern and pattern parameters */
2773 core_link_read_dpcd(
2776 &dpcd_test_pattern.raw,
2777 sizeof(dpcd_test_pattern));
2778 core_link_read_dpcd(
2781 &dpcd_test_params.raw,
2782 sizeof(dpcd_test_params));
2784 switch (dpcd_test_pattern.bits.PATTERN) {
2785 case LINK_TEST_PATTERN_COLOR_RAMP:
2786 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2788 case LINK_TEST_PATTERN_VERTICAL_BARS:
2789 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2790 break; /* black and white */
2791 case LINK_TEST_PATTERN_COLOR_SQUARES:
2792 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2793 TEST_DYN_RANGE_VESA ?
2794 DP_TEST_PATTERN_COLOR_SQUARES :
2795 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2798 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2802 if (dpcd_test_params.bits.CLR_FORMAT == 0)
2803 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2805 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2806 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2807 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2809 dc_link_dp_set_test_pattern(
2812 test_pattern_color_space,
2818 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
2820 union audio_test_mode dpcd_test_mode = {0};
2821 struct audio_test_pattern_type dpcd_pattern_type = {0};
2822 union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
2823 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2825 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2826 struct pipe_ctx *pipe_ctx = &pipes[0];
2827 unsigned int channel_count;
2828 unsigned int channel = 0;
2829 unsigned int modes = 0;
2830 unsigned int sampling_rate_in_hz = 0;
2832 // get audio test mode and test pattern parameters
2833 core_link_read_dpcd(
2836 &dpcd_test_mode.raw,
2837 sizeof(dpcd_test_mode));
2839 core_link_read_dpcd(
2841 DP_TEST_AUDIO_PATTERN_TYPE,
2842 &dpcd_pattern_type.value,
2843 sizeof(dpcd_pattern_type));
2845 channel_count = dpcd_test_mode.bits.channel_count + 1;
2847 // read pattern periods for requested channels when sawTooth pattern is requested
2848 if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
2849 dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
2851 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
2852 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2853 // read period for each channel
2854 for (channel = 0; channel < channel_count; channel++) {
2855 core_link_read_dpcd(
2857 DP_TEST_AUDIO_PERIOD_CH1 + channel,
2858 &dpcd_pattern_period[channel].raw,
2859 sizeof(dpcd_pattern_period[channel]));
2863 // translate sampling rate
2864 switch (dpcd_test_mode.bits.sampling_rate) {
2865 case AUDIO_SAMPLING_RATE_32KHZ:
2866 sampling_rate_in_hz = 32000;
2868 case AUDIO_SAMPLING_RATE_44_1KHZ:
2869 sampling_rate_in_hz = 44100;
2871 case AUDIO_SAMPLING_RATE_48KHZ:
2872 sampling_rate_in_hz = 48000;
2874 case AUDIO_SAMPLING_RATE_88_2KHZ:
2875 sampling_rate_in_hz = 88200;
2877 case AUDIO_SAMPLING_RATE_96KHZ:
2878 sampling_rate_in_hz = 96000;
2880 case AUDIO_SAMPLING_RATE_176_4KHZ:
2881 sampling_rate_in_hz = 176400;
2883 case AUDIO_SAMPLING_RATE_192KHZ:
2884 sampling_rate_in_hz = 192000;
2887 sampling_rate_in_hz = 0;
2891 link->audio_test_data.flags.test_requested = 1;
2892 link->audio_test_data.flags.disable_video = disable_video;
2893 link->audio_test_data.sampling_rate = sampling_rate_in_hz;
2894 link->audio_test_data.channel_count = channel_count;
2895 link->audio_test_data.pattern_type = test_pattern;
2897 if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
2898 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
2899 link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
2904 static void handle_automated_test(struct dc_link *link)
2906 union test_request test_request;
2907 union test_response test_response;
2909 memset(&test_request, 0, sizeof(test_request));
2910 memset(&test_response, 0, sizeof(test_response));
2912 core_link_read_dpcd(
2916 sizeof(union test_request));
2917 if (test_request.bits.LINK_TRAINING) {
2918 /* ACK first to let DP RX test box monitor LT sequence */
2919 test_response.bits.ACK = 1;
2920 core_link_write_dpcd(
2924 sizeof(test_response));
2925 dp_test_send_link_training(link);
2926 /* no acknowledge request is needed again */
2927 test_response.bits.ACK = 0;
2929 if (test_request.bits.LINK_TEST_PATTRN) {
2930 dp_test_send_link_test_pattern(link);
2931 test_response.bits.ACK = 1;
2934 if (test_request.bits.AUDIO_TEST_PATTERN) {
2935 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
2936 test_response.bits.ACK = 1;
2939 if (test_request.bits.PHY_TEST_PATTERN) {
2940 dp_test_send_phy_test_pattern(link);
2941 test_response.bits.ACK = 1;
2944 /* send request acknowledgment */
2945 if (test_response.bits.ACK)
2946 core_link_write_dpcd(
2950 sizeof(test_response));
2953 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
2955 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
2956 union device_service_irq device_service_clear = { { 0 } };
2957 enum dc_status result;
2958 bool status = false;
2959 struct pipe_ctx *pipe_ctx;
2963 *out_link_loss = false;
2964 /* For use cases related to down stream connection status change,
2965 * PSR and device auto test, refer to function handle_sst_hpd_irq
2968 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2969 __func__, link->link_index);
2972 /* All the "handle_hpd_irq_xxx()" methods
2973 * should be called only after
2974 * dal_dpsst_ls_read_hpd_irq_data
2975 * Order of calls is important too
2977 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
2978 if (out_hpd_irq_dpcd_data)
2979 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
2981 if (result != DC_OK) {
2982 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2987 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2988 device_service_clear.bits.AUTOMATED_TEST = 1;
2989 core_link_write_dpcd(
2991 DP_DEVICE_SERVICE_IRQ_VECTOR,
2992 &device_service_clear.raw,
2993 sizeof(device_service_clear.raw));
2994 device_service_clear.raw = 0;
2995 handle_automated_test(link);
2999 if (!allow_hpd_rx_irq(link)) {
3000 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3001 __func__, link->link_index);
3005 if (handle_hpd_irq_psr_sink(link))
3006 /* PSR-related error was detected and handled */
3009 /* If PSR-related error handled, Main link may be off,
3010 * so do not handle as a normal sink status change interrupt.
3013 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3016 /* check if we have MST msg and return since we poll for it */
3017 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3020 /* For now we only handle 'Downstream port status' case.
3021 * If we got sink count changed it means
3022 * Downstream port status changed,
3023 * then DM should call DC to do the detection.
3024 * NOTE: Do not handle link loss on eDP since it is internal link*/
3025 if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3026 hpd_rx_irq_check_link_loss_status(
3028 &hpd_irq_dpcd_data)) {
3029 /* Connectivity log: link loss */
3030 CONN_DATA_LINK_LOSS(link,
3031 hpd_irq_dpcd_data.raw,
3032 sizeof(hpd_irq_dpcd_data),
3035 for (i = 0; i < MAX_PIPES; i++) {
3036 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3037 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3041 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3045 for (i = 0; i < MAX_PIPES; i++) {
3046 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3047 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3048 pipe_ctx->stream->link == link)
3049 core_link_disable_stream(pipe_ctx);
3052 for (i = 0; i < MAX_PIPES; i++) {
3053 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3054 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3055 pipe_ctx->stream->link == link)
3056 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3061 *out_link_loss = true;
3064 if (link->type == dc_connection_active_dongle &&
3065 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3066 != link->dpcd_sink_count)
3069 /* reasons for HPD RX:
3070 * 1. Link Loss - ie Re-train the Link
3071 * 2. MST sideband message
3072 * 3. Automated Test - ie. Internal Commit
3073 * 4. CP (copy protection) - (not interesting for DM???)
3075 * 6. Downstream Port status changed
3076 * -ie. Detect - this the only one
3077 * which is interesting for DM because
3078 * it must call dc_link_detect.
3083 /*query dpcd for version and mst cap addresses*/
3084 bool is_mst_supported(struct dc_link *link)
3087 enum dc_status st = DC_OK;
3091 if (link->preferred_training_settings.mst_enable &&
3092 *link->preferred_training_settings.mst_enable == false) {
3099 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3102 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3104 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3105 &cap.raw, sizeof(cap));
3106 if (st == DC_OK && cap.bits.MST_CAP == 1)
3113 bool is_dp_active_dongle(const struct dc_link *link)
3115 return link->dpcd_caps.is_branch_dev;
3118 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3121 case DOWN_STREAM_MAX_8BPC:
3123 case DOWN_STREAM_MAX_10BPC:
3125 case DOWN_STREAM_MAX_12BPC:
3127 case DOWN_STREAM_MAX_16BPC:
3136 static void read_dp_device_vendor_id(struct dc_link *link)
3138 struct dp_device_vendor_id dp_id;
3140 /* read IEEE branch device id */
3141 core_link_read_dpcd(
3147 link->dpcd_caps.branch_dev_id =
3148 (dp_id.ieee_oui[0] << 16) +
3149 (dp_id.ieee_oui[1] << 8) +
3153 link->dpcd_caps.branch_dev_name,
3154 dp_id.ieee_device_id,
3155 sizeof(dp_id.ieee_device_id));
3160 static void get_active_converter_info(
3161 uint8_t data, struct dc_link *link)
3163 union dp_downstream_port_present ds_port = { .byte = data };
3164 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3166 /* decode converter info*/
3167 if (!ds_port.fields.PORT_PRESENT) {
3168 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3169 ddc_service_set_dongle_type(link->ddc,
3170 link->dpcd_caps.dongle_type);
3171 link->dpcd_caps.is_branch_dev = false;
3175 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3176 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3178 switch (ds_port.fields.PORT_TYPE) {
3179 case DOWNSTREAM_VGA:
3180 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3182 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3183 /* At this point we don't know is it DVI or HDMI or DP++,
3185 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3188 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3192 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3193 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3194 union dwnstream_port_caps_byte0 *port_caps =
3195 (union dwnstream_port_caps_byte0 *)det_caps;
3196 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3197 det_caps, sizeof(det_caps)) == DC_OK) {
3199 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3200 /*Handle DP case as DONGLE_NONE*/
3201 case DOWN_STREAM_DETAILED_DP:
3202 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3204 case DOWN_STREAM_DETAILED_VGA:
3205 link->dpcd_caps.dongle_type =
3206 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3208 case DOWN_STREAM_DETAILED_DVI:
3209 link->dpcd_caps.dongle_type =
3210 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3212 case DOWN_STREAM_DETAILED_HDMI:
3213 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3214 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3215 link->dpcd_caps.dongle_type =
3216 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3218 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3219 if (ds_port.fields.DETAILED_CAPS) {
3221 union dwnstream_port_caps_byte3_hdmi
3222 hdmi_caps = {.raw = det_caps[3] };
3223 union dwnstream_port_caps_byte2
3224 hdmi_color_caps = {.raw = det_caps[2] };
3225 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3228 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3229 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3230 /*YCBCR capability only for HDMI case*/
3231 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3232 == DOWN_STREAM_DETAILED_HDMI) {
3233 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3234 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3235 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3236 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3237 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3238 hdmi_caps.bits.YCrCr422_CONVERSION;
3239 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3240 hdmi_caps.bits.YCrCr420_CONVERSION;
3243 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3244 translate_dpcd_max_bpc(
3245 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3247 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3248 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3256 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3259 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3261 core_link_read_dpcd(
3263 DP_BRANCH_REVISION_START,
3264 (uint8_t *)&dp_hw_fw_revision,
3265 sizeof(dp_hw_fw_revision));
3267 link->dpcd_caps.branch_hw_revision =
3268 dp_hw_fw_revision.ieee_hw_rev;
3271 link->dpcd_caps.branch_fw_revision,
3272 dp_hw_fw_revision.ieee_fw_rev,
3273 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3277 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3282 if (!link->dpcd_caps.dpcd_rev.raw) {
3284 dp_receiver_power_ctrl(link, true);
3285 core_link_read_dpcd(link, DP_DPCD_REV,
3287 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3290 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3293 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3294 switch (link->dpcd_caps.branch_dev_id) {
3295 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3296 * all internal circuits including AUX communication preventing
3297 * reading DPCD table and EDID (spec violation).
3298 * Encoder will skip DP RX power down on disable_output to
3299 * keep receiver powered all the time.*/
3300 case DP_BRANCH_DEVICE_ID_0010FA:
3301 case DP_BRANCH_DEVICE_ID_0080E1:
3302 case DP_BRANCH_DEVICE_ID_00E04C:
3303 link->wa_flags.dp_keep_receiver_powered = true;
3306 /* TODO: May need work around for other dongles. */
3308 link->wa_flags.dp_keep_receiver_powered = false;
3312 link->wa_flags.dp_keep_receiver_powered = false;
3315 /* Read additional sink caps defined in source specific DPCD area
3316 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3318 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3325 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3328 link->dpcd_sink_ext_caps.raw = dpcd_data;
3332 static bool retrieve_link_cap(struct dc_link *link)
3334 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3335 * which means size 16 will be good for both of those DPCD register block reads
3337 uint8_t dpcd_data[16];
3338 uint8_t lttpr_dpcd_data[6];
3340 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3342 uint8_t dpcd_dprx_data = '\0';
3343 uint8_t dpcd_power_state = '\0';
3345 struct dp_device_vendor_id sink_id;
3346 union down_stream_port_count down_strm_port_count;
3347 union edp_configuration_cap edp_config_cap;
3348 union dp_downstream_port_present ds_port = { 0 };
3349 enum dc_status status = DC_ERROR_UNEXPECTED;
3350 uint32_t read_dpcd_retry_cnt = 3;
3352 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3353 bool is_lttpr_present = false;
3354 const uint32_t post_oui_delay = 30; // 30ms
3356 memset(dpcd_data, '\0', sizeof(dpcd_data));
3357 memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3358 memset(&down_strm_port_count,
3359 '\0', sizeof(union down_stream_port_count));
3360 memset(&edp_config_cap, '\0',
3361 sizeof(union edp_configuration_cap));
3363 /* if extended timeout is supported in hardware,
3364 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3365 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3367 dc_link_aux_try_to_configure_timeout(link->ddc,
3368 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3370 status = core_link_read_dpcd(link, DP_SET_POWER,
3371 &dpcd_power_state, sizeof(dpcd_power_state));
3373 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3374 * section 2.3.1.2, if AUX CH may be powered down due to
3375 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3376 * signal and may need up to 1 ms before being able to reply.
3378 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3381 dpcd_set_source_specific_data(link);
3382 /* Sink may need to configure internals based on vendor, so allow some
3383 * time before proceeding with possibly vendor specific transactions
3385 msleep(post_oui_delay);
3387 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3388 status = core_link_read_dpcd(
3393 if (status == DC_OK)
3397 if (status != DC_OK) {
3398 dm_error("%s: Read dpcd data failed.\n", __func__);
3402 if (link->dc->caps.extended_aux_timeout_support &&
3403 link->dc->config.allow_lttpr_non_transparent_mode) {
3404 /* By reading LTTPR capability, RX assumes that we will enable
3405 * LTTPR non transparent if LTTPR is present.
3406 * Therefore, only query LTTPR capability when both LTTPR
3407 * extended aux timeout and
3408 * non transparent mode is supported by hardware
3410 status = core_link_read_dpcd(
3412 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3414 sizeof(lttpr_dpcd_data));
3416 link->dpcd_caps.lttpr_caps.revision.raw =
3417 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3418 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3420 link->dpcd_caps.lttpr_caps.max_link_rate =
3421 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3422 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3424 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3425 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3426 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3428 link->dpcd_caps.lttpr_caps.max_lane_count =
3429 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3430 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3432 link->dpcd_caps.lttpr_caps.mode =
3433 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3434 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3436 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3437 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3438 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3440 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3441 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3442 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3443 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3444 if (is_lttpr_present)
3445 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3448 /* decide lttpr non transparent mode */
3449 link->lttpr_non_transparent_mode = is_lttpr_present;
3451 if (!is_lttpr_present)
3452 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3456 union training_aux_rd_interval aux_rd_interval;
3458 aux_rd_interval.raw =
3459 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3461 link->dpcd_caps.ext_receiver_cap_field_present =
3462 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3464 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3465 uint8_t ext_cap_data[16];
3467 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3468 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3469 status = core_link_read_dpcd(
3473 sizeof(ext_cap_data));
3474 if (status == DC_OK) {
3475 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3479 if (status != DC_OK)
3480 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3484 link->dpcd_caps.dpcd_rev.raw =
3485 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3487 if (link->dpcd_caps.ext_receiver_cap_field_present) {
3488 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3489 status = core_link_read_dpcd(
3491 DP_DPRX_FEATURE_ENUMERATION_LIST,
3493 sizeof(dpcd_dprx_data));
3494 if (status == DC_OK)
3498 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3500 if (status != DC_OK)
3501 dm_error("%s: Read DPRX caps data failed.\n", __func__);
3505 link->dpcd_caps.dprx_feature.raw = 0;
3509 /* Error condition checking...
3510 * It is impossible for Sink to report Max Lane Count = 0.
3511 * It is possible for Sink to report Max Link Rate = 0, if it is
3512 * an eDP device that is reporting specialized link rates in the
3513 * SUPPORTED_LINK_RATE table.
3515 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3518 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3521 read_dp_device_vendor_id(link);
3523 get_active_converter_info(ds_port.byte, link);
3525 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3527 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3530 link->dpcd_caps.allow_invalid_MSA_timing_param =
3531 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3533 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3534 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3536 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3537 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3539 link->reported_link_cap.lane_count =
3540 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3541 link->reported_link_cap.link_rate = dpcd_data[
3542 DP_MAX_LINK_RATE - DP_DPCD_REV];
3543 link->reported_link_cap.link_spread =
3544 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3545 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3547 edp_config_cap.raw = dpcd_data[
3548 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3549 link->dpcd_caps.panel_mode_edp =
3550 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3551 link->dpcd_caps.dpcd_display_control_capable =
3552 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3554 link->test_pattern_enabled = false;
3555 link->compliance_test_state.raw = 0;
3557 /* read sink count */
3558 core_link_read_dpcd(link,
3560 &link->dpcd_caps.sink_count.raw,
3561 sizeof(link->dpcd_caps.sink_count.raw));
3563 /* read sink ieee oui */
3564 core_link_read_dpcd(link,
3566 (uint8_t *)(&sink_id),
3569 link->dpcd_caps.sink_dev_id =
3570 (sink_id.ieee_oui[0] << 16) +
3571 (sink_id.ieee_oui[1] << 8) +
3572 (sink_id.ieee_oui[2]);
3575 link->dpcd_caps.sink_dev_id_str,
3576 sink_id.ieee_device_id,
3577 sizeof(sink_id.ieee_device_id));
3579 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3581 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3583 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3584 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3585 sizeof(str_mbp_2017))) {
3586 link->reported_link_cap.link_rate = 0x0c;
3590 core_link_read_dpcd(
3592 DP_SINK_HW_REVISION_START,
3593 (uint8_t *)&dp_hw_fw_revision,
3594 sizeof(dp_hw_fw_revision));
3596 link->dpcd_caps.sink_hw_revision =
3597 dp_hw_fw_revision.ieee_hw_rev;
3600 link->dpcd_caps.sink_fw_revision,
3601 dp_hw_fw_revision.ieee_fw_rev,
3602 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3604 memset(&link->dpcd_caps.dsc_caps, '\0',
3605 sizeof(link->dpcd_caps.dsc_caps));
3606 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3607 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3608 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3609 status = core_link_read_dpcd(
3612 &link->dpcd_caps.fec_cap.raw,
3613 sizeof(link->dpcd_caps.fec_cap.raw));
3614 status = core_link_read_dpcd(
3617 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3618 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3619 status = core_link_read_dpcd(
3621 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3622 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3623 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3626 if (!dpcd_read_sink_ext_caps(link))
3627 link->dpcd_sink_ext_caps.raw = 0;
3629 /* Connectivity log: detection */
3630 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3635 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3637 uint8_t dpcd_data[16];
3638 uint32_t read_dpcd_retry_cnt = 3;
3639 enum dc_status status = DC_ERROR_UNEXPECTED;
3640 union dp_downstream_port_present ds_port = { 0 };
3641 union down_stream_port_count down_strm_port_count;
3642 union edp_configuration_cap edp_config_cap;
3646 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3647 status = core_link_read_dpcd(
3652 if (status == DC_OK)
3656 link->dpcd_caps.dpcd_rev.raw =
3657 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3659 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3662 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3665 get_active_converter_info(ds_port.byte, link);
3667 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3670 link->dpcd_caps.allow_invalid_MSA_timing_param =
3671 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3673 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3674 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3676 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3677 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3679 link->reported_link_cap.lane_count =
3680 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3681 link->reported_link_cap.link_rate = dpcd_data[
3682 DP_MAX_LINK_RATE - DP_DPCD_REV];
3683 link->reported_link_cap.link_spread =
3684 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3685 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3687 edp_config_cap.raw = dpcd_data[
3688 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3689 link->dpcd_caps.panel_mode_edp =
3690 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3691 link->dpcd_caps.dpcd_display_control_capable =
3692 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3697 bool detect_dp_sink_caps(struct dc_link *link)
3699 return retrieve_link_cap(link);
3701 /* dc init_hw has power encoder using default
3702 * signal for connector. For native DP, no
3703 * need to power up encoder again. If not native
3704 * DP, hw_init may need check signal or power up
3707 /* TODO save sink caps in link->sink */
3710 enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3712 enum dc_link_rate link_rate;
3713 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3714 switch (link_rate_in_khz) {
3716 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
3719 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
3722 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
3725 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
3728 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
3731 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
3734 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
3737 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
3740 link_rate = LINK_RATE_UNKNOWN;
3746 void detect_edp_sink_caps(struct dc_link *link)
3748 uint8_t supported_link_rates[16];
3750 uint32_t link_rate_in_khz;
3751 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
3752 uint8_t backlight_adj_cap;
3754 retrieve_link_cap(link);
3755 link->dpcd_caps.edp_supported_link_rates_count = 0;
3756 memset(supported_link_rates, 0, sizeof(supported_link_rates));
3758 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
3759 (link->dc->config.optimize_edp_link_rate ||
3760 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
3761 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3762 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3763 supported_link_rates, sizeof(supported_link_rates));
3765 for (entry = 0; entry < 16; entry += 2) {
3766 // DPCD register reports per-lane link rate = 16-bit link rate capability
3767 // value X 200 kHz. Need multiplier to find link rate in kHz.
3768 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3769 supported_link_rates[entry]) * 200;
3771 if (link_rate_in_khz != 0) {
3772 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
3773 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
3774 link->dpcd_caps.edp_supported_link_rates_count++;
3776 if (link->reported_link_cap.link_rate < link_rate)
3777 link->reported_link_cap.link_rate = link_rate;
3781 link->verified_link_cap = link->reported_link_cap;
3783 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
3784 &backlight_adj_cap, sizeof(backlight_adj_cap));
3786 link->dpcd_caps.dynamic_backlight_capable_edp =
3787 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
3789 dc_link_set_default_brightness_aux(link);
3792 void dc_link_dp_enable_hpd(const struct dc_link *link)
3794 struct link_encoder *encoder = link->link_enc;
3796 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3797 encoder->funcs->enable_hpd(encoder);
3800 void dc_link_dp_disable_hpd(const struct dc_link *link)
3802 struct link_encoder *encoder = link->link_enc;
3804 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3805 encoder->funcs->disable_hpd(encoder);
3808 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
3810 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
3811 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
3812 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
3818 static void set_crtc_test_pattern(struct dc_link *link,
3819 struct pipe_ctx *pipe_ctx,
3820 enum dp_test_pattern test_pattern,
3821 enum dp_test_pattern_color_space test_pattern_color_space)
3823 enum controller_dp_test_pattern controller_test_pattern;
3824 enum dc_color_depth color_depth = pipe_ctx->
3825 stream->timing.display_color_depth;
3826 struct bit_depth_reduction_params params;
3827 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
3828 int width = pipe_ctx->stream->timing.h_addressable +
3829 pipe_ctx->stream->timing.h_border_left +
3830 pipe_ctx->stream->timing.h_border_right;
3831 int height = pipe_ctx->stream->timing.v_addressable +
3832 pipe_ctx->stream->timing.v_border_bottom +
3833 pipe_ctx->stream->timing.v_border_top;
3835 memset(¶ms, 0, sizeof(params));
3837 switch (test_pattern) {
3838 case DP_TEST_PATTERN_COLOR_SQUARES:
3839 controller_test_pattern =
3840 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
3842 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3843 controller_test_pattern =
3844 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
3846 case DP_TEST_PATTERN_VERTICAL_BARS:
3847 controller_test_pattern =
3848 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
3850 case DP_TEST_PATTERN_HORIZONTAL_BARS:
3851 controller_test_pattern =
3852 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
3854 case DP_TEST_PATTERN_COLOR_RAMP:
3855 controller_test_pattern =
3856 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
3859 controller_test_pattern =
3860 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
3864 switch (test_pattern) {
3865 case DP_TEST_PATTERN_COLOR_SQUARES:
3866 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3867 case DP_TEST_PATTERN_VERTICAL_BARS:
3868 case DP_TEST_PATTERN_HORIZONTAL_BARS:
3869 case DP_TEST_PATTERN_COLOR_RAMP:
3871 /* disable bit depth reduction */
3872 pipe_ctx->stream->bit_depth_params = params;
3873 opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms);
3874 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3875 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3876 controller_test_pattern, color_depth);
3877 else if (link->dc->hwss.set_disp_pattern_generator) {
3878 struct pipe_ctx *odm_pipe;
3879 enum controller_dp_color_space controller_color_space;
3882 int dpg_width = width;
3884 switch (test_pattern_color_space) {
3885 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3886 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
3888 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3889 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
3891 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
3892 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
3894 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
3896 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
3897 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
3902 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3904 dpg_width = width / opp_cnt;
3907 link->dc->hwss.set_disp_pattern_generator(link->dc,
3909 controller_test_pattern,
3910 controller_color_space,
3917 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3918 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3920 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
3921 link->dc->hwss.set_disp_pattern_generator(link->dc,
3923 controller_test_pattern,
3924 controller_color_space,
3935 case DP_TEST_PATTERN_VIDEO_MODE:
3937 /* restore bitdepth reduction */
3938 resource_build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms);
3939 pipe_ctx->stream->bit_depth_params = params;
3940 opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms);
3941 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3942 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3943 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3945 else if (link->dc->hwss.set_disp_pattern_generator) {
3946 struct pipe_ctx *odm_pipe;
3948 int dpg_width = width;
3950 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3953 dpg_width = width / opp_cnt;
3954 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3955 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3957 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
3958 link->dc->hwss.set_disp_pattern_generator(link->dc,
3960 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3961 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3968 link->dc->hwss.set_disp_pattern_generator(link->dc,
3970 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3971 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3986 bool dc_link_dp_set_test_pattern(
3987 struct dc_link *link,
3988 enum dp_test_pattern test_pattern,
3989 enum dp_test_pattern_color_space test_pattern_color_space,
3990 const struct link_training_settings *p_link_settings,
3991 const unsigned char *p_custom_pattern,
3992 unsigned int cust_pattern_size)
3994 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3995 struct pipe_ctx *pipe_ctx = &pipes[0];
3998 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
3999 union dpcd_training_pattern training_pattern;
4000 enum dpcd_phy_test_patterns pattern;
4002 memset(&training_pattern, 0, sizeof(training_pattern));
4004 for (i = 0; i < MAX_PIPES; i++) {
4005 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4006 pipe_ctx = &pipes[i];
4011 /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4012 if (link->test_pattern_enabled && test_pattern ==
4013 DP_TEST_PATTERN_VIDEO_MODE) {
4014 /* Set CRTC Test Pattern */
4015 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4016 dp_set_hw_test_pattern(link, test_pattern,
4017 (uint8_t *)p_custom_pattern,
4018 (uint32_t)cust_pattern_size);
4020 /* Unblank Stream */
4021 link->dc->hwss.unblank_stream(
4023 &link->verified_link_cap);
4024 /* TODO:m_pHwss->MuteAudioEndpoint
4025 * (pPathMode->pDisplayPath, false);
4028 /* Reset Test Pattern state */
4029 link->test_pattern_enabled = false;
4034 /* Check for PHY Test Patterns */
4035 if (is_dp_phy_pattern(test_pattern)) {
4036 /* Set DPCD Lane Settings before running test pattern */
4037 if (p_link_settings != NULL) {
4038 dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4039 dpcd_set_lane_settings(link, p_link_settings, DPRX);
4042 /* Blank stream if running test pattern */
4043 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4046 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4049 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4052 dp_set_hw_test_pattern(link, test_pattern,
4053 (uint8_t *)p_custom_pattern,
4054 (uint32_t)cust_pattern_size);
4056 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4057 /* Set Test Pattern state */
4058 link->test_pattern_enabled = true;
4059 if (p_link_settings != NULL)
4060 dpcd_set_link_settings(link,
4064 switch (test_pattern) {
4065 case DP_TEST_PATTERN_VIDEO_MODE:
4066 pattern = PHY_TEST_PATTERN_NONE;
4068 case DP_TEST_PATTERN_D102:
4069 pattern = PHY_TEST_PATTERN_D10_2;
4071 case DP_TEST_PATTERN_SYMBOL_ERROR:
4072 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4074 case DP_TEST_PATTERN_PRBS7:
4075 pattern = PHY_TEST_PATTERN_PRBS7;
4077 case DP_TEST_PATTERN_80BIT_CUSTOM:
4078 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4080 case DP_TEST_PATTERN_CP2520_1:
4081 pattern = PHY_TEST_PATTERN_CP2520_1;
4083 case DP_TEST_PATTERN_CP2520_2:
4084 pattern = PHY_TEST_PATTERN_CP2520_2;
4086 case DP_TEST_PATTERN_CP2520_3:
4087 pattern = PHY_TEST_PATTERN_CP2520_3;
4093 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4094 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4097 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4098 /* tell receiver that we are sending qualification
4099 * pattern DP 1.2 or later - DP receiver's link quality
4100 * pattern is set using DPCD LINK_QUAL_LANEx_SET
4101 * register (0x10B~0x10E)\
4103 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4104 link_qual_pattern[lane] =
4105 (unsigned char)(pattern);
4107 core_link_write_dpcd(link,
4108 DP_LINK_QUAL_LANE0_SET,
4110 sizeof(link_qual_pattern));
4111 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4112 link->dpcd_caps.dpcd_rev.raw == 0) {
4113 /* tell receiver that we are sending qualification
4114 * pattern DP 1.1a or earlier - DP receiver's link
4115 * quality pattern is set using
4116 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4117 * register (0x102). We will use v_1.3 when we are
4118 * setting test pattern for DP 1.1.
4120 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4121 &training_pattern.raw,
4122 sizeof(training_pattern));
4123 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4124 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4125 &training_pattern.raw,
4126 sizeof(training_pattern));
4129 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4131 switch (test_pattern_color_space) {
4132 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4133 color_space = COLOR_SPACE_SRGB;
4134 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4135 color_space = COLOR_SPACE_SRGB_LIMITED;
4138 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4139 color_space = COLOR_SPACE_YCBCR601;
4140 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4141 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4143 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4144 color_space = COLOR_SPACE_YCBCR709;
4145 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4146 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4152 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4153 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4154 union dmub_hw_lock_flags hw_locks = { 0 };
4155 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4157 hw_locks.bits.lock_dig = 1;
4158 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4160 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4165 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4166 pipe_ctx->stream_res.tg);
4169 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4170 /* update MSA to requested color space */
4171 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4172 &pipe_ctx->stream->timing,
4174 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4175 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4177 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4178 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4179 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4181 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4182 resource_build_info_frame(pipe_ctx);
4183 link->dc->hwss.update_info_frame(pipe_ctx);
4187 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4188 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4189 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4190 CRTC_STATE_VACTIVE);
4191 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4193 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4194 CRTC_STATE_VACTIVE);
4196 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4197 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4198 union dmub_hw_lock_flags hw_locks = { 0 };
4199 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4201 hw_locks.bits.lock_dig = 1;
4202 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4204 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4209 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4210 pipe_ctx->stream_res.tg);
4213 /* Set Test Pattern state */
4214 link->test_pattern_enabled = true;
4220 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4222 unsigned char mstmCntl;
4224 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4226 mstmCntl |= DP_MST_EN;
4228 mstmCntl &= (~DP_MST_EN);
4230 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4233 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4235 union dpcd_edp_config edp_config_set;
4236 bool panel_mode_edp = false;
4238 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4240 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4242 switch (panel_mode) {
4243 case DP_PANEL_MODE_EDP:
4244 case DP_PANEL_MODE_SPECIAL:
4245 panel_mode_edp = true;
4252 /*set edp panel mode in receiver*/
4253 core_link_read_dpcd(
4255 DP_EDP_CONFIGURATION_SET,
4256 &edp_config_set.raw,
4257 sizeof(edp_config_set.raw));
4259 if (edp_config_set.bits.PANEL_MODE_EDP
4260 != panel_mode_edp) {
4261 enum dc_status result = DC_ERROR_UNEXPECTED;
4263 edp_config_set.bits.PANEL_MODE_EDP =
4265 result = core_link_write_dpcd(
4267 DP_EDP_CONFIGURATION_SET,
4268 &edp_config_set.raw,
4269 sizeof(edp_config_set.raw));
4271 ASSERT(result == DC_OK);
4274 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4275 "eDP panel mode enabled: %d \n",
4277 link->dpcd_caps.panel_mode_edp,
4281 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4283 /* We need to explicitly check that connector
4284 * is not DP. Some Travis_VGA get reported
4285 * by video bios as DP.
4287 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4289 switch (link->dpcd_caps.branch_dev_id) {
4290 case DP_BRANCH_DEVICE_ID_0022B9:
4291 /* alternate scrambler reset is required for Travis
4292 * for the case when external chip does not
4293 * provide sink device id, alternate scrambler
4294 * scheme will be overriden later by querying
4298 link->dpcd_caps.branch_dev_name,
4299 DP_VGA_LVDS_CONVERTER_ID_2,
4302 branch_dev_name)) == 0) {
4303 return DP_PANEL_MODE_SPECIAL;
4306 case DP_BRANCH_DEVICE_ID_00001A:
4307 /* alternate scrambler reset is required for Travis
4308 * for the case when external chip does not provide
4309 * sink device id, alternate scrambler scheme will
4310 * be overriden later by querying Encoder feature
4312 if (strncmp(link->dpcd_caps.branch_dev_name,
4313 DP_VGA_LVDS_CONVERTER_ID_3,
4316 branch_dev_name)) == 0) {
4317 return DP_PANEL_MODE_SPECIAL;
4325 if (link->dpcd_caps.panel_mode_edp) {
4326 return DP_PANEL_MODE_EDP;
4329 return DP_PANEL_MODE_DEFAULT;
4332 void dp_set_fec_ready(struct dc_link *link, bool ready)
4334 /* FEC has to be "set ready" before the link training.
4335 * The policy is to always train with FEC
4336 * if the sink supports it and leave it enabled on link.
4337 * If FEC is not supported, disable it.
4339 struct link_encoder *link_enc = link->link_enc;
4340 uint8_t fec_config = 0;
4342 if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
4345 if (link_enc->funcs->fec_set_ready &&
4346 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4349 if (core_link_write_dpcd(link,
4350 DP_FEC_CONFIGURATION,
4352 sizeof(fec_config)) == DC_OK) {
4353 link_enc->funcs->fec_set_ready(link_enc, true);
4354 link->fec_state = dc_link_fec_ready;
4356 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4357 link->fec_state = dc_link_fec_not_ready;
4358 dm_error("dpcd write failed to set fec_ready");
4360 } else if (link->fec_state == dc_link_fec_ready) {
4362 core_link_write_dpcd(link,
4363 DP_FEC_CONFIGURATION,
4365 sizeof(fec_config));
4366 link->link_enc->funcs->fec_set_ready(
4367 link->link_enc, false);
4368 link->fec_state = dc_link_fec_not_ready;
4373 void dp_set_fec_enable(struct dc_link *link, bool enable)
4375 struct link_encoder *link_enc = link->link_enc;
4377 if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
4380 if (link_enc->funcs->fec_set_enable &&
4381 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4382 if (link->fec_state == dc_link_fec_ready && enable) {
4383 /* Accord to DP spec, FEC enable sequence can first
4384 * be transmitted anytime after 1000 LL codes have
4385 * been transmitted on the link after link training
4386 * completion. Using 1 lane RBR should have the maximum
4387 * time for transmitting 1000 LL codes which is 6.173 us.
4388 * So use 7 microseconds delay instead.
4391 link_enc->funcs->fec_set_enable(link_enc, true);
4392 link->fec_state = dc_link_fec_enabled;
4393 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4394 link_enc->funcs->fec_set_enable(link_enc, false);
4395 link->fec_state = dc_link_fec_ready;
4400 void dpcd_set_source_specific_data(struct dc_link *link)
4402 if (!link->dc->vendor_signature.is_valid) {
4403 enum dc_status result_write_min_hblank = DC_NOT_SUPPORTED;
4404 struct dpcd_amd_signature amd_signature;
4405 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4406 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4407 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4408 amd_signature.device_id_byte1 =
4409 (uint8_t)(link->ctx->asic_id.chip_id);
4410 amd_signature.device_id_byte2 =
4411 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4412 memset(&amd_signature.zero, 0, 4);
4413 amd_signature.dce_version =
4414 (uint8_t)(link->ctx->dce_version);
4415 amd_signature.dal_version_byte1 = 0x0; // needed? where to get?
4416 amd_signature.dal_version_byte2 = 0x0; // needed? where to get?
4418 core_link_write_dpcd(link, DP_SOURCE_OUI,
4419 (uint8_t *)(&amd_signature),
4420 sizeof(amd_signature));
4422 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4423 link->dc->caps.min_horizontal_blanking_period != 0) {
4425 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4427 result_write_min_hblank = core_link_write_dpcd(link,
4428 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4429 sizeof(hblank_size));
4431 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4432 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4433 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4434 result_write_min_hblank,
4436 link->ctx->dce_version,
4437 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4438 link->dc->caps.min_horizontal_blanking_period,
4439 link->dpcd_caps.branch_dev_id,
4440 link->dpcd_caps.branch_dev_name[0],
4441 link->dpcd_caps.branch_dev_name[1],
4442 link->dpcd_caps.branch_dev_name[2],
4443 link->dpcd_caps.branch_dev_name[3],
4444 link->dpcd_caps.branch_dev_name[4],
4445 link->dpcd_caps.branch_dev_name[5]);
4447 core_link_write_dpcd(link, DP_SOURCE_OUI,
4448 link->dc->vendor_signature.data.raw,
4449 sizeof(link->dc->vendor_signature.data.raw));
4453 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4455 uint32_t backlight_millinits,
4456 uint32_t transition_time_in_ms)
4458 struct dpcd_source_backlight_set dpcd_backlight_set;
4459 uint8_t backlight_control = isHDR ? 1 : 0;
4461 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4462 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4465 // OLEDs have no PWM, they can only use AUX
4466 if (link->dpcd_sink_ext_caps.bits.oled == 1)
4467 backlight_control = 1;
4469 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4470 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4473 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4474 (uint8_t *)(&dpcd_backlight_set),
4475 sizeof(dpcd_backlight_set)) != DC_OK)
4478 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4479 &backlight_control, 1) != DC_OK)
4485 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4486 uint32_t *backlight_millinits_avg,
4487 uint32_t *backlight_millinits_peak)
4489 union dpcd_source_backlight_get dpcd_backlight_get;
4491 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4493 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4494 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4497 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4498 dpcd_backlight_get.raw,
4499 sizeof(union dpcd_source_backlight_get)) != DC_OK)
4502 *backlight_millinits_avg =
4503 dpcd_backlight_get.bytes.backlight_millinits_avg;
4504 *backlight_millinits_peak =
4505 dpcd_backlight_get.bytes.backlight_millinits_peak;
4507 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4508 if (*backlight_millinits_avg == 0 ||
4509 *backlight_millinits_avg > *backlight_millinits_peak)
4515 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4517 uint8_t backlight_enable = enable ? 1 : 0;
4519 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4520 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4523 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4524 &backlight_enable, 1) != DC_OK)
4530 // we read default from 0x320 because we expect BIOS wrote it there
4531 // regular get_backlight_nit reads from panel set at 0x326
4532 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4534 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4535 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4538 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4539 (uint8_t *) backlight_millinits,
4540 sizeof(uint32_t)) != DC_OK)
4546 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4548 uint32_t default_backlight;
4551 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4552 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4553 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4554 default_backlight = 150000;
4555 // if < 5 nits or > 5000, it might be wrong readback
4556 if (default_backlight < 5000 || default_backlight > 5000000)
4557 default_backlight = 150000; //
4559 return dc_link_set_backlight_level_nits(link, true,
4560 default_backlight, 0);