2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/slab.h>
28 #include "dm_services.h"
32 #include "core_status.h"
33 #include "core_types.h"
34 #include "hw_sequencer.h"
35 #include "dce/dce_hwseq.h"
40 #include "clock_source.h"
41 #include "dc_bios_types.h"
43 #include "bios_parser_interface.h"
44 #include "bios/bios_parser_helper.h"
45 #include "include/irq_service_interface.h"
46 #include "transform.h"
49 #include "timing_generator.h"
51 #include "virtual/virtual_link_encoder.h"
54 #include "link_hwss.h"
55 #include "link_encoder.h"
56 #include "link_enc_cfg.h"
59 #include "dc_link_ddc.h"
60 #include "dm_helpers.h"
61 #include "mem_input.h"
63 #include "dc_link_dp.h"
64 #include "dc_dmub_srv.h"
68 #include "vm_helper.h"
70 #include "dce/dce_i2c.h"
72 #include "dmub/dmub_srv.h"
74 #include "i2caux_interface.h"
75 #include "dce/dmub_hw_lock_mgr.h"
85 static const char DC_BUILD_ID[] = "production-build";
90 * DC is the OS-agnostic component of the amdgpu DC driver.
92 * DC maintains and validates a set of structs representing the state of the
93 * driver and writes that state to AMD hardware
97 * struct dc - The central struct. One per driver. Created on driver load,
98 * destroyed on driver unload.
100 * struct dc_context - One per driver.
101 * Used as a backpointer by most other structs in dc.
103 * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
104 * plugpoints). Created on driver load, destroyed on driver unload.
106 * struct dc_sink - One per display. Created on boot or hotplug.
107 * Destroyed on shutdown or hotunplug. A dc_link can have a local sink
108 * (the display directly attached). It may also have one or more remote
109 * sinks (in the Multi-Stream Transport case)
111 * struct resource_pool - One per driver. Represents the hw blocks not in the
112 * main pipeline. Not directly accessible by dm.
114 * Main dc state structs:
116 * These structs can be created and destroyed as needed. There is a full set of
117 * these structs in dc->current_state representing the currently programmed state.
119 * struct dc_state - The global DC state to track global state information,
120 * such as bandwidth values.
122 * struct dc_stream_state - Represents the hw configuration for the pipeline from
123 * a framebuffer to a display. Maps one-to-one with dc_sink.
125 * struct dc_plane_state - Represents a framebuffer. Each stream has at least one,
126 * and may have more in the Multi-Plane Overlay case.
128 * struct resource_context - Represents the programmable state of everything in
129 * the resource_pool. Not directly accessible by dm.
131 * struct pipe_ctx - A member of struct resource_context. Represents the
132 * internal hardware pipeline components. Each dc_plane_state has either
133 * one or two (in the pipe-split case).
136 /*******************************************************************************
138 ******************************************************************************/
140 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
146 static void destroy_links(struct dc *dc)
150 for (i = 0; i < dc->link_count; i++) {
151 if (NULL != dc->links[i])
152 link_destroy(&dc->links[i]);
156 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
161 for (i = 0; i < num_links; i++) {
162 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
163 links[i]->is_internal_display)
170 static int get_seamless_boot_stream_count(struct dc_state *ctx)
173 uint8_t seamless_boot_stream_count = 0;
175 for (i = 0; i < ctx->stream_count; i++)
176 if (ctx->streams[i]->apply_seamless_boot_optimization)
177 seamless_boot_stream_count++;
179 return seamless_boot_stream_count;
182 static bool create_links(
184 uint32_t num_virtual_links)
188 struct dc_bios *bios = dc->ctx->dc_bios;
192 connectors_num = bios->funcs->get_connectors_number(bios);
194 DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
196 if (connectors_num > ENUM_ID_COUNT) {
198 "DC: Number of connectors %d exceeds maximum of %d!\n",
204 dm_output_to_console(
205 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
210 for (i = 0; i < connectors_num; i++) {
211 struct link_init_data link_init_params = {0};
212 struct dc_link *link;
214 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
216 link_init_params.ctx = dc->ctx;
217 /* next BIOS object table connector */
218 link_init_params.connector_index = i;
219 link_init_params.link_index = dc->link_count;
220 link_init_params.dc = dc;
221 link = link_create(&link_init_params);
224 dc->links[dc->link_count] = link;
230 DC_LOG_DC("BIOS object table - end");
232 for (i = 0; i < num_virtual_links; i++) {
233 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
234 struct encoder_init_data enc_init = {0};
241 link->link_index = dc->link_count;
242 dc->links[dc->link_count] = link;
247 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
248 link->link_id.type = OBJECT_TYPE_CONNECTOR;
249 link->link_id.id = CONNECTOR_ID_VIRTUAL;
250 link->link_id.enum_id = ENUM_ID_1;
251 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
253 if (!link->link_enc) {
258 link->link_status.dpcd_caps = &link->dpcd_caps;
260 enc_init.ctx = dc->ctx;
261 enc_init.channel = CHANNEL_ID_UNKNOWN;
262 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
263 enc_init.transmitter = TRANSMITTER_UNKNOWN;
264 enc_init.connector = link->link_id;
265 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
266 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
267 enc_init.encoder.enum_id = ENUM_ID_1;
268 virtual_link_encoder_construct(link->link_enc, &enc_init);
271 dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
279 static struct dc_perf_trace *dc_perf_trace_create(void)
281 return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
284 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
291 * dc_stream_adjust_vmin_vmax:
293 * Looks up the pipe context of dc_stream_state and updates the
294 * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
295 * Rate, which is a power-saving feature that targets reducing panel
296 * refresh rate while the screen is static
299 * @stream: Initial dc stream state
300 * @adjust: Updated parameters for vertical_total_min and vertical_total_max
302 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
303 struct dc_stream_state *stream,
304 struct dc_crtc_timing_adjust *adjust)
309 stream->adjust.v_total_max = adjust->v_total_max;
310 stream->adjust.v_total_mid = adjust->v_total_mid;
311 stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
312 stream->adjust.v_total_min = adjust->v_total_min;
314 for (i = 0; i < MAX_PIPES; i++) {
315 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
317 if (pipe->stream == stream && pipe->stream_res.tg) {
318 dc->hwss.set_drr(&pipe,
329 *****************************************************************************
330 * Function: dc_stream_get_last_vrr_vtotal
333 * Looks up the pipe context of dc_stream_state and gets the
334 * last VTOTAL used by DRR (Dynamic Refresh Rate)
336 * @param [in] dc: dc reference
337 * @param [in] stream: Initial dc stream state
338 * @param [in] adjust: Updated parameters for vertical_total_min and
340 *****************************************************************************
342 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
343 struct dc_stream_state *stream,
344 uint32_t *refresh_rate)
350 for (i = 0; i < MAX_PIPES; i++) {
351 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
353 if (pipe->stream == stream && pipe->stream_res.tg) {
354 /* Only execute if a function pointer has been defined for
355 * the DC version in question
357 if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
358 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
370 bool dc_stream_get_crtc_position(struct dc *dc,
371 struct dc_stream_state **streams, int num_streams,
372 unsigned int *v_pos, unsigned int *nom_v_pos)
374 /* TODO: Support multiple streams */
375 const struct dc_stream_state *stream = streams[0];
378 struct crtc_position position;
380 for (i = 0; i < MAX_PIPES; i++) {
381 struct pipe_ctx *pipe =
382 &dc->current_state->res_ctx.pipe_ctx[i];
384 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
385 dc->hwss.get_position(&pipe, 1, &position);
387 *v_pos = position.vertical_count;
388 *nom_v_pos = position.nominal_vcount;
395 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
396 bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream,
397 struct crc_params *crc_window)
400 struct dmcu *dmcu = dc->res_pool->dmcu;
401 struct pipe_ctx *pipe;
402 struct crc_region tmp_win, *crc_win;
403 struct otg_phy_mux mapping_tmp, *mux_mapping;
405 /*crc window can't be null*/
409 if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
411 mux_mapping = &mapping_tmp;
413 tmp_win.x_start = crc_window->windowa_x_start;
414 tmp_win.y_start = crc_window->windowa_y_start;
415 tmp_win.x_end = crc_window->windowa_x_end;
416 tmp_win.y_end = crc_window->windowa_y_end;
418 for (i = 0; i < MAX_PIPES; i++) {
419 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
420 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
424 /* Stream not found */
429 /*set mux routing info*/
430 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
431 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
433 dmcu->funcs->forward_crc_window(dmcu, crc_win, mux_mapping);
435 DC_LOG_DC("dmcu is not initialized");
442 bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, struct dc_stream_state *stream)
445 struct dmcu *dmcu = dc->res_pool->dmcu;
446 struct pipe_ctx *pipe;
447 struct otg_phy_mux mapping_tmp, *mux_mapping;
449 if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
450 mux_mapping = &mapping_tmp;
452 for (i = 0; i < MAX_PIPES; i++) {
453 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
454 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
458 /* Stream not found */
463 /*set mux routing info*/
464 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
465 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
467 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
469 DC_LOG_DC("dmcu is not initialized");
478 * dc_stream_configure_crc() - Configure CRC capture for the given stream.
480 * @stream: The stream to configure CRC on.
481 * @enable: Enable CRC if true, disable otherwise.
482 * @crc_window: CRC window (x/y start/end) information
483 * @continuous: Capture CRC on every frame if true. Otherwise, only capture
486 * By default, only CRC0 is configured, and the entire frame is used to
489 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
490 struct crc_params *crc_window, bool enable, bool continuous)
493 struct pipe_ctx *pipe;
494 struct crc_params param;
495 struct timing_generator *tg;
497 for (i = 0; i < MAX_PIPES; i++) {
498 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
499 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
502 /* Stream not found */
506 /* By default, capture the full frame */
507 param.windowa_x_start = 0;
508 param.windowa_y_start = 0;
509 param.windowa_x_end = pipe->stream->timing.h_addressable;
510 param.windowa_y_end = pipe->stream->timing.v_addressable;
511 param.windowb_x_start = 0;
512 param.windowb_y_start = 0;
513 param.windowb_x_end = pipe->stream->timing.h_addressable;
514 param.windowb_y_end = pipe->stream->timing.v_addressable;
517 param.windowa_x_start = crc_window->windowa_x_start;
518 param.windowa_y_start = crc_window->windowa_y_start;
519 param.windowa_x_end = crc_window->windowa_x_end;
520 param.windowa_y_end = crc_window->windowa_y_end;
521 param.windowb_x_start = crc_window->windowb_x_start;
522 param.windowb_y_start = crc_window->windowb_y_start;
523 param.windowb_x_end = crc_window->windowb_x_end;
524 param.windowb_y_end = crc_window->windowb_y_end;
527 param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
528 param.odm_mode = pipe->next_odm_pipe ? 1:0;
530 /* Default to the union of both windows */
531 param.selection = UNION_WINDOW_A_B;
532 param.continuous_mode = continuous;
533 param.enable = enable;
535 tg = pipe->stream_res.tg;
537 /* Only call if supported */
538 if (tg->funcs->configure_crc)
539 return tg->funcs->configure_crc(tg, ¶m);
540 DC_LOG_WARNING("CRC capture not supported.");
545 * dc_stream_get_crc() - Get CRC values for the given stream.
547 * @stream: The DC stream state of the stream to get CRCs from.
548 * @r_cr: CRC value for the first of the 3 channels stored here.
549 * @g_y: CRC value for the second of the 3 channels stored here.
550 * @b_cb: CRC value for the third of the 3 channels stored here.
552 * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
553 * Return false if stream is not found, or if CRCs are not enabled.
555 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
556 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
559 struct pipe_ctx *pipe;
560 struct timing_generator *tg;
562 for (i = 0; i < MAX_PIPES; i++) {
563 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
564 if (pipe->stream == stream)
567 /* Stream not found */
571 tg = pipe->stream_res.tg;
573 if (tg->funcs->get_crc)
574 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
575 DC_LOG_WARNING("CRC capture not supported.");
579 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
580 enum dc_dynamic_expansion option)
582 /* OPP FMT dyn expansion updates*/
584 struct pipe_ctx *pipe_ctx;
586 for (i = 0; i < MAX_PIPES; i++) {
587 if (dc->current_state->res_ctx.pipe_ctx[i].stream
589 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
590 pipe_ctx->stream_res.opp->dyn_expansion = option;
591 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
592 pipe_ctx->stream_res.opp,
593 COLOR_SPACE_YCBCR601,
594 stream->timing.display_color_depth,
600 void dc_stream_set_dither_option(struct dc_stream_state *stream,
601 enum dc_dither_option option)
603 struct bit_depth_reduction_params params;
604 struct dc_link *link = stream->link;
605 struct pipe_ctx *pipes = NULL;
608 for (i = 0; i < MAX_PIPES; i++) {
609 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
611 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
618 if (option > DITHER_OPTION_MAX)
621 stream->dither_option = option;
623 memset(¶ms, 0, sizeof(params));
624 resource_build_bit_depth_reduction_params(stream, ¶ms);
625 stream->bit_depth_params = params;
627 if (pipes->plane_res.xfm &&
628 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
629 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
630 pipes->plane_res.xfm,
631 pipes->plane_res.scl_data.lb_params.depth,
632 &stream->bit_depth_params);
635 pipes->stream_res.opp->funcs->
636 opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms);
639 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
643 struct pipe_ctx *pipes;
645 for (i = 0; i < MAX_PIPES; i++) {
646 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
647 pipes = &dc->current_state->res_ctx.pipe_ctx[i];
648 dc->hwss.program_gamut_remap(pipes);
656 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
660 struct pipe_ctx *pipes;
662 for (i = 0; i < MAX_PIPES; i++) {
663 if (dc->current_state->res_ctx.pipe_ctx[i].stream
666 pipes = &dc->current_state->res_ctx.pipe_ctx[i];
667 dc->hwss.program_output_csc(dc,
669 stream->output_color_space,
670 stream->csc_color_matrix.matrix,
671 pipes->stream_res.opp->inst);
679 void dc_stream_set_static_screen_params(struct dc *dc,
680 struct dc_stream_state **streams,
682 const struct dc_static_screen_params *params)
685 struct pipe_ctx *pipes_affected[MAX_PIPES];
686 int num_pipes_affected = 0;
688 for (i = 0; i < num_streams; i++) {
689 struct dc_stream_state *stream = streams[i];
691 for (j = 0; j < MAX_PIPES; j++) {
692 if (dc->current_state->res_ctx.pipe_ctx[j].stream
694 pipes_affected[num_pipes_affected++] =
695 &dc->current_state->res_ctx.pipe_ctx[j];
700 dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
703 static void dc_destruct(struct dc *dc)
705 if (dc->current_state) {
706 dc_release_state(dc->current_state);
707 dc->current_state = NULL;
713 dc_destroy_clk_mgr(dc->clk_mgr);
717 dc_destroy_resource_pool(dc);
719 if (dc->ctx->gpio_service)
720 dal_gpio_service_destroy(&dc->ctx->gpio_service);
722 if (dc->ctx->created_bios)
723 dal_bios_parser_destroy(&dc->ctx->dc_bios);
725 dc_perf_trace_destroy(&dc->ctx->perf_trace);
736 #ifdef CONFIG_DRM_AMD_DC_DCN
744 kfree(dc->vm_helper);
745 dc->vm_helper = NULL;
749 static bool dc_construct_ctx(struct dc *dc,
750 const struct dc_init_data *init_params)
752 struct dc_context *dc_ctx;
753 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
755 dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
759 dc_ctx->cgs_device = init_params->cgs_device;
760 dc_ctx->driver_context = init_params->driver;
762 dc_ctx->asic_id = init_params->asic_id;
763 dc_ctx->dc_sink_id_count = 0;
764 dc_ctx->dc_stream_id_count = 0;
765 dc_ctx->dce_environment = init_params->dce_environment;
769 dc_version = resource_parse_asic_id(init_params->asic_id);
770 dc_ctx->dce_version = dc_version;
772 dc_ctx->perf_trace = dc_perf_trace_create();
773 if (!dc_ctx->perf_trace) {
774 ASSERT_CRITICAL(false);
783 static bool dc_construct(struct dc *dc,
784 const struct dc_init_data *init_params)
786 struct dc_context *dc_ctx;
787 struct bw_calcs_dceip *dc_dceip;
788 struct bw_calcs_vbios *dc_vbios;
789 #ifdef CONFIG_DRM_AMD_DC_DCN
790 struct dcn_soc_bounding_box *dcn_soc;
791 struct dcn_ip_params *dcn_ip;
794 dc->config = init_params->flags;
796 // Allocate memory for the vm_helper
797 dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
798 if (!dc->vm_helper) {
799 dm_error("%s: failed to create dc->vm_helper\n", __func__);
803 memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
805 dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
807 dm_error("%s: failed to create dceip\n", __func__);
811 dc->bw_dceip = dc_dceip;
813 dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
815 dm_error("%s: failed to create vbios\n", __func__);
819 dc->bw_vbios = dc_vbios;
820 #ifdef CONFIG_DRM_AMD_DC_DCN
821 dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
823 dm_error("%s: failed to create dcn_soc\n", __func__);
827 dc->dcn_soc = dcn_soc;
829 dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
831 dm_error("%s: failed to create dcn_ip\n", __func__);
838 if (!dc_construct_ctx(dc, init_params)) {
839 dm_error("%s: failed to create ctx\n", __func__);
845 /* Resource should construct all asic specific resources.
846 * This should be the only place where we need to parse the asic id
848 if (init_params->vbios_override)
849 dc_ctx->dc_bios = init_params->vbios_override;
851 /* Create BIOS parser */
852 struct bp_init_data bp_init_data;
854 bp_init_data.ctx = dc_ctx;
855 bp_init_data.bios = init_params->asic_id.atombios_base_address;
857 dc_ctx->dc_bios = dal_bios_parser_create(
858 &bp_init_data, dc_ctx->dce_version);
860 if (!dc_ctx->dc_bios) {
861 ASSERT_CRITICAL(false);
865 dc_ctx->created_bios = true;
868 dc->vendor_signature = init_params->vendor_signature;
870 /* Create GPIO service */
871 dc_ctx->gpio_service = dal_gpio_service_create(
873 dc_ctx->dce_environment,
876 if (!dc_ctx->gpio_service) {
877 ASSERT_CRITICAL(false);
881 dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
885 /* set i2c speed if not done by the respective dcnxxx__resource.c */
886 if (dc->caps.i2c_speed_in_khz_hdcp == 0)
887 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
889 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
892 #ifdef CONFIG_DRM_AMD_DC_DCN
893 dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
896 if (dc->res_pool->funcs->update_bw_bounding_box)
897 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
899 /* Creation of current_state must occur after dc->dml
900 * is initialized in dc_create_resource_pool because
901 * on creation it copies the contents of dc->dml
904 dc->current_state = dc_create_state(dc);
906 if (!dc->current_state) {
907 dm_error("%s: failed to create validate ctx\n", __func__);
911 dc_resource_state_construct(dc, dc->current_state);
913 if (!create_links(dc, init_params->num_virtual_links))
916 /* Initialise DIG link encoder resource tracking variables. */
917 link_enc_cfg_init(dc, dc->current_state);
925 static void disable_all_writeback_pipes_for_stream(
927 struct dc_stream_state *stream,
928 struct dc_state *context)
932 for (i = 0; i < stream->num_wb_info; i++)
933 stream->writeback_info[i].wb_enabled = false;
936 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context,
937 struct dc_stream_state *stream, bool lock)
941 /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
942 if (dc->hwss.interdependent_update_lock)
943 dc->hwss.interdependent_update_lock(dc, context, lock);
945 for (i = 0; i < dc->res_pool->pipe_count; i++) {
946 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
947 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
949 // Copied conditions that were previously in dce110_apply_ctx_for_surface
950 if (stream == pipe_ctx->stream) {
951 if (!pipe_ctx->top_pipe &&
952 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
953 dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
959 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
962 struct dc_state *dangling_context = dc_create_state(dc);
963 struct dc_state *current_ctx;
965 if (dangling_context == NULL)
968 dc_resource_state_copy_construct(dc->current_state, dangling_context);
970 for (i = 0; i < dc->res_pool->pipe_count; i++) {
971 struct dc_stream_state *old_stream =
972 dc->current_state->res_ctx.pipe_ctx[i].stream;
973 bool should_disable = true;
975 for (j = 0; j < context->stream_count; j++) {
976 if (old_stream == context->streams[j]) {
977 should_disable = false;
981 if (should_disable && old_stream) {
982 dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
983 disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
985 if (dc->hwss.apply_ctx_for_surface) {
986 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
987 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
988 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
989 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
991 if (dc->hwss.program_front_end_for_ctx) {
992 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
993 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
994 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
995 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1000 current_ctx = dc->current_state;
1001 dc->current_state = dangling_context;
1002 dc_release_state(current_ctx);
1005 static void disable_vbios_mode_if_required(
1007 struct dc_state *context)
1011 /* check if timing_changed, disable stream*/
1012 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1013 struct dc_stream_state *stream = NULL;
1014 struct dc_link *link = NULL;
1015 struct pipe_ctx *pipe = NULL;
1017 pipe = &context->res_ctx.pipe_ctx[i];
1018 stream = pipe->stream;
1022 // only looking for first odm pipe
1023 if (pipe->prev_odm_pipe)
1026 if (stream->link->local_sink &&
1027 stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1028 link = stream->link;
1031 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
1032 unsigned int enc_inst, tg_inst = 0;
1033 unsigned int pix_clk_100hz;
1035 enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1036 if (enc_inst != ENGINE_ID_UNKNOWN) {
1037 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
1038 if (dc->res_pool->stream_enc[j]->id == enc_inst) {
1039 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
1040 dc->res_pool->stream_enc[j]);
1045 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1046 dc->res_pool->dp_clock_source,
1047 tg_inst, &pix_clk_100hz);
1049 if (link->link_status.link_active) {
1050 uint32_t requested_pix_clk_100hz =
1051 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1053 if (pix_clk_100hz != requested_pix_clk_100hz) {
1054 core_link_disable_stream(pipe);
1055 pipe->stream->dpms_off = false;
1063 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1067 for (i = 0; i < MAX_PIPES; i++) {
1069 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1071 if (!pipe->plane_state)
1074 /* Timeout 100 ms */
1075 while (count < 100000) {
1076 /* Must set to false to start with, due to OR in update function */
1077 pipe->plane_state->status.is_flip_pending = false;
1078 dc->hwss.update_pending_status(pipe);
1079 if (!pipe->plane_state->status.is_flip_pending)
1084 ASSERT(!pipe->plane_state->status.is_flip_pending);
1089 /*******************************************************************************
1091 ******************************************************************************/
1093 struct dc *dc_create(const struct dc_init_data *init_params)
1095 struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1096 unsigned int full_pipe_count;
1101 if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1102 if (!dc_construct_ctx(dc, init_params))
1105 if (!dc_construct(dc, init_params))
1108 full_pipe_count = dc->res_pool->pipe_count;
1109 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1111 dc->caps.max_streams = min(
1113 dc->res_pool->stream_enc_count);
1115 dc->caps.max_links = dc->link_count;
1116 dc->caps.max_audios = dc->res_pool->audio_count;
1117 dc->caps.linear_pitch_alignment = 64;
1119 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1121 if (dc->res_pool->dmcu != NULL)
1122 dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1125 /* Populate versioning information */
1126 dc->versions.dc_ver = DC_VER;
1128 dc->build_id = DC_BUILD_ID;
1130 DC_LOG_DC("Display Core initialized\n");
1142 static void detect_edp_presence(struct dc *dc)
1144 struct dc_link *edp_links[MAX_NUM_EDP];
1145 struct dc_link *edp_link = NULL;
1146 enum dc_connection_type type;
1150 get_edp_links(dc, edp_links, &edp_num);
1154 for (i = 0; i < edp_num; i++) {
1155 edp_link = edp_links[i];
1156 if (dc->config.edp_not_connected) {
1157 edp_link->edp_sink_present = false;
1159 dc_link_detect_sink(edp_link, &type);
1160 edp_link->edp_sink_present = (type != dc_connection_none);
1165 void dc_hardware_init(struct dc *dc)
1168 detect_edp_presence(dc);
1169 if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1170 dc->hwss.init_hw(dc);
1173 void dc_init_callbacks(struct dc *dc,
1174 const struct dc_callback_init *init_params)
1176 #ifdef CONFIG_DRM_AMD_DC_HDCP
1177 dc->ctx->cp_psp = init_params->cp_psp;
1181 void dc_deinit_callbacks(struct dc *dc)
1183 #ifdef CONFIG_DRM_AMD_DC_HDCP
1184 memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1188 void dc_destroy(struct dc **dc)
1195 static void enable_timing_multisync(
1197 struct dc_state *ctx)
1199 int i, multisync_count = 0;
1200 int pipe_count = dc->res_pool->pipe_count;
1201 struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1203 for (i = 0; i < pipe_count; i++) {
1204 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1205 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1207 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1209 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1213 if (multisync_count > 0) {
1214 dc->hwss.enable_per_frame_crtc_position_reset(
1215 dc, multisync_count, multisync_pipes);
1219 static void program_timing_sync(
1221 struct dc_state *ctx)
1224 int group_index = 0;
1226 int pipe_count = dc->res_pool->pipe_count;
1227 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1229 for (i = 0; i < pipe_count; i++) {
1230 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
1233 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1236 for (i = 0; i < pipe_count; i++) {
1238 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1239 struct pipe_ctx *pipe_set[MAX_PIPES];
1241 if (!unsynced_pipes[i])
1244 pipe_set[0] = unsynced_pipes[i];
1245 unsynced_pipes[i] = NULL;
1247 /* Add tg to the set, search rest of the tg's for ones with
1248 * same timing, add all tgs with same timing to the group
1250 for (j = i + 1; j < pipe_count; j++) {
1251 if (!unsynced_pipes[j])
1253 if (sync_type != TIMING_SYNCHRONIZABLE &&
1254 dc->hwss.enable_vblanks_synchronization &&
1255 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1256 resource_are_vblanks_synchronizable(
1257 unsynced_pipes[j]->stream,
1258 pipe_set[0]->stream)) {
1259 sync_type = VBLANK_SYNCHRONIZABLE;
1260 pipe_set[group_size] = unsynced_pipes[j];
1261 unsynced_pipes[j] = NULL;
1264 if (sync_type != VBLANK_SYNCHRONIZABLE &&
1265 resource_are_streams_timing_synchronizable(
1266 unsynced_pipes[j]->stream,
1267 pipe_set[0]->stream)) {
1268 sync_type = TIMING_SYNCHRONIZABLE;
1269 pipe_set[group_size] = unsynced_pipes[j];
1270 unsynced_pipes[j] = NULL;
1275 /* set first unblanked pipe as master */
1276 for (j = 0; j < group_size; j++) {
1279 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1281 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1284 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1289 swap(pipe_set[0], pipe_set[j]);
1294 for (k = 0; k < group_size; k++) {
1295 struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1297 status->timing_sync_info.group_id = num_group;
1298 status->timing_sync_info.group_size = group_size;
1300 status->timing_sync_info.master = true;
1302 status->timing_sync_info.master = false;
1305 /* remove any other unblanked pipes as they have already been synced */
1306 for (j = j + 1; j < group_size; j++) {
1309 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1311 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1314 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1317 pipe_set[j] = pipe_set[group_size];
1322 if (group_size > 1) {
1323 if (sync_type == TIMING_SYNCHRONIZABLE) {
1324 dc->hwss.enable_timing_synchronization(
1325 dc, group_index, group_size, pipe_set);
1327 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1328 dc->hwss.enable_vblanks_synchronization(
1329 dc, group_index, group_size, pipe_set);
1337 static bool context_changed(
1339 struct dc_state *context)
1343 if (context->stream_count != dc->current_state->stream_count)
1346 for (i = 0; i < dc->current_state->stream_count; i++) {
1347 if (dc->current_state->streams[i] != context->streams[i])
1354 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1355 const struct dc_sink *sink,
1356 struct dc_crtc_timing *crtc_timing)
1358 struct timing_generator *tg;
1359 struct stream_encoder *se = NULL;
1361 struct dc_crtc_timing hw_crtc_timing = {0};
1363 struct dc_link *link = sink->link;
1364 unsigned int i, enc_inst, tg_inst = 0;
1366 /* Support seamless boot on EDP displays only */
1367 if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1371 /* Check for enabled DIG to identify enabled display */
1372 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1375 enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1377 if (enc_inst == ENGINE_ID_UNKNOWN)
1380 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1381 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1383 se = dc->res_pool->stream_enc[i];
1385 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1386 dc->res_pool->stream_enc[i]);
1391 // tg_inst not found
1392 if (i == dc->res_pool->stream_enc_count)
1395 if (tg_inst >= dc->res_pool->timing_generator_count)
1398 tg = dc->res_pool->timing_generators[tg_inst];
1400 if (!tg->funcs->get_hw_timing)
1403 if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1406 if (crtc_timing->h_total != hw_crtc_timing.h_total)
1409 if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1412 if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1415 if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1418 if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1421 if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1424 if (crtc_timing->v_total != hw_crtc_timing.v_total)
1427 if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1430 if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1433 if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1436 if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1439 if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1442 /* block DSC for now, as VBIOS does not currently support DSC timings */
1443 if (crtc_timing->flags.DSC)
1446 if (dc_is_dp_signal(link->connector_signal)) {
1447 unsigned int pix_clk_100hz;
1449 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1450 dc->res_pool->dp_clock_source,
1451 tg_inst, &pix_clk_100hz);
1453 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1456 if (!se->funcs->dp_get_pixel_format)
1459 if (!se->funcs->dp_get_pixel_format(
1461 &hw_crtc_timing.pixel_encoding,
1462 &hw_crtc_timing.display_color_depth))
1465 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1468 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1472 if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1476 if (is_edp_ilr_optimization_required(link, crtc_timing)) {
1477 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1484 static inline bool should_update_pipe_for_stream(
1485 struct dc_state *context,
1486 struct pipe_ctx *pipe_ctx,
1487 struct dc_stream_state *stream)
1489 return (pipe_ctx->stream && pipe_ctx->stream == stream);
1492 static inline bool should_update_pipe_for_plane(
1493 struct dc_state *context,
1494 struct pipe_ctx *pipe_ctx,
1495 struct dc_plane_state *plane_state)
1497 return (pipe_ctx->plane_state == plane_state);
1500 void dc_enable_stereo(
1502 struct dc_state *context,
1503 struct dc_stream_state *streams[],
1504 uint8_t stream_count)
1507 struct pipe_ctx *pipe;
1509 for (i = 0; i < MAX_PIPES; i++) {
1510 if (context != NULL) {
1511 pipe = &context->res_ctx.pipe_ctx[i];
1513 context = dc->current_state;
1514 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1517 for (j = 0; pipe && j < stream_count; j++) {
1518 if (should_update_pipe_for_stream(context, pipe, streams[j]) &&
1519 dc->hwss.setup_stereo)
1520 dc->hwss.setup_stereo(pipe, dc);
1525 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1527 if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1528 enable_timing_multisync(dc, context);
1529 program_timing_sync(dc, context);
1533 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1536 unsigned int stream_mask = 0;
1538 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1539 if (context->res_ctx.pipe_ctx[i].stream)
1540 stream_mask |= 1 << i;
1546 #if defined(CONFIG_DRM_AMD_DC_DCN)
1547 void dc_z10_restore(struct dc *dc)
1549 if (dc->hwss.z10_restore)
1550 dc->hwss.z10_restore(dc);
1553 void dc_z10_save_init(struct dc *dc)
1555 if (dc->hwss.z10_save_init)
1556 dc->hwss.z10_save_init(dc);
1560 * Applies given context to HW and copy it into current context.
1561 * It's up to the user to release the src context afterwards.
1563 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1565 struct dc_bios *dcb = dc->ctx->dc_bios;
1566 enum dc_status result = DC_ERROR_UNEXPECTED;
1567 struct pipe_ctx *pipe;
1569 struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1571 #if defined(CONFIG_DRM_AMD_DC_DCN)
1573 dc_allow_idle_optimizations(dc, false);
1576 for (i = 0; i < context->stream_count; i++)
1577 dc_streams[i] = context->streams[i];
1579 if (!dcb->funcs->is_accelerated_mode(dcb)) {
1580 disable_vbios_mode_if_required(dc, context);
1581 dc->hwss.enable_accelerated_mode(dc, context);
1584 if (context->stream_count > get_seamless_boot_stream_count(context) ||
1585 context->stream_count == 0)
1586 dc->hwss.prepare_bandwidth(dc, context);
1588 disable_dangling_plane(dc, context);
1589 /* re-program planes for existing stream, in case we need to
1590 * free up plane resource for later use
1592 if (dc->hwss.apply_ctx_for_surface) {
1593 for (i = 0; i < context->stream_count; i++) {
1594 if (context->streams[i]->mode_changed)
1596 apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1597 dc->hwss.apply_ctx_for_surface(
1598 dc, context->streams[i],
1599 context->stream_status[i].plane_count,
1600 context); /* use new pipe config in new context */
1601 apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1602 dc->hwss.post_unlock_program_front_end(dc, context);
1606 /* Program hardware */
1607 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1608 pipe = &context->res_ctx.pipe_ctx[i];
1609 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1612 result = dc->hwss.apply_ctx_to_hw(dc, context);
1614 if (result != DC_OK)
1617 dc_trigger_sync(dc, context);
1619 /* Program all planes within new context*/
1620 if (dc->hwss.program_front_end_for_ctx) {
1621 dc->hwss.interdependent_update_lock(dc, context, true);
1622 dc->hwss.program_front_end_for_ctx(dc, context);
1623 dc->hwss.interdependent_update_lock(dc, context, false);
1624 dc->hwss.post_unlock_program_front_end(dc, context);
1626 for (i = 0; i < context->stream_count; i++) {
1627 const struct dc_link *link = context->streams[i]->link;
1629 if (!context->streams[i]->mode_changed)
1632 if (dc->hwss.apply_ctx_for_surface) {
1633 apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1634 dc->hwss.apply_ctx_for_surface(
1635 dc, context->streams[i],
1636 context->stream_status[i].plane_count,
1638 apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1639 dc->hwss.post_unlock_program_front_end(dc, context);
1644 * TODO rework dc_enable_stereo call to work with validation sets?
1646 for (k = 0; k < MAX_PIPES; k++) {
1647 pipe = &context->res_ctx.pipe_ctx[k];
1649 for (l = 0 ; pipe && l < context->stream_count; l++) {
1650 if (context->streams[l] &&
1651 context->streams[l] == pipe->stream &&
1652 dc->hwss.setup_stereo)
1653 dc->hwss.setup_stereo(pipe, dc);
1657 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1658 context->streams[i]->timing.h_addressable,
1659 context->streams[i]->timing.v_addressable,
1660 context->streams[i]->timing.h_total,
1661 context->streams[i]->timing.v_total,
1662 context->streams[i]->timing.pix_clk_100hz / 10);
1665 dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1667 if (context->stream_count > get_seamless_boot_stream_count(context) ||
1668 context->stream_count == 0) {
1669 /* Must wait for no flips to be pending before doing optimize bw */
1670 wait_for_no_pipes_pending(dc, context);
1671 /* pplib is notified if disp_num changed */
1672 dc->hwss.optimize_bandwidth(dc, context);
1675 if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1676 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1678 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1680 context->stream_mask = get_stream_mask(dc, context);
1682 if (context->stream_mask != dc->current_state->stream_mask)
1683 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1685 for (i = 0; i < context->stream_count; i++)
1686 context->streams[i]->mode_changed = false;
1688 dc_release_state(dc->current_state);
1690 dc->current_state = context;
1692 dc_retain_state(dc->current_state);
1697 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1699 enum dc_status result = DC_ERROR_UNEXPECTED;
1702 if (!context_changed(dc, context))
1705 DC_LOG_DC("%s: %d streams\n",
1706 __func__, context->stream_count);
1708 for (i = 0; i < context->stream_count; i++) {
1709 struct dc_stream_state *stream = context->streams[i];
1711 dc_stream_log(dc, stream);
1714 result = dc_commit_state_no_check(dc, context);
1716 return (result == DC_OK);
1719 #if defined(CONFIG_DRM_AMD_DC_DCN)
1720 bool dc_acquire_release_mpc_3dlut(
1721 struct dc *dc, bool acquire,
1722 struct dc_stream_state *stream,
1723 struct dc_3dlut **lut,
1724 struct dc_transfer_func **shaper)
1728 bool found_pipe_idx = false;
1729 const struct resource_pool *pool = dc->res_pool;
1730 struct resource_context *res_ctx = &dc->current_state->res_ctx;
1733 if (pool && res_ctx) {
1735 /*find pipe idx for the given stream*/
1736 for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1737 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1738 found_pipe_idx = true;
1739 mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1744 found_pipe_idx = true;/*for release pipe_idx is not required*/
1746 if (found_pipe_idx) {
1747 if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1748 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1749 else if (!acquire && pool->funcs->release_post_bldn_3dlut)
1750 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1756 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1759 struct pipe_ctx *pipe;
1761 for (i = 0; i < MAX_PIPES; i++) {
1762 pipe = &context->res_ctx.pipe_ctx[i];
1764 if (!pipe->plane_state)
1767 /* Must set to false to start with, due to OR in update function */
1768 pipe->plane_state->status.is_flip_pending = false;
1769 dc->hwss.update_pending_status(pipe);
1770 if (pipe->plane_state->status.is_flip_pending)
1776 void dc_post_update_surfaces_to_stream(struct dc *dc)
1779 struct dc_state *context = dc->current_state;
1781 if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
1784 post_surface_trace(dc);
1786 if (is_flip_pending_in_pipes(dc, context))
1789 for (i = 0; i < dc->res_pool->pipe_count; i++)
1790 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1791 context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1792 context->res_ctx.pipe_ctx[i].pipe_idx = i;
1793 dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1796 dc->hwss.optimize_bandwidth(dc, context);
1798 dc->optimized_required = false;
1799 dc->wm_optimized_required = false;
1802 static void init_state(struct dc *dc, struct dc_state *context)
1804 /* Each context must have their own instance of VBA and in order to
1805 * initialize and obtain IP and SOC the base DML instance from DC is
1806 * initially copied into every context
1808 #ifdef CONFIG_DRM_AMD_DC_DCN
1809 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1813 struct dc_state *dc_create_state(struct dc *dc)
1815 struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1821 init_state(dc, context);
1823 kref_init(&context->refcount);
1828 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1831 struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1835 memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1837 for (i = 0; i < MAX_PIPES; i++) {
1838 struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1840 if (cur_pipe->top_pipe)
1841 cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1843 if (cur_pipe->bottom_pipe)
1844 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1846 if (cur_pipe->prev_odm_pipe)
1847 cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1849 if (cur_pipe->next_odm_pipe)
1850 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1854 for (i = 0; i < new_ctx->stream_count; i++) {
1855 dc_stream_retain(new_ctx->streams[i]);
1856 for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1857 dc_plane_state_retain(
1858 new_ctx->stream_status[i].plane_states[j]);
1861 kref_init(&new_ctx->refcount);
1866 void dc_retain_state(struct dc_state *context)
1868 kref_get(&context->refcount);
1871 static void dc_state_free(struct kref *kref)
1873 struct dc_state *context = container_of(kref, struct dc_state, refcount);
1874 dc_resource_state_destruct(context);
1878 void dc_release_state(struct dc_state *context)
1880 kref_put(&context->refcount, dc_state_free);
1883 bool dc_set_generic_gpio_for_stereo(bool enable,
1884 struct gpio_service *gpio_service)
1886 enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1887 struct gpio_pin_info pin_info;
1888 struct gpio *generic;
1889 struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1894 pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1896 if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1900 generic = dal_gpio_service_create_generic_mux(
1911 gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1913 config->enable_output_from_mux = enable;
1914 config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1916 if (gpio_result == GPIO_RESULT_OK)
1917 gpio_result = dal_mux_setup_config(generic, config);
1919 if (gpio_result == GPIO_RESULT_OK) {
1920 dal_gpio_close(generic);
1921 dal_gpio_destroy_generic_mux(&generic);
1925 dal_gpio_close(generic);
1926 dal_gpio_destroy_generic_mux(&generic);
1932 static bool is_surface_in_context(
1933 const struct dc_state *context,
1934 const struct dc_plane_state *plane_state)
1938 for (j = 0; j < MAX_PIPES; j++) {
1939 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1941 if (plane_state == pipe_ctx->plane_state) {
1949 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1951 union surface_update_flags *update_flags = &u->surface->update_flags;
1952 enum surface_update_type update_type = UPDATE_TYPE_FAST;
1955 return UPDATE_TYPE_FAST;
1957 if (u->plane_info->color_space != u->surface->color_space) {
1958 update_flags->bits.color_space_change = 1;
1959 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1962 if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1963 update_flags->bits.horizontal_mirror_change = 1;
1964 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1967 if (u->plane_info->rotation != u->surface->rotation) {
1968 update_flags->bits.rotation_change = 1;
1969 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1972 if (u->plane_info->format != u->surface->format) {
1973 update_flags->bits.pixel_format_change = 1;
1974 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1977 if (u->plane_info->stereo_format != u->surface->stereo_format) {
1978 update_flags->bits.stereo_format_change = 1;
1979 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1982 if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1983 update_flags->bits.per_pixel_alpha_change = 1;
1984 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1987 if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1988 update_flags->bits.global_alpha_change = 1;
1989 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1992 if (u->plane_info->dcc.enable != u->surface->dcc.enable
1993 || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1994 || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1995 /* During DCC on/off, stutter period is calculated before
1996 * DCC has fully transitioned. This results in incorrect
1997 * stutter period calculation. Triggering a full update will
1998 * recalculate stutter period.
2000 update_flags->bits.dcc_change = 1;
2001 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2004 if (resource_pixel_format_to_bpp(u->plane_info->format) !=
2005 resource_pixel_format_to_bpp(u->surface->format)) {
2006 /* different bytes per element will require full bandwidth
2007 * and DML calculation
2009 update_flags->bits.bpp_change = 1;
2010 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2013 if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
2014 || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
2015 update_flags->bits.plane_size_change = 1;
2016 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2020 if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
2021 sizeof(union dc_tiling_info)) != 0) {
2022 update_flags->bits.swizzle_change = 1;
2023 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2025 /* todo: below are HW dependent, we should add a hook to
2026 * DCE/N resource and validated there.
2028 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
2029 /* swizzled mode requires RQ to be setup properly,
2030 * thus need to run DML to calculate RQ settings
2032 update_flags->bits.bandwidth_change = 1;
2033 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2037 /* This should be UPDATE_TYPE_FAST if nothing has changed. */
2041 static enum surface_update_type get_scaling_info_update_type(
2042 const struct dc_surface_update *u)
2044 union surface_update_flags *update_flags = &u->surface->update_flags;
2046 if (!u->scaling_info)
2047 return UPDATE_TYPE_FAST;
2049 if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
2050 || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
2051 || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
2052 || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
2053 || u->scaling_info->scaling_quality.integer_scaling !=
2054 u->surface->scaling_quality.integer_scaling
2056 update_flags->bits.scaling_change = 1;
2058 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
2059 || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
2060 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
2061 || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
2062 /* Making dst rect smaller requires a bandwidth change */
2063 update_flags->bits.bandwidth_change = 1;
2066 if (u->scaling_info->src_rect.width != u->surface->src_rect.width
2067 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
2069 update_flags->bits.scaling_change = 1;
2070 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
2071 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
2072 /* Making src rect bigger requires a bandwidth change */
2073 update_flags->bits.clock_change = 1;
2076 if (u->scaling_info->src_rect.x != u->surface->src_rect.x
2077 || u->scaling_info->src_rect.y != u->surface->src_rect.y
2078 || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
2079 || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2080 || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2081 || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2082 update_flags->bits.position_change = 1;
2084 if (update_flags->bits.clock_change
2085 || update_flags->bits.bandwidth_change
2086 || update_flags->bits.scaling_change)
2087 return UPDATE_TYPE_FULL;
2089 if (update_flags->bits.position_change)
2090 return UPDATE_TYPE_MED;
2092 return UPDATE_TYPE_FAST;
2095 static enum surface_update_type det_surface_update(const struct dc *dc,
2096 const struct dc_surface_update *u)
2098 const struct dc_state *context = dc->current_state;
2099 enum surface_update_type type;
2100 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2101 union surface_update_flags *update_flags = &u->surface->update_flags;
2104 update_flags->bits.addr_update = 1;
2106 if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2107 update_flags->raw = 0xFFFFFFFF;
2108 return UPDATE_TYPE_FULL;
2111 update_flags->raw = 0; // Reset all flags
2113 type = get_plane_info_update_type(u);
2114 elevate_update_type(&overall_type, type);
2116 type = get_scaling_info_update_type(u);
2117 elevate_update_type(&overall_type, type);
2120 update_flags->bits.addr_update = 1;
2122 if (u->in_transfer_func)
2123 update_flags->bits.in_transfer_func_change = 1;
2125 if (u->input_csc_color_matrix)
2126 update_flags->bits.input_csc_change = 1;
2128 if (u->coeff_reduction_factor)
2129 update_flags->bits.coeff_reduction_change = 1;
2131 if (u->gamut_remap_matrix)
2132 update_flags->bits.gamut_remap_change = 1;
2135 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2138 format = u->plane_info->format;
2139 else if (u->surface)
2140 format = u->surface->format;
2142 if (dce_use_lut(format))
2143 update_flags->bits.gamma_change = 1;
2146 if (u->hdr_mult.value)
2147 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2148 update_flags->bits.hdr_mult = 1;
2149 elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2152 if (update_flags->bits.in_transfer_func_change) {
2153 type = UPDATE_TYPE_MED;
2154 elevate_update_type(&overall_type, type);
2157 if (update_flags->bits.input_csc_change
2158 || update_flags->bits.coeff_reduction_change
2159 || update_flags->bits.gamma_change
2160 || update_flags->bits.gamut_remap_change) {
2161 type = UPDATE_TYPE_FULL;
2162 elevate_update_type(&overall_type, type);
2165 return overall_type;
2168 static enum surface_update_type check_update_surfaces_for_stream(
2170 struct dc_surface_update *updates,
2172 struct dc_stream_update *stream_update,
2173 const struct dc_stream_status *stream_status)
2176 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2178 #if defined(CONFIG_DRM_AMD_DC_DCN)
2179 if (dc->idle_optimizations_allowed)
2180 overall_type = UPDATE_TYPE_FULL;
2183 if (stream_status == NULL || stream_status->plane_count != surface_count)
2184 overall_type = UPDATE_TYPE_FULL;
2186 if (stream_update && stream_update->pending_test_pattern) {
2187 overall_type = UPDATE_TYPE_FULL;
2190 /* some stream updates require passive update */
2191 if (stream_update) {
2192 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2194 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2195 (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2196 stream_update->integer_scaling_update)
2197 su_flags->bits.scaling = 1;
2199 if (stream_update->out_transfer_func)
2200 su_flags->bits.out_tf = 1;
2202 if (stream_update->abm_level)
2203 su_flags->bits.abm_level = 1;
2205 if (stream_update->dpms_off)
2206 su_flags->bits.dpms_off = 1;
2208 if (stream_update->gamut_remap)
2209 su_flags->bits.gamut_remap = 1;
2211 if (stream_update->wb_update)
2212 su_flags->bits.wb_update = 1;
2214 if (stream_update->dsc_config)
2215 su_flags->bits.dsc_changed = 1;
2217 if (su_flags->raw != 0)
2218 overall_type = UPDATE_TYPE_FULL;
2220 if (stream_update->output_csc_transform || stream_update->output_color_space)
2221 su_flags->bits.out_csc = 1;
2224 for (i = 0 ; i < surface_count; i++) {
2225 enum surface_update_type type =
2226 det_surface_update(dc, &updates[i]);
2228 elevate_update_type(&overall_type, type);
2231 return overall_type;
2235 * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2237 * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2239 enum surface_update_type dc_check_update_surfaces_for_stream(
2241 struct dc_surface_update *updates,
2243 struct dc_stream_update *stream_update,
2244 const struct dc_stream_status *stream_status)
2247 enum surface_update_type type;
2250 stream_update->stream->update_flags.raw = 0;
2251 for (i = 0; i < surface_count; i++)
2252 updates[i].surface->update_flags.raw = 0;
2254 type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2255 if (type == UPDATE_TYPE_FULL) {
2256 if (stream_update) {
2257 uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2258 stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2259 stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2261 for (i = 0; i < surface_count; i++)
2262 updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2265 if (type == UPDATE_TYPE_FAST) {
2266 // If there's an available clock comparator, we use that.
2267 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2268 if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2269 dc->optimized_required = true;
2270 // Else we fallback to mem compare.
2271 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2272 dc->optimized_required = true;
2275 dc->optimized_required |= dc->wm_optimized_required;
2281 static struct dc_stream_status *stream_get_status(
2282 struct dc_state *ctx,
2283 struct dc_stream_state *stream)
2287 for (i = 0; i < ctx->stream_count; i++) {
2288 if (stream == ctx->streams[i]) {
2289 return &ctx->stream_status[i];
2296 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2298 static void copy_surface_update_to_plane(
2299 struct dc_plane_state *surface,
2300 struct dc_surface_update *srf_update)
2302 if (srf_update->flip_addr) {
2303 surface->address = srf_update->flip_addr->address;
2304 surface->flip_immediate =
2305 srf_update->flip_addr->flip_immediate;
2306 surface->time.time_elapsed_in_us[surface->time.index] =
2307 srf_update->flip_addr->flip_timestamp_in_us -
2308 surface->time.prev_update_time_in_us;
2309 surface->time.prev_update_time_in_us =
2310 srf_update->flip_addr->flip_timestamp_in_us;
2311 surface->time.index++;
2312 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2313 surface->time.index = 0;
2315 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2318 if (srf_update->scaling_info) {
2319 surface->scaling_quality =
2320 srf_update->scaling_info->scaling_quality;
2322 srf_update->scaling_info->dst_rect;
2324 srf_update->scaling_info->src_rect;
2325 surface->clip_rect =
2326 srf_update->scaling_info->clip_rect;
2329 if (srf_update->plane_info) {
2330 surface->color_space =
2331 srf_update->plane_info->color_space;
2333 srf_update->plane_info->format;
2334 surface->plane_size =
2335 srf_update->plane_info->plane_size;
2337 srf_update->plane_info->rotation;
2338 surface->horizontal_mirror =
2339 srf_update->plane_info->horizontal_mirror;
2340 surface->stereo_format =
2341 srf_update->plane_info->stereo_format;
2342 surface->tiling_info =
2343 srf_update->plane_info->tiling_info;
2345 srf_update->plane_info->visible;
2346 surface->per_pixel_alpha =
2347 srf_update->plane_info->per_pixel_alpha;
2348 surface->global_alpha =
2349 srf_update->plane_info->global_alpha;
2350 surface->global_alpha_value =
2351 srf_update->plane_info->global_alpha_value;
2353 srf_update->plane_info->dcc;
2354 surface->layer_index =
2355 srf_update->plane_info->layer_index;
2358 if (srf_update->gamma &&
2359 (surface->gamma_correction !=
2360 srf_update->gamma)) {
2361 memcpy(&surface->gamma_correction->entries,
2362 &srf_update->gamma->entries,
2363 sizeof(struct dc_gamma_entries));
2364 surface->gamma_correction->is_identity =
2365 srf_update->gamma->is_identity;
2366 surface->gamma_correction->num_entries =
2367 srf_update->gamma->num_entries;
2368 surface->gamma_correction->type =
2369 srf_update->gamma->type;
2372 if (srf_update->in_transfer_func &&
2373 (surface->in_transfer_func !=
2374 srf_update->in_transfer_func)) {
2375 surface->in_transfer_func->sdr_ref_white_level =
2376 srf_update->in_transfer_func->sdr_ref_white_level;
2377 surface->in_transfer_func->tf =
2378 srf_update->in_transfer_func->tf;
2379 surface->in_transfer_func->type =
2380 srf_update->in_transfer_func->type;
2381 memcpy(&surface->in_transfer_func->tf_pts,
2382 &srf_update->in_transfer_func->tf_pts,
2383 sizeof(struct dc_transfer_func_distributed_points));
2386 if (srf_update->func_shaper &&
2387 (surface->in_shaper_func !=
2388 srf_update->func_shaper))
2389 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2390 sizeof(*surface->in_shaper_func));
2392 if (srf_update->lut3d_func &&
2393 (surface->lut3d_func !=
2394 srf_update->lut3d_func))
2395 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2396 sizeof(*surface->lut3d_func));
2398 if (srf_update->hdr_mult.value)
2400 srf_update->hdr_mult;
2402 if (srf_update->blend_tf &&
2403 (surface->blend_tf !=
2404 srf_update->blend_tf))
2405 memcpy(surface->blend_tf, srf_update->blend_tf,
2406 sizeof(*surface->blend_tf));
2408 if (srf_update->input_csc_color_matrix)
2409 surface->input_csc_color_matrix =
2410 *srf_update->input_csc_color_matrix;
2412 if (srf_update->coeff_reduction_factor)
2413 surface->coeff_reduction_factor =
2414 *srf_update->coeff_reduction_factor;
2416 if (srf_update->gamut_remap_matrix)
2417 surface->gamut_remap_matrix =
2418 *srf_update->gamut_remap_matrix;
2421 static void copy_stream_update_to_stream(struct dc *dc,
2422 struct dc_state *context,
2423 struct dc_stream_state *stream,
2424 struct dc_stream_update *update)
2426 struct dc_context *dc_ctx = dc->ctx;
2428 if (update == NULL || stream == NULL)
2431 if (update->src.height && update->src.width)
2432 stream->src = update->src;
2434 if (update->dst.height && update->dst.width)
2435 stream->dst = update->dst;
2437 if (update->out_transfer_func &&
2438 stream->out_transfer_func != update->out_transfer_func) {
2439 stream->out_transfer_func->sdr_ref_white_level =
2440 update->out_transfer_func->sdr_ref_white_level;
2441 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2442 stream->out_transfer_func->type =
2443 update->out_transfer_func->type;
2444 memcpy(&stream->out_transfer_func->tf_pts,
2445 &update->out_transfer_func->tf_pts,
2446 sizeof(struct dc_transfer_func_distributed_points));
2449 if (update->hdr_static_metadata)
2450 stream->hdr_static_metadata = *update->hdr_static_metadata;
2452 if (update->abm_level)
2453 stream->abm_level = *update->abm_level;
2455 if (update->periodic_interrupt0)
2456 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2458 if (update->periodic_interrupt1)
2459 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2461 if (update->gamut_remap)
2462 stream->gamut_remap_matrix = *update->gamut_remap;
2464 /* Note: this being updated after mode set is currently not a use case
2465 * however if it arises OCSC would need to be reprogrammed at the
2468 if (update->output_color_space)
2469 stream->output_color_space = *update->output_color_space;
2471 if (update->output_csc_transform)
2472 stream->csc_color_matrix = *update->output_csc_transform;
2474 if (update->vrr_infopacket)
2475 stream->vrr_infopacket = *update->vrr_infopacket;
2477 if (update->dpms_off)
2478 stream->dpms_off = *update->dpms_off;
2480 if (update->vsc_infopacket)
2481 stream->vsc_infopacket = *update->vsc_infopacket;
2483 if (update->vsp_infopacket)
2484 stream->vsp_infopacket = *update->vsp_infopacket;
2486 if (update->dither_option)
2487 stream->dither_option = *update->dither_option;
2489 if (update->pending_test_pattern)
2490 stream->test_pattern = *update->pending_test_pattern;
2491 /* update current stream with writeback info */
2492 if (update->wb_update) {
2495 stream->num_wb_info = update->wb_update->num_wb_info;
2496 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2497 for (i = 0; i < stream->num_wb_info; i++)
2498 stream->writeback_info[i] =
2499 update->wb_update->writeback_info[i];
2501 if (update->dsc_config) {
2502 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2503 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2504 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2505 update->dsc_config->num_slices_v != 0);
2507 /* Use temporarry context for validating new DSC config */
2508 struct dc_state *dsc_validate_context = dc_create_state(dc);
2510 if (dsc_validate_context) {
2511 dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2513 stream->timing.dsc_cfg = *update->dsc_config;
2514 stream->timing.flags.DSC = enable_dsc;
2515 if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2516 stream->timing.dsc_cfg = old_dsc_cfg;
2517 stream->timing.flags.DSC = old_dsc_enabled;
2518 update->dsc_config = NULL;
2521 dc_release_state(dsc_validate_context);
2523 DC_ERROR("Failed to allocate new validate context for DSC change\n");
2524 update->dsc_config = NULL;
2529 static void commit_planes_do_stream_update(struct dc *dc,
2530 struct dc_stream_state *stream,
2531 struct dc_stream_update *stream_update,
2532 enum surface_update_type update_type,
2533 struct dc_state *context)
2538 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2539 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2541 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2543 if (stream_update->periodic_interrupt0 &&
2544 dc->hwss.setup_periodic_interrupt)
2545 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2547 if (stream_update->periodic_interrupt1 &&
2548 dc->hwss.setup_periodic_interrupt)
2549 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2551 if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2552 stream_update->vrr_infopacket ||
2553 stream_update->vsc_infopacket ||
2554 stream_update->vsp_infopacket) {
2555 resource_build_info_frame(pipe_ctx);
2556 dc->hwss.update_info_frame(pipe_ctx);
2559 if (stream_update->hdr_static_metadata &&
2560 stream->use_dynamic_meta &&
2561 dc->hwss.set_dmdata_attributes &&
2562 pipe_ctx->stream->dmdata_address.quad_part != 0)
2563 dc->hwss.set_dmdata_attributes(pipe_ctx);
2565 if (stream_update->gamut_remap)
2566 dc_stream_set_gamut_remap(dc, stream);
2568 if (stream_update->output_csc_transform)
2569 dc_stream_program_csc_matrix(dc, stream);
2571 if (stream_update->dither_option) {
2572 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2573 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2574 &pipe_ctx->stream->bit_depth_params);
2575 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2576 &stream->bit_depth_params,
2579 odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2580 &stream->bit_depth_params,
2582 odm_pipe = odm_pipe->next_odm_pipe;
2588 if (update_type == UPDATE_TYPE_FAST)
2591 if (stream_update->dsc_config)
2592 dp_update_dsc_config(pipe_ctx);
2594 if (stream_update->pending_test_pattern) {
2595 dc_link_dp_set_test_pattern(stream->link,
2596 stream->test_pattern.type,
2597 stream->test_pattern.color_space,
2598 stream->test_pattern.p_link_settings,
2599 stream->test_pattern.p_custom_pattern,
2600 stream->test_pattern.cust_pattern_size);
2603 if (stream_update->dpms_off) {
2604 if (*stream_update->dpms_off) {
2605 core_link_disable_stream(pipe_ctx);
2606 /* for dpms, keep acquired resources*/
2607 if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2608 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2610 dc->optimized_required = true;
2613 if (get_seamless_boot_stream_count(context) == 0)
2614 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2616 core_link_enable_stream(dc->current_state, pipe_ctx);
2620 if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2621 bool should_program_abm = true;
2623 // if otg funcs defined check if blanked before programming
2624 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2625 if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2626 should_program_abm = false;
2628 if (should_program_abm) {
2629 if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2630 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2632 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2633 pipe_ctx->stream_res.abm, stream->abm_level);
2641 static void commit_planes_for_stream(struct dc *dc,
2642 struct dc_surface_update *srf_updates,
2644 struct dc_stream_state *stream,
2645 struct dc_stream_update *stream_update,
2646 enum surface_update_type update_type,
2647 struct dc_state *context)
2650 struct pipe_ctx *top_pipe_to_program = NULL;
2651 bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
2653 #if defined(CONFIG_DRM_AMD_DC_DCN)
2657 if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
2658 /* Optimize seamless boot flag keeps clocks and watermarks high until
2659 * first flip. After first flip, optimization is required to lower
2660 * bandwidth. Important to note that it is expected UEFI will
2661 * only light up a single display on POST, therefore we only expect
2662 * one stream with seamless boot flag set.
2664 if (stream->apply_seamless_boot_optimization) {
2665 stream->apply_seamless_boot_optimization = false;
2667 if (get_seamless_boot_stream_count(context) == 0)
2668 dc->optimized_required = true;
2672 if (update_type == UPDATE_TYPE_FULL) {
2673 #if defined(CONFIG_DRM_AMD_DC_DCN)
2674 dc_allow_idle_optimizations(dc, false);
2677 if (get_seamless_boot_stream_count(context) == 0)
2678 dc->hwss.prepare_bandwidth(dc, context);
2680 context_clock_trace(dc, context);
2683 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2684 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2686 if (!pipe_ctx->top_pipe &&
2687 !pipe_ctx->prev_odm_pipe &&
2689 pipe_ctx->stream == stream) {
2690 top_pipe_to_program = pipe_ctx;
2694 #ifdef CONFIG_DRM_AMD_DC_DCN
2695 if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
2696 struct pipe_ctx *mpcc_pipe;
2697 struct pipe_ctx *odm_pipe;
2699 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
2700 for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2701 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
2705 if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2706 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2707 if (should_use_dmub_lock(stream->link)) {
2708 union dmub_hw_lock_flags hw_locks = { 0 };
2709 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2711 hw_locks.bits.lock_dig = 1;
2712 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2714 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2719 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2720 top_pipe_to_program->stream_res.tg);
2723 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
2724 dc->hwss.interdependent_update_lock(dc, context, true);
2726 /* Lock the top pipe while updating plane addrs, since freesync requires
2727 * plane addr update event triggers to be synchronized.
2728 * top_pipe_to_program is expected to never be NULL
2730 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2734 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2736 if (surface_count == 0) {
2738 * In case of turning off screen, no need to program front end a second time.
2739 * just return after program blank.
2741 if (dc->hwss.apply_ctx_for_surface)
2742 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2743 if (dc->hwss.program_front_end_for_ctx)
2744 dc->hwss.program_front_end_for_ctx(dc, context);
2746 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
2747 dc->hwss.interdependent_update_lock(dc, context, false);
2749 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2750 dc->hwss.post_unlock_program_front_end(dc, context);
2754 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2755 for (i = 0; i < surface_count; i++) {
2756 struct dc_plane_state *plane_state = srf_updates[i].surface;
2757 /*set logical flag for lock/unlock use*/
2758 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2759 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2760 if (!pipe_ctx->plane_state)
2762 if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
2764 pipe_ctx->plane_state->triplebuffer_flips = false;
2765 if (update_type == UPDATE_TYPE_FAST &&
2766 dc->hwss.program_triplebuffer != NULL &&
2767 !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2768 /*triple buffer for VUpdate only*/
2769 pipe_ctx->plane_state->triplebuffer_flips = true;
2772 if (update_type == UPDATE_TYPE_FULL) {
2773 /* force vsync flip when reconfiguring pipes to prevent underflow */
2774 plane_state->flip_immediate = false;
2779 // Update Type FULL, Surface updates
2780 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2781 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2783 if (!pipe_ctx->top_pipe &&
2784 !pipe_ctx->prev_odm_pipe &&
2785 should_update_pipe_for_stream(context, pipe_ctx, stream)) {
2786 struct dc_stream_status *stream_status = NULL;
2788 if (!pipe_ctx->plane_state)
2792 if (update_type == UPDATE_TYPE_FAST)
2795 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2797 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2798 /*turn off triple buffer for full update*/
2799 dc->hwss.program_triplebuffer(
2800 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2803 stream_get_status(context, pipe_ctx->stream);
2805 if (dc->hwss.apply_ctx_for_surface)
2806 dc->hwss.apply_ctx_for_surface(
2807 dc, pipe_ctx->stream, stream_status->plane_count, context);
2810 if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2811 dc->hwss.program_front_end_for_ctx(dc, context);
2812 #ifdef CONFIG_DRM_AMD_DC_DCN
2813 if (dc->debug.validate_dml_output) {
2814 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2815 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2816 if (cur_pipe.stream == NULL)
2819 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2820 cur_pipe.plane_res.hubp, dc->ctx,
2821 &context->res_ctx.pipe_ctx[i].rq_regs,
2822 &context->res_ctx.pipe_ctx[i].dlg_regs,
2823 &context->res_ctx.pipe_ctx[i].ttu_regs);
2829 // Update Type FAST, Surface updates
2830 if (update_type == UPDATE_TYPE_FAST) {
2831 if (dc->hwss.set_flip_control_gsl)
2832 for (i = 0; i < surface_count; i++) {
2833 struct dc_plane_state *plane_state = srf_updates[i].surface;
2835 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2836 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2838 if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
2841 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
2844 // GSL has to be used for flip immediate
2845 dc->hwss.set_flip_control_gsl(pipe_ctx,
2846 pipe_ctx->plane_state->flip_immediate);
2850 /* Perform requested Updates */
2851 for (i = 0; i < surface_count; i++) {
2852 struct dc_plane_state *plane_state = srf_updates[i].surface;
2854 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2855 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2857 if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
2860 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
2863 /*program triple buffer after lock based on flip type*/
2864 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2865 /*only enable triplebuffer for fast_update*/
2866 dc->hwss.program_triplebuffer(
2867 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2869 if (pipe_ctx->plane_state->update_flags.bits.addr_update)
2870 dc->hwss.update_plane_addr(dc, pipe_ctx);
2876 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
2877 dc->hwss.interdependent_update_lock(dc, context, false);
2879 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2881 if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2882 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2883 top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2884 top_pipe_to_program->stream_res.tg,
2885 CRTC_STATE_VACTIVE);
2886 top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2887 top_pipe_to_program->stream_res.tg,
2889 top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2890 top_pipe_to_program->stream_res.tg,
2891 CRTC_STATE_VACTIVE);
2893 if (stream && should_use_dmub_lock(stream->link)) {
2894 union dmub_hw_lock_flags hw_locks = { 0 };
2895 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2897 hw_locks.bits.lock_dig = 1;
2898 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2900 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2905 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2906 top_pipe_to_program->stream_res.tg);
2909 if (update_type != UPDATE_TYPE_FAST)
2910 dc->hwss.post_unlock_program_front_end(dc, context);
2912 // Fire manual trigger only when bottom plane is flipped
2913 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2914 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2916 if (!pipe_ctx->plane_state)
2919 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
2920 !pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||
2921 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
2922 pipe_ctx->plane_state->skip_manual_trigger)
2925 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2926 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2930 void dc_commit_updates_for_stream(struct dc *dc,
2931 struct dc_surface_update *srf_updates,
2933 struct dc_stream_state *stream,
2934 struct dc_stream_update *stream_update,
2935 struct dc_state *state)
2937 const struct dc_stream_status *stream_status;
2938 enum surface_update_type update_type;
2939 struct dc_state *context;
2940 struct dc_context *dc_ctx = dc->ctx;
2943 stream_status = dc_stream_get_status(stream);
2944 context = dc->current_state;
2946 update_type = dc_check_update_surfaces_for_stream(
2947 dc, srf_updates, surface_count, stream_update, stream_status);
2949 if (update_type >= update_surface_trace_level)
2950 update_surface_trace(dc, srf_updates, surface_count);
2953 if (update_type >= UPDATE_TYPE_FULL) {
2955 /* initialize scratch memory for building context */
2956 context = dc_create_state(dc);
2957 if (context == NULL) {
2958 DC_ERROR("Failed to allocate new validate context!\n");
2962 dc_resource_state_copy_construct(state, context);
2964 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2965 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2966 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2968 if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2969 new_pipe->plane_state->force_full_update = true;
2974 for (i = 0; i < surface_count; i++) {
2975 struct dc_plane_state *surface = srf_updates[i].surface;
2977 copy_surface_update_to_plane(surface, &srf_updates[i]);
2979 if (update_type >= UPDATE_TYPE_MED) {
2980 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2981 struct pipe_ctx *pipe_ctx =
2982 &context->res_ctx.pipe_ctx[j];
2984 if (pipe_ctx->plane_state != surface)
2987 resource_build_scaling_params(pipe_ctx);
2992 copy_stream_update_to_stream(dc, context, stream, stream_update);
2994 if (update_type >= UPDATE_TYPE_FULL) {
2995 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2996 DC_ERROR("Mode validation failed for stream update!\n");
2997 dc_release_state(context);
3002 TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
3004 commit_planes_for_stream(
3012 /*update current_State*/
3013 if (dc->current_state != context) {
3015 struct dc_state *old = dc->current_state;
3017 dc->current_state = context;
3018 dc_release_state(old);
3020 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3021 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
3023 if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
3024 pipe_ctx->plane_state->force_full_update = false;
3027 /*let's use current_state to update watermark etc*/
3028 if (update_type >= UPDATE_TYPE_FULL) {
3029 dc_post_update_surfaces_to_stream(dc);
3031 if (dc_ctx->dce_version >= DCE_VERSION_MAX)
3032 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
3034 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
3041 uint8_t dc_get_current_stream_count(struct dc *dc)
3043 return dc->current_state->stream_count;
3046 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
3048 if (i < dc->current_state->stream_count)
3049 return dc->current_state->streams[i];
3053 struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link)
3056 struct dc_context *ctx = link->ctx;
3058 for (i = 0; i < ctx->dc->current_state->stream_count; i++) {
3059 if (ctx->dc->current_state->streams[i]->link == link)
3060 return ctx->dc->current_state->streams[i];
3066 enum dc_irq_source dc_interrupt_to_irq_source(
3071 return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
3075 * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
3077 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
3083 return dal_irq_service_set(dc->res_pool->irqs, src, enable);
3086 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
3088 dal_irq_service_ack(dc->res_pool->irqs, src);
3091 void dc_power_down_on_boot(struct dc *dc)
3093 if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
3094 dc->hwss.power_down_on_boot)
3095 dc->hwss.power_down_on_boot(dc);
3098 void dc_set_power_state(
3100 enum dc_acpi_cm_power_state power_state)
3102 struct kref refcount;
3103 struct display_mode_lib *dml;
3105 if (!dc->current_state)
3108 switch (power_state) {
3109 case DC_ACPI_CM_POWER_STATE_D0:
3110 dc_resource_state_construct(dc, dc->current_state);
3112 #if defined(CONFIG_DRM_AMD_DC_DCN)
3115 if (dc->ctx->dmub_srv)
3116 dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
3118 dc->hwss.init_hw(dc);
3120 if (dc->hwss.init_sys_ctx != NULL &&
3121 dc->vm_pa_config.valid) {
3122 dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
3127 ASSERT(dc->current_state->stream_count == 0);
3128 /* Zero out the current context so that on resume we start with
3129 * clean state, and dc hw programming optimizations will not
3130 * cause any trouble.
3132 dml = kzalloc(sizeof(struct display_mode_lib),
3139 /* Preserve refcount */
3140 refcount = dc->current_state->refcount;
3141 /* Preserve display mode lib */
3142 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
3144 dc_resource_state_destruct(dc->current_state);
3145 memset(dc->current_state, 0,
3146 sizeof(*dc->current_state));
3148 dc->current_state->refcount = refcount;
3149 dc->current_state->bw_ctx.dml = *dml;
3157 void dc_resume(struct dc *dc)
3161 for (i = 0; i < dc->link_count; i++)
3162 core_link_resume(dc->links[i]);
3165 bool dc_is_dmcu_initialized(struct dc *dc)
3167 struct dmcu *dmcu = dc->res_pool->dmcu;
3170 return dmcu->funcs->is_dmcu_initialized(dmcu);
3176 uint32_t link_index,
3177 struct i2c_command *cmd)
3180 struct dc_link *link = dc->links[link_index];
3181 struct ddc_service *ddc = link->ddc;
3182 return dce_i2c_submit_command(
3188 bool dc_submit_i2c_oem(
3190 struct i2c_command *cmd)
3192 struct ddc_service *ddc = dc->res_pool->oem_device;
3193 return dce_i2c_submit_command(
3199 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
3201 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
3202 BREAK_TO_DEBUGGER();
3206 dc_sink_retain(sink);
3208 dc_link->remote_sinks[dc_link->sink_count] = sink;
3209 dc_link->sink_count++;
3215 * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
3217 * EDID length is in bytes
3219 struct dc_sink *dc_link_add_remote_sink(
3220 struct dc_link *link,
3221 const uint8_t *edid,
3223 struct dc_sink_init_data *init_data)
3225 struct dc_sink *dc_sink;
3226 enum dc_edid_status edid_status;
3228 if (len > DC_MAX_EDID_BUFFER_SIZE) {
3229 dm_error("Max EDID buffer size breached!\n");
3234 BREAK_TO_DEBUGGER();
3238 if (!init_data->link) {
3239 BREAK_TO_DEBUGGER();
3243 dc_sink = dc_sink_create(init_data);
3248 memmove(dc_sink->dc_edid.raw_edid, edid, len);
3249 dc_sink->dc_edid.length = len;
3251 if (!link_add_remote_sink_helper(
3256 edid_status = dm_helpers_parse_edid_caps(
3259 &dc_sink->edid_caps);
3262 * Treat device as no EDID device if EDID
3265 if (edid_status != EDID_OK) {
3266 dc_sink->dc_edid.length = 0;
3267 dm_error("Bad EDID, status%d!\n", edid_status);
3273 dc_sink_release(dc_sink);
3278 * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
3280 * Note that this just removes the struct dc_sink - it doesn't
3281 * program hardware or alter other members of dc_link
3283 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
3287 if (!link->sink_count) {
3288 BREAK_TO_DEBUGGER();
3292 for (i = 0; i < link->sink_count; i++) {
3293 if (link->remote_sinks[i] == sink) {
3294 dc_sink_release(sink);
3295 link->remote_sinks[i] = NULL;
3297 /* shrink array to remove empty place */
3298 while (i < link->sink_count - 1) {
3299 link->remote_sinks[i] = link->remote_sinks[i+1];
3302 link->remote_sinks[i] = NULL;
3309 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
3311 info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
3312 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
3313 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
3314 info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
3315 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
3316 info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
3317 info->dcfClockDeepSleep = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
3318 info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
3319 info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
3321 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
3323 if (dc->hwss.set_clock)
3324 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
3325 return DC_ERROR_UNEXPECTED;
3327 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
3329 if (dc->hwss.get_clock)
3330 dc->hwss.get_clock(dc, clock_type, clock_cfg);
3333 /* enable/disable eDP PSR without specify stream for eDP */
3334 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
3338 for (i = 0; i < dc->current_state->stream_count ; i++) {
3339 struct dc_link *link;
3340 struct dc_stream_state *stream = dc->current_state->streams[i];
3342 link = stream->link;
3346 if (link->psr_settings.psr_feature_enabled) {
3347 if (enable && !link->psr_settings.psr_allow_active) {
3348 if (!dc_link_set_psr_allow_active(link, true, false, false))
3350 } else if (!enable && link->psr_settings.psr_allow_active) {
3351 if (!dc_link_set_psr_allow_active(link, false, true, false))
3360 #if defined(CONFIG_DRM_AMD_DC_DCN)
3362 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
3364 if (dc->debug.disable_idle_power_optimizations)
3367 if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
3368 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
3371 if (allow == dc->idle_optimizations_allowed)
3374 if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3375 dc->idle_optimizations_allowed = allow;
3379 * blank all streams, and set min and max memory clock to
3380 * lowest and highest DPM level, respectively
3382 void dc_unlock_memory_clock_frequency(struct dc *dc)
3386 for (i = 0; i < MAX_PIPES; i++)
3387 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3388 core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3390 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3391 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3395 * set min memory clock to the min required for current mode,
3396 * max to maxDPM, and unblank streams
3398 void dc_lock_memory_clock_frequency(struct dc *dc)
3402 dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3403 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3404 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3406 for (i = 0; i < MAX_PIPES; i++)
3407 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3408 core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3411 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
3412 struct dc_cursor_attributes *cursor_attr)
3414 if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
3419 /* cleanup on driver unload */
3420 void dc_hardware_release(struct dc *dc)
3422 if (dc->hwss.hardware_release)
3423 dc->hwss.hardware_release(dc);
3428 * dc_enable_dmub_notifications - Returns whether dmub notification can be enabled
3431 * Returns: True to enable dmub notifications, False otherwise
3433 bool dc_enable_dmub_notifications(struct dc *dc)
3435 /* dmub aux needs dmub notifications to be enabled */
3436 return dc->debug.enable_dmub_aux_for_legacy_ddc;
3440 * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
3441 * Sets port index appropriately for legacy DDC
3443 * @link_index: link index
3444 * @payload: aux payload
3446 * Returns: True if successful, False if failure
3448 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
3449 uint32_t link_index,
3450 struct aux_payload *payload)
3453 union dmub_rb_cmd cmd = {0};
3454 struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv;
3456 ASSERT(payload->length <= 16);
3458 cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
3459 cmd.dp_aux_access.header.payload_bytes = 0;
3460 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
3461 cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
3462 cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
3463 cmd.dp_aux_access.aux_control.timeout = 0;
3464 cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
3465 cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
3466 cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
3468 /* set aux action */
3469 if (payload->i2c_over_aux) {
3470 if (payload->write) {
3472 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
3474 action = DP_AUX_REQ_ACTION_I2C_WRITE;
3477 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
3479 action = DP_AUX_REQ_ACTION_I2C_READ;
3483 action = DP_AUX_REQ_ACTION_DPCD_WRITE;
3485 action = DP_AUX_REQ_ACTION_DPCD_READ;
3488 cmd.dp_aux_access.aux_control.dpaux.action = action;
3490 if (payload->length && payload->write) {
3491 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
3497 dc_dmub_srv_cmd_queue(dmub_srv, &cmd);
3498 dc_dmub_srv_cmd_execute(dmub_srv);
3499 dc_dmub_srv_wait_idle(dmub_srv);
3505 * dc_disable_accelerated_mode - disable accelerated mode
3508 void dc_disable_accelerated_mode(struct dc *dc)
3510 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);