drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "include/irq_service_interface.h"
  45 #include "transform.h"
  46 #include "dmcu.h"
  47 #include "dpp.h"
  48 #include "timing_generator.h"
  49 #include "abm.h"
  50 #include "virtual/virtual_link_encoder.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54
  55 #include "dc_link_ddc.h"
  56 #include "dm_helpers.h"
  57 #include "mem_input.h"
  58 #include "hubp.h"
  59
  60 #include "dc_link_dp.h"
  61 #include "dc_dmub_srv.h"
  62
  63 #include "dsc.h"
  64
  65 #include "vm_helper.h"
  66
  67 #include "dce/dce_i2c.h"
  68
  69 #include "dmub/dmub_srv.h"
  70
  71 #include "dce/dmub_hw_lock_mgr.h"
  72
  73 #include "dc_trace.h"
  74
  75 #define CTX \
  76         dc->ctx
  77
  78 #define DC_LOGGER \
  79         dc->ctx->logger
  80
  81 static const char DC_BUILD_ID[] = "production-build";
  82
  83 /**
  84  * DOC: Overview
  85  *
  86  * DC is the OS-agnostic component of the amdgpu DC driver.
  87  *
  88  * DC maintains and validates a set of structs representing the state of the
  89  * driver and writes that state to AMD hardware
  90  *
  91  * Main DC HW structs:
  92  *
  93  * struct dc - The central struct.  One per driver.  Created on driver load,
  94  * destroyed on driver unload.
  95  *
  96  * struct dc_context - One per driver.
  97  * Used as a backpointer by most other structs in dc.
  98  *
  99  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 100  * plugpoints).  Created on driver load, destroyed on driver unload.
 101  *
 102  * struct dc_sink - One per display.  Created on boot or hotplug.
 103  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 104  * (the display directly attached).  It may also have one or more remote
 105  * sinks (in the Multi-Stream Transport case)
 106  *
 107  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 108  * main pipeline.  Not directly accessible by dm.
 109  *
 110  * Main dc state structs:
 111  *
 112  * These structs can be created and destroyed as needed.  There is a full set of
 113  * these structs in dc->current_state representing the currently programmed state.
 114  *
 115  * struct dc_state - The global DC state to track global state information,
 116  * such as bandwidth values.
 117  *
 118  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 119  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 120  *
 121  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 122  * and may have more in the Multi-Plane Overlay case.
 123  *
 124  * struct resource_context - Represents the programmable state of everything in
 125  * the resource_pool.  Not directly accessible by dm.
 126  *
 127  * struct pipe_ctx - A member of struct resource_context.  Represents the
 128  * internal hardware pipeline components.  Each dc_plane_state has either
 129  * one or two (in the pipe-split case).
 130  */
 131
 132 /*******************************************************************************
 133  * Private functions
 134  ******************************************************************************/
 135
 136 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 137 {
 138         if (new > *original)
 139                 *original = new;
 140 }
 141
 142 static void destroy_links(struct dc *dc)
 143 {
 144         uint32_t i;
 145
 146         for (i = 0; i < dc->link_count; i++) {
 147                 if (NULL != dc->links[i])
 148                         link_destroy(&dc->links[i]);
 149         }
 150 }
 151
 152 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
 153 {
 154         int i;
 155         uint32_t count = 0;
 156
 157         for (i = 0; i < num_links; i++) {
 158                 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
 159                                 links[i]->is_internal_display)
 160                         count++;
 161         }
 162
 163         return count;
 164 }
 165
 166 static bool create_links(
 167                 struct dc *dc,
 168                 uint32_t num_virtual_links)
 169 {
 170         int i;
 171         int connectors_num;
 172         struct dc_bios *bios = dc->ctx->dc_bios;
 173
 174         dc->link_count = 0;
 175
 176         connectors_num = bios->funcs->get_connectors_number(bios);
 177
 178         if (connectors_num > ENUM_ID_COUNT) {
 179                 dm_error(
 180                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 181                         connectors_num,
 182                         ENUM_ID_COUNT);
 183                 return false;
 184         }
 185
 186         dm_output_to_console(
 187                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 188                 __func__,
 189                 connectors_num,
 190                 num_virtual_links);
 191
 192         for (i = 0; i < connectors_num; i++) {
 193                 struct link_init_data link_init_params = {0};
 194                 struct dc_link *link;
 195
 196                 link_init_params.ctx = dc->ctx;
 197                 /* next BIOS object table connector */
 198                 link_init_params.connector_index = i;
 199                 link_init_params.link_index = dc->link_count;
 200                 link_init_params.dc = dc;
 201                 link = link_create(&link_init_params);
 202
 203                 if (link) {
 204                         bool should_destory_link = false;
 205
 206                         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 207                                 if (dc->config.edp_not_connected) {
 208                                         if (!IS_DIAG_DC(dc->ctx->dce_environment))
 209                                                 should_destory_link = true;
 210                                 } else {
 211                                         enum dc_connection_type type;
 212                                         dc_link_detect_sink(link, &type);
 213                                         if (type == dc_connection_none)
 214                                                 should_destory_link = true;
 215                                 }
 216                         }
 217
 218                         if (dc->config.force_enum_edp || !should_destory_link) {
 219                                 dc->links[dc->link_count] = link;
 220                                 link->dc = dc;
 221                                 ++dc->link_count;
 222                         } else {
 223                                 link_destroy(&link);
 224                         }
 225                 }
 226         }
 227
 228         for (i = 0; i < num_virtual_links; i++) {
 229                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 230                 struct encoder_init_data enc_init = {0};
 231
 232                 if (link == NULL) {
 233                         BREAK_TO_DEBUGGER();
 234                         goto failed_alloc;
 235                 }
 236
 237                 link->link_index = dc->link_count;
 238                 dc->links[dc->link_count] = link;
 239                 dc->link_count++;
 240
 241                 link->ctx = dc->ctx;
 242                 link->dc = dc;
 243                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 244                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 245                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 246                 link->link_id.enum_id = ENUM_ID_1;
 247                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 248
 249                 if (!link->link_enc) {
 250                         BREAK_TO_DEBUGGER();
 251                         goto failed_alloc;
 252                 }
 253
 254                 link->link_status.dpcd_caps = &link->dpcd_caps;
 255
 256                 enc_init.ctx = dc->ctx;
 257                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 258                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 259                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 260                 enc_init.connector = link->link_id;
 261                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 262                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 263                 enc_init.encoder.enum_id = ENUM_ID_1;
 264                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 265         }
 266
 267         dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
 268
 269         return true;
 270
 271 failed_alloc:
 272         return false;
 273 }
 274
 275 static struct dc_perf_trace *dc_perf_trace_create(void)
 276 {
 277         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 278 }
 279
 280 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 281 {
 282         kfree(*perf_trace);
 283         *perf_trace = NULL;
 284 }
 285
 286 /**
 287  *****************************************************************************
 288  *  Function: dc_stream_adjust_vmin_vmax
 289  *
 290  *  @brief
 291  *     Looks up the pipe context of dc_stream_state and updates the
 292  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 293  *     Rate, which is a power-saving feature that targets reducing panel
 294  *     refresh rate while the screen is static
 295  *
 296  *  @param [in] dc: dc reference
 297  *  @param [in] stream: Initial dc stream state
 298  *  @param [in] adjust: Updated parameters for vertical_total_min and
 299  *  vertical_total_max
 300  *****************************************************************************
 301  */
 302 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 303                 struct dc_stream_state *stream,
 304                 struct dc_crtc_timing_adjust *adjust)
 305 {
 306         int i = 0;
 307         bool ret = false;
 308
 309         stream->adjust = *adjust;
 310
 311         for (i = 0; i < MAX_PIPES; i++) {
 312                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 313
 314                 if (pipe->stream == stream && pipe->stream_res.tg) {
 315                         dc->hwss.set_drr(&pipe,
 316                                         1,
 317                                         adjust->v_total_min,
 318                                         adjust->v_total_max,
 319                                         adjust->v_total_mid,
 320                                         adjust->v_total_mid_frame_num);
 321
 322                         ret = true;
 323                 }
 324         }
 325         return ret;
 326 }
 327
 328 bool dc_stream_get_crtc_position(struct dc *dc,
 329                 struct dc_stream_state **streams, int num_streams,
 330                 unsigned int *v_pos, unsigned int *nom_v_pos)
 331 {
 332         /* TODO: Support multiple streams */
 333         const struct dc_stream_state *stream = streams[0];
 334         int i = 0;
 335         bool ret = false;
 336         struct crtc_position position;
 337
 338         for (i = 0; i < MAX_PIPES; i++) {
 339                 struct pipe_ctx *pipe =
 340                                 &dc->current_state->res_ctx.pipe_ctx[i];
 341
 342                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 343                         dc->hwss.get_position(&pipe, 1, &position);
 344
 345                         *v_pos = position.vertical_count;
 346                         *nom_v_pos = position.nominal_vcount;
 347                         ret = true;
 348                 }
 349         }
 350         return ret;
 351 }
 352
 353 /**
 354  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 355  * @dc: DC Object
 356  * @stream: The stream to configure CRC on.
 357  * @enable: Enable CRC if true, disable otherwise.
 358  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 359  *              once.
 360  *
 361  * By default, only CRC0 is configured, and the entire frame is used to
 362  * calculate the crc.
 363  */
 364 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 365                              struct crc_params *crc_window, bool enable, bool continuous)
 366 {
 367         int i;
 368         struct pipe_ctx *pipe;
 369         struct crc_params param;
 370         struct timing_generator *tg;
 371
 372         for (i = 0; i < MAX_PIPES; i++) {
 373                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 374                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 375                         break;
 376         }
 377         /* Stream not found */
 378         if (i == MAX_PIPES)
 379                 return false;
 380
 381         /* By default, capture the full frame */
 382         param.windowa_x_start = 0;
 383         param.windowa_y_start = 0;
 384         param.windowa_x_end = pipe->stream->timing.h_addressable;
 385         param.windowa_y_end = pipe->stream->timing.v_addressable;
 386         param.windowb_x_start = 0;
 387         param.windowb_y_start = 0;
 388         param.windowb_x_end = pipe->stream->timing.h_addressable;
 389         param.windowb_y_end = pipe->stream->timing.v_addressable;
 390
 391         if (crc_window) {
 392                 param.windowa_x_start = crc_window->windowa_x_start;
 393                 param.windowa_y_start = crc_window->windowa_y_start;
 394                 param.windowa_x_end = crc_window->windowa_x_end;
 395                 param.windowa_y_end = crc_window->windowa_y_end;
 396                 param.windowb_x_start = crc_window->windowb_x_start;
 397                 param.windowb_y_start = crc_window->windowb_y_start;
 398                 param.windowb_x_end = crc_window->windowb_x_end;
 399                 param.windowb_y_end = crc_window->windowb_y_end;
 400         }
 401
 402         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 403         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 404
 405         /* Default to the union of both windows */
 406         param.selection = UNION_WINDOW_A_B;
 407         param.continuous_mode = continuous;
 408         param.enable = enable;
 409
 410         tg = pipe->stream_res.tg;
 411
 412         /* Only call if supported */
 413         if (tg->funcs->configure_crc)
 414                 return tg->funcs->configure_crc(tg, &param);
 415         DC_LOG_WARNING("CRC capture not supported.");
 416         return false;
 417 }
 418
 419 /**
 420  * dc_stream_get_crc() - Get CRC values for the given stream.
 421  * @dc: DC object
 422  * @stream: The DC stream state of the stream to get CRCs from.
 423  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 424  *
 425  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 426  * Return false if stream is not found, or if CRCs are not enabled.
 427  */
 428 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 429                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 430 {
 431         int i;
 432         struct pipe_ctx *pipe;
 433         struct timing_generator *tg;
 434
 435         for (i = 0; i < MAX_PIPES; i++) {
 436                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 437                 if (pipe->stream == stream)
 438                         break;
 439         }
 440         /* Stream not found */
 441         if (i == MAX_PIPES)
 442                 return false;
 443
 444         tg = pipe->stream_res.tg;
 445
 446         if (tg->funcs->get_crc)
 447                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 448         DC_LOG_WARNING("CRC capture not supported.");
 449         return false;
 450 }
 451
 452 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 453                 enum dc_dynamic_expansion option)
 454 {
 455         /* OPP FMT dyn expansion updates*/
 456         int i = 0;
 457         struct pipe_ctx *pipe_ctx;
 458
 459         for (i = 0; i < MAX_PIPES; i++) {
 460                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 461                                 == stream) {
 462                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 463                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 464                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 465                                         pipe_ctx->stream_res.opp,
 466                                         COLOR_SPACE_YCBCR601,
 467                                         stream->timing.display_color_depth,
 468                                         stream->signal);
 469                 }
 470         }
 471 }
 472
 473 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 474                 enum dc_dither_option option)
 475 {
 476         struct bit_depth_reduction_params params;
 477         struct dc_link *link = stream->link;
 478         struct pipe_ctx *pipes = NULL;
 479         int i;
 480
 481         for (i = 0; i < MAX_PIPES; i++) {
 482                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 483                                 stream) {
 484                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 485                         break;
 486                 }
 487         }
 488
 489         if (!pipes)
 490                 return;
 491         if (option > DITHER_OPTION_MAX)
 492                 return;
 493
 494         stream->dither_option = option;
 495
 496         memset(&params, 0, sizeof(params));
 497         resource_build_bit_depth_reduction_params(stream, &params);
 498         stream->bit_depth_params = params;
 499
 500         if (pipes->plane_res.xfm &&
 501             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 502                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 503                         pipes->plane_res.xfm,
 504                         pipes->plane_res.scl_data.lb_params.depth,
 505                         &stream->bit_depth_params);
 506         }
 507
 508         pipes->stream_res.opp->funcs->
 509                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 510 }
 511
 512 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 513 {
 514         int i = 0;
 515         bool ret = false;
 516         struct pipe_ctx *pipes;
 517
 518         for (i = 0; i < MAX_PIPES; i++) {
 519                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 520                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 521                         dc->hwss.program_gamut_remap(pipes);
 522                         ret = true;
 523                 }
 524         }
 525
 526         return ret;
 527 }
 528
 529 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 530 {
 531         int i = 0;
 532         bool ret = false;
 533         struct pipe_ctx *pipes;
 534
 535         for (i = 0; i < MAX_PIPES; i++) {
 536                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 537                                 == stream) {
 538
 539                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 540                         dc->hwss.program_output_csc(dc,
 541                                         pipes,
 542                                         stream->output_color_space,
 543                                         stream->csc_color_matrix.matrix,
 544                                         pipes->stream_res.opp->inst);
 545                         ret = true;
 546                 }
 547         }
 548
 549         return ret;
 550 }
 551
 552 void dc_stream_set_static_screen_params(struct dc *dc,
 553                 struct dc_stream_state **streams,
 554                 int num_streams,
 555                 const struct dc_static_screen_params *params)
 556 {
 557         int i = 0;
 558         int j = 0;
 559         struct pipe_ctx *pipes_affected[MAX_PIPES];
 560         int num_pipes_affected = 0;
 561
 562         for (i = 0; i < num_streams; i++) {
 563                 struct dc_stream_state *stream = streams[i];
 564
 565                 for (j = 0; j < MAX_PIPES; j++) {
 566                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 567                                         == stream) {
 568                                 pipes_affected[num_pipes_affected++] =
 569                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 570                         }
 571                 }
 572         }
 573
 574         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 575 }
 576
 577 static void dc_destruct(struct dc *dc)
 578 {
 579         if (dc->current_state) {
 580                 dc_release_state(dc->current_state);
 581                 dc->current_state = NULL;
 582         }
 583
 584         destroy_links(dc);
 585
 586         if (dc->clk_mgr) {
 587                 dc_destroy_clk_mgr(dc->clk_mgr);
 588                 dc->clk_mgr = NULL;
 589         }
 590
 591         dc_destroy_resource_pool(dc);
 592
 593         if (dc->ctx->gpio_service)
 594                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 595
 596         if (dc->ctx->created_bios)
 597                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 598
 599         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 600
 601         kfree(dc->ctx);
 602         dc->ctx = NULL;
 603
 604         kfree(dc->bw_vbios);
 605         dc->bw_vbios = NULL;
 606
 607         kfree(dc->bw_dceip);
 608         dc->bw_dceip = NULL;
 609
 610 #ifdef CONFIG_DRM_AMD_DC_DCN
 611         kfree(dc->dcn_soc);
 612         dc->dcn_soc = NULL;
 613
 614         kfree(dc->dcn_ip);
 615         dc->dcn_ip = NULL;
 616
 617 #endif
 618         kfree(dc->vm_helper);
 619         dc->vm_helper = NULL;
 620
 621 }
 622
 623 static bool dc_construct_ctx(struct dc *dc,
 624                 const struct dc_init_data *init_params)
 625 {
 626         struct dc_context *dc_ctx;
 627         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 628
 629         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 630         if (!dc_ctx)
 631                 return false;
 632
 633         dc_ctx->cgs_device = init_params->cgs_device;
 634         dc_ctx->driver_context = init_params->driver;
 635         dc_ctx->dc = dc;
 636         dc_ctx->asic_id = init_params->asic_id;
 637         dc_ctx->dc_sink_id_count = 0;
 638         dc_ctx->dc_stream_id_count = 0;
 639         dc_ctx->dce_environment = init_params->dce_environment;
 640
 641         /* Create logger */
 642
 643         dc_version = resource_parse_asic_id(init_params->asic_id);
 644         dc_ctx->dce_version = dc_version;
 645
 646         dc_ctx->perf_trace = dc_perf_trace_create();
 647         if (!dc_ctx->perf_trace) {
 648                 ASSERT_CRITICAL(false);
 649                 return false;
 650         }
 651
 652         dc->ctx = dc_ctx;
 653
 654         return true;
 655 }
 656
 657 static bool dc_construct(struct dc *dc,
 658                 const struct dc_init_data *init_params)
 659 {
 660         struct dc_context *dc_ctx;
 661         struct bw_calcs_dceip *dc_dceip;
 662         struct bw_calcs_vbios *dc_vbios;
 663 #ifdef CONFIG_DRM_AMD_DC_DCN
 664         struct dcn_soc_bounding_box *dcn_soc;
 665         struct dcn_ip_params *dcn_ip;
 666 #endif
 667
 668         dc->config = init_params->flags;
 669
 670         // Allocate memory for the vm_helper
 671         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 672         if (!dc->vm_helper) {
 673                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 674                 goto fail;
 675         }
 676
 677         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 678
 679         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 680         if (!dc_dceip) {
 681                 dm_error("%s: failed to create dceip\n", __func__);
 682                 goto fail;
 683         }
 684
 685         dc->bw_dceip = dc_dceip;
 686
 687         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 688         if (!dc_vbios) {
 689                 dm_error("%s: failed to create vbios\n", __func__);
 690                 goto fail;
 691         }
 692
 693         dc->bw_vbios = dc_vbios;
 694 #ifdef CONFIG_DRM_AMD_DC_DCN
 695         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 696         if (!dcn_soc) {
 697                 dm_error("%s: failed to create dcn_soc\n", __func__);
 698                 goto fail;
 699         }
 700
 701         dc->dcn_soc = dcn_soc;
 702
 703         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 704         if (!dcn_ip) {
 705                 dm_error("%s: failed to create dcn_ip\n", __func__);
 706                 goto fail;
 707         }
 708
 709         dc->dcn_ip = dcn_ip;
 710         dc->soc_bounding_box = init_params->soc_bounding_box;
 711 #endif
 712
 713         if (!dc_construct_ctx(dc, init_params)) {
 714                 dm_error("%s: failed to create ctx\n", __func__);
 715                 goto fail;
 716         }
 717
 718         dc_ctx = dc->ctx;
 719
 720         /* Resource should construct all asic specific resources.
 721          * This should be the only place where we need to parse the asic id
 722          */
 723         if (init_params->vbios_override)
 724                 dc_ctx->dc_bios = init_params->vbios_override;
 725         else {
 726                 /* Create BIOS parser */
 727                 struct bp_init_data bp_init_data;
 728
 729                 bp_init_data.ctx = dc_ctx;
 730                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 731
 732                 dc_ctx->dc_bios = dal_bios_parser_create(
 733                                 &bp_init_data, dc_ctx->dce_version);
 734
 735                 if (!dc_ctx->dc_bios) {
 736                         ASSERT_CRITICAL(false);
 737                         goto fail;
 738                 }
 739
 740                 dc_ctx->created_bios = true;
 741         }
 742
 743         dc->vendor_signature = init_params->vendor_signature;
 744
 745         /* Create GPIO service */
 746         dc_ctx->gpio_service = dal_gpio_service_create(
 747                         dc_ctx->dce_version,
 748                         dc_ctx->dce_environment,
 749                         dc_ctx);
 750
 751         if (!dc_ctx->gpio_service) {
 752                 ASSERT_CRITICAL(false);
 753                 goto fail;
 754         }
 755
 756         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 757         if (!dc->res_pool)
 758                 goto fail;
 759
 760         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 761         if (!dc->clk_mgr)
 762                 goto fail;
 763 #ifdef CONFIG_DRM_AMD_DC_DCN
 764         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 765 #endif
 766
 767         dc->debug.force_ignore_link_settings = init_params->force_ignore_link_settings;
 768
 769         if (dc->res_pool->funcs->update_bw_bounding_box)
 770                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 771
 772         /* Creation of current_state must occur after dc->dml
 773          * is initialized in dc_create_resource_pool because
 774          * on creation it copies the contents of dc->dml
 775          */
 776
 777         dc->current_state = dc_create_state(dc);
 778
 779         if (!dc->current_state) {
 780                 dm_error("%s: failed to create validate ctx\n", __func__);
 781                 goto fail;
 782         }
 783
 784         dc_resource_state_construct(dc, dc->current_state);
 785
 786         if (!create_links(dc, init_params->num_virtual_links))
 787                 goto fail;
 788
 789         return true;
 790
 791 fail:
 792         return false;
 793 }
 794
 795 static void disable_all_writeback_pipes_for_stream(
 796                 const struct dc *dc,
 797                 struct dc_stream_state *stream,
 798                 struct dc_state *context)
 799 {
 800         int i;
 801
 802         for (i = 0; i < stream->num_wb_info; i++)
 803                 stream->writeback_info[i].wb_enabled = false;
 804 }
 805
 806 void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock)
 807 {
 808         int i = 0;
 809
 810         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 811         if (dc->hwss.interdependent_update_lock)
 812                 dc->hwss.interdependent_update_lock(dc, context, lock);
 813         else {
 814                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 815                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 816                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 817
 818                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 819                         if (stream == pipe_ctx->stream) {
 820                                 if (!pipe_ctx->top_pipe &&
 821                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 822                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 823                         }
 824                 }
 825         }
 826 }
 827
 828 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 829 {
 830         int i, j;
 831         struct dc_state *dangling_context = dc_create_state(dc);
 832         struct dc_state *current_ctx;
 833
 834         if (dangling_context == NULL)
 835                 return;
 836
 837         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 838
 839         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 840                 struct dc_stream_state *old_stream =
 841                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 842                 bool should_disable = true;
 843
 844                 for (j = 0; j < context->stream_count; j++) {
 845                         if (old_stream == context->streams[j]) {
 846                                 should_disable = false;
 847                                 break;
 848                         }
 849                 }
 850                 if (should_disable && old_stream) {
 851                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 852                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 853
 854                         if (dc->hwss.apply_ctx_for_surface) {
 855                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 856                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 857                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 858                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 859                         }
 860                         if (dc->hwss.program_front_end_for_ctx) {
 861                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 862                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 863                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 864                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 865                         }
 866                 }
 867         }
 868
 869         current_ctx = dc->current_state;
 870         dc->current_state = dangling_context;
 871         dc_release_state(current_ctx);
 872 }
 873
 874 static void disable_vbios_mode_if_required(
 875                 struct dc *dc,
 876                 struct dc_state *context)
 877 {
 878         unsigned int i, j;
 879
 880         /* check if timing_changed, disable stream*/
 881         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 882                 struct dc_stream_state *stream = NULL;
 883                 struct dc_link *link = NULL;
 884                 struct pipe_ctx *pipe = NULL;
 885
 886                 pipe = &context->res_ctx.pipe_ctx[i];
 887                 stream = pipe->stream;
 888                 if (stream == NULL)
 889                         continue;
 890
 891                 // only looking for first odm pipe
 892                 if (pipe->prev_odm_pipe)
 893                         continue;
 894
 895                 if (stream->link->local_sink &&
 896                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
 897                         link = stream->link;
 898                 }
 899
 900                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 901                         unsigned int enc_inst, tg_inst = 0;
 902                         unsigned int pix_clk_100hz;
 903
 904                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 905                         if (enc_inst != ENGINE_ID_UNKNOWN) {
 906                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
 907                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
 908                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
 909                                                         dc->res_pool->stream_enc[j]);
 910                                                 break;
 911                                         }
 912                                 }
 913
 914                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
 915                                         dc->res_pool->dp_clock_source,
 916                                         tg_inst, &pix_clk_100hz);
 917
 918                                 if (link->link_status.link_active) {
 919                                         uint32_t requested_pix_clk_100hz =
 920                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
 921
 922                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
 923                                                 core_link_disable_stream(pipe);
 924                                                 pipe->stream->dpms_off = false;
 925                                         }
 926                                 }
 927                         }
 928                 }
 929         }
 930 }
 931
 932 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 933 {
 934         int i;
 935         PERF_TRACE();
 936         for (i = 0; i < MAX_PIPES; i++) {
 937                 int count = 0;
 938                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 939
 940                 if (!pipe->plane_state)
 941                         continue;
 942
 943                 /* Timeout 100 ms */
 944                 while (count < 100000) {
 945                         /* Must set to false to start with, due to OR in update function */
 946                         pipe->plane_state->status.is_flip_pending = false;
 947                         dc->hwss.update_pending_status(pipe);
 948                         if (!pipe->plane_state->status.is_flip_pending)
 949                                 break;
 950                         udelay(1);
 951                         count++;
 952                 }
 953                 ASSERT(!pipe->plane_state->status.is_flip_pending);
 954         }
 955         PERF_TRACE();
 956 }
 957
 958 /*******************************************************************************
 959  * Public functions
 960  ******************************************************************************/
 961
 962 struct dc *dc_create(const struct dc_init_data *init_params)
 963 {
 964         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 965         unsigned int full_pipe_count;
 966
 967         if (NULL == dc)
 968                 goto alloc_fail;
 969
 970         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
 971                 if (false == dc_construct_ctx(dc, init_params)) {
 972                         dc_destruct(dc);
 973                         goto construct_fail;
 974                 }
 975         } else {
 976                 if (false == dc_construct(dc, init_params)) {
 977                         dc_destruct(dc);
 978                         goto construct_fail;
 979                 }
 980
 981                 full_pipe_count = dc->res_pool->pipe_count;
 982                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 983                         full_pipe_count--;
 984                 dc->caps.max_streams = min(
 985                                 full_pipe_count,
 986                                 dc->res_pool->stream_enc_count);
 987
 988                 dc->optimize_seamless_boot_streams = 0;
 989                 dc->caps.max_links = dc->link_count;
 990                 dc->caps.max_audios = dc->res_pool->audio_count;
 991                 dc->caps.linear_pitch_alignment = 64;
 992
 993                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
 994
 995                 if (dc->res_pool->dmcu != NULL)
 996                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 997         }
 998
 999         /* Populate versioning information */
1000         dc->versions.dc_ver = DC_VER;
1001
1002         dc->build_id = DC_BUILD_ID;
1003
1004         DC_LOG_DC("Display Core initialized\n");
1005
1006
1007
1008         return dc;
1009
1010 construct_fail:
1011         kfree(dc);
1012
1013 alloc_fail:
1014         return NULL;
1015 }
1016
1017 void dc_hardware_init(struct dc *dc)
1018 {
1019         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1020                 dc->hwss.init_hw(dc);
1021 }
1022
1023 void dc_init_callbacks(struct dc *dc,
1024                 const struct dc_callback_init *init_params)
1025 {
1026 #ifdef CONFIG_DRM_AMD_DC_HDCP
1027         dc->ctx->cp_psp = init_params->cp_psp;
1028 #endif
1029 }
1030
1031 void dc_deinit_callbacks(struct dc *dc)
1032 {
1033 #ifdef CONFIG_DRM_AMD_DC_HDCP
1034         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1035 #endif
1036 }
1037
1038 void dc_destroy(struct dc **dc)
1039 {
1040         dc_destruct(*dc);
1041         kfree(*dc);
1042         *dc = NULL;
1043 }
1044
1045 static void enable_timing_multisync(
1046                 struct dc *dc,
1047                 struct dc_state *ctx)
1048 {
1049         int i = 0, multisync_count = 0;
1050         int pipe_count = dc->res_pool->pipe_count;
1051         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1052
1053         for (i = 0; i < pipe_count; i++) {
1054                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1055                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1056                         continue;
1057                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1058                         continue;
1059                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1060                 multisync_count++;
1061         }
1062
1063         if (multisync_count > 0) {
1064                 dc->hwss.enable_per_frame_crtc_position_reset(
1065                         dc, multisync_count, multisync_pipes);
1066         }
1067 }
1068
1069 static void program_timing_sync(
1070                 struct dc *dc,
1071                 struct dc_state *ctx)
1072 {
1073         int i, j, k;
1074         int group_index = 0;
1075         int num_group = 0;
1076         int pipe_count = dc->res_pool->pipe_count;
1077         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1078
1079         for (i = 0; i < pipe_count; i++) {
1080                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
1081                         continue;
1082
1083                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1084         }
1085
1086         for (i = 0; i < pipe_count; i++) {
1087                 int group_size = 1;
1088                 struct pipe_ctx *pipe_set[MAX_PIPES];
1089
1090                 if (!unsynced_pipes[i])
1091                         continue;
1092
1093                 pipe_set[0] = unsynced_pipes[i];
1094                 unsynced_pipes[i] = NULL;
1095
1096                 /* Add tg to the set, search rest of the tg's for ones with
1097                  * same timing, add all tgs with same timing to the group
1098                  */
1099                 for (j = i + 1; j < pipe_count; j++) {
1100                         if (!unsynced_pipes[j])
1101                                 continue;
1102
1103                         if (resource_are_streams_timing_synchronizable(
1104                                         unsynced_pipes[j]->stream,
1105                                         pipe_set[0]->stream)) {
1106                                 pipe_set[group_size] = unsynced_pipes[j];
1107                                 unsynced_pipes[j] = NULL;
1108                                 group_size++;
1109                         }
1110                 }
1111
1112                 /* set first unblanked pipe as master */
1113                 for (j = 0; j < group_size; j++) {
1114                         bool is_blanked;
1115
1116                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1117                                 is_blanked =
1118                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1119                         else
1120                                 is_blanked =
1121                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1122                         if (!is_blanked) {
1123                                 if (j == 0)
1124                                         break;
1125
1126                                 swap(pipe_set[0], pipe_set[j]);
1127                                 break;
1128                         }
1129                 }
1130
1131
1132                 for (k = 0; k < group_size; k++) {
1133                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1134
1135                         status->timing_sync_info.group_id = num_group;
1136                         status->timing_sync_info.group_size = group_size;
1137                         if (k == 0)
1138                                 status->timing_sync_info.master = true;
1139                         else
1140                                 status->timing_sync_info.master = false;
1141
1142                 }
1143                 /* remove any other unblanked pipes as they have already been synced */
1144                 for (j = j + 1; j < group_size; j++) {
1145                         bool is_blanked;
1146
1147                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1148                                 is_blanked =
1149                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1150                         else
1151                                 is_blanked =
1152                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1153                         if (!is_blanked) {
1154                                 group_size--;
1155                                 pipe_set[j] = pipe_set[group_size];
1156                                 j--;
1157                         }
1158                 }
1159
1160                 if (group_size > 1) {
1161                         dc->hwss.enable_timing_synchronization(
1162                                 dc, group_index, group_size, pipe_set);
1163                         group_index++;
1164                 }
1165                 num_group++;
1166         }
1167 }
1168
1169 static bool context_changed(
1170                 struct dc *dc,
1171                 struct dc_state *context)
1172 {
1173         uint8_t i;
1174
1175         if (context->stream_count != dc->current_state->stream_count)
1176                 return true;
1177
1178         for (i = 0; i < dc->current_state->stream_count; i++) {
1179                 if (dc->current_state->streams[i] != context->streams[i])
1180                         return true;
1181         }
1182
1183         return false;
1184 }
1185
1186 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1187                                 const struct dc_sink *sink,
1188                                 struct dc_crtc_timing *crtc_timing)
1189 {
1190         struct timing_generator *tg;
1191         struct stream_encoder *se = NULL;
1192
1193         struct dc_crtc_timing hw_crtc_timing = {0};
1194
1195         struct dc_link *link = sink->link;
1196         unsigned int i, enc_inst, tg_inst = 0;
1197
1198         // Seamless port only support single DP and EDP so far
1199         if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
1200                 sink->sink_signal != SIGNAL_TYPE_EDP)
1201                 return false;
1202
1203         /* Check for enabled DIG to identify enabled display */
1204         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1205                 return false;
1206
1207         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1208
1209         if (enc_inst == ENGINE_ID_UNKNOWN)
1210                 return false;
1211
1212         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1213                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1214
1215                         se = dc->res_pool->stream_enc[i];
1216
1217                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1218                                 dc->res_pool->stream_enc[i]);
1219                         break;
1220                 }
1221         }
1222
1223         // tg_inst not found
1224         if (i == dc->res_pool->stream_enc_count)
1225                 return false;
1226
1227         if (tg_inst >= dc->res_pool->timing_generator_count)
1228                 return false;
1229
1230         tg = dc->res_pool->timing_generators[tg_inst];
1231
1232         if (!tg->funcs->get_hw_timing)
1233                 return false;
1234
1235         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1236                 return false;
1237
1238         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1239                 return false;
1240
1241         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1242                 return false;
1243
1244         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1245                 return false;
1246
1247         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1248                 return false;
1249
1250         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1251                 return false;
1252
1253         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1254                 return false;
1255
1256         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1257                 return false;
1258
1259         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1260                 return false;
1261
1262         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1263                 return false;
1264
1265         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1266                 return false;
1267
1268         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1269                 return false;
1270
1271         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1272                 return false;
1273
1274         if (dc_is_dp_signal(link->connector_signal)) {
1275                 unsigned int pix_clk_100hz;
1276
1277                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1278                         dc->res_pool->dp_clock_source,
1279                         tg_inst, &pix_clk_100hz);
1280
1281                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1282                         return false;
1283
1284                 if (!se->funcs->dp_get_pixel_format)
1285                         return false;
1286
1287                 if (!se->funcs->dp_get_pixel_format(
1288                         se,
1289                         &hw_crtc_timing.pixel_encoding,
1290                         &hw_crtc_timing.display_color_depth))
1291                         return false;
1292
1293                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1294                         return false;
1295
1296                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1297                         return false;
1298         }
1299
1300         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1301                 return false;
1302         }
1303
1304         return true;
1305 }
1306
1307 void dc_enable_stereo(
1308         struct dc *dc,
1309         struct dc_state *context,
1310         struct dc_stream_state *streams[],
1311         uint8_t stream_count)
1312 {
1313         int i, j;
1314         struct pipe_ctx *pipe;
1315
1316         for (i = 0; i < MAX_PIPES; i++) {
1317                 if (context != NULL)
1318                         pipe = &context->res_ctx.pipe_ctx[i];
1319                 else
1320                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1321                 for (j = 0 ; pipe && j < stream_count; j++)  {
1322                         if (streams[j] && streams[j] == pipe->stream &&
1323                                 dc->hwss.setup_stereo)
1324                                 dc->hwss.setup_stereo(pipe, dc);
1325                 }
1326         }
1327 }
1328
1329 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1330 {
1331         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1332                 enable_timing_multisync(dc, context);
1333                 program_timing_sync(dc, context);
1334         }
1335 }
1336
1337 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1338 {
1339         int i;
1340         unsigned int stream_mask = 0;
1341
1342         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1343                 if (context->res_ctx.pipe_ctx[i].stream)
1344                         stream_mask |= 1 << i;
1345         }
1346
1347         return stream_mask;
1348 }
1349
1350 /*
1351  * Applies given context to HW and copy it into current context.
1352  * It's up to the user to release the src context afterwards.
1353  */
1354 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1355 {
1356         struct dc_bios *dcb = dc->ctx->dc_bios;
1357         enum dc_status result = DC_ERROR_UNEXPECTED;
1358         struct pipe_ctx *pipe;
1359         int i, k, l;
1360         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1361
1362 #if defined(CONFIG_DRM_AMD_DC_DCN)
1363         dc_allow_idle_optimizations(dc, false);
1364 #endif
1365
1366         for (i = 0; i < context->stream_count; i++)
1367                 dc_streams[i] =  context->streams[i];
1368
1369         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1370                 disable_vbios_mode_if_required(dc, context);
1371                 dc->hwss.enable_accelerated_mode(dc, context);
1372         }
1373
1374         for (i = 0; i < context->stream_count; i++)
1375                 if (context->streams[i]->apply_seamless_boot_optimization)
1376                         dc->optimize_seamless_boot_streams++;
1377
1378         if (context->stream_count > dc->optimize_seamless_boot_streams ||
1379                 context->stream_count == 0)
1380                 dc->hwss.prepare_bandwidth(dc, context);
1381
1382         disable_dangling_plane(dc, context);
1383         /* re-program planes for existing stream, in case we need to
1384          * free up plane resource for later use
1385          */
1386         if (dc->hwss.apply_ctx_for_surface) {
1387                 for (i = 0; i < context->stream_count; i++) {
1388                         if (context->streams[i]->mode_changed)
1389                                 continue;
1390                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1391                         dc->hwss.apply_ctx_for_surface(
1392                                 dc, context->streams[i],
1393                                 context->stream_status[i].plane_count,
1394                                 context); /* use new pipe config in new context */
1395                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1396                         dc->hwss.post_unlock_program_front_end(dc, context);
1397                 }
1398         }
1399
1400         /* Program hardware */
1401         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1402                 pipe = &context->res_ctx.pipe_ctx[i];
1403                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1404         }
1405
1406         result = dc->hwss.apply_ctx_to_hw(dc, context);
1407
1408         if (result != DC_OK)
1409                 return result;
1410
1411         dc_trigger_sync(dc, context);
1412
1413         /* Program all planes within new context*/
1414         if (dc->hwss.program_front_end_for_ctx) {
1415                 dc->hwss.interdependent_update_lock(dc, context, true);
1416                 dc->hwss.program_front_end_for_ctx(dc, context);
1417                 dc->hwss.interdependent_update_lock(dc, context, false);
1418                 dc->hwss.post_unlock_program_front_end(dc, context);
1419         }
1420         for (i = 0; i < context->stream_count; i++) {
1421                 const struct dc_link *link = context->streams[i]->link;
1422
1423                 if (!context->streams[i]->mode_changed)
1424                         continue;
1425
1426                 if (dc->hwss.apply_ctx_for_surface) {
1427                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1428                         dc->hwss.apply_ctx_for_surface(
1429                                         dc, context->streams[i],
1430                                         context->stream_status[i].plane_count,
1431                                         context);
1432                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1433                         dc->hwss.post_unlock_program_front_end(dc, context);
1434                 }
1435
1436                 /*
1437                  * enable stereo
1438                  * TODO rework dc_enable_stereo call to work with validation sets?
1439                  */
1440                 for (k = 0; k < MAX_PIPES; k++) {
1441                         pipe = &context->res_ctx.pipe_ctx[k];
1442
1443                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1444                                 if (context->streams[l] &&
1445                                         context->streams[l] == pipe->stream &&
1446                                         dc->hwss.setup_stereo)
1447                                         dc->hwss.setup_stereo(pipe, dc);
1448                         }
1449                 }
1450
1451                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1452                                 context->streams[i]->timing.h_addressable,
1453                                 context->streams[i]->timing.v_addressable,
1454                                 context->streams[i]->timing.h_total,
1455                                 context->streams[i]->timing.v_total,
1456                                 context->streams[i]->timing.pix_clk_100hz / 10);
1457         }
1458
1459         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1460
1461         if (context->stream_count > dc->optimize_seamless_boot_streams ||
1462                 context->stream_count == 0) {
1463                 /* Must wait for no flips to be pending before doing optimize bw */
1464                 wait_for_no_pipes_pending(dc, context);
1465                 /* pplib is notified if disp_num changed */
1466                 dc->hwss.optimize_bandwidth(dc, context);
1467         }
1468
1469         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1470                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1471         else
1472                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1473
1474         context->stream_mask = get_stream_mask(dc, context);
1475
1476         if (context->stream_mask != dc->current_state->stream_mask)
1477                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1478
1479         for (i = 0; i < context->stream_count; i++)
1480                 context->streams[i]->mode_changed = false;
1481
1482         dc_release_state(dc->current_state);
1483
1484         dc->current_state = context;
1485
1486         dc_retain_state(dc->current_state);
1487
1488         return result;
1489 }
1490
1491 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1492 {
1493         enum dc_status result = DC_ERROR_UNEXPECTED;
1494         int i;
1495
1496         if (false == context_changed(dc, context))
1497                 return DC_OK;
1498
1499         DC_LOG_DC("%s: %d streams\n",
1500                                 __func__, context->stream_count);
1501
1502         for (i = 0; i < context->stream_count; i++) {
1503                 struct dc_stream_state *stream = context->streams[i];
1504
1505                 dc_stream_log(dc, stream);
1506         }
1507
1508         result = dc_commit_state_no_check(dc, context);
1509
1510         return (result == DC_OK);
1511 }
1512
1513 #if defined(CONFIG_DRM_AMD_DC_DCN)
1514 bool dc_acquire_release_mpc_3dlut(
1515                 struct dc *dc, bool acquire,
1516                 struct dc_stream_state *stream,
1517                 struct dc_3dlut **lut,
1518                 struct dc_transfer_func **shaper)
1519 {
1520         int pipe_idx;
1521         bool ret = false;
1522         bool found_pipe_idx = false;
1523         const struct resource_pool *pool = dc->res_pool;
1524         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1525         int mpcc_id = 0;
1526
1527         if (pool && res_ctx) {
1528                 if (acquire) {
1529                         /*find pipe idx for the given stream*/
1530                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1531                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1532                                         found_pipe_idx = true;
1533                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1534                                         break;
1535                                 }
1536                         }
1537                 } else
1538                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1539
1540                 if (found_pipe_idx) {
1541                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1542                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1543                         else if (acquire == false && pool->funcs->release_post_bldn_3dlut)
1544                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1545                 }
1546         }
1547         return ret;
1548 }
1549 #endif
1550 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1551 {
1552         int i;
1553         struct pipe_ctx *pipe;
1554
1555         for (i = 0; i < MAX_PIPES; i++) {
1556                 pipe = &context->res_ctx.pipe_ctx[i];
1557
1558                 if (!pipe->plane_state)
1559                         continue;
1560
1561                 /* Must set to false to start with, due to OR in update function */
1562                 pipe->plane_state->status.is_flip_pending = false;
1563                 dc->hwss.update_pending_status(pipe);
1564                 if (pipe->plane_state->status.is_flip_pending)
1565                         return true;
1566         }
1567         return false;
1568 }
1569
1570 void dc_post_update_surfaces_to_stream(struct dc *dc)
1571 {
1572         int i;
1573         struct dc_state *context = dc->current_state;
1574
1575         if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0)
1576                 return;
1577
1578         post_surface_trace(dc);
1579
1580         if (is_flip_pending_in_pipes(dc, context))
1581                 return;
1582
1583         for (i = 0; i < dc->res_pool->pipe_count; i++)
1584                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1585                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1586                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1587                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1588                 }
1589
1590         dc->hwss.optimize_bandwidth(dc, context);
1591
1592         dc->optimized_required = false;
1593         dc->wm_optimized_required = false;
1594 }
1595
1596 static void init_state(struct dc *dc, struct dc_state *context)
1597 {
1598         /* Each context must have their own instance of VBA and in order to
1599          * initialize and obtain IP and SOC the base DML instance from DC is
1600          * initially copied into every context
1601          */
1602 #ifdef CONFIG_DRM_AMD_DC_DCN
1603         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1604 #endif
1605 }
1606
1607 struct dc_state *dc_create_state(struct dc *dc)
1608 {
1609         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1610                                             GFP_KERNEL);
1611
1612         if (!context)
1613                 return NULL;
1614
1615         init_state(dc, context);
1616
1617         kref_init(&context->refcount);
1618
1619         return context;
1620 }
1621
1622 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1623 {
1624         int i, j;
1625         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1626
1627         if (!new_ctx)
1628                 return NULL;
1629         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1630
1631         for (i = 0; i < MAX_PIPES; i++) {
1632                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1633
1634                         if (cur_pipe->top_pipe)
1635                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1636
1637                         if (cur_pipe->bottom_pipe)
1638                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1639
1640                         if (cur_pipe->prev_odm_pipe)
1641                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1642
1643                         if (cur_pipe->next_odm_pipe)
1644                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1645
1646         }
1647
1648         for (i = 0; i < new_ctx->stream_count; i++) {
1649                         dc_stream_retain(new_ctx->streams[i]);
1650                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1651                                 dc_plane_state_retain(
1652                                         new_ctx->stream_status[i].plane_states[j]);
1653         }
1654
1655         kref_init(&new_ctx->refcount);
1656
1657         return new_ctx;
1658 }
1659
1660 void dc_retain_state(struct dc_state *context)
1661 {
1662         kref_get(&context->refcount);
1663 }
1664
1665 static void dc_state_free(struct kref *kref)
1666 {
1667         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1668         dc_resource_state_destruct(context);
1669         kvfree(context);
1670 }
1671
1672 void dc_release_state(struct dc_state *context)
1673 {
1674         kref_put(&context->refcount, dc_state_free);
1675 }
1676
1677 bool dc_set_generic_gpio_for_stereo(bool enable,
1678                 struct gpio_service *gpio_service)
1679 {
1680         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1681         struct gpio_pin_info pin_info;
1682         struct gpio *generic;
1683         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1684                            GFP_KERNEL);
1685
1686         if (!config)
1687                 return false;
1688         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1689
1690         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1691                 kfree(config);
1692                 return false;
1693         } else {
1694                 generic = dal_gpio_service_create_generic_mux(
1695                         gpio_service,
1696                         pin_info.offset,
1697                         pin_info.mask);
1698         }
1699
1700         if (!generic) {
1701                 kfree(config);
1702                 return false;
1703         }
1704
1705         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1706
1707         config->enable_output_from_mux = enable;
1708         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1709
1710         if (gpio_result == GPIO_RESULT_OK)
1711                 gpio_result = dal_mux_setup_config(generic, config);
1712
1713         if (gpio_result == GPIO_RESULT_OK) {
1714                 dal_gpio_close(generic);
1715                 dal_gpio_destroy_generic_mux(&generic);
1716                 kfree(config);
1717                 return true;
1718         } else {
1719                 dal_gpio_close(generic);
1720                 dal_gpio_destroy_generic_mux(&generic);
1721                 kfree(config);
1722                 return false;
1723         }
1724 }
1725
1726 static bool is_surface_in_context(
1727                 const struct dc_state *context,
1728                 const struct dc_plane_state *plane_state)
1729 {
1730         int j;
1731
1732         for (j = 0; j < MAX_PIPES; j++) {
1733                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1734
1735                 if (plane_state == pipe_ctx->plane_state) {
1736                         return true;
1737                 }
1738         }
1739
1740         return false;
1741 }
1742
1743 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1744 {
1745         union surface_update_flags *update_flags = &u->surface->update_flags;
1746         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1747
1748         if (!u->plane_info)
1749                 return UPDATE_TYPE_FAST;
1750
1751         if (u->plane_info->color_space != u->surface->color_space) {
1752                 update_flags->bits.color_space_change = 1;
1753                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1754         }
1755
1756         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1757                 update_flags->bits.horizontal_mirror_change = 1;
1758                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1759         }
1760
1761         if (u->plane_info->rotation != u->surface->rotation) {
1762                 update_flags->bits.rotation_change = 1;
1763                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1764         }
1765
1766         if (u->plane_info->format != u->surface->format) {
1767                 update_flags->bits.pixel_format_change = 1;
1768                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1769         }
1770
1771         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1772                 update_flags->bits.stereo_format_change = 1;
1773                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1774         }
1775
1776         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1777                 update_flags->bits.per_pixel_alpha_change = 1;
1778                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1779         }
1780
1781         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1782                 update_flags->bits.global_alpha_change = 1;
1783                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1784         }
1785
1786         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1787                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1788                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1789                 update_flags->bits.dcc_change = 1;
1790                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1791         }
1792
1793         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1794                         resource_pixel_format_to_bpp(u->surface->format)) {
1795                 /* different bytes per element will require full bandwidth
1796                  * and DML calculation
1797                  */
1798                 update_flags->bits.bpp_change = 1;
1799                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1800         }
1801
1802         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1803                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1804                 update_flags->bits.plane_size_change = 1;
1805                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1806         }
1807
1808
1809         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1810                         sizeof(union dc_tiling_info)) != 0) {
1811                 update_flags->bits.swizzle_change = 1;
1812                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1813
1814                 /* todo: below are HW dependent, we should add a hook to
1815                  * DCE/N resource and validated there.
1816                  */
1817                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1818                         /* swizzled mode requires RQ to be setup properly,
1819                          * thus need to run DML to calculate RQ settings
1820                          */
1821                         update_flags->bits.bandwidth_change = 1;
1822                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1823                 }
1824         }
1825
1826         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1827         return update_type;
1828 }
1829
1830 static enum surface_update_type get_scaling_info_update_type(
1831                 const struct dc_surface_update *u)
1832 {
1833         union surface_update_flags *update_flags = &u->surface->update_flags;
1834
1835         if (!u->scaling_info)
1836                 return UPDATE_TYPE_FAST;
1837
1838         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1839                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1840                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1841                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1842                         || u->scaling_info->scaling_quality.integer_scaling !=
1843                                 u->surface->scaling_quality.integer_scaling
1844                         ) {
1845                 update_flags->bits.scaling_change = 1;
1846
1847                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1848                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1849                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1850                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1851                         /* Making dst rect smaller requires a bandwidth change */
1852                         update_flags->bits.bandwidth_change = 1;
1853         }
1854
1855         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1856                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1857
1858                 update_flags->bits.scaling_change = 1;
1859                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1860                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
1861                         /* Making src rect bigger requires a bandwidth change */
1862                         update_flags->bits.clock_change = 1;
1863         }
1864
1865         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1866                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1867                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1868                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1869                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1870                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1871                 update_flags->bits.position_change = 1;
1872
1873         if (update_flags->bits.clock_change
1874                         || update_flags->bits.bandwidth_change
1875                         || update_flags->bits.scaling_change)
1876                 return UPDATE_TYPE_FULL;
1877
1878         if (update_flags->bits.position_change)
1879                 return UPDATE_TYPE_MED;
1880
1881         return UPDATE_TYPE_FAST;
1882 }
1883
1884 static enum surface_update_type det_surface_update(const struct dc *dc,
1885                 const struct dc_surface_update *u)
1886 {
1887         const struct dc_state *context = dc->current_state;
1888         enum surface_update_type type;
1889         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1890         union surface_update_flags *update_flags = &u->surface->update_flags;
1891
1892         if (u->flip_addr)
1893                 update_flags->bits.addr_update = 1;
1894
1895         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
1896                 update_flags->raw = 0xFFFFFFFF;
1897                 return UPDATE_TYPE_FULL;
1898         }
1899
1900         update_flags->raw = 0; // Reset all flags
1901
1902         type = get_plane_info_update_type(u);
1903         elevate_update_type(&overall_type, type);
1904
1905         type = get_scaling_info_update_type(u);
1906         elevate_update_type(&overall_type, type);
1907
1908         if (u->flip_addr)
1909                 update_flags->bits.addr_update = 1;
1910
1911         if (u->in_transfer_func)
1912                 update_flags->bits.in_transfer_func_change = 1;
1913
1914         if (u->input_csc_color_matrix)
1915                 update_flags->bits.input_csc_change = 1;
1916
1917         if (u->coeff_reduction_factor)
1918                 update_flags->bits.coeff_reduction_change = 1;
1919
1920         if (u->gamut_remap_matrix)
1921                 update_flags->bits.gamut_remap_change = 1;
1922
1923         if (u->gamma) {
1924                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1925
1926                 if (u->plane_info)
1927                         format = u->plane_info->format;
1928                 else if (u->surface)
1929                         format = u->surface->format;
1930
1931                 if (dce_use_lut(format))
1932                         update_flags->bits.gamma_change = 1;
1933         }
1934
1935         if (u->hdr_mult.value)
1936                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
1937                         update_flags->bits.hdr_mult = 1;
1938                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
1939                 }
1940
1941         if (update_flags->bits.in_transfer_func_change) {
1942                 type = UPDATE_TYPE_MED;
1943                 elevate_update_type(&overall_type, type);
1944         }
1945
1946         if (update_flags->bits.input_csc_change
1947                         || update_flags->bits.coeff_reduction_change
1948                         || update_flags->bits.gamma_change
1949                         || update_flags->bits.gamut_remap_change) {
1950                 type = UPDATE_TYPE_FULL;
1951                 elevate_update_type(&overall_type, type);
1952         }
1953
1954         return overall_type;
1955 }
1956
1957 static enum surface_update_type check_update_surfaces_for_stream(
1958                 struct dc *dc,
1959                 struct dc_surface_update *updates,
1960                 int surface_count,
1961                 struct dc_stream_update *stream_update,
1962                 const struct dc_stream_status *stream_status)
1963 {
1964         int i;
1965         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1966
1967 #if defined(CONFIG_DRM_AMD_DC_DCN)
1968         if (dc->idle_optimizations_allowed)
1969                 overall_type = UPDATE_TYPE_FULL;
1970
1971 #endif
1972         if (stream_status == NULL || stream_status->plane_count != surface_count)
1973                 overall_type = UPDATE_TYPE_FULL;
1974
1975         /* some stream updates require passive update */
1976         if (stream_update) {
1977                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
1978
1979                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
1980                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
1981                         stream_update->integer_scaling_update)
1982                         su_flags->bits.scaling = 1;
1983
1984                 if (stream_update->out_transfer_func)
1985                         su_flags->bits.out_tf = 1;
1986
1987                 if (stream_update->abm_level)
1988                         su_flags->bits.abm_level = 1;
1989
1990                 if (stream_update->dpms_off)
1991                         su_flags->bits.dpms_off = 1;
1992
1993                 if (stream_update->gamut_remap)
1994                         su_flags->bits.gamut_remap = 1;
1995
1996                 if (stream_update->wb_update)
1997                         su_flags->bits.wb_update = 1;
1998
1999                 if (stream_update->dsc_config)
2000                         su_flags->bits.dsc_changed = 1;
2001
2002                 if (su_flags->raw != 0)
2003                         overall_type = UPDATE_TYPE_FULL;
2004
2005                 if (stream_update->output_csc_transform || stream_update->output_color_space)
2006                         su_flags->bits.out_csc = 1;
2007         }
2008
2009         for (i = 0 ; i < surface_count; i++) {
2010                 enum surface_update_type type =
2011                                 det_surface_update(dc, &updates[i]);
2012
2013                 elevate_update_type(&overall_type, type);
2014         }
2015
2016         return overall_type;
2017 }
2018
2019 /**
2020  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2021  *
2022  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2023  */
2024 enum surface_update_type dc_check_update_surfaces_for_stream(
2025                 struct dc *dc,
2026                 struct dc_surface_update *updates,
2027                 int surface_count,
2028                 struct dc_stream_update *stream_update,
2029                 const struct dc_stream_status *stream_status)
2030 {
2031         int i;
2032         enum surface_update_type type;
2033
2034         if (stream_update)
2035                 stream_update->stream->update_flags.raw = 0;
2036         for (i = 0; i < surface_count; i++)
2037                 updates[i].surface->update_flags.raw = 0;
2038
2039         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2040         if (type == UPDATE_TYPE_FULL) {
2041                 if (stream_update) {
2042                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2043                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2044                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2045                 }
2046                 for (i = 0; i < surface_count; i++)
2047                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2048         }
2049
2050         if (type == UPDATE_TYPE_FAST) {
2051                 // If there's an available clock comparator, we use that.
2052                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2053                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2054                                 dc->optimized_required = true;
2055                 // Else we fallback to mem compare.
2056                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2057                         dc->optimized_required = true;
2058                 }
2059
2060                 dc->optimized_required |= dc->wm_optimized_required;
2061         }
2062
2063         return type;
2064 }
2065
2066 static struct dc_stream_status *stream_get_status(
2067         struct dc_state *ctx,
2068         struct dc_stream_state *stream)
2069 {
2070         uint8_t i;
2071
2072         for (i = 0; i < ctx->stream_count; i++) {
2073                 if (stream == ctx->streams[i]) {
2074                         return &ctx->stream_status[i];
2075                 }
2076         }
2077
2078         return NULL;
2079 }
2080
2081 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2082
2083 static void copy_surface_update_to_plane(
2084                 struct dc_plane_state *surface,
2085                 struct dc_surface_update *srf_update)
2086 {
2087         if (srf_update->flip_addr) {
2088                 surface->address = srf_update->flip_addr->address;
2089                 surface->flip_immediate =
2090                         srf_update->flip_addr->flip_immediate;
2091                 surface->time.time_elapsed_in_us[surface->time.index] =
2092                         srf_update->flip_addr->flip_timestamp_in_us -
2093                                 surface->time.prev_update_time_in_us;
2094                 surface->time.prev_update_time_in_us =
2095                         srf_update->flip_addr->flip_timestamp_in_us;
2096                 surface->time.index++;
2097                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2098                         surface->time.index = 0;
2099
2100                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2101         }
2102
2103         if (srf_update->scaling_info) {
2104                 surface->scaling_quality =
2105                                 srf_update->scaling_info->scaling_quality;
2106                 surface->dst_rect =
2107                                 srf_update->scaling_info->dst_rect;
2108                 surface->src_rect =
2109                                 srf_update->scaling_info->src_rect;
2110                 surface->clip_rect =
2111                                 srf_update->scaling_info->clip_rect;
2112         }
2113
2114         if (srf_update->plane_info) {
2115                 surface->color_space =
2116                                 srf_update->plane_info->color_space;
2117                 surface->format =
2118                                 srf_update->plane_info->format;
2119                 surface->plane_size =
2120                                 srf_update->plane_info->plane_size;
2121                 surface->rotation =
2122                                 srf_update->plane_info->rotation;
2123                 surface->horizontal_mirror =
2124                                 srf_update->plane_info->horizontal_mirror;
2125                 surface->stereo_format =
2126                                 srf_update->plane_info->stereo_format;
2127                 surface->tiling_info =
2128                                 srf_update->plane_info->tiling_info;
2129                 surface->visible =
2130                                 srf_update->plane_info->visible;
2131                 surface->per_pixel_alpha =
2132                                 srf_update->plane_info->per_pixel_alpha;
2133                 surface->global_alpha =
2134                                 srf_update->plane_info->global_alpha;
2135                 surface->global_alpha_value =
2136                                 srf_update->plane_info->global_alpha_value;
2137                 surface->dcc =
2138                                 srf_update->plane_info->dcc;
2139                 surface->layer_index =
2140                                 srf_update->plane_info->layer_index;
2141         }
2142
2143         if (srf_update->gamma &&
2144                         (surface->gamma_correction !=
2145                                         srf_update->gamma)) {
2146                 memcpy(&surface->gamma_correction->entries,
2147                         &srf_update->gamma->entries,
2148                         sizeof(struct dc_gamma_entries));
2149                 surface->gamma_correction->is_identity =
2150                         srf_update->gamma->is_identity;
2151                 surface->gamma_correction->num_entries =
2152                         srf_update->gamma->num_entries;
2153                 surface->gamma_correction->type =
2154                         srf_update->gamma->type;
2155         }
2156
2157         if (srf_update->in_transfer_func &&
2158                         (surface->in_transfer_func !=
2159                                 srf_update->in_transfer_func)) {
2160                 surface->in_transfer_func->sdr_ref_white_level =
2161                         srf_update->in_transfer_func->sdr_ref_white_level;
2162                 surface->in_transfer_func->tf =
2163                         srf_update->in_transfer_func->tf;
2164                 surface->in_transfer_func->type =
2165                         srf_update->in_transfer_func->type;
2166                 memcpy(&surface->in_transfer_func->tf_pts,
2167                         &srf_update->in_transfer_func->tf_pts,
2168                         sizeof(struct dc_transfer_func_distributed_points));
2169         }
2170
2171         if (srf_update->func_shaper &&
2172                         (surface->in_shaper_func !=
2173                         srf_update->func_shaper))
2174                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2175                 sizeof(*surface->in_shaper_func));
2176
2177         if (srf_update->lut3d_func &&
2178                         (surface->lut3d_func !=
2179                         srf_update->lut3d_func))
2180                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2181                 sizeof(*surface->lut3d_func));
2182
2183         if (srf_update->hdr_mult.value)
2184                 surface->hdr_mult =
2185                                 srf_update->hdr_mult;
2186
2187         if (srf_update->blend_tf &&
2188                         (surface->blend_tf !=
2189                         srf_update->blend_tf))
2190                 memcpy(surface->blend_tf, srf_update->blend_tf,
2191                 sizeof(*surface->blend_tf));
2192
2193         if (srf_update->input_csc_color_matrix)
2194                 surface->input_csc_color_matrix =
2195                         *srf_update->input_csc_color_matrix;
2196
2197         if (srf_update->coeff_reduction_factor)
2198                 surface->coeff_reduction_factor =
2199                         *srf_update->coeff_reduction_factor;
2200
2201         if (srf_update->gamut_remap_matrix)
2202                 surface->gamut_remap_matrix =
2203                         *srf_update->gamut_remap_matrix;
2204 }
2205
2206 static void copy_stream_update_to_stream(struct dc *dc,
2207                                          struct dc_state *context,
2208                                          struct dc_stream_state *stream,
2209                                          struct dc_stream_update *update)
2210 {
2211         struct dc_context *dc_ctx = dc->ctx;
2212
2213         if (update == NULL || stream == NULL)
2214                 return;
2215
2216         if (update->src.height && update->src.width)
2217                 stream->src = update->src;
2218
2219         if (update->dst.height && update->dst.width)
2220                 stream->dst = update->dst;
2221
2222         if (update->out_transfer_func &&
2223             stream->out_transfer_func != update->out_transfer_func) {
2224                 stream->out_transfer_func->sdr_ref_white_level =
2225                         update->out_transfer_func->sdr_ref_white_level;
2226                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2227                 stream->out_transfer_func->type =
2228                         update->out_transfer_func->type;
2229                 memcpy(&stream->out_transfer_func->tf_pts,
2230                        &update->out_transfer_func->tf_pts,
2231                        sizeof(struct dc_transfer_func_distributed_points));
2232         }
2233
2234         if (update->hdr_static_metadata)
2235                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2236
2237         if (update->abm_level)
2238                 stream->abm_level = *update->abm_level;
2239
2240         if (update->periodic_interrupt0)
2241                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2242
2243         if (update->periodic_interrupt1)
2244                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2245
2246         if (update->gamut_remap)
2247                 stream->gamut_remap_matrix = *update->gamut_remap;
2248
2249         /* Note: this being updated after mode set is currently not a use case
2250          * however if it arises OCSC would need to be reprogrammed at the
2251          * minimum
2252          */
2253         if (update->output_color_space)
2254                 stream->output_color_space = *update->output_color_space;
2255
2256         if (update->output_csc_transform)
2257                 stream->csc_color_matrix = *update->output_csc_transform;
2258
2259         if (update->vrr_infopacket)
2260                 stream->vrr_infopacket = *update->vrr_infopacket;
2261
2262         if (update->dpms_off)
2263                 stream->dpms_off = *update->dpms_off;
2264
2265         if (update->vsc_infopacket)
2266                 stream->vsc_infopacket = *update->vsc_infopacket;
2267
2268         if (update->vsp_infopacket)
2269                 stream->vsp_infopacket = *update->vsp_infopacket;
2270
2271         if (update->dither_option)
2272                 stream->dither_option = *update->dither_option;
2273         /* update current stream with writeback info */
2274         if (update->wb_update) {
2275                 int i;
2276
2277                 stream->num_wb_info = update->wb_update->num_wb_info;
2278                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2279                 for (i = 0; i < stream->num_wb_info; i++)
2280                         stream->writeback_info[i] =
2281                                 update->wb_update->writeback_info[i];
2282         }
2283         if (update->dsc_config) {
2284                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2285                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2286                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2287                                        update->dsc_config->num_slices_v != 0);
2288
2289                 /* Use temporarry context for validating new DSC config */
2290                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2291
2292                 if (dsc_validate_context) {
2293                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2294
2295                         stream->timing.dsc_cfg = *update->dsc_config;
2296                         stream->timing.flags.DSC = enable_dsc;
2297                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2298                                 stream->timing.dsc_cfg = old_dsc_cfg;
2299                                 stream->timing.flags.DSC = old_dsc_enabled;
2300                                 update->dsc_config = NULL;
2301                         }
2302
2303                         dc_release_state(dsc_validate_context);
2304                 } else {
2305                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2306                         update->dsc_config = NULL;
2307                 }
2308         }
2309 }
2310
2311 static void commit_planes_do_stream_update(struct dc *dc,
2312                 struct dc_stream_state *stream,
2313                 struct dc_stream_update *stream_update,
2314                 enum surface_update_type update_type,
2315                 struct dc_state *context)
2316 {
2317         int j;
2318         bool should_program_abm;
2319
2320         // Stream updates
2321         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2322                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2323
2324                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2325
2326                         if (stream_update->periodic_interrupt0 &&
2327                                         dc->hwss.setup_periodic_interrupt)
2328                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2329
2330                         if (stream_update->periodic_interrupt1 &&
2331                                         dc->hwss.setup_periodic_interrupt)
2332                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2333
2334                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2335                                         stream_update->vrr_infopacket ||
2336                                         stream_update->vsc_infopacket ||
2337                                         stream_update->vsp_infopacket) {
2338                                 resource_build_info_frame(pipe_ctx);
2339                                 dc->hwss.update_info_frame(pipe_ctx);
2340                         }
2341
2342                         if (stream_update->hdr_static_metadata &&
2343                                         stream->use_dynamic_meta &&
2344                                         dc->hwss.set_dmdata_attributes &&
2345                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2346                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2347
2348                         if (stream_update->gamut_remap)
2349                                 dc_stream_set_gamut_remap(dc, stream);
2350
2351                         if (stream_update->output_csc_transform)
2352                                 dc_stream_program_csc_matrix(dc, stream);
2353
2354                         if (stream_update->dither_option) {
2355                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2356                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2357                                                                         &pipe_ctx->stream->bit_depth_params);
2358                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2359                                                 &stream->bit_depth_params,
2360                                                 &stream->clamping);
2361                                 while (odm_pipe) {
2362                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2363                                                         &stream->bit_depth_params,
2364                                                         &stream->clamping);
2365                                         odm_pipe = odm_pipe->next_odm_pipe;
2366                                 }
2367                         }
2368
2369                         /* Full fe update*/
2370                         if (update_type == UPDATE_TYPE_FAST)
2371                                 continue;
2372
2373                         if (stream_update->dsc_config)
2374                                 dp_update_dsc_config(pipe_ctx);
2375
2376                         if (stream_update->dpms_off) {
2377                                 if (*stream_update->dpms_off) {
2378                                         core_link_disable_stream(pipe_ctx);
2379                                         /* for dpms, keep acquired resources*/
2380                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2381                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2382
2383                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
2384                                 } else {
2385                                         if (dc->optimize_seamless_boot_streams == 0)
2386                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2387
2388                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2389                                 }
2390                         }
2391
2392                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2393                                 should_program_abm = true;
2394
2395                                 // if otg funcs defined check if blanked before programming
2396                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2397                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2398                                                 should_program_abm = false;
2399
2400                                 if (should_program_abm) {
2401                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2402                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2403                                         } else {
2404                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2405                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2406                                         }
2407                                 }
2408                         }
2409                 }
2410         }
2411 }
2412
2413 static void commit_planes_for_stream(struct dc *dc,
2414                 struct dc_surface_update *srf_updates,
2415                 int surface_count,
2416                 struct dc_stream_state *stream,
2417                 struct dc_stream_update *stream_update,
2418                 enum surface_update_type update_type,
2419                 struct dc_state *context)
2420 {
2421         int i, j;
2422         struct pipe_ctx *top_pipe_to_program = NULL;
2423
2424         if (dc->optimize_seamless_boot_streams > 0 && surface_count > 0) {
2425                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2426                  * first flip. After first flip, optimization is required to lower
2427                  * bandwidth. Important to note that it is expected UEFI will
2428                  * only light up a single display on POST, therefore we only expect
2429                  * one stream with seamless boot flag set.
2430                  */
2431                 if (stream->apply_seamless_boot_optimization) {
2432                         stream->apply_seamless_boot_optimization = false;
2433                         dc->optimize_seamless_boot_streams--;
2434
2435                         if (dc->optimize_seamless_boot_streams == 0)
2436                                 dc->optimized_required = true;
2437                 }
2438         }
2439
2440         if (update_type == UPDATE_TYPE_FULL) {
2441 #if defined(CONFIG_DRM_AMD_DC_DCN)
2442                 dc_allow_idle_optimizations(dc, false);
2443
2444 #endif
2445                 if (dc->optimize_seamless_boot_streams == 0)
2446                         dc->hwss.prepare_bandwidth(dc, context);
2447
2448                 context_clock_trace(dc, context);
2449         }
2450
2451         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2452                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2453
2454                 if (!pipe_ctx->top_pipe &&
2455                         !pipe_ctx->prev_odm_pipe &&
2456                         pipe_ctx->stream &&
2457                         pipe_ctx->stream == stream) {
2458                         top_pipe_to_program = pipe_ctx;
2459                 }
2460         }
2461
2462         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2463                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2464                         if (should_use_dmub_lock(stream->link)) {
2465                                 union dmub_hw_lock_flags hw_locks = { 0 };
2466                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2467
2468                                 hw_locks.bits.lock_dig = 1;
2469                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2470
2471                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2472                                                         true,
2473                                                         &hw_locks,
2474                                                         &inst_flags);
2475                         } else
2476                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2477                                                 top_pipe_to_program->stream_res.tg);
2478                 }
2479
2480         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2481                 dc->hwss.interdependent_update_lock(dc, context, true);
2482         else
2483                 /* Lock the top pipe while updating plane addrs, since freesync requires
2484                  *  plane addr update event triggers to be synchronized.
2485                  *  top_pipe_to_program is expected to never be NULL
2486                  */
2487                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2488
2489         // Stream updates
2490         if (stream_update)
2491                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2492
2493         if (surface_count == 0) {
2494                 /*
2495                  * In case of turning off screen, no need to program front end a second time.
2496                  * just return after program blank.
2497                  */
2498                 if (dc->hwss.apply_ctx_for_surface)
2499                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2500                 if (dc->hwss.program_front_end_for_ctx)
2501                         dc->hwss.program_front_end_for_ctx(dc, context);
2502
2503                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2504                         dc->hwss.interdependent_update_lock(dc, context, false);
2505                 else
2506                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2507
2508                 dc->hwss.post_unlock_program_front_end(dc, context);
2509                 return;
2510         }
2511
2512         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2513                 for (i = 0; i < surface_count; i++) {
2514                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2515                         /*set logical flag for lock/unlock use*/
2516                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2517                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2518                                 if (!pipe_ctx->plane_state)
2519                                         continue;
2520                                 if (pipe_ctx->plane_state != plane_state)
2521                                         continue;
2522                                 plane_state->triplebuffer_flips = false;
2523                                 if (update_type == UPDATE_TYPE_FAST &&
2524                                         dc->hwss.program_triplebuffer != NULL &&
2525                                         !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2526                                                 /*triple buffer for VUpdate  only*/
2527                                                 plane_state->triplebuffer_flips = true;
2528                                 }
2529                         }
2530                 }
2531         }
2532
2533         // Update Type FULL, Surface updates
2534         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2535                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2536
2537                 if (!pipe_ctx->top_pipe &&
2538                         !pipe_ctx->prev_odm_pipe &&
2539                         pipe_ctx->stream &&
2540                         pipe_ctx->stream == stream) {
2541                         struct dc_stream_status *stream_status = NULL;
2542
2543                         if (!pipe_ctx->plane_state)
2544                                 continue;
2545
2546                         /* Full fe update*/
2547                         if (update_type == UPDATE_TYPE_FAST)
2548                                 continue;
2549
2550                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2551
2552                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2553                                 /*turn off triple buffer for full update*/
2554                                 dc->hwss.program_triplebuffer(
2555                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2556                         }
2557                         stream_status =
2558                                 stream_get_status(context, pipe_ctx->stream);
2559
2560                         if (dc->hwss.apply_ctx_for_surface)
2561                                 dc->hwss.apply_ctx_for_surface(
2562                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2563                 }
2564         }
2565         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2566                 dc->hwss.program_front_end_for_ctx(dc, context);
2567 #ifdef CONFIG_DRM_AMD_DC_DCN
2568                 if (dc->debug.validate_dml_output) {
2569                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2570                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2571                                 if (cur_pipe.stream == NULL)
2572                                         continue;
2573
2574                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2575                                                 cur_pipe.plane_res.hubp, dc->ctx,
2576                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2577                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2578                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2579                         }
2580                 }
2581 #endif
2582         }
2583
2584         // Update Type FAST, Surface updates
2585         if (update_type == UPDATE_TYPE_FAST) {
2586                 if (dc->hwss.set_flip_control_gsl)
2587                         for (i = 0; i < surface_count; i++) {
2588                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2589
2590                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2591                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2592
2593                                         if (pipe_ctx->stream != stream)
2594                                                 continue;
2595
2596                                         if (pipe_ctx->plane_state != plane_state)
2597                                                 continue;
2598
2599                                         // GSL has to be used for flip immediate
2600                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2601                                                         plane_state->flip_immediate);
2602                                 }
2603                         }
2604                 /* Perform requested Updates */
2605                 for (i = 0; i < surface_count; i++) {
2606                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2607
2608                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2609                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2610
2611                                 if (pipe_ctx->stream != stream)
2612                                         continue;
2613
2614                                 if (pipe_ctx->plane_state != plane_state)
2615                                         continue;
2616                                 /*program triple buffer after lock based on flip type*/
2617                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2618                                         /*only enable triplebuffer for  fast_update*/
2619                                         dc->hwss.program_triplebuffer(
2620                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2621                                 }
2622                                 if (srf_updates[i].flip_addr)
2623                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2624                         }
2625                 }
2626         }
2627
2628         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2629                 dc->hwss.interdependent_update_lock(dc, context, false);
2630         else
2631                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2632
2633         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2634                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2635                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2636                                         top_pipe_to_program->stream_res.tg,
2637                                         CRTC_STATE_VACTIVE);
2638                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2639                                         top_pipe_to_program->stream_res.tg,
2640                                         CRTC_STATE_VBLANK);
2641                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2642                                         top_pipe_to_program->stream_res.tg,
2643                                         CRTC_STATE_VACTIVE);
2644
2645                         if (stream && should_use_dmub_lock(stream->link)) {
2646                                 union dmub_hw_lock_flags hw_locks = { 0 };
2647                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2648
2649                                 hw_locks.bits.lock_dig = 1;
2650                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2651
2652                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2653                                                         false,
2654                                                         &hw_locks,
2655                                                         &inst_flags);
2656                         } else
2657                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2658                                         top_pipe_to_program->stream_res.tg);
2659                 }
2660
2661         if (update_type != UPDATE_TYPE_FAST)
2662                 dc->hwss.post_unlock_program_front_end(dc, context);
2663
2664         // Fire manual trigger only when bottom plane is flipped
2665         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2666                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2667
2668                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
2669                                 !pipe_ctx->stream || pipe_ctx->stream != stream ||
2670                                 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2671                         continue;
2672
2673                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2674                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2675         }
2676 }
2677
2678 void dc_commit_updates_for_stream(struct dc *dc,
2679                 struct dc_surface_update *srf_updates,
2680                 int surface_count,
2681                 struct dc_stream_state *stream,
2682                 struct dc_stream_update *stream_update,
2683                 struct dc_state *state)
2684 {
2685         const struct dc_stream_status *stream_status;
2686         enum surface_update_type update_type;
2687         struct dc_state *context;
2688         struct dc_context *dc_ctx = dc->ctx;
2689         int i, j;
2690
2691         stream_status = dc_stream_get_status(stream);
2692         context = dc->current_state;
2693
2694         update_type = dc_check_update_surfaces_for_stream(
2695                                 dc, srf_updates, surface_count, stream_update, stream_status);
2696
2697         if (update_type >= update_surface_trace_level)
2698                 update_surface_trace(dc, srf_updates, surface_count);
2699
2700
2701         if (update_type >= UPDATE_TYPE_FULL) {
2702
2703                 /* initialize scratch memory for building context */
2704                 context = dc_create_state(dc);
2705                 if (context == NULL) {
2706                         DC_ERROR("Failed to allocate new validate context!\n");
2707                         return;
2708                 }
2709
2710                 dc_resource_state_copy_construct(state, context);
2711
2712                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2713                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2714                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2715
2716                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2717                                 new_pipe->plane_state->force_full_update = true;
2718                 }
2719         }
2720
2721
2722         for (i = 0; i < surface_count; i++) {
2723                 struct dc_plane_state *surface = srf_updates[i].surface;
2724
2725                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2726
2727                 if (update_type >= UPDATE_TYPE_MED) {
2728                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2729                                 struct pipe_ctx *pipe_ctx =
2730                                         &context->res_ctx.pipe_ctx[j];
2731
2732                                 if (pipe_ctx->plane_state != surface)
2733                                         continue;
2734
2735                                 resource_build_scaling_params(pipe_ctx);
2736                         }
2737                 }
2738         }
2739
2740         copy_stream_update_to_stream(dc, context, stream, stream_update);
2741
2742         if (update_type >= UPDATE_TYPE_FULL) {
2743                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2744                         DC_ERROR("Mode validation failed for stream update!\n");
2745                         dc_release_state(context);
2746                         return;
2747                 }
2748         }
2749
2750         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
2751
2752         commit_planes_for_stream(
2753                                 dc,
2754                                 srf_updates,
2755                                 surface_count,
2756                                 stream,
2757                                 stream_update,
2758                                 update_type,
2759                                 context);
2760         /*update current_State*/
2761         if (dc->current_state != context) {
2762
2763                 struct dc_state *old = dc->current_state;
2764
2765                 dc->current_state = context;
2766                 dc_release_state(old);
2767
2768                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2769                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2770
2771                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2772                                 pipe_ctx->plane_state->force_full_update = false;
2773                 }
2774         }
2775         /*let's use current_state to update watermark etc*/
2776         if (update_type >= UPDATE_TYPE_FULL) {
2777                 dc_post_update_surfaces_to_stream(dc);
2778
2779                 if (dc_ctx->dce_version >= DCE_VERSION_MAX)
2780                         TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2781                 else
2782                         TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2783         }
2784
2785         return;
2786
2787 }
2788
2789 uint8_t dc_get_current_stream_count(struct dc *dc)
2790 {
2791         return dc->current_state->stream_count;
2792 }
2793
2794 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2795 {
2796         if (i < dc->current_state->stream_count)
2797                 return dc->current_state->streams[i];
2798         return NULL;
2799 }
2800
2801 struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link)
2802 {
2803         uint8_t i;
2804         struct dc_context *ctx = link->ctx;
2805
2806         for (i = 0; i < ctx->dc->current_state->stream_count; i++) {
2807                 if (ctx->dc->current_state->streams[i]->link == link)
2808                         return ctx->dc->current_state->streams[i];
2809         }
2810
2811         return NULL;
2812 }
2813
2814 enum dc_irq_source dc_interrupt_to_irq_source(
2815                 struct dc *dc,
2816                 uint32_t src_id,
2817                 uint32_t ext_id)
2818 {
2819         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2820 }
2821
2822 /**
2823  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2824  */
2825 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2826 {
2827
2828         if (dc == NULL)
2829                 return false;
2830
2831         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2832 }
2833
2834 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
2835 {
2836         dal_irq_service_ack(dc->res_pool->irqs, src);
2837 }
2838
2839 void dc_power_down_on_boot(struct dc *dc)
2840 {
2841         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
2842                         dc->hwss.power_down_on_boot)
2843                 dc->hwss.power_down_on_boot(dc);
2844 }
2845
2846 void dc_set_power_state(
2847         struct dc *dc,
2848         enum dc_acpi_cm_power_state power_state)
2849 {
2850         struct kref refcount;
2851         struct display_mode_lib *dml;
2852
2853         switch (power_state) {
2854         case DC_ACPI_CM_POWER_STATE_D0:
2855                 dc_resource_state_construct(dc, dc->current_state);
2856
2857                 if (dc->ctx->dmub_srv)
2858                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
2859
2860                 dc->hwss.init_hw(dc);
2861
2862                 if (dc->hwss.init_sys_ctx != NULL &&
2863                         dc->vm_pa_config.valid) {
2864                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
2865                 }
2866
2867                 break;
2868         default:
2869                 ASSERT(dc->current_state->stream_count == 0);
2870                 /* Zero out the current context so that on resume we start with
2871                  * clean state, and dc hw programming optimizations will not
2872                  * cause any trouble.
2873                  */
2874                 dml = kzalloc(sizeof(struct display_mode_lib),
2875                                 GFP_KERNEL);
2876
2877                 ASSERT(dml);
2878                 if (!dml)
2879                         return;
2880
2881                 /* Preserve refcount */
2882                 refcount = dc->current_state->refcount;
2883                 /* Preserve display mode lib */
2884                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2885
2886                 dc_resource_state_destruct(dc->current_state);
2887                 memset(dc->current_state, 0,
2888                                 sizeof(*dc->current_state));
2889
2890                 dc->current_state->refcount = refcount;
2891                 dc->current_state->bw_ctx.dml = *dml;
2892
2893                 kfree(dml);
2894
2895                 break;
2896         }
2897 }
2898
2899 void dc_resume(struct dc *dc)
2900 {
2901         uint32_t i;
2902
2903         for (i = 0; i < dc->link_count; i++)
2904                 core_link_resume(dc->links[i]);
2905 }
2906
2907 bool dc_is_dmcu_initialized(struct dc *dc)
2908 {
2909         struct dmcu *dmcu = dc->res_pool->dmcu;
2910
2911         if (dmcu)
2912                 return dmcu->funcs->is_dmcu_initialized(dmcu);
2913         return false;
2914 }
2915
2916 bool dc_submit_i2c(
2917                 struct dc *dc,
2918                 uint32_t link_index,
2919                 struct i2c_command *cmd)
2920 {
2921
2922         struct dc_link *link = dc->links[link_index];
2923         struct ddc_service *ddc = link->ddc;
2924         return dce_i2c_submit_command(
2925                 dc->res_pool,
2926                 ddc->ddc_pin,
2927                 cmd);
2928 }
2929
2930 bool dc_submit_i2c_oem(
2931                 struct dc *dc,
2932                 struct i2c_command *cmd)
2933 {
2934         struct ddc_service *ddc = dc->res_pool->oem_device;
2935         return dce_i2c_submit_command(
2936                 dc->res_pool,
2937                 ddc->ddc_pin,
2938                 cmd);
2939 }
2940
2941 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2942 {
2943         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2944                 BREAK_TO_DEBUGGER();
2945                 return false;
2946         }
2947
2948         dc_sink_retain(sink);
2949
2950         dc_link->remote_sinks[dc_link->sink_count] = sink;
2951         dc_link->sink_count++;
2952
2953         return true;
2954 }
2955
2956 /**
2957  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2958  *
2959  * EDID length is in bytes
2960  */
2961 struct dc_sink *dc_link_add_remote_sink(
2962                 struct dc_link *link,
2963                 const uint8_t *edid,
2964                 int len,
2965                 struct dc_sink_init_data *init_data)
2966 {
2967         struct dc_sink *dc_sink;
2968         enum dc_edid_status edid_status;
2969
2970         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2971                 dm_error("Max EDID buffer size breached!\n");
2972                 return NULL;
2973         }
2974
2975         if (!init_data) {
2976                 BREAK_TO_DEBUGGER();
2977                 return NULL;
2978         }
2979
2980         if (!init_data->link) {
2981                 BREAK_TO_DEBUGGER();
2982                 return NULL;
2983         }
2984
2985         dc_sink = dc_sink_create(init_data);
2986
2987         if (!dc_sink)
2988                 return NULL;
2989
2990         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2991         dc_sink->dc_edid.length = len;
2992
2993         if (!link_add_remote_sink_helper(
2994                         link,
2995                         dc_sink))
2996                 goto fail_add_sink;
2997
2998         edid_status = dm_helpers_parse_edid_caps(
2999                         link->ctx,
3000                         &dc_sink->dc_edid,
3001                         &dc_sink->edid_caps);
3002
3003         /*
3004          * Treat device as no EDID device if EDID
3005          * parsing fails
3006          */
3007         if (edid_status != EDID_OK) {
3008                 dc_sink->dc_edid.length = 0;
3009                 dm_error("Bad EDID, status%d!\n", edid_status);
3010         }
3011
3012         return dc_sink;
3013
3014 fail_add_sink:
3015         dc_sink_release(dc_sink);
3016         return NULL;
3017 }
3018
3019 /**
3020  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
3021  *
3022  * Note that this just removes the struct dc_sink - it doesn't
3023  * program hardware or alter other members of dc_link
3024  */
3025 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
3026 {
3027         int i;
3028
3029         if (!link->sink_count) {
3030                 BREAK_TO_DEBUGGER();
3031                 return;
3032         }
3033
3034         for (i = 0; i < link->sink_count; i++) {
3035                 if (link->remote_sinks[i] == sink) {
3036                         dc_sink_release(sink);
3037                         link->remote_sinks[i] = NULL;
3038
3039                         /* shrink array to remove empty place */
3040                         while (i < link->sink_count - 1) {
3041                                 link->remote_sinks[i] = link->remote_sinks[i+1];
3042                                 i++;
3043                         }
3044                         link->remote_sinks[i] = NULL;
3045                         link->sink_count--;
3046                         return;
3047                 }
3048         }
3049 }
3050
3051 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
3052 {
3053         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
3054         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
3055         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
3056         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
3057         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
3058         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
3059         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
3060         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
3061         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
3062 }
3063 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
3064 {
3065         if (dc->hwss.set_clock)
3066                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
3067         return DC_ERROR_UNEXPECTED;
3068 }
3069 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
3070 {
3071         if (dc->hwss.get_clock)
3072                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
3073 }
3074
3075 /* enable/disable eDP PSR without specify stream for eDP */
3076 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
3077 {
3078         int i;
3079
3080         for (i = 0; i < dc->current_state->stream_count ; i++) {
3081                 struct dc_link *link;
3082                 struct dc_stream_state *stream = dc->current_state->streams[i];
3083
3084                 link = stream->link;
3085                 if (!link)
3086                         continue;
3087
3088                 if (link->psr_settings.psr_feature_enabled) {
3089                         if (enable && !link->psr_settings.psr_allow_active)
3090                                 return dc_link_set_psr_allow_active(link, true, false, false);
3091                         else if (!enable && link->psr_settings.psr_allow_active)
3092                                 return dc_link_set_psr_allow_active(link, false, true, false);
3093                 }
3094         }
3095
3096         return true;
3097 }
3098
3099 #if defined(CONFIG_DRM_AMD_DC_DCN)
3100
3101 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
3102 {
3103         if (dc->debug.disable_idle_power_optimizations)
3104                 return;
3105
3106         if (allow == dc->idle_optimizations_allowed)
3107                 return;
3108
3109         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3110                 dc->idle_optimizations_allowed = allow;
3111 }
3112
3113 /*
3114  * blank all streams, and set min and max memory clock to
3115  * lowest and highest DPM level, respectively
3116  */
3117 void dc_unlock_memory_clock_frequency(struct dc *dc)
3118 {
3119         unsigned int i;
3120
3121         for (i = 0; i < MAX_PIPES; i++)
3122                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3123                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3124
3125         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3126         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3127 }
3128
3129 /*
3130  * set min memory clock to the min required for current mode,
3131  * max to maxDPM, and unblank streams
3132  */
3133 void dc_lock_memory_clock_frequency(struct dc *dc)
3134 {
3135         unsigned int i;
3136
3137         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3138         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3139         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3140
3141         for (i = 0; i < MAX_PIPES; i++)
3142                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3143                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3144 }
3145
3146 bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc,
3147                                                  struct dc_plane_state *plane)
3148 {
3149         return false;
3150 }
3151
3152 /* cleanup on driver unload */
3153 void dc_hardware_release(struct dc *dc)
3154 {
3155         if (dc->hwss.hardware_release)
3156                 dc->hwss.hardware_release(dc);
3157 }
3158 #endif