drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dccg.h"
  27 #include "clk_mgr_internal.h"
  28
  29
  30 #include "dcn20/dcn20_clk_mgr.h"
  31 #include "rn_clk_mgr.h"
  32
  33
  34 #include "dce100/dce_clk_mgr.h"
  35 #include "rn_clk_mgr_vbios_smu.h"
  36 #include "reg_helper.h"
  37 #include "core_types.h"
  38 #include "dm_helpers.h"
  39
  40 #include "atomfirmware.h"
  41 #include "clk/clk_10_0_2_offset.h"
  42 #include "clk/clk_10_0_2_sh_mask.h"
  43 #include "renoir_ip_offset.h"
  44
  45
  46 /* Constants */
  47
  48 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
  49 #define SMU_VER_55_51_0 0x373300 /* SMU Version that is able to set DISPCLK below 100MHz */
  50
  51 /* Macros */
  52
  53 #define REG(reg_name) \
  54         (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
  55
  56
  57 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
  58 int rn_get_active_display_cnt_wa(
  59                 struct dc *dc,
  60                 struct dc_state *context)
  61 {
  62         int i, display_count;
  63         bool tmds_present = false;
  64
  65         display_count = 0;
  66         for (i = 0; i < context->stream_count; i++) {
  67                 const struct dc_stream_state *stream = context->streams[i];
  68
  69                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  70                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  71                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  72                         tmds_present = true;
  73         }
  74
  75         for (i = 0; i < dc->link_count; i++) {
  76                 const struct dc_link *link = dc->links[i];
  77
  78                 /*
  79                  * Only notify active stream or virtual stream.
  80                  * Need to notify virtual stream to work around
  81                  * headless case. HPD does not fire when system is in
  82                  * S0i2.
  83                  */
  84                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
  85                 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL ||
  86                                 link->link_enc->funcs->is_dig_enabled(link->link_enc))
  87                         display_count++;
  88         }
  89
  90         /* WA for hang on HDMI after display off back back on*/
  91         if (display_count == 0 && tmds_present)
  92                 display_count = 1;
  93
  94         return display_count;
  95 }
  96
  97 void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
  98 {
  99         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 100
 101         rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
 102         /* update power state */
 103         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 104 }
 105
 106 static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 107                 struct dc_state *context, int ref_dpp_clk, bool safe_to_lower)
 108 {
 109         int i;
 110
 111         clk_mgr->dccg->ref_dppclk = ref_dpp_clk;
 112
 113         for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
 114                 int dpp_inst, dppclk_khz, prev_dppclk_khz;
 115
 116                 /* Loop index will match dpp->inst if resource exists,
 117                  * and we want to avoid dependency on dpp object
 118                  */
 119                 dpp_inst = i;
 120                 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
 121
 122                 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
 123
 124                 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
 125                         clk_mgr->dccg->funcs->update_dpp_dto(
 126                                                         clk_mgr->dccg, dpp_inst, dppclk_khz);
 127         }
 128 }
 129
 130
 131 void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 132                         struct dc_state *context,
 133                         bool safe_to_lower)
 134 {
 135         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 136         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 137         struct dc *dc = clk_mgr_base->ctx->dc;
 138         int display_count;
 139         bool update_dppclk = false;
 140         bool update_dispclk = false;
 141         bool dpp_clock_lowered = false;
 142
 143         struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
 144
 145         if (dc->work_arounds.skip_clock_update)
 146                 return;
 147
 148         /*
 149          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 150          * also if safe to lower is false, we just go in the higher state
 151          */
 152         if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) {
 153                 /* check that we're not already in lower */
 154                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 155
 156                         display_count = rn_get_active_display_cnt_wa(dc, context);
 157                         /* if we can go lower, go lower */
 158                         if (display_count == 0) {
 159                                 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
 160                                 /* update power state */
 161                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 162                         }
 163                 }
 164         } else {
 165                 /* check that we're not already in D0 */
 166                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 167                         rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
 168                         /* update power state */
 169                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 170                 }
 171         }
 172
 173         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 174                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 175                 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 176         }
 177
 178         if (should_set_clock(safe_to_lower,
 179                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 180                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 181                 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 182         }
 183
 184         // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
 185         // Do not adjust dppclk if dppclk is 0 to avoid unexpected result
 186         if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0)
 187                 new_clocks->dppclk_khz = 100000;
 188
 189         /*
 190          * Temporally ignore thew 0 cases for disp and dpp clks.
 191          * We may have a new feature that requires 0 clks in the future.
 192          */
 193         if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) {
 194                 new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz;
 195                 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz;
 196         }
 197
 198         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
 199                 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
 200                         dpp_clock_lowered = true;
 201                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 202                 update_dppclk = true;
 203         }
 204
 205         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 206                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 207                 clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 208
 209                 update_dispclk = true;
 210         }
 211
 212         if (dpp_clock_lowered) {
 213                 // increase per DPP DTO before lowering global dppclk with requested dppclk
 214                 rn_update_clocks_update_dpp_dto(
 215                                 clk_mgr,
 216                                 context,
 217                                 clk_mgr_base->clks.dppclk_khz,
 218                                 safe_to_lower);
 219
 220                 clk_mgr_base->clks.actual_dppclk_khz =
 221                                 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 222
 223                 //update dpp dto with actual dpp clk.
 224                 rn_update_clocks_update_dpp_dto(
 225                                 clk_mgr,
 226                                 context,
 227                                 clk_mgr_base->clks.actual_dppclk_khz,
 228                                 safe_to_lower);
 229
 230         } else {
 231                 // increase global DPPCLK before lowering per DPP DTO
 232                 if (update_dppclk || update_dispclk)
 233                         clk_mgr_base->clks.actual_dppclk_khz =
 234                                         rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 235
 236                 // always update dtos unless clock is lowered and not safe to lower
 237                 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
 238                         rn_update_clocks_update_dpp_dto(
 239                                         clk_mgr,
 240                                         context,
 241                                         clk_mgr_base->clks.actual_dppclk_khz,
 242                                         safe_to_lower);
 243         }
 244
 245         if (update_dispclk &&
 246                         dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
 247                 /*update dmcu for wait_loop count*/
 248                 dmcu->funcs->set_psr_wait_loop(dmcu,
 249                         clk_mgr_base->clks.dispclk_khz / 1000 / 7);
 250         }
 251 }
 252
 253 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 254 {
 255         /* get FbMult value */
 256         struct fixed31_32 pll_req;
 257         unsigned int fbmult_frac_val = 0;
 258         unsigned int fbmult_int_val = 0;
 259
 260
 261         /*
 262          * Register value of fbmult is in 8.16 format, we are converting to 31.32
 263          * to leverage the fix point operations available in driver
 264          */
 265
 266         REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
 267         REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
 268
 269         pll_req = dc_fixpt_from_int(fbmult_int_val);
 270
 271         /*
 272          * since fractional part is only 16 bit in register definition but is 32 bit
 273          * in our fix point definiton, need to shift left by 16 to obtain correct value
 274          */
 275         pll_req.value |= fbmult_frac_val << 16;
 276
 277         /* multiply by REFCLK period */
 278         pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
 279
 280         /* integer part is now VCO frequency in kHz */
 281         return dc_fixpt_floor(pll_req);
 282 }
 283
 284 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
 285 {
 286         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 287
 288         internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
 289         internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
 290
 291         internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);      //dcf deep sleep divider
 292         internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
 293
 294         internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
 295         internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
 296
 297         internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
 298         internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
 299
 300         internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
 301         internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
 302 }
 303
 304 /* This function collect raw clk register values */
 305 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 306                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 307 {
 308         struct rn_clk_internal internal = {0};
 309         char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
 310         unsigned int chars_printed = 0;
 311         unsigned int remaining_buffer = log_info->bufSize;
 312
 313         rn_dump_clk_registers_internal(&internal, clk_mgr_base);
 314
 315         regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
 316         regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
 317         regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
 318         regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
 319         regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
 320         regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 321
 322         regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
 323         if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
 324                 regs_and_bypass->dppclk_bypass = 0;
 325         regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
 326         if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
 327                 regs_and_bypass->dcfclk_bypass = 0;
 328         regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
 329         if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
 330                 regs_and_bypass->dispclk_bypass = 0;
 331         regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
 332         if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
 333                 regs_and_bypass->dprefclk_bypass = 0;
 334
 335         if (log_info->enabled) {
 336                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
 337                 remaining_buffer -= chars_printed;
 338                 *log_info->sum_chars_printed += chars_printed;
 339                 log_info->pBuf += chars_printed;
 340
 341                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
 342                         regs_and_bypass->dcfclk,
 343                         regs_and_bypass->dcf_deep_sleep_divider,
 344                         regs_and_bypass->dcf_deep_sleep_allow,
 345                         bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
 346                 remaining_buffer -= chars_printed;
 347                 *log_info->sum_chars_printed += chars_printed;
 348                 log_info->pBuf += chars_printed;
 349
 350                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
 351                         regs_and_bypass->dprefclk,
 352                         bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
 353                 remaining_buffer -= chars_printed;
 354                 *log_info->sum_chars_printed += chars_printed;
 355                 log_info->pBuf += chars_printed;
 356
 357                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
 358                         regs_and_bypass->dispclk,
 359                         bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
 360                 remaining_buffer -= chars_printed;
 361                 *log_info->sum_chars_printed += chars_printed;
 362                 log_info->pBuf += chars_printed;
 363
 364                 //split
 365                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
 366                 remaining_buffer -= chars_printed;
 367                 *log_info->sum_chars_printed += chars_printed;
 368                 log_info->pBuf += chars_printed;
 369
 370                 // REGISTER VALUES
 371                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
 372                 remaining_buffer -= chars_printed;
 373                 *log_info->sum_chars_printed += chars_printed;
 374                 log_info->pBuf += chars_printed;
 375
 376                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
 377                                 internal.CLK1_CLK3_CURRENT_CNT);
 378                 remaining_buffer -= chars_printed;
 379                 *log_info->sum_chars_printed += chars_printed;
 380                 log_info->pBuf += chars_printed;
 381
 382                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
 383                                         internal.CLK1_CLK3_DS_CNTL);
 384                 remaining_buffer -= chars_printed;
 385                 *log_info->sum_chars_printed += chars_printed;
 386                 log_info->pBuf += chars_printed;
 387
 388                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
 389                                         internal.CLK1_CLK3_ALLOW_DS);
 390                 remaining_buffer -= chars_printed;
 391                 *log_info->sum_chars_printed += chars_printed;
 392                 log_info->pBuf += chars_printed;
 393
 394                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
 395                                         internal.CLK1_CLK2_CURRENT_CNT);
 396                 remaining_buffer -= chars_printed;
 397                 *log_info->sum_chars_printed += chars_printed;
 398                 log_info->pBuf += chars_printed;
 399
 400                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
 401                                         internal.CLK1_CLK0_CURRENT_CNT);
 402                 remaining_buffer -= chars_printed;
 403                 *log_info->sum_chars_printed += chars_printed;
 404                 log_info->pBuf += chars_printed;
 405
 406                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
 407                                         internal.CLK1_CLK1_CURRENT_CNT);
 408                 remaining_buffer -= chars_printed;
 409                 *log_info->sum_chars_printed += chars_printed;
 410                 log_info->pBuf += chars_printed;
 411
 412                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
 413                                         internal.CLK1_CLK3_BYPASS_CNTL);
 414                 remaining_buffer -= chars_printed;
 415                 *log_info->sum_chars_printed += chars_printed;
 416                 log_info->pBuf += chars_printed;
 417
 418                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
 419                                         internal.CLK1_CLK2_BYPASS_CNTL);
 420                 remaining_buffer -= chars_printed;
 421                 *log_info->sum_chars_printed += chars_printed;
 422                 log_info->pBuf += chars_printed;
 423
 424                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
 425                                         internal.CLK1_CLK0_BYPASS_CNTL);
 426                 remaining_buffer -= chars_printed;
 427                 *log_info->sum_chars_printed += chars_printed;
 428                 log_info->pBuf += chars_printed;
 429
 430                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
 431                                         internal.CLK1_CLK1_BYPASS_CNTL);
 432                 remaining_buffer -= chars_printed;
 433                 *log_info->sum_chars_printed += chars_printed;
 434                 log_info->pBuf += chars_printed;
 435         }
 436 }
 437
 438 /* This function produce translated logical clk state values*/
 439 void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
 440 {
 441         struct clk_state_registers_and_bypass sb = { 0 };
 442         struct clk_log_info log_info = { 0 };
 443
 444         rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
 445
 446         s->dprefclk_khz = sb.dprefclk * 1000;
 447 }
 448
 449 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 450 {
 451         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 452
 453         rn_vbios_smu_enable_pme_wa(clk_mgr);
 454 }
 455
 456 void rn_init_clocks(struct clk_mgr *clk_mgr)
 457 {
 458         memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
 459         // Assumption is that boot state always supports pstate
 460         clk_mgr->clks.p_state_change_support = true;
 461         clk_mgr->clks.prev_p_state_change_support = true;
 462         clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 463 }
 464
 465 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
 466 {
 467         int i, num_valid_sets;
 468
 469         num_valid_sets = 0;
 470
 471         for (i = 0; i < WM_SET_COUNT; i++) {
 472                 /* skip empty entries, the smu array has no holes*/
 473                 if (!bw_params->wm_table.entries[i].valid)
 474                         continue;
 475
 476                 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
 477                 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
 478                 /* We will not select WM based on fclk, so leave it as unconstrained */
 479                 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 480                 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 481                 /* dcfclk wil be used to select WM*/
 482
 483                 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
 484                         if (i == 0)
 485                                 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0;
 486                         else {
 487                                 /* add 1 to make it non-overlapping with next lvl */
 488                                 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
 489                         }
 490                         ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
 491
 492                 } else {
 493                         /* unconstrained for memory retraining */
 494                         ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 495                         ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 496
 497                         /* Modify previous watermark range to cover up to max */
 498                         ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 499                 }
 500                 num_valid_sets++;
 501         }
 502
 503         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 504         ranges->num_reader_wm_sets = num_valid_sets;
 505
 506         /* modify the min and max to make sure we cover the whole range*/
 507         ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 508         ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 509         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 510         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 511
 512         /* This is for writeback only, does not matter currently as no writeback support*/
 513         ranges->num_writer_wm_sets = 1;
 514         ranges->writer_wm_sets[0].wm_inst = WM_A;
 515         ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 516         ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 517         ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 518         ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 519
 520 }
 521
 522 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 523 {
 524         struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
 525         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 526         struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
 527
 528         if (!debug->disable_pplib_wm_range) {
 529                 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges);
 530
 531                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
 532                 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
 533                         pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges);
 534         }
 535
 536 }
 537
 538 static bool rn_are_clock_states_equal(struct dc_clocks *a,
 539                 struct dc_clocks *b)
 540 {
 541         if (a->dispclk_khz != b->dispclk_khz)
 542                 return false;
 543         else if (a->dppclk_khz != b->dppclk_khz)
 544                 return false;
 545         else if (a->dcfclk_khz != b->dcfclk_khz)
 546                 return false;
 547         else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 548                 return false;
 549
 550         return true;
 551 }
 552
 553
 554 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
 555 static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
 556 {
 557         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 558         unsigned int i, max_phyclk_req = 0;
 559
 560         clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
 561
 562         for (i = 0; i < MAX_PIPES * 2; i++) {
 563                 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
 564                         max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
 565         }
 566
 567         if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
 568                 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
 569                 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
 570         }
 571 }
 572
 573 static struct clk_mgr_funcs dcn21_funcs = {
 574         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 575         .update_clocks = rn_update_clocks,
 576         .init_clocks = rn_init_clocks,
 577         .enable_pme_wa = rn_enable_pme_wa,
 578         .are_clock_states_equal = rn_are_clock_states_equal,
 579         .set_low_power_state = rn_set_low_power_state,
 580         .notify_wm_ranges = rn_notify_wm_ranges,
 581         .notify_link_rate_change = rn_notify_link_rate_change,
 582 };
 583
 584 static struct clk_bw_params rn_bw_params = {
 585         .vram_type = Ddr4MemType,
 586         .num_channels = 1,
 587         .clk_table = {
 588                 .entries = {
 589                         {
 590                                 .voltage = 0,
 591                                 .dcfclk_mhz = 400,
 592                                 .fclk_mhz = 400,
 593                                 .memclk_mhz = 800,
 594                                 .socclk_mhz = 0,
 595                         },
 596                         {
 597                                 .voltage = 0,
 598                                 .dcfclk_mhz = 483,
 599                                 .fclk_mhz = 800,
 600                                 .memclk_mhz = 1600,
 601                                 .socclk_mhz = 0,
 602                         },
 603                         {
 604                                 .voltage = 0,
 605                                 .dcfclk_mhz = 602,
 606                                 .fclk_mhz = 1067,
 607                                 .memclk_mhz = 1067,
 608                                 .socclk_mhz = 0,
 609                         },
 610                         {
 611                                 .voltage = 0,
 612                                 .dcfclk_mhz = 738,
 613                                 .fclk_mhz = 1333,
 614                                 .memclk_mhz = 1600,
 615                                 .socclk_mhz = 0,
 616                         },
 617                 },
 618
 619                 .num_entries = 4,
 620         },
 621
 622 };
 623
 624 static struct wm_table ddr4_wm_table_gs = {
 625         .entries = {
 626                 {
 627                         .wm_inst = WM_A,
 628                         .wm_type = WM_TYPE_PSTATE_CHG,
 629                         .pstate_latency_us = 11.72,
 630                         .sr_exit_time_us = 7.09,
 631                         .sr_enter_plus_exit_time_us = 8.14,
 632                         .valid = true,
 633                 },
 634                 {
 635                         .wm_inst = WM_B,
 636                         .wm_type = WM_TYPE_PSTATE_CHG,
 637                         .pstate_latency_us = 11.72,
 638                         .sr_exit_time_us = 10.12,
 639                         .sr_enter_plus_exit_time_us = 11.48,
 640                         .valid = true,
 641                 },
 642                 {
 643                         .wm_inst = WM_C,
 644                         .wm_type = WM_TYPE_PSTATE_CHG,
 645                         .pstate_latency_us = 11.72,
 646                         .sr_exit_time_us = 10.12,
 647                         .sr_enter_plus_exit_time_us = 11.48,
 648                         .valid = true,
 649                 },
 650                 {
 651                         .wm_inst = WM_D,
 652                         .wm_type = WM_TYPE_PSTATE_CHG,
 653                         .pstate_latency_us = 11.72,
 654                         .sr_exit_time_us = 10.12,
 655                         .sr_enter_plus_exit_time_us = 11.48,
 656                         .valid = true,
 657                 },
 658         }
 659 };
 660
 661 static struct wm_table lpddr4_wm_table_gs = {
 662         .entries = {
 663                 {
 664                         .wm_inst = WM_A,
 665                         .wm_type = WM_TYPE_PSTATE_CHG,
 666                         .pstate_latency_us = 11.65333,
 667                         .sr_exit_time_us = 5.32,
 668                         .sr_enter_plus_exit_time_us = 6.38,
 669                         .valid = true,
 670                 },
 671                 {
 672                         .wm_inst = WM_B,
 673                         .wm_type = WM_TYPE_PSTATE_CHG,
 674                         .pstate_latency_us = 11.65333,
 675                         .sr_exit_time_us = 9.82,
 676                         .sr_enter_plus_exit_time_us = 11.196,
 677                         .valid = true,
 678                 },
 679                 {
 680                         .wm_inst = WM_C,
 681                         .wm_type = WM_TYPE_PSTATE_CHG,
 682                         .pstate_latency_us = 11.65333,
 683                         .sr_exit_time_us = 9.89,
 684                         .sr_enter_plus_exit_time_us = 11.24,
 685                         .valid = true,
 686                 },
 687                 {
 688                         .wm_inst = WM_D,
 689                         .wm_type = WM_TYPE_PSTATE_CHG,
 690                         .pstate_latency_us = 11.65333,
 691                         .sr_exit_time_us = 9.748,
 692                         .sr_enter_plus_exit_time_us = 11.102,
 693                         .valid = true,
 694                 },
 695         }
 696 };
 697
 698 static struct wm_table lpddr4_wm_table_with_disabled_ppt = {
 699         .entries = {
 700                 {
 701                         .wm_inst = WM_A,
 702                         .wm_type = WM_TYPE_PSTATE_CHG,
 703                         .pstate_latency_us = 11.65333,
 704                         .sr_exit_time_us = 8.32,
 705                         .sr_enter_plus_exit_time_us = 9.38,
 706                         .valid = true,
 707                 },
 708                 {
 709                         .wm_inst = WM_B,
 710                         .wm_type = WM_TYPE_PSTATE_CHG,
 711                         .pstate_latency_us = 11.65333,
 712                         .sr_exit_time_us = 9.82,
 713                         .sr_enter_plus_exit_time_us = 11.196,
 714                         .valid = true,
 715                 },
 716                 {
 717                         .wm_inst = WM_C,
 718                         .wm_type = WM_TYPE_PSTATE_CHG,
 719                         .pstate_latency_us = 11.65333,
 720                         .sr_exit_time_us = 9.89,
 721                         .sr_enter_plus_exit_time_us = 11.24,
 722                         .valid = true,
 723                 },
 724                 {
 725                         .wm_inst = WM_D,
 726                         .wm_type = WM_TYPE_PSTATE_CHG,
 727                         .pstate_latency_us = 11.65333,
 728                         .sr_exit_time_us = 9.748,
 729                         .sr_enter_plus_exit_time_us = 11.102,
 730                         .valid = true,
 731                 },
 732         }
 733 };
 734
 735 static struct wm_table ddr4_wm_table_rn = {
 736         .entries = {
 737                 {
 738                         .wm_inst = WM_A,
 739                         .wm_type = WM_TYPE_PSTATE_CHG,
 740                         .pstate_latency_us = 11.72,
 741                         .sr_exit_time_us = 9.09,
 742                         .sr_enter_plus_exit_time_us = 10.14,
 743                         .valid = true,
 744                 },
 745                 {
 746                         .wm_inst = WM_B,
 747                         .wm_type = WM_TYPE_PSTATE_CHG,
 748                         .pstate_latency_us = 11.72,
 749                         .sr_exit_time_us = 11.12,
 750                         .sr_enter_plus_exit_time_us = 12.48,
 751                         .valid = true,
 752                 },
 753                 {
 754                         .wm_inst = WM_C,
 755                         .wm_type = WM_TYPE_PSTATE_CHG,
 756                         .pstate_latency_us = 11.72,
 757                         .sr_exit_time_us = 11.12,
 758                         .sr_enter_plus_exit_time_us = 12.48,
 759                         .valid = true,
 760                 },
 761                 {
 762                         .wm_inst = WM_D,
 763                         .wm_type = WM_TYPE_PSTATE_CHG,
 764                         .pstate_latency_us = 11.72,
 765                         .sr_exit_time_us = 11.12,
 766                         .sr_enter_plus_exit_time_us = 12.48,
 767                         .valid = true,
 768                 },
 769         }
 770 };
 771
 772 static struct wm_table lpddr4_wm_table_rn = {
 773         .entries = {
 774                 {
 775                         .wm_inst = WM_A,
 776                         .wm_type = WM_TYPE_PSTATE_CHG,
 777                         .pstate_latency_us = 11.65333,
 778                         .sr_exit_time_us = 7.32,
 779                         .sr_enter_plus_exit_time_us = 8.38,
 780                         .valid = true,
 781                 },
 782                 {
 783                         .wm_inst = WM_B,
 784                         .wm_type = WM_TYPE_PSTATE_CHG,
 785                         .pstate_latency_us = 11.65333,
 786                         .sr_exit_time_us = 9.82,
 787                         .sr_enter_plus_exit_time_us = 11.196,
 788                         .valid = true,
 789                 },
 790                 {
 791                         .wm_inst = WM_C,
 792                         .wm_type = WM_TYPE_PSTATE_CHG,
 793                         .pstate_latency_us = 11.65333,
 794                         .sr_exit_time_us = 9.89,
 795                         .sr_enter_plus_exit_time_us = 11.24,
 796                         .valid = true,
 797                 },
 798                 {
 799                         .wm_inst = WM_D,
 800                         .wm_type = WM_TYPE_PSTATE_CHG,
 801                         .pstate_latency_us = 11.65333,
 802                         .sr_exit_time_us = 9.748,
 803                         .sr_enter_plus_exit_time_us = 11.102,
 804                         .valid = true,
 805                 },
 806         }
 807 };
 808
 809 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 810 {
 811         int i;
 812
 813         for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
 814                 if (clock_table->DcfClocks[i].Vol == voltage)
 815                         return clock_table->DcfClocks[i].Freq;
 816         }
 817
 818         ASSERT(0);
 819         return 0;
 820 }
 821
 822 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
 823 {
 824         int i, j = 0;
 825
 826         j = -1;
 827
 828         ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
 829
 830         /* Find lowest DPM, FCLK is filled in reverse order*/
 831
 832         for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
 833                 if (clock_table->FClocks[i].Freq != 0 && clock_table->FClocks[i].Vol != 0) {
 834                         j = i;
 835                         break;
 836                 }
 837         }
 838
 839         if (j == -1) {
 840                 /* clock table is all 0s, just use our own hardcode */
 841                 ASSERT(0);
 842                 return;
 843         }
 844
 845         bw_params->clk_table.num_entries = j + 1;
 846
 847         for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
 848                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
 849                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
 850                 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
 851                 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
 852         }
 853
 854         bw_params->vram_type = bios_info->memory_type;
 855         bw_params->num_channels = bios_info->ma_channel_number;
 856
 857         for (i = 0; i < WM_SET_COUNT; i++) {
 858                 bw_params->wm_table.entries[i].wm_inst = i;
 859
 860                 if (i >= bw_params->clk_table.num_entries) {
 861                         bw_params->wm_table.entries[i].valid = false;
 862                         continue;
 863                 }
 864
 865                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 866                 bw_params->wm_table.entries[i].valid = true;
 867         }
 868
 869         if (bw_params->vram_type == LpDdr4MemType) {
 870                 /*
 871                  * WM set D will be re-purposed for memory retraining
 872                  */
 873                 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
 874                 bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
 875                 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
 876                 bw_params->wm_table.entries[WM_D].valid = true;
 877         }
 878
 879 }
 880
 881 void rn_clk_mgr_construct(
 882                 struct dc_context *ctx,
 883                 struct clk_mgr_internal *clk_mgr,
 884                 struct pp_smu_funcs *pp_smu,
 885                 struct dccg *dccg)
 886 {
 887         struct dc_debug_options *debug = &ctx->dc->debug;
 888         struct dpm_clocks clock_table = { 0 };
 889         enum pp_smu_status status = 0;
 890         int is_green_sardine = 0;
 891
 892 #if defined(CONFIG_DRM_AMD_DC_DCN)
 893         is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);
 894 #endif
 895
 896         clk_mgr->base.ctx = ctx;
 897         clk_mgr->base.funcs = &dcn21_funcs;
 898
 899         clk_mgr->pp_smu = pp_smu;
 900
 901         clk_mgr->dccg = dccg;
 902         clk_mgr->dfs_bypass_disp_clk = 0;
 903
 904         clk_mgr->dprefclk_ss_percentage = 0;
 905         clk_mgr->dprefclk_ss_divider = 1000;
 906         clk_mgr->ss_on_dprefclk = false;
 907         clk_mgr->dfs_ref_freq_khz = 48000;
 908
 909         clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
 910
 911         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
 912                 dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
 913                 clk_mgr->base.dentist_vco_freq_khz = 3600000;
 914         } else {
 915                 struct clk_log_info log_info = {0};
 916
 917                 clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);
 918
 919                 /* SMU Version 55.51.0 and up no longer have an issue
 920                  * that needs to limit minimum dispclk */
 921                 if (clk_mgr->smu_ver >= SMU_VER_55_51_0)
 922                         debug->min_disp_clk_khz = 0;
 923
 924                 /* TODO: Check we get what we expect during bringup */
 925                 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
 926
 927                 /* in case we don't get a value from the register, use default */
 928                 if (clk_mgr->base.dentist_vco_freq_khz == 0)
 929                         clk_mgr->base.dentist_vco_freq_khz = 3600000;
 930
 931                 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
 932                         if (clk_mgr->periodic_retraining_disabled) {
 933                                 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
 934                         } else {
 935                                 if (is_green_sardine)
 936                                         rn_bw_params.wm_table = lpddr4_wm_table_gs;
 937                                 else
 938                                         rn_bw_params.wm_table = lpddr4_wm_table_rn;
 939                         }
 940                 } else {
 941                         if (is_green_sardine)
 942                                 rn_bw_params.wm_table = ddr4_wm_table_gs;
 943                         else
 944                                 rn_bw_params.wm_table = ddr4_wm_table_rn;
 945                 }
 946                 /* Saved clocks configured at boot for debug purposes */
 947                 rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
 948         }
 949
 950         clk_mgr->base.dprefclk_khz = 600000;
 951         dce_clock_read_ss_info(clk_mgr);
 952
 953
 954         clk_mgr->base.bw_params = &rn_bw_params;
 955
 956         if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
 957                 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
 958
 959                 if (status == PP_SMU_RESULT_OK &&
 960                     ctx->dc_bios && ctx->dc_bios->integrated_info) {
 961                         rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
 962                 }
 963         }
 964
 965         if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
 966                 /* enable powerfeatures when displaycount goes to 0 */
 967                 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
 968         }
 969 }
 970