2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm/drm_atomic.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_dp_mst_helper.h>
29 #include <drm/drm_dp_helper.h>
30 #include "dm_services.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_mst_types.h"
36 #include "dm_helpers.h"
38 #include "dc_link_ddc.h"
40 #include "i2caux_interface.h"
42 #if defined(CONFIG_DEBUG_FS)
43 #include "amdgpu_dm_debugfs.h"
46 #if defined(CONFIG_DRM_AMD_DC_DCN)
47 #include "dc/dcn20/dcn20_resource.h"
50 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
51 struct drm_dp_aux_msg *msg)
54 struct aux_payload payload;
55 enum aux_return_code_type operation_result;
57 if (WARN_ON(msg->size > 16))
60 payload.address = msg->address;
61 payload.data = msg->buffer;
62 payload.length = msg->size;
63 payload.reply = &msg->reply;
64 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
65 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
66 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
67 payload.defer_delay = 0;
69 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
72 if (payload.write && result >= 0)
76 switch (operation_result) {
79 case AUX_RET_ERROR_HPD_DISCON:
80 case AUX_RET_ERROR_UNKNOWN:
81 case AUX_RET_ERROR_INVALID_OPERATION:
82 case AUX_RET_ERROR_PROTOCOL_ERROR:
85 case AUX_RET_ERROR_INVALID_REPLY:
86 case AUX_RET_ERROR_ENGINE_ACQUIRE:
89 case AUX_RET_ERROR_TIMEOUT:
98 dm_dp_mst_connector_destroy(struct drm_connector *connector)
100 struct amdgpu_dm_connector *aconnector =
101 to_amdgpu_dm_connector(connector);
103 if (aconnector->dc_sink) {
104 dc_link_remove_remote_sink(aconnector->dc_link,
105 aconnector->dc_sink);
106 dc_sink_release(aconnector->dc_sink);
109 kfree(aconnector->edid);
111 drm_connector_cleanup(connector);
112 drm_dp_mst_put_port_malloc(aconnector->port);
117 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
119 struct amdgpu_dm_connector *amdgpu_dm_connector =
120 to_amdgpu_dm_connector(connector);
123 r = drm_dp_mst_connector_late_register(connector,
124 amdgpu_dm_connector->port);
128 #if defined(CONFIG_DEBUG_FS)
129 connector_debugfs_init(amdgpu_dm_connector);
136 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
138 struct amdgpu_dm_connector *amdgpu_dm_connector =
139 to_amdgpu_dm_connector(connector);
140 struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
142 drm_dp_mst_connector_early_unregister(connector, port);
145 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
146 .fill_modes = drm_helper_probe_single_connector_modes,
147 .destroy = dm_dp_mst_connector_destroy,
148 .reset = amdgpu_dm_connector_funcs_reset,
149 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
150 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
151 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
152 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
153 .late_register = amdgpu_dm_mst_connector_late_register,
154 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
157 #if defined(CONFIG_DRM_AMD_DC_DCN)
158 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
160 struct dc_sink *dc_sink = aconnector->dc_sink;
161 struct drm_dp_mst_port *port = aconnector->port;
162 u8 dsc_caps[16] = { 0 };
163 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
164 u8 *dsc_branch_dec_caps = NULL;
166 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
167 #if defined(CONFIG_HP_HOOK_WORKAROUND)
169 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
170 * because it only check the dsc/fec caps of the "port variable" and not the dock
172 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
174 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
178 if (!aconnector->dsc_aux && !port->parent->port_parent)
179 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
181 if (!aconnector->dsc_aux)
184 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
187 if (drm_dp_dpcd_read(aconnector->dsc_aux,
188 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
189 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
191 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
192 dsc_caps, dsc_branch_dec_caps,
193 &dc_sink->dsc_caps.dsc_dec_caps))
200 static int dm_dp_mst_get_modes(struct drm_connector *connector)
202 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
206 return drm_add_edid_modes(connector, NULL);
208 if (!aconnector->edid) {
210 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
213 drm_connector_update_edid_property(
217 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
218 if (!aconnector->dc_sink) {
219 struct dc_sink *dc_sink;
220 struct dc_sink_init_data init_params = {
221 .link = aconnector->dc_link,
222 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
224 dc_sink = dc_link_add_remote_sink(
231 DRM_ERROR("Unable to add a remote sink\n");
235 dc_sink->priv = aconnector;
236 aconnector->dc_sink = dc_sink;
242 aconnector->edid = edid;
245 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
246 dc_sink_release(aconnector->dc_sink);
247 aconnector->dc_sink = NULL;
250 if (!aconnector->dc_sink) {
251 struct dc_sink *dc_sink;
252 struct dc_sink_init_data init_params = {
253 .link = aconnector->dc_link,
254 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
255 dc_sink = dc_link_add_remote_sink(
257 (uint8_t *)aconnector->edid,
258 (aconnector->edid->extensions + 1) * EDID_LENGTH,
262 DRM_ERROR("Unable to add a remote sink\n");
266 dc_sink->priv = aconnector;
267 /* dc_link_add_remote_sink returns a new reference */
268 aconnector->dc_sink = dc_sink;
270 if (aconnector->dc_sink) {
271 amdgpu_dm_update_freesync_caps(
272 connector, aconnector->edid);
274 #if defined(CONFIG_DRM_AMD_DC_DCN)
275 if (!validate_dsc_caps_on_connector(aconnector))
276 memset(&aconnector->dc_sink->dsc_caps,
277 0, sizeof(aconnector->dc_sink->dsc_caps));
282 drm_connector_update_edid_property(
283 &aconnector->base, aconnector->edid);
285 ret = drm_add_edid_modes(connector, aconnector->edid);
290 static struct drm_encoder *
291 dm_mst_atomic_best_encoder(struct drm_connector *connector,
292 struct drm_atomic_state *state)
294 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
296 struct drm_device *dev = connector->dev;
297 struct amdgpu_device *adev = drm_to_adev(dev);
298 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
300 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
304 dm_dp_mst_detect(struct drm_connector *connector,
305 struct drm_modeset_acquire_ctx *ctx, bool force)
307 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
308 struct amdgpu_dm_connector *master = aconnector->mst_port;
310 if (drm_connector_is_unregistered(connector))
311 return connector_status_disconnected;
313 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
317 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
318 struct drm_atomic_state *state)
320 struct drm_connector_state *new_conn_state =
321 drm_atomic_get_new_connector_state(state, connector);
322 struct drm_connector_state *old_conn_state =
323 drm_atomic_get_old_connector_state(state, connector);
324 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
325 struct drm_crtc_state *new_crtc_state;
326 struct drm_dp_mst_topology_mgr *mst_mgr;
327 struct drm_dp_mst_port *mst_port;
329 mst_port = aconnector->port;
330 mst_mgr = &aconnector->mst_port->mst_mgr;
332 if (!old_conn_state->crtc)
335 if (new_conn_state->crtc) {
336 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
337 if (!new_crtc_state ||
338 !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
339 new_crtc_state->enable)
343 return drm_dp_atomic_release_vcpi_slots(state,
348 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
349 .get_modes = dm_dp_mst_get_modes,
350 .mode_valid = amdgpu_dm_connector_mode_valid,
351 .atomic_best_encoder = dm_mst_atomic_best_encoder,
352 .detect_ctx = dm_dp_mst_detect,
353 .atomic_check = dm_dp_mst_atomic_check,
356 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
358 drm_encoder_cleanup(encoder);
362 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
363 .destroy = amdgpu_dm_encoder_destroy,
367 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
369 struct drm_device *dev = adev_to_drm(adev);
372 for (i = 0; i < adev->dm.display_indexes_num; i++) {
373 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
374 struct drm_encoder *encoder = &amdgpu_encoder->base;
376 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
380 &amdgpu_encoder->base,
381 &amdgpu_dm_encoder_funcs,
382 DRM_MODE_ENCODER_DPMST,
385 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
389 static struct drm_connector *
390 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
391 struct drm_dp_mst_port *port,
392 const char *pathprop)
394 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
395 struct drm_device *dev = master->base.dev;
396 struct amdgpu_device *adev = drm_to_adev(dev);
397 struct amdgpu_dm_connector *aconnector;
398 struct drm_connector *connector;
401 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
405 connector = &aconnector->base;
406 aconnector->port = port;
407 aconnector->mst_port = master;
409 if (drm_connector_init(
412 &dm_dp_mst_connector_funcs,
413 DRM_MODE_CONNECTOR_DisplayPort)) {
417 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
419 amdgpu_dm_connector_init_helper(
422 DRM_MODE_CONNECTOR_DisplayPort,
424 master->connector_id);
426 for (i = 0; i < adev->dm.display_indexes_num; i++) {
427 drm_connector_attach_encoder(&aconnector->base,
428 &adev->dm.mst_encoders[i].base);
431 connector->max_bpc_property = master->base.max_bpc_property;
432 if (connector->max_bpc_property)
433 drm_connector_attach_max_bpc_property(connector, 8, 16);
435 connector->vrr_capable_property = master->base.vrr_capable_property;
436 if (connector->vrr_capable_property)
437 drm_connector_attach_vrr_capable_property(connector);
439 drm_object_attach_property(
441 dev->mode_config.path_property,
443 drm_object_attach_property(
445 dev->mode_config.tile_property,
448 drm_connector_set_path_property(connector, pathprop);
451 * Initialize connector state before adding the connectror to drm and
454 amdgpu_dm_connector_funcs_reset(connector);
456 drm_dp_mst_get_port_malloc(port);
461 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
462 .add_connector = dm_dp_add_mst_connector,
465 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
466 struct amdgpu_dm_connector *aconnector,
469 struct dc_link_settings max_link_enc_cap = {0};
471 aconnector->dm_dp_aux.aux.name =
472 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
474 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
475 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
476 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
478 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
479 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
482 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
485 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
486 aconnector->mst_mgr.cbs = &dm_mst_cbs;
487 drm_dp_mst_topology_mgr_init(
488 &aconnector->mst_mgr,
489 adev_to_drm(dm->adev),
490 &aconnector->dm_dp_aux.aux,
493 max_link_enc_cap.lane_count,
494 drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate),
495 aconnector->connector_id);
497 drm_connector_attach_dp_subconnector_property(&aconnector->base);
500 int dm_mst_get_pbn_divider(struct dc_link *link)
505 return dc_link_bandwidth_kbps(link,
506 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
509 #if defined(CONFIG_DRM_AMD_DC_DCN)
511 struct dsc_mst_fairness_params {
512 struct dc_crtc_timing *timing;
513 struct dc_sink *sink;
514 struct dc_dsc_bw_range bw_range;
515 bool compression_possible;
516 struct drm_dp_mst_port *port;
517 enum dsc_clock_force_state clock_force_enable;
518 uint32_t num_slices_h;
519 uint32_t num_slices_v;
520 uint32_t bpp_overwrite;
523 struct dsc_mst_fairness_vars {
529 static int kbps_to_peak_pbn(int kbps)
531 u64 peak_kbps = kbps;
534 peak_kbps = div_u64(peak_kbps, 1000);
535 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
538 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
539 struct dsc_mst_fairness_vars *vars,
544 for (i = 0; i < count; i++) {
545 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
546 if (vars[i].dsc_enabled && dc_dsc_compute_config(
547 params[i].sink->ctx->dc->res_pool->dscs[0],
548 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
549 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
553 ¶ms[i].timing->dsc_cfg)) {
554 params[i].timing->flags.DSC = 1;
556 if (params[i].bpp_overwrite)
557 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
559 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
561 if (params[i].num_slices_h)
562 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
564 if (params[i].num_slices_v)
565 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
567 params[i].timing->flags.DSC = 0;
572 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
574 struct dc_dsc_config dsc_config;
577 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
578 dc_dsc_compute_config(
579 param.sink->ctx->dc->res_pool->dscs[0],
580 ¶m.sink->dsc_caps.dsc_dec_caps,
581 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
583 (int) kbps, param.timing, &dsc_config);
585 return dsc_config.bits_per_pixel;
588 static void increase_dsc_bpp(struct drm_atomic_state *state,
589 struct dc_link *dc_link,
590 struct dsc_mst_fairness_params *params,
591 struct dsc_mst_fairness_vars *vars,
595 bool bpp_increased[MAX_PIPES];
596 int initial_slack[MAX_PIPES];
597 int min_initial_slack;
599 int remaining_to_increase = 0;
600 int pbn_per_timeslot;
601 int link_timeslots_used;
604 pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link);
606 for (i = 0; i < count; i++) {
607 if (vars[i].dsc_enabled) {
608 initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
609 bpp_increased[i] = false;
610 remaining_to_increase += 1;
612 initial_slack[i] = 0;
613 bpp_increased[i] = true;
617 while (remaining_to_increase) {
619 min_initial_slack = -1;
620 for (i = 0; i < count; i++) {
621 if (!bpp_increased[i]) {
622 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
623 min_initial_slack = initial_slack[i];
629 if (next_index == -1)
632 link_timeslots_used = 0;
634 for (i = 0; i < count; i++)
635 link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
637 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
639 if (initial_slack[next_index] > fair_pbn_alloc) {
640 vars[next_index].pbn += fair_pbn_alloc;
641 if (drm_dp_atomic_find_vcpi_slots(state,
642 params[next_index].port->mgr,
643 params[next_index].port,
644 vars[next_index].pbn,
645 pbn_per_timeslot) < 0)
647 if (!drm_dp_mst_atomic_check(state)) {
648 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
650 vars[next_index].pbn -= fair_pbn_alloc;
651 if (drm_dp_atomic_find_vcpi_slots(state,
652 params[next_index].port->mgr,
653 params[next_index].port,
654 vars[next_index].pbn,
655 pbn_per_timeslot) < 0)
659 vars[next_index].pbn += initial_slack[next_index];
660 if (drm_dp_atomic_find_vcpi_slots(state,
661 params[next_index].port->mgr,
662 params[next_index].port,
663 vars[next_index].pbn,
664 pbn_per_timeslot) < 0)
666 if (!drm_dp_mst_atomic_check(state)) {
667 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
669 vars[next_index].pbn -= initial_slack[next_index];
670 if (drm_dp_atomic_find_vcpi_slots(state,
671 params[next_index].port->mgr,
672 params[next_index].port,
673 vars[next_index].pbn,
674 pbn_per_timeslot) < 0)
679 bpp_increased[next_index] = true;
680 remaining_to_increase--;
684 static void try_disable_dsc(struct drm_atomic_state *state,
685 struct dc_link *dc_link,
686 struct dsc_mst_fairness_params *params,
687 struct dsc_mst_fairness_vars *vars,
691 bool tried[MAX_PIPES];
692 int kbps_increase[MAX_PIPES];
693 int max_kbps_increase;
695 int remaining_to_try = 0;
697 for (i = 0; i < count; i++) {
698 if (vars[i].dsc_enabled
699 && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16
700 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
701 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
703 remaining_to_try += 1;
705 kbps_increase[i] = 0;
710 while (remaining_to_try) {
712 max_kbps_increase = -1;
713 for (i = 0; i < count; i++) {
715 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
716 max_kbps_increase = kbps_increase[i];
722 if (next_index == -1)
725 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
726 if (drm_dp_atomic_find_vcpi_slots(state,
727 params[next_index].port->mgr,
728 params[next_index].port,
729 vars[next_index].pbn,
730 dm_mst_get_pbn_divider(dc_link)) < 0)
733 if (!drm_dp_mst_atomic_check(state)) {
734 vars[next_index].dsc_enabled = false;
735 vars[next_index].bpp_x16 = 0;
737 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
738 if (drm_dp_atomic_find_vcpi_slots(state,
739 params[next_index].port->mgr,
740 params[next_index].port,
741 vars[next_index].pbn,
742 dm_mst_get_pbn_divider(dc_link)) < 0)
746 tried[next_index] = true;
751 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
752 struct dc_state *dc_state,
753 struct dc_link *dc_link)
756 struct dc_stream_state *stream;
757 struct dsc_mst_fairness_params params[MAX_PIPES];
758 struct dsc_mst_fairness_vars vars[MAX_PIPES];
759 struct amdgpu_dm_connector *aconnector;
761 bool debugfs_overwrite = false;
763 memset(params, 0, sizeof(params));
766 for (i = 0; i < dc_state->stream_count; i++) {
767 struct dc_dsc_policy dsc_policy = {0};
769 stream = dc_state->streams[i];
771 if (stream->link != dc_link)
774 stream->timing.flags.DSC = 0;
776 params[count].timing = &stream->timing;
777 params[count].sink = stream->sink;
778 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
779 params[count].port = aconnector->port;
780 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
781 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
782 debugfs_overwrite = true;
783 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
784 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
785 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
786 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
787 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
788 if (!dc_dsc_compute_bandwidth_range(
789 stream->sink->ctx->dc->res_pool->dscs[0],
790 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
791 dsc_policy.min_target_bpp * 16,
792 dsc_policy.max_target_bpp * 16,
793 &stream->sink->dsc_caps.dsc_dec_caps,
794 &stream->timing, ¶ms[count].bw_range))
795 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
799 /* Try no compression */
800 for (i = 0; i < count; i++) {
801 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
802 vars[i].dsc_enabled = false;
804 if (drm_dp_atomic_find_vcpi_slots(state,
808 dm_mst_get_pbn_divider(dc_link)) < 0)
811 if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
812 set_dsc_configs_from_fairness_vars(params, vars, count);
816 /* Try max compression */
817 for (i = 0; i < count; i++) {
818 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
819 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
820 vars[i].dsc_enabled = true;
821 vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
822 if (drm_dp_atomic_find_vcpi_slots(state,
826 dm_mst_get_pbn_divider(dc_link)) < 0)
829 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
830 vars[i].dsc_enabled = false;
832 if (drm_dp_atomic_find_vcpi_slots(state,
836 dm_mst_get_pbn_divider(dc_link)) < 0)
840 if (drm_dp_mst_atomic_check(state))
843 /* Optimize degree of compression */
844 increase_dsc_bpp(state, dc_link, params, vars, count);
846 try_disable_dsc(state, dc_link, params, vars, count);
848 set_dsc_configs_from_fairness_vars(params, vars, count);
853 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
854 struct dc_state *dc_state)
857 struct dc_stream_state *stream;
858 bool computed_streams[MAX_PIPES];
859 struct amdgpu_dm_connector *aconnector;
861 for (i = 0; i < dc_state->stream_count; i++)
862 computed_streams[i] = false;
864 for (i = 0; i < dc_state->stream_count; i++) {
865 stream = dc_state->streams[i];
867 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
870 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
872 if (!aconnector || !aconnector->dc_sink)
875 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
878 if (computed_streams[i])
881 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
884 mutex_lock(&aconnector->mst_mgr.lock);
885 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
886 mutex_unlock(&aconnector->mst_mgr.lock);
889 mutex_unlock(&aconnector->mst_mgr.lock);
891 for (j = 0; j < dc_state->stream_count; j++) {
892 if (dc_state->streams[j]->link == stream->link)
893 computed_streams[j] = true;
897 for (i = 0; i < dc_state->stream_count; i++) {
898 stream = dc_state->streams[i];
900 if (stream->timing.flags.DSC == 1)
901 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)