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26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_connector.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_dp_mst_helper.h>
33 #include <drm/drm_plane.h>
36 * This file contains the definition for amdgpu_display_manager
37 * and its API for amdgpu driver's use.
38 * This component provides all the display related functionality
39 * and this is the only component that calls DAL API.
40 * The API contained here intended for amdgpu driver use.
41 * The API that is called directly from KMS framework is located
42 * in amdgpu_dm_kms.h file
45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
47 #define AMDGPU_DM_MAX_CRTC 6
49 #define AMDGPU_DM_MAX_NUM_EDP 2
51 #include "include/amdgpu_dal_power_if.h"
52 #include "amdgpu_dm_irq.h"
55 #include "irq_types.h"
56 #include "signal_types.h"
57 #include "amdgpu_dm_crc.h"
59 enum aux_return_code_type;
61 /* Forward declarations */
68 struct dc_plane_state;
69 struct dmub_notification;
71 struct common_irq_params {
72 struct amdgpu_device *adev;
73 enum dc_irq_source irq_src;
74 atomic64_t previous_timestamp;
78 * struct dm_compressor_info - Buffer info used by frame buffer compression
79 * @cpu_addr: MMIO cpu addr
80 * @bo_ptr: Pointer to the buffer object
81 * @gpu_addr: MMIO gpu addr
83 struct dm_compressor_info {
85 struct amdgpu_bo *bo_ptr;
90 * struct vblank_control_work - Work data for vblank control
91 * @work: Kernel work data for the work event
92 * @dm: amdgpu display manager device
93 * @acrtc: amdgpu CRTC instance for which the event has occurred
94 * @stream: DC stream for which the event has occurred
95 * @enable: true if enabling vblank
97 struct vblank_control_work {
98 struct work_struct work;
99 struct amdgpu_display_manager *dm;
100 struct amdgpu_crtc *acrtc;
101 struct dc_stream_state *stream;
106 * struct amdgpu_dm_backlight_caps - Information about backlight
108 * Describe the backlight support for ACPI or eDP AUX.
110 struct amdgpu_dm_backlight_caps {
112 * @ext_caps: Keep the data struct with all the information about the
113 * display support for HDR.
115 union dpcd_sink_ext_caps *ext_caps;
117 * @aux_min_input_signal: Min brightness value supported by the display
119 u32 aux_min_input_signal;
121 * @aux_max_input_signal: Max brightness value supported by the display
124 u32 aux_max_input_signal;
126 * @min_input_signal: minimum possible input in range 0-255.
128 int min_input_signal;
130 * @max_input_signal: maximum possible input in range 0-255.
132 int max_input_signal;
134 * @caps_valid: true if these values are from the ACPI interface.
138 * @aux_support: Describes if the display supports AUX backlight.
144 * struct dal_allocation - Tracks mapped FB memory for SMU communication
145 * @list: list of dal allocations
146 * @bo: GPU buffer object
147 * @cpu_ptr: CPU virtual address of the GPU buffer object
148 * @gpu_addr: GPU virtual address of the GPU buffer object
150 struct dal_allocation {
151 struct list_head list;
152 struct amdgpu_bo *bo;
158 * struct amdgpu_display_manager - Central amdgpu display manager device
160 * @dc: Display Core control structure
161 * @adev: AMDGPU base driver structure
162 * @ddev: DRM base driver structure
163 * @display_indexes_num: Max number of display streams supported
164 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
165 * @backlight_dev: Backlight control device
166 * @backlight_link: Link on which to control backlight
167 * @backlight_caps: Capabilities of the backlight device
168 * @freesync_module: Module handling freesync calculations
169 * @hdcp_workqueue: AMDGPU content protection queue
170 * @fw_dmcu: Reference to DMCU firmware
171 * @dmcu_fw_version: Version of the DMCU firmware
172 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
173 * @cached_state: Caches device atomic state for suspend/resume
174 * @cached_dc_state: Cached state of content streams
175 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
176 * @force_timing_sync: set via debugfs. When set, indicates that all connected
177 * displays will be forced to synchronize.
178 * @dmcub_trace_event_en: enable dmcub trace events
180 struct amdgpu_display_manager {
187 * DMUB service, used for controlling the DMUB on hardware
188 * that supports it. The pointer to the dmub_srv will be
189 * NULL on hardware that does not support it.
191 struct dmub_srv *dmub_srv;
193 struct dmub_notification *dmub_notify;
198 * Framebuffer regions for the DMUB.
200 struct dmub_srv_fb_info *dmub_fb_info;
205 * DMUB firmware, required on hardware that has DMUB support.
207 const struct firmware *dmub_fw;
212 * Buffer object for the DMUB.
214 struct amdgpu_bo *dmub_bo;
219 * GPU virtual address for the DMUB buffer object.
221 u64 dmub_bo_gpu_addr;
226 * CPU address for the DMUB buffer object.
228 void *dmub_bo_cpu_addr;
233 * DMCUB firmware version.
235 uint32_t dmcub_fw_version;
240 * The Common Graphics Services device. It provides an interface for
241 * accessing registers.
243 struct cgs_device *cgs_device;
245 struct amdgpu_device *adev;
246 struct drm_device *ddev;
247 u16 display_indexes_num;
252 * In combination with &dm_atomic_state it helps manage
253 * global atomic state that doesn't map cleanly into existing
254 * drm resources, like &dc_context.
256 struct drm_private_obj atomic_obj;
261 * Guards access to DC functions that can issue register write
264 struct mutex dc_lock;
269 * Guards access to audio instance changes.
271 struct mutex audio_lock;
273 #if defined(CONFIG_DRM_AMD_DC_DCN)
277 * Guards access to deferred vblank work state.
279 spinlock_t vblank_lock;
285 * Used to notify ELD changes to sound driver.
287 struct drm_audio_component *audio_component;
292 * True if the audio component has been registered
293 * successfully, false otherwise.
295 bool audio_registered;
298 * @irq_handler_list_low_tab:
300 * Low priority IRQ handler table.
302 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
303 * source. Low priority IRQ handlers are deferred to a workqueue to be
304 * processed. Hence, they can sleep.
306 * Note that handlers are called in the same order as they were
309 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
312 * @irq_handler_list_high_tab:
314 * High priority IRQ handler table.
316 * It is a n*m table, same as &irq_handler_list_low_tab. However,
317 * handlers in this table are not deferred and are called immediately.
319 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
324 * Page flip IRQ parameters, passed to registered handlers when
327 struct common_irq_params
328 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
333 * Vertical blanking IRQ parameters, passed to registered handlers when
336 struct common_irq_params
337 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
342 * OTG vertical interrupt0 IRQ parameters, passed to registered
343 * handlers when triggered.
345 struct common_irq_params
346 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];
351 * Vertical update IRQ parameters, passed to registered handlers when
354 struct common_irq_params
355 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
358 * @dmub_trace_params:
360 * DMUB trace event IRQ parameters, passed to registered handlers when
363 struct common_irq_params
364 dmub_trace_params[1];
366 struct common_irq_params
367 dmub_outbox_params[1];
369 spinlock_t irq_handler_list_table_lock;
371 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];
373 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
377 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
379 struct mod_freesync *freesync_module;
380 #ifdef CONFIG_DRM_AMD_DC_HDCP
381 struct hdcp_workqueue *hdcp_workqueue;
384 #if defined(CONFIG_DRM_AMD_DC_DCN)
386 * @vblank_control_workqueue:
388 * Deferred work for vblank control events.
390 struct workqueue_struct *vblank_control_workqueue;
393 struct drm_atomic_state *cached_state;
394 struct dc_state *cached_dc_state;
396 struct dm_compressor_info compressor;
398 const struct firmware *fw_dmcu;
399 uint32_t dmcu_fw_version;
403 * gpu_info FW provided soc bounding box struct or 0 if not
406 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
408 #if defined(CONFIG_DRM_AMD_DC_DCN)
410 * @active_vblank_irq_count:
412 * number of currently active vblank irqs
414 uint32_t active_vblank_irq_count;
417 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
421 * Work to be executed in a separate thread to communicate with PSP.
423 struct crc_rd_work *crc_rd_wrk;
429 * fake encoders used for DP MST.
431 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
432 bool force_timing_sync;
433 bool disable_hpd_irq;
434 bool dmcub_trace_event_en;
438 * DAL fb memory allocation list, for communication with SMU.
440 struct list_head da_list;
441 struct completion dmub_aux_transfer_done;
446 * cached backlight values.
448 u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
451 enum dsc_clock_force_state {
452 DSC_CLK_FORCE_DEFAULT = 0,
453 DSC_CLK_FORCE_ENABLE,
454 DSC_CLK_FORCE_DISABLE,
457 struct dsc_preferred_settings {
458 enum dsc_clock_force_state dsc_force_enable;
459 uint32_t dsc_num_slices_v;
460 uint32_t dsc_num_slices_h;
461 uint32_t dsc_bits_per_pixel;
462 bool dsc_force_disable_passthrough;
465 struct amdgpu_dm_connector {
467 struct drm_connector base;
468 uint32_t connector_id;
470 /* we need to mind the EDID between detect
471 and get modes due to analog/digital/tvencoder */
474 /* shared with amdgpu */
475 struct amdgpu_hpd hpd;
477 /* number of modes generated from EDID at 'dc_sink' */
480 /* The 'old' sink - before an HPD.
481 * The 'current' sink is in dc_link->sink. */
482 struct dc_sink *dc_sink;
483 struct dc_link *dc_link;
484 struct dc_sink *dc_em_sink;
487 struct drm_dp_mst_topology_mgr mst_mgr;
488 struct amdgpu_dm_dp_aux dm_dp_aux;
489 struct drm_dp_mst_port *port;
490 struct amdgpu_dm_connector *mst_port;
491 struct drm_dp_aux *dsc_aux;
493 /* TODO see if we can merge with ddc_bus or make a dm_connector */
494 struct amdgpu_i2c_adapter *i2c;
496 /* Monitor range limits */
501 /* Audio instance - protected by audio_lock. */
504 struct mutex hpd_lock;
507 #ifdef CONFIG_DEBUG_FS
508 uint32_t debugfs_dpcd_address;
509 uint32_t debugfs_dpcd_size;
511 bool force_yuv420_output;
512 struct dsc_preferred_settings dsc_settings;
513 /* Cached display modes */
514 struct drm_display_mode freesync_vid_base;
519 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
521 extern const struct amdgpu_ip_block_version dm_ip_block;
523 struct dm_plane_state {
524 struct drm_plane_state base;
525 struct dc_plane_state *dc_state;
528 struct dm_crtc_state {
529 struct drm_crtc_state base;
530 struct dc_stream_state *stream;
533 bool cm_is_degamma_srgb;
540 bool freesync_timing_changed;
541 bool freesync_vrr_info_changed;
543 bool dsc_force_changed;
545 struct mod_freesync_config freesync_config;
546 struct dc_info_packet vrr_infopacket;
551 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
553 struct dm_atomic_state {
554 struct drm_private_state base;
556 struct dc_state *context;
559 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
561 struct dm_connector_state {
562 struct drm_connector_state base;
564 enum amdgpu_rmx_type scaling;
565 uint8_t underscan_vborder;
566 uint8_t underscan_hborder;
567 bool underscan_enable;
568 bool freesync_capable;
569 #ifdef CONFIG_DRM_AMD_DC_HDCP
577 struct amdgpu_hdmi_vsdb_info {
578 unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */
579 bool freesync_supported; /* FreeSync Supported */
580 unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */
581 unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */
585 #define to_dm_connector_state(x)\
586 container_of((x), struct dm_connector_state, base)
588 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
589 struct drm_connector_state *
590 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
591 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
592 struct drm_connector_state *state,
593 struct drm_property *property,
596 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
597 const struct drm_connector_state *state,
598 struct drm_property *property,
601 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
603 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
604 struct amdgpu_dm_connector *aconnector,
606 struct dc_link *link,
609 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
610 struct drm_display_mode *mode);
612 void dm_restore_drm_connector_state(struct drm_device *dev,
613 struct drm_connector *connector);
615 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
618 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
620 #define MAX_COLOR_LUT_ENTRIES 4096
621 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
622 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
624 void amdgpu_dm_init_color_mod(void);
625 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
626 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
627 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
628 struct dc_plane_state *dc_plane_state);
630 void amdgpu_dm_update_connector_after_detect(
631 struct amdgpu_dm_connector *aconnector);
633 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
635 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex,
636 struct aux_payload *payload, enum aux_return_code_type *operation_result);
637 #endif /* __AMDGPU_DM_H__ */