drivers/gpu/drm/amd/amdgpu/vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26
  27 #include <drm/amdgpu_drm.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_atombios.h"
  31 #include "amdgpu_ih.h"
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "amdgpu_ucode.h"
  35 #include "atom.h"
  36 #include "amd_pcie.h"
  37
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "gmc/gmc_8_1_sh_mask.h"
  40
  41 #include "oss/oss_3_0_d.h"
  42 #include "oss/oss_3_0_sh_mask.h"
  43
  44 #include "bif/bif_5_0_d.h"
  45 #include "bif/bif_5_0_sh_mask.h"
  46
  47 #include "gca/gfx_8_0_d.h"
  48 #include "gca/gfx_8_0_sh_mask.h"
  49
  50 #include "smu/smu_7_1_1_d.h"
  51 #include "smu/smu_7_1_1_sh_mask.h"
  52
  53 #include "uvd/uvd_5_0_d.h"
  54 #include "uvd/uvd_5_0_sh_mask.h"
  55
  56 #include "vce/vce_3_0_d.h"
  57 #include "vce/vce_3_0_sh_mask.h"
  58
  59 #include "dce/dce_10_0_d.h"
  60 #include "dce/dce_10_0_sh_mask.h"
  61
  62 #include "vid.h"
  63 #include "vi.h"
  64 #include "gmc_v8_0.h"
  65 #include "gmc_v7_0.h"
  66 #include "gfx_v8_0.h"
  67 #include "sdma_v2_4.h"
  68 #include "sdma_v3_0.h"
  69 #include "dce_v10_0.h"
  70 #include "dce_v11_0.h"
  71 #include "iceland_ih.h"
  72 #include "tonga_ih.h"
  73 #include "cz_ih.h"
  74 #include "uvd_v5_0.h"
  75 #include "uvd_v6_0.h"
  76 #include "vce_v3_0.h"
  77 #if defined(CONFIG_DRM_AMD_ACP)
  78 #include "amdgpu_acp.h"
  79 #endif
  80 #include "amdgpu_vkms.h"
  81 #include "mxgpu_vi.h"
  82 #include "amdgpu_dm.h"
  83
  84 #define ixPCIE_LC_L1_PM_SUBSTATE        0x100100C6
  85 #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK        0x00000001L
  86 #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK    0x00000002L
  87 #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK    0x00000004L
  88 #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK              0x00000008L
  89 #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK              0x00000010L
  90 #define ixPCIE_L1_PM_SUB_CNTL   0x378
  91 #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK  0x00000004L
  92 #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK  0x00000008L
  93 #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK        0x00000001L
  94 #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK        0x00000002L
  95 #define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK             0x00200000L
  96 #define LINK_CAP        0x64
  97 #define PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK      0x00040000L
  98 #define ixCPM_CONTROL   0x1400118
  99 #define ixPCIE_LC_CNTL7 0x100100BC
 100 #define PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK       0x00000400L
 101 #define PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT 0x00000007
 102 #define PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT  0x00000009
 103 #define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK   0x01000000L
 104 #define PCIE_L1_PM_SUB_CNTL     0x378
 105 #define ASIC_IS_P22(asic_type, rid)     ((asic_type >= CHIP_POLARIS10) && \
 106                                                                         (asic_type <= CHIP_POLARIS12) && \
 107                                                                         (rid >= 0x6E))
 108 /* Topaz */
 109 static const struct amdgpu_video_codecs topaz_video_codecs_encode =
 110 {
 111         .codec_count = 0,
 112         .codec_array = NULL,
 113 };
 114
 115 /* Tonga, CZ, ST, Fiji */
 116 static const struct amdgpu_video_codec_info tonga_video_codecs_encode_array[] =
 117 {
 118         {
 119                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 120                 .max_width = 4096,
 121                 .max_height = 2304,
 122                 .max_pixels_per_frame = 4096 * 2304,
 123                 .max_level = 0,
 124         },
 125 };
 126
 127 static const struct amdgpu_video_codecs tonga_video_codecs_encode =
 128 {
 129         .codec_count = ARRAY_SIZE(tonga_video_codecs_encode_array),
 130         .codec_array = tonga_video_codecs_encode_array,
 131 };
 132
 133 /* Polaris */
 134 static const struct amdgpu_video_codec_info polaris_video_codecs_encode_array[] =
 135 {
 136         {
 137                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 138                 .max_width = 4096,
 139                 .max_height = 2304,
 140                 .max_pixels_per_frame = 4096 * 2304,
 141                 .max_level = 0,
 142         },
 143         {
 144                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 145                 .max_width = 4096,
 146                 .max_height = 2304,
 147                 .max_pixels_per_frame = 4096 * 2304,
 148                 .max_level = 0,
 149         },
 150 };
 151
 152 static const struct amdgpu_video_codecs polaris_video_codecs_encode =
 153 {
 154         .codec_count = ARRAY_SIZE(polaris_video_codecs_encode_array),
 155         .codec_array = polaris_video_codecs_encode_array,
 156 };
 157
 158 /* Topaz */
 159 static const struct amdgpu_video_codecs topaz_video_codecs_decode =
 160 {
 161         .codec_count = 0,
 162         .codec_array = NULL,
 163 };
 164
 165 /* Tonga */
 166 static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
 167 {
 168         {
 169                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
 170                 .max_width = 4096,
 171                 .max_height = 4096,
 172                 .max_pixels_per_frame = 4096 * 4096,
 173                 .max_level = 3,
 174         },
 175         {
 176                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
 177                 .max_width = 4096,
 178                 .max_height = 4096,
 179                 .max_pixels_per_frame = 4096 * 4096,
 180                 .max_level = 5,
 181         },
 182         {
 183                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 184                 .max_width = 4096,
 185                 .max_height = 4096,
 186                 .max_pixels_per_frame = 4096 * 4096,
 187                 .max_level = 52,
 188         },
 189         {
 190                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
 191                 .max_width = 4096,
 192                 .max_height = 4096,
 193                 .max_pixels_per_frame = 4096 * 4096,
 194                 .max_level = 4,
 195         },
 196 };
 197
 198 static const struct amdgpu_video_codecs tonga_video_codecs_decode =
 199 {
 200         .codec_count = ARRAY_SIZE(tonga_video_codecs_decode_array),
 201         .codec_array = tonga_video_codecs_decode_array,
 202 };
 203
 204 /* CZ, ST, Fiji, Polaris */
 205 static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
 206 {
 207         {
 208                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
 209                 .max_width = 4096,
 210                 .max_height = 4096,
 211                 .max_pixels_per_frame = 4096 * 4096,
 212                 .max_level = 3,
 213         },
 214         {
 215                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
 216                 .max_width = 4096,
 217                 .max_height = 4096,
 218                 .max_pixels_per_frame = 4096 * 4096,
 219                 .max_level = 5,
 220         },
 221         {
 222                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 223                 .max_width = 4096,
 224                 .max_height = 4096,
 225                 .max_pixels_per_frame = 4096 * 4096,
 226                 .max_level = 52,
 227         },
 228         {
 229                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
 230                 .max_width = 4096,
 231                 .max_height = 4096,
 232                 .max_pixels_per_frame = 4096 * 4096,
 233                 .max_level = 4,
 234         },
 235         {
 236                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 237                 .max_width = 4096,
 238                 .max_height = 4096,
 239                 .max_pixels_per_frame = 4096 * 4096,
 240                 .max_level = 186,
 241         },
 242         {
 243                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
 244                 .max_width = 4096,
 245                 .max_height = 4096,
 246                 .max_pixels_per_frame = 4096 * 4096,
 247                 .max_level = 0,
 248         },
 249 };
 250
 251 static const struct amdgpu_video_codecs cz_video_codecs_decode =
 252 {
 253         .codec_count = ARRAY_SIZE(cz_video_codecs_decode_array),
 254         .codec_array = cz_video_codecs_decode_array,
 255 };
 256
 257 static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode,
 258                                  const struct amdgpu_video_codecs **codecs)
 259 {
 260         switch (adev->asic_type) {
 261         case CHIP_TOPAZ:
 262                 if (encode)
 263                         *codecs = &topaz_video_codecs_encode;
 264                 else
 265                         *codecs = &topaz_video_codecs_decode;
 266                 return 0;
 267         case CHIP_TONGA:
 268                 if (encode)
 269                         *codecs = &tonga_video_codecs_encode;
 270                 else
 271                         *codecs = &tonga_video_codecs_decode;
 272                 return 0;
 273         case CHIP_POLARIS10:
 274         case CHIP_POLARIS11:
 275         case CHIP_POLARIS12:
 276         case CHIP_VEGAM:
 277                 if (encode)
 278                         *codecs = &polaris_video_codecs_encode;
 279                 else
 280                         *codecs = &cz_video_codecs_decode;
 281                 return 0;
 282         case CHIP_FIJI:
 283         case CHIP_CARRIZO:
 284         case CHIP_STONEY:
 285                 if (encode)
 286                         *codecs = &tonga_video_codecs_encode;
 287                 else
 288                         *codecs = &cz_video_codecs_decode;
 289                 return 0;
 290         default:
 291                 return -EINVAL;
 292         }
 293 }
 294
 295 /*
 296  * Indirect registers accessor
 297  */
 298 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 299 {
 300         unsigned long flags;
 301         u32 r;
 302
 303         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 304         WREG32_NO_KIQ(mmPCIE_INDEX, reg);
 305         (void)RREG32_NO_KIQ(mmPCIE_INDEX);
 306         r = RREG32_NO_KIQ(mmPCIE_DATA);
 307         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 308         return r;
 309 }
 310
 311 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 312 {
 313         unsigned long flags;
 314
 315         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 316         WREG32_NO_KIQ(mmPCIE_INDEX, reg);
 317         (void)RREG32_NO_KIQ(mmPCIE_INDEX);
 318         WREG32_NO_KIQ(mmPCIE_DATA, v);
 319         (void)RREG32_NO_KIQ(mmPCIE_DATA);
 320         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 321 }
 322
 323 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
 324 {
 325         unsigned long flags;
 326         u32 r;
 327
 328         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 329         WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
 330         r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
 331         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 332         return r;
 333 }
 334
 335 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 336 {
 337         unsigned long flags;
 338
 339         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 340         WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
 341         WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
 342         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 343 }
 344
 345 /* smu_8_0_d.h */
 346 #define mmMP0PUB_IND_INDEX                                                      0x180
 347 #define mmMP0PUB_IND_DATA                                                       0x181
 348
 349 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
 350 {
 351         unsigned long flags;
 352         u32 r;
 353
 354         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 355         WREG32(mmMP0PUB_IND_INDEX, (reg));
 356         r = RREG32(mmMP0PUB_IND_DATA);
 357         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 358         return r;
 359 }
 360
 361 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 362 {
 363         unsigned long flags;
 364
 365         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 366         WREG32(mmMP0PUB_IND_INDEX, (reg));
 367         WREG32(mmMP0PUB_IND_DATA, (v));
 368         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 369 }
 370
 371 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 372 {
 373         unsigned long flags;
 374         u32 r;
 375
 376         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 377         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 378         r = RREG32(mmUVD_CTX_DATA);
 379         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 380         return r;
 381 }
 382
 383 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 384 {
 385         unsigned long flags;
 386
 387         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 388         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 389         WREG32(mmUVD_CTX_DATA, (v));
 390         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 391 }
 392
 393 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
 394 {
 395         unsigned long flags;
 396         u32 r;
 397
 398         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 399         WREG32(mmDIDT_IND_INDEX, (reg));
 400         r = RREG32(mmDIDT_IND_DATA);
 401         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 402         return r;
 403 }
 404
 405 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 406 {
 407         unsigned long flags;
 408
 409         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 410         WREG32(mmDIDT_IND_INDEX, (reg));
 411         WREG32(mmDIDT_IND_DATA, (v));
 412         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 413 }
 414
 415 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 416 {
 417         unsigned long flags;
 418         u32 r;
 419
 420         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 421         WREG32(mmGC_CAC_IND_INDEX, (reg));
 422         r = RREG32(mmGC_CAC_IND_DATA);
 423         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 424         return r;
 425 }
 426
 427 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 428 {
 429         unsigned long flags;
 430
 431         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 432         WREG32(mmGC_CAC_IND_INDEX, (reg));
 433         WREG32(mmGC_CAC_IND_DATA, (v));
 434         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 435 }
 436
 437
 438 static const u32 tonga_mgcg_cgcg_init[] =
 439 {
 440         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 441         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 442         mmPCIE_DATA, 0x000f0000, 0x00000000,
 443         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 444         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 445         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 446         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 447 };
 448
 449 static const u32 fiji_mgcg_cgcg_init[] =
 450 {
 451         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 452         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 453         mmPCIE_DATA, 0x000f0000, 0x00000000,
 454         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 455         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 456         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 457         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 458 };
 459
 460 static const u32 iceland_mgcg_cgcg_init[] =
 461 {
 462         mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
 463         mmPCIE_DATA, 0x000f0000, 0x00000000,
 464         mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
 465         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 466         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 467 };
 468
 469 static const u32 cz_mgcg_cgcg_init[] =
 470 {
 471         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 472         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 473         mmPCIE_DATA, 0x000f0000, 0x00000000,
 474         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 475         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 476 };
 477
 478 static const u32 stoney_mgcg_cgcg_init[] =
 479 {
 480         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
 481         mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
 482         mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
 483 };
 484
 485 static void vi_init_golden_registers(struct amdgpu_device *adev)
 486 {
 487         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 488         mutex_lock(&adev->grbm_idx_mutex);
 489
 490         if (amdgpu_sriov_vf(adev)) {
 491                 xgpu_vi_init_golden_registers(adev);
 492                 mutex_unlock(&adev->grbm_idx_mutex);
 493                 return;
 494         }
 495
 496         switch (adev->asic_type) {
 497         case CHIP_TOPAZ:
 498                 amdgpu_device_program_register_sequence(adev,
 499                                                         iceland_mgcg_cgcg_init,
 500                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
 501                 break;
 502         case CHIP_FIJI:
 503                 amdgpu_device_program_register_sequence(adev,
 504                                                         fiji_mgcg_cgcg_init,
 505                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 506                 break;
 507         case CHIP_TONGA:
 508                 amdgpu_device_program_register_sequence(adev,
 509                                                         tonga_mgcg_cgcg_init,
 510                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 511                 break;
 512         case CHIP_CARRIZO:
 513                 amdgpu_device_program_register_sequence(adev,
 514                                                         cz_mgcg_cgcg_init,
 515                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 516                 break;
 517         case CHIP_STONEY:
 518                 amdgpu_device_program_register_sequence(adev,
 519                                                         stoney_mgcg_cgcg_init,
 520                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 521                 break;
 522         case CHIP_POLARIS10:
 523         case CHIP_POLARIS11:
 524         case CHIP_POLARIS12:
 525         case CHIP_VEGAM:
 526         default:
 527                 break;
 528         }
 529         mutex_unlock(&adev->grbm_idx_mutex);
 530 }
 531
 532 /**
 533  * vi_get_xclk - get the xclk
 534  *
 535  * @adev: amdgpu_device pointer
 536  *
 537  * Returns the reference clock used by the gfx engine
 538  * (VI).
 539  */
 540 static u32 vi_get_xclk(struct amdgpu_device *adev)
 541 {
 542         u32 reference_clock = adev->clock.spll.reference_freq;
 543         u32 tmp;
 544
 545         if (adev->flags & AMD_IS_APU)
 546                 return reference_clock;
 547
 548         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
 549         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
 550                 return 1000;
 551
 552         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
 553         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
 554                 return reference_clock / 4;
 555
 556         return reference_clock;
 557 }
 558
 559 /**
 560  * vi_srbm_select - select specific register instances
 561  *
 562  * @adev: amdgpu_device pointer
 563  * @me: selected ME (micro engine)
 564  * @pipe: pipe
 565  * @queue: queue
 566  * @vmid: VMID
 567  *
 568  * Switches the currently active registers instances.  Some
 569  * registers are instanced per VMID, others are instanced per
 570  * me/pipe/queue combination.
 571  */
 572 void vi_srbm_select(struct amdgpu_device *adev,
 573                      u32 me, u32 pipe, u32 queue, u32 vmid)
 574 {
 575         u32 srbm_gfx_cntl = 0;
 576         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
 577         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
 578         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
 579         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
 580         WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
 581 }
 582
 583 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
 584 {
 585         /* todo */
 586 }
 587
 588 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
 589 {
 590         u32 bus_cntl;
 591         u32 d1vga_control = 0;
 592         u32 d2vga_control = 0;
 593         u32 vga_render_control = 0;
 594         u32 rom_cntl;
 595         bool r;
 596
 597         bus_cntl = RREG32(mmBUS_CNTL);
 598         if (adev->mode_info.num_crtc) {
 599                 d1vga_control = RREG32(mmD1VGA_CONTROL);
 600                 d2vga_control = RREG32(mmD2VGA_CONTROL);
 601                 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 602         }
 603         rom_cntl = RREG32_SMC(ixROM_CNTL);
 604
 605         /* enable the rom */
 606         WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
 607         if (adev->mode_info.num_crtc) {
 608                 /* Disable VGA mode */
 609                 WREG32(mmD1VGA_CONTROL,
 610                        (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
 611                                           D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
 612                 WREG32(mmD2VGA_CONTROL,
 613                        (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
 614                                           D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
 615                 WREG32(mmVGA_RENDER_CONTROL,
 616                        (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
 617         }
 618         WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
 619
 620         r = amdgpu_read_bios(adev);
 621
 622         /* restore regs */
 623         WREG32(mmBUS_CNTL, bus_cntl);
 624         if (adev->mode_info.num_crtc) {
 625                 WREG32(mmD1VGA_CONTROL, d1vga_control);
 626                 WREG32(mmD2VGA_CONTROL, d2vga_control);
 627                 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
 628         }
 629         WREG32_SMC(ixROM_CNTL, rom_cntl);
 630         return r;
 631 }
 632
 633 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
 634                                   u8 *bios, u32 length_bytes)
 635 {
 636         u32 *dw_ptr;
 637         unsigned long flags;
 638         u32 i, length_dw;
 639
 640         if (bios == NULL)
 641                 return false;
 642         if (length_bytes == 0)
 643                 return false;
 644         /* APU vbios image is part of sbios image */
 645         if (adev->flags & AMD_IS_APU)
 646                 return false;
 647
 648         dw_ptr = (u32 *)bios;
 649         length_dw = ALIGN(length_bytes, 4) / 4;
 650         /* take the smc lock since we are using the smc index */
 651         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 652         /* set rom index to 0 */
 653         WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
 654         WREG32(mmSMC_IND_DATA_11, 0);
 655         /* set index to data for continous read */
 656         WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
 657         for (i = 0; i < length_dw; i++)
 658                 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
 659         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 660
 661         return true;
 662 }
 663
 664 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
 665         {mmGRBM_STATUS},
 666         {mmGRBM_STATUS2},
 667         {mmGRBM_STATUS_SE0},
 668         {mmGRBM_STATUS_SE1},
 669         {mmGRBM_STATUS_SE2},
 670         {mmGRBM_STATUS_SE3},
 671         {mmSRBM_STATUS},
 672         {mmSRBM_STATUS2},
 673         {mmSRBM_STATUS3},
 674         {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
 675         {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
 676         {mmCP_STAT},
 677         {mmCP_STALLED_STAT1},
 678         {mmCP_STALLED_STAT2},
 679         {mmCP_STALLED_STAT3},
 680         {mmCP_CPF_BUSY_STAT},
 681         {mmCP_CPF_STALLED_STAT1},
 682         {mmCP_CPF_STATUS},
 683         {mmCP_CPC_BUSY_STAT},
 684         {mmCP_CPC_STALLED_STAT1},
 685         {mmCP_CPC_STATUS},
 686         {mmGB_ADDR_CONFIG},
 687         {mmMC_ARB_RAMCFG},
 688         {mmGB_TILE_MODE0},
 689         {mmGB_TILE_MODE1},
 690         {mmGB_TILE_MODE2},
 691         {mmGB_TILE_MODE3},
 692         {mmGB_TILE_MODE4},
 693         {mmGB_TILE_MODE5},
 694         {mmGB_TILE_MODE6},
 695         {mmGB_TILE_MODE7},
 696         {mmGB_TILE_MODE8},
 697         {mmGB_TILE_MODE9},
 698         {mmGB_TILE_MODE10},
 699         {mmGB_TILE_MODE11},
 700         {mmGB_TILE_MODE12},
 701         {mmGB_TILE_MODE13},
 702         {mmGB_TILE_MODE14},
 703         {mmGB_TILE_MODE15},
 704         {mmGB_TILE_MODE16},
 705         {mmGB_TILE_MODE17},
 706         {mmGB_TILE_MODE18},
 707         {mmGB_TILE_MODE19},
 708         {mmGB_TILE_MODE20},
 709         {mmGB_TILE_MODE21},
 710         {mmGB_TILE_MODE22},
 711         {mmGB_TILE_MODE23},
 712         {mmGB_TILE_MODE24},
 713         {mmGB_TILE_MODE25},
 714         {mmGB_TILE_MODE26},
 715         {mmGB_TILE_MODE27},
 716         {mmGB_TILE_MODE28},
 717         {mmGB_TILE_MODE29},
 718         {mmGB_TILE_MODE30},
 719         {mmGB_TILE_MODE31},
 720         {mmGB_MACROTILE_MODE0},
 721         {mmGB_MACROTILE_MODE1},
 722         {mmGB_MACROTILE_MODE2},
 723         {mmGB_MACROTILE_MODE3},
 724         {mmGB_MACROTILE_MODE4},
 725         {mmGB_MACROTILE_MODE5},
 726         {mmGB_MACROTILE_MODE6},
 727         {mmGB_MACROTILE_MODE7},
 728         {mmGB_MACROTILE_MODE8},
 729         {mmGB_MACROTILE_MODE9},
 730         {mmGB_MACROTILE_MODE10},
 731         {mmGB_MACROTILE_MODE11},
 732         {mmGB_MACROTILE_MODE12},
 733         {mmGB_MACROTILE_MODE13},
 734         {mmGB_MACROTILE_MODE14},
 735         {mmGB_MACROTILE_MODE15},
 736         {mmCC_RB_BACKEND_DISABLE, true},
 737         {mmGC_USER_RB_BACKEND_DISABLE, true},
 738         {mmGB_BACKEND_MAP, false},
 739         {mmPA_SC_RASTER_CONFIG, true},
 740         {mmPA_SC_RASTER_CONFIG_1, true},
 741 };
 742
 743 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
 744                                       bool indexed, u32 se_num,
 745                                       u32 sh_num, u32 reg_offset)
 746 {
 747         if (indexed) {
 748                 uint32_t val;
 749                 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
 750                 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
 751
 752                 switch (reg_offset) {
 753                 case mmCC_RB_BACKEND_DISABLE:
 754                         return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
 755                 case mmGC_USER_RB_BACKEND_DISABLE:
 756                         return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
 757                 case mmPA_SC_RASTER_CONFIG:
 758                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
 759                 case mmPA_SC_RASTER_CONFIG_1:
 760                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
 761                 }
 762
 763                 mutex_lock(&adev->grbm_idx_mutex);
 764                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 765                         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 766
 767                 val = RREG32(reg_offset);
 768
 769                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 770                         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 771                 mutex_unlock(&adev->grbm_idx_mutex);
 772                 return val;
 773         } else {
 774                 unsigned idx;
 775
 776                 switch (reg_offset) {
 777                 case mmGB_ADDR_CONFIG:
 778                         return adev->gfx.config.gb_addr_config;
 779                 case mmMC_ARB_RAMCFG:
 780                         return adev->gfx.config.mc_arb_ramcfg;
 781                 case mmGB_TILE_MODE0:
 782                 case mmGB_TILE_MODE1:
 783                 case mmGB_TILE_MODE2:
 784                 case mmGB_TILE_MODE3:
 785                 case mmGB_TILE_MODE4:
 786                 case mmGB_TILE_MODE5:
 787                 case mmGB_TILE_MODE6:
 788                 case mmGB_TILE_MODE7:
 789                 case mmGB_TILE_MODE8:
 790                 case mmGB_TILE_MODE9:
 791                 case mmGB_TILE_MODE10:
 792                 case mmGB_TILE_MODE11:
 793                 case mmGB_TILE_MODE12:
 794                 case mmGB_TILE_MODE13:
 795                 case mmGB_TILE_MODE14:
 796                 case mmGB_TILE_MODE15:
 797                 case mmGB_TILE_MODE16:
 798                 case mmGB_TILE_MODE17:
 799                 case mmGB_TILE_MODE18:
 800                 case mmGB_TILE_MODE19:
 801                 case mmGB_TILE_MODE20:
 802                 case mmGB_TILE_MODE21:
 803                 case mmGB_TILE_MODE22:
 804                 case mmGB_TILE_MODE23:
 805                 case mmGB_TILE_MODE24:
 806                 case mmGB_TILE_MODE25:
 807                 case mmGB_TILE_MODE26:
 808                 case mmGB_TILE_MODE27:
 809                 case mmGB_TILE_MODE28:
 810                 case mmGB_TILE_MODE29:
 811                 case mmGB_TILE_MODE30:
 812                 case mmGB_TILE_MODE31:
 813                         idx = (reg_offset - mmGB_TILE_MODE0);
 814                         return adev->gfx.config.tile_mode_array[idx];
 815                 case mmGB_MACROTILE_MODE0:
 816                 case mmGB_MACROTILE_MODE1:
 817                 case mmGB_MACROTILE_MODE2:
 818                 case mmGB_MACROTILE_MODE3:
 819                 case mmGB_MACROTILE_MODE4:
 820                 case mmGB_MACROTILE_MODE5:
 821                 case mmGB_MACROTILE_MODE6:
 822                 case mmGB_MACROTILE_MODE7:
 823                 case mmGB_MACROTILE_MODE8:
 824                 case mmGB_MACROTILE_MODE9:
 825                 case mmGB_MACROTILE_MODE10:
 826                 case mmGB_MACROTILE_MODE11:
 827                 case mmGB_MACROTILE_MODE12:
 828                 case mmGB_MACROTILE_MODE13:
 829                 case mmGB_MACROTILE_MODE14:
 830                 case mmGB_MACROTILE_MODE15:
 831                         idx = (reg_offset - mmGB_MACROTILE_MODE0);
 832                         return adev->gfx.config.macrotile_mode_array[idx];
 833                 default:
 834                         return RREG32(reg_offset);
 835                 }
 836         }
 837 }
 838
 839 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
 840                             u32 sh_num, u32 reg_offset, u32 *value)
 841 {
 842         uint32_t i;
 843
 844         *value = 0;
 845         for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
 846                 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
 847
 848                 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
 849                         continue;
 850
 851                 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
 852                                                reg_offset);
 853                 return 0;
 854         }
 855         return -EINVAL;
 856 }
 857
 858 /**
 859  * vi_asic_pci_config_reset - soft reset GPU
 860  *
 861  * @adev: amdgpu_device pointer
 862  *
 863  * Use PCI Config method to reset the GPU.
 864  *
 865  * Returns 0 for success.
 866  */
 867 static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
 868 {
 869         u32 i;
 870         int r = -EINVAL;
 871
 872         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 873
 874         /* disable BM */
 875         pci_clear_master(adev->pdev);
 876         /* reset */
 877         amdgpu_device_pci_config_reset(adev);
 878
 879         udelay(100);
 880
 881         /* wait for asic to come out of reset */
 882         for (i = 0; i < adev->usec_timeout; i++) {
 883                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
 884                         /* enable BM */
 885                         pci_set_master(adev->pdev);
 886                         adev->has_hw_reset = true;
 887                         r = 0;
 888                         break;
 889                 }
 890                 udelay(1);
 891         }
 892
 893         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 894
 895         return r;
 896 }
 897
 898 static bool vi_asic_supports_baco(struct amdgpu_device *adev)
 899 {
 900         switch (adev->asic_type) {
 901         case CHIP_FIJI:
 902         case CHIP_TONGA:
 903         case CHIP_POLARIS10:
 904         case CHIP_POLARIS11:
 905         case CHIP_POLARIS12:
 906         case CHIP_TOPAZ:
 907                 return amdgpu_dpm_is_baco_supported(adev);
 908         default:
 909                 return false;
 910         }
 911 }
 912
 913 static enum amd_reset_method
 914 vi_asic_reset_method(struct amdgpu_device *adev)
 915 {
 916         bool baco_reset;
 917
 918         if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY ||
 919             amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 920                 return amdgpu_reset_method;
 921
 922         if (amdgpu_reset_method != -1)
 923                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 924                                   amdgpu_reset_method);
 925
 926         switch (adev->asic_type) {
 927         case CHIP_FIJI:
 928         case CHIP_TONGA:
 929         case CHIP_POLARIS10:
 930         case CHIP_POLARIS11:
 931         case CHIP_POLARIS12:
 932         case CHIP_TOPAZ:
 933                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 934                 break;
 935         default:
 936                 baco_reset = false;
 937                 break;
 938         }
 939
 940         if (baco_reset)
 941                 return AMD_RESET_METHOD_BACO;
 942         else
 943                 return AMD_RESET_METHOD_LEGACY;
 944 }
 945
 946 /**
 947  * vi_asic_reset - soft reset GPU
 948  *
 949  * @adev: amdgpu_device pointer
 950  *
 951  * Look up which blocks are hung and attempt
 952  * to reset them.
 953  * Returns 0 for success.
 954  */
 955 static int vi_asic_reset(struct amdgpu_device *adev)
 956 {
 957         int r;
 958
 959         if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 960                 dev_info(adev->dev, "BACO reset\n");
 961                 r = amdgpu_dpm_baco_reset(adev);
 962         } else {
 963                 dev_info(adev->dev, "PCI CONFIG reset\n");
 964                 r = vi_asic_pci_config_reset(adev);
 965         }
 966
 967         return r;
 968 }
 969
 970 static u32 vi_get_config_memsize(struct amdgpu_device *adev)
 971 {
 972         return RREG32(mmCONFIG_MEMSIZE);
 973 }
 974
 975 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 976                         u32 cntl_reg, u32 status_reg)
 977 {
 978         int r, i;
 979         struct atom_clock_dividers dividers;
 980         uint32_t tmp;
 981
 982         r = amdgpu_atombios_get_clock_dividers(adev,
 983                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 984                                                clock, false, &dividers);
 985         if (r)
 986                 return r;
 987
 988         tmp = RREG32_SMC(cntl_reg);
 989
 990         if (adev->flags & AMD_IS_APU)
 991                 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
 992         else
 993                 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
 994                                 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
 995         tmp |= dividers.post_divider;
 996         WREG32_SMC(cntl_reg, tmp);
 997
 998         for (i = 0; i < 100; i++) {
 999                 tmp = RREG32_SMC(status_reg);
1000                 if (adev->flags & AMD_IS_APU) {
1001                         if (tmp & 0x10000)
1002                                 break;
1003                 } else {
1004                         if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1005                                 break;
1006                 }
1007                 mdelay(10);
1008         }
1009         if (i == 100)
1010                 return -ETIMEDOUT;
1011         return 0;
1012 }
1013
1014 #define ixGNB_CLK1_DFS_CNTL 0xD82200F0
1015 #define ixGNB_CLK1_STATUS   0xD822010C
1016 #define ixGNB_CLK2_DFS_CNTL 0xD8220110
1017 #define ixGNB_CLK2_STATUS   0xD822012C
1018 #define ixGNB_CLK3_DFS_CNTL 0xD8220130
1019 #define ixGNB_CLK3_STATUS   0xD822014C
1020
1021 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1022 {
1023         int r;
1024
1025         if (adev->flags & AMD_IS_APU) {
1026                 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
1027                 if (r)
1028                         return r;
1029
1030                 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
1031                 if (r)
1032                         return r;
1033         } else {
1034                 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1035                 if (r)
1036                         return r;
1037
1038                 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1039                 if (r)
1040                         return r;
1041         }
1042
1043         return 0;
1044 }
1045
1046 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1047 {
1048         int r, i;
1049         struct atom_clock_dividers dividers;
1050         u32 tmp;
1051         u32 reg_ctrl;
1052         u32 reg_status;
1053         u32 status_mask;
1054         u32 reg_mask;
1055
1056         if (adev->flags & AMD_IS_APU) {
1057                 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
1058                 reg_status = ixGNB_CLK3_STATUS;
1059                 status_mask = 0x00010000;
1060                 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
1061         } else {
1062                 reg_ctrl = ixCG_ECLK_CNTL;
1063                 reg_status = ixCG_ECLK_STATUS;
1064                 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
1065                 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
1066         }
1067
1068         r = amdgpu_atombios_get_clock_dividers(adev,
1069                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1070                                                ecclk, false, &dividers);
1071         if (r)
1072                 return r;
1073
1074         for (i = 0; i < 100; i++) {
1075                 if (RREG32_SMC(reg_status) & status_mask)
1076                         break;
1077                 mdelay(10);
1078         }
1079
1080         if (i == 100)
1081                 return -ETIMEDOUT;
1082
1083         tmp = RREG32_SMC(reg_ctrl);
1084         tmp &= ~reg_mask;
1085         tmp |= dividers.post_divider;
1086         WREG32_SMC(reg_ctrl, tmp);
1087
1088         for (i = 0; i < 100; i++) {
1089                 if (RREG32_SMC(reg_status) & status_mask)
1090                         break;
1091                 mdelay(10);
1092         }
1093
1094         if (i == 100)
1095                 return -ETIMEDOUT;
1096
1097         return 0;
1098 }
1099
1100 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
1101 {
1102         if (pci_is_root_bus(adev->pdev->bus))
1103                 return;
1104
1105         if (amdgpu_pcie_gen2 == 0)
1106                 return;
1107
1108         if (adev->flags & AMD_IS_APU)
1109                 return;
1110
1111         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1112                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1113                 return;
1114
1115         /* todo */
1116 }
1117
1118 static void vi_enable_aspm(struct amdgpu_device *adev)
1119 {
1120         u32 data, orig;
1121
1122         orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1123         data |= PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT <<
1124                         PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
1125         data |= PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT <<
1126                         PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
1127         data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1128         data |= PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK;
1129         if (orig != data)
1130                 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1131 }
1132
1133 static void vi_program_aspm(struct amdgpu_device *adev)
1134 {
1135         u32 data, data1, orig;
1136         bool bL1SS = false;
1137         bool bClkReqSupport = true;
1138
1139         if (!amdgpu_aspm)
1140                 return;
1141
1142         if (adev->flags & AMD_IS_APU ||
1143             adev->asic_type < CHIP_POLARIS10)
1144                 return;
1145
1146         orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1147         data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
1148         data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1149         data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1150         if (orig != data)
1151                 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1152
1153         orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1154         data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
1155         data |= 0x0024 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT;
1156         data |= PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;
1157         if (orig != data)
1158                 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data);
1159
1160         orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
1161         data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
1162         if (orig != data)
1163                 WREG32_PCIE(ixPCIE_LC_CNTL3, data);
1164
1165         orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
1166         data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
1167         if (orig != data)
1168                 WREG32_PCIE(ixPCIE_P_CNTL, data);
1169
1170         data = RREG32_PCIE(ixPCIE_LC_L1_PM_SUBSTATE);
1171         pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, &data1);
1172         if (data & PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK &&
1173             (data & (PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK |
1174                     PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK |
1175                         PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK |
1176                         PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK))) {
1177                 bL1SS = true;
1178         } else if (data1 & (PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK |
1179             PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK |
1180             PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK |
1181             PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK)) {
1182                 bL1SS = true;
1183         }
1184
1185         orig = data = RREG32_PCIE(ixPCIE_LC_CNTL6);
1186         data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK;
1187         if (orig != data)
1188                 WREG32_PCIE(ixPCIE_LC_CNTL6, data);
1189
1190         orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1191         data |= PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
1192         if (orig != data)
1193                 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data);
1194
1195         pci_read_config_dword(adev->pdev, LINK_CAP, &data);
1196         if (!(data & PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK))
1197                 bClkReqSupport = false;
1198
1199         if (bClkReqSupport) {
1200                 orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1201                 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | THM_CLK_CNTL__TMON_CLK_SEL_MASK);
1202                 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) |
1203                                 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT);
1204                 if (orig != data)
1205                         WREG32_SMC(ixTHM_CLK_CNTL, data);
1206
1207                 orig = data = RREG32_SMC(ixMISC_CLK_CTRL);
1208                 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK |
1209                         MISC_CLK_CTRL__ZCLK_SEL_MASK | MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK);
1210                 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) |
1211                                 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT);
1212                 data |= (0x20 << MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT);
1213                 if (orig != data)
1214                         WREG32_SMC(ixMISC_CLK_CTRL, data);
1215
1216                 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);
1217                 data |= CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK;
1218                 if (orig != data)
1219                         WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1220
1221                 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
1222                 data |= CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK;
1223                 if (orig != data)
1224                         WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1225
1226                 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);
1227                 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;
1228                 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT);
1229                 if (orig != data)
1230                         WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
1231
1232                 orig = data = RREG32_PCIE(ixCPM_CONTROL);
1233                 data |= (CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK |
1234                                 CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK);
1235                 if (orig != data)
1236                         WREG32_PCIE(ixCPM_CONTROL, data);
1237
1238                 orig = data = RREG32_PCIE(ixPCIE_CONFIG_CNTL);
1239                 data &= ~PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK;
1240                 data |= (0xE << PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT);
1241                 if (orig != data)
1242                         WREG32_PCIE(ixPCIE_CONFIG_CNTL, data);
1243
1244                 orig = data = RREG32(mmBIF_CLK_CTRL);
1245                 data |= BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK;
1246                 if (orig != data)
1247                         WREG32(mmBIF_CLK_CTRL, data);
1248
1249                 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL7);
1250                 data |= PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK;
1251                 if (orig != data)
1252                         WREG32_PCIE(ixPCIE_LC_CNTL7, data);
1253
1254                 orig = data = RREG32_PCIE(ixPCIE_HW_DEBUG);
1255                 data |= PCIE_HW_DEBUG__HW_01_DEBUG_MASK;
1256                 if (orig != data)
1257                         WREG32_PCIE(ixPCIE_HW_DEBUG, data);
1258
1259                 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
1260                 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
1261                 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK;
1262                 if (bL1SS)
1263                         data &= ~PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK;
1264                 if (orig != data)
1265                         WREG32_PCIE(ixPCIE_LC_CNTL2, data);
1266
1267         }
1268
1269         vi_enable_aspm(adev);
1270
1271         data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1272         data1 = RREG32_PCIE(ixPCIE_LC_STATUS1);
1273         if (((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) &&
1274             data1 & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK &&
1275             data1 & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK) {
1276                 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1277                 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1278                 if (orig != data)
1279                         WREG32_PCIE(ixPCIE_LC_CNTL, data);
1280         }
1281
1282         if ((adev->asic_type == CHIP_POLARIS12 &&
1283             !(ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))) ||
1284             ASIC_IS_P22(adev->asic_type, adev->external_rev_id)) {
1285                 orig = data = RREG32_PCIE(ixPCIE_LC_TRAINING_CNTL);
1286                 data &= ~PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK;
1287                 if (orig != data)
1288                         WREG32_PCIE(ixPCIE_LC_TRAINING_CNTL, data);
1289         }
1290 }
1291
1292 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1293                                         bool enable)
1294 {
1295         u32 tmp;
1296
1297         /* not necessary on CZ */
1298         if (adev->flags & AMD_IS_APU)
1299                 return;
1300
1301         tmp = RREG32(mmBIF_DOORBELL_APER_EN);
1302         if (enable)
1303                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
1304         else
1305                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
1306
1307         WREG32(mmBIF_DOORBELL_APER_EN, tmp);
1308 }
1309
1310 #define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
1311 #define ATI_REV_ID_FUSE_MACRO__SHIFT        9
1312 #define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
1313
1314 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1315 {
1316         if (adev->flags & AMD_IS_APU)
1317                 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1318                         >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1319         else
1320                 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1321                         >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1322 }
1323
1324 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1325 {
1326         if (!ring || !ring->funcs->emit_wreg) {
1327                 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1328                 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1329         } else {
1330                 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1331         }
1332 }
1333
1334 static void vi_invalidate_hdp(struct amdgpu_device *adev,
1335                               struct amdgpu_ring *ring)
1336 {
1337         if (!ring || !ring->funcs->emit_wreg) {
1338                 WREG32(mmHDP_DEBUG0, 1);
1339                 RREG32(mmHDP_DEBUG0);
1340         } else {
1341                 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
1342         }
1343 }
1344
1345 static bool vi_need_full_reset(struct amdgpu_device *adev)
1346 {
1347         switch (adev->asic_type) {
1348         case CHIP_CARRIZO:
1349         case CHIP_STONEY:
1350                 /* CZ has hang issues with full reset at the moment */
1351                 return false;
1352         case CHIP_FIJI:
1353         case CHIP_TONGA:
1354                 /* XXX: soft reset should work on fiji and tonga */
1355                 return true;
1356         case CHIP_POLARIS10:
1357         case CHIP_POLARIS11:
1358         case CHIP_POLARIS12:
1359         case CHIP_TOPAZ:
1360         default:
1361                 /* change this when we support soft reset */
1362                 return true;
1363         }
1364 }
1365
1366 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1367                               uint64_t *count1)
1368 {
1369         uint32_t perfctr = 0;
1370         uint64_t cnt0_of, cnt1_of;
1371         int tmp;
1372
1373         /* This reports 0 on APUs, so return to avoid writing/reading registers
1374          * that may or may not be different from their GPU counterparts
1375          */
1376         if (adev->flags & AMD_IS_APU)
1377                 return;
1378
1379         /* Set the 2 events that we wish to watch, defined above */
1380         /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
1381         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1382         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1383
1384         /* Write to enable desired perf counters */
1385         WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1386         /* Zero out and enable the perf counters
1387          * Write 0x5:
1388          * Bit 0 = Start all counters(1)
1389          * Bit 2 = Global counter reset enable(1)
1390          */
1391         WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1392
1393         msleep(1000);
1394
1395         /* Load the shadow and disable the perf counters
1396          * Write 0x2:
1397          * Bit 0 = Stop counters(0)
1398          * Bit 1 = Load the shadow counters(1)
1399          */
1400         WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1401
1402         /* Read register values to get any >32bit overflow */
1403         tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1404         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1405         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1406
1407         /* Get the values and add the overflow */
1408         *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1409         *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1410 }
1411
1412 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
1413 {
1414         uint64_t nak_r, nak_g;
1415
1416         /* Get the number of NAKs received and generated */
1417         nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1418         nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1419
1420         /* Add the total number of NAKs, i.e the number of replays */
1421         return (nak_r + nak_g);
1422 }
1423
1424 static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1425 {
1426         u32 clock_cntl, pc;
1427
1428         if (adev->flags & AMD_IS_APU)
1429                 return false;
1430
1431         /* check if the SMC is already running */
1432         clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
1433         pc = RREG32_SMC(ixSMC_PC_C);
1434         if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
1435             (0x20100 <= pc))
1436                 return true;
1437
1438         return false;
1439 }
1440
1441 static void vi_pre_asic_init(struct amdgpu_device *adev)
1442 {
1443 }
1444
1445 static const struct amdgpu_asic_funcs vi_asic_funcs =
1446 {
1447         .read_disabled_bios = &vi_read_disabled_bios,
1448         .read_bios_from_rom = &vi_read_bios_from_rom,
1449         .read_register = &vi_read_register,
1450         .reset = &vi_asic_reset,
1451         .reset_method = &vi_asic_reset_method,
1452         .set_vga_state = &vi_vga_set_state,
1453         .get_xclk = &vi_get_xclk,
1454         .set_uvd_clocks = &vi_set_uvd_clocks,
1455         .set_vce_clocks = &vi_set_vce_clocks,
1456         .get_config_memsize = &vi_get_config_memsize,
1457         .flush_hdp = &vi_flush_hdp,
1458         .invalidate_hdp = &vi_invalidate_hdp,
1459         .need_full_reset = &vi_need_full_reset,
1460         .init_doorbell_index = &legacy_doorbell_index_init,
1461         .get_pcie_usage = &vi_get_pcie_usage,
1462         .need_reset_on_init = &vi_need_reset_on_init,
1463         .get_pcie_replay_count = &vi_get_pcie_replay_count,
1464         .supports_baco = &vi_asic_supports_baco,
1465         .pre_asic_init = &vi_pre_asic_init,
1466         .query_video_codecs = &vi_query_video_codecs,
1467 };
1468
1469 #define CZ_REV_BRISTOL(rev)      \
1470         ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
1471
1472 static int vi_common_early_init(void *handle)
1473 {
1474         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1475
1476         if (adev->flags & AMD_IS_APU) {
1477                 adev->smc_rreg = &cz_smc_rreg;
1478                 adev->smc_wreg = &cz_smc_wreg;
1479         } else {
1480                 adev->smc_rreg = &vi_smc_rreg;
1481                 adev->smc_wreg = &vi_smc_wreg;
1482         }
1483         adev->pcie_rreg = &vi_pcie_rreg;
1484         adev->pcie_wreg = &vi_pcie_wreg;
1485         adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1486         adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1487         adev->didt_rreg = &vi_didt_rreg;
1488         adev->didt_wreg = &vi_didt_wreg;
1489         adev->gc_cac_rreg = &vi_gc_cac_rreg;
1490         adev->gc_cac_wreg = &vi_gc_cac_wreg;
1491
1492         adev->asic_funcs = &vi_asic_funcs;
1493
1494         adev->rev_id = vi_get_rev_id(adev);
1495         adev->external_rev_id = 0xFF;
1496         switch (adev->asic_type) {
1497         case CHIP_TOPAZ:
1498                 adev->cg_flags = 0;
1499                 adev->pg_flags = 0;
1500                 adev->external_rev_id = 0x1;
1501                 break;
1502         case CHIP_FIJI:
1503                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1504                         AMD_CG_SUPPORT_GFX_MGLS |
1505                         AMD_CG_SUPPORT_GFX_RLC_LS |
1506                         AMD_CG_SUPPORT_GFX_CP_LS |
1507                         AMD_CG_SUPPORT_GFX_CGTS |
1508                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1509                         AMD_CG_SUPPORT_GFX_CGCG |
1510                         AMD_CG_SUPPORT_GFX_CGLS |
1511                         AMD_CG_SUPPORT_SDMA_MGCG |
1512                         AMD_CG_SUPPORT_SDMA_LS |
1513                         AMD_CG_SUPPORT_BIF_LS |
1514                         AMD_CG_SUPPORT_HDP_MGCG |
1515                         AMD_CG_SUPPORT_HDP_LS |
1516                         AMD_CG_SUPPORT_ROM_MGCG |
1517                         AMD_CG_SUPPORT_MC_MGCG |
1518                         AMD_CG_SUPPORT_MC_LS |
1519                         AMD_CG_SUPPORT_UVD_MGCG;
1520                 adev->pg_flags = 0;
1521                 adev->external_rev_id = adev->rev_id + 0x3c;
1522                 break;
1523         case CHIP_TONGA:
1524                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1525                         AMD_CG_SUPPORT_GFX_CGCG |
1526                         AMD_CG_SUPPORT_GFX_CGLS |
1527                         AMD_CG_SUPPORT_SDMA_MGCG |
1528                         AMD_CG_SUPPORT_SDMA_LS |
1529                         AMD_CG_SUPPORT_BIF_LS |
1530                         AMD_CG_SUPPORT_HDP_MGCG |
1531                         AMD_CG_SUPPORT_HDP_LS |
1532                         AMD_CG_SUPPORT_ROM_MGCG |
1533                         AMD_CG_SUPPORT_MC_MGCG |
1534                         AMD_CG_SUPPORT_MC_LS |
1535                         AMD_CG_SUPPORT_DRM_LS |
1536                         AMD_CG_SUPPORT_UVD_MGCG;
1537                 adev->pg_flags = 0;
1538                 adev->external_rev_id = adev->rev_id + 0x14;
1539                 break;
1540         case CHIP_POLARIS11:
1541                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1542                         AMD_CG_SUPPORT_GFX_RLC_LS |
1543                         AMD_CG_SUPPORT_GFX_CP_LS |
1544                         AMD_CG_SUPPORT_GFX_CGCG |
1545                         AMD_CG_SUPPORT_GFX_CGLS |
1546                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1547                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1548                         AMD_CG_SUPPORT_SDMA_MGCG |
1549                         AMD_CG_SUPPORT_SDMA_LS |
1550                         AMD_CG_SUPPORT_BIF_MGCG |
1551                         AMD_CG_SUPPORT_BIF_LS |
1552                         AMD_CG_SUPPORT_HDP_MGCG |
1553                         AMD_CG_SUPPORT_HDP_LS |
1554                         AMD_CG_SUPPORT_ROM_MGCG |
1555                         AMD_CG_SUPPORT_MC_MGCG |
1556                         AMD_CG_SUPPORT_MC_LS |
1557                         AMD_CG_SUPPORT_DRM_LS |
1558                         AMD_CG_SUPPORT_UVD_MGCG |
1559                         AMD_CG_SUPPORT_VCE_MGCG;
1560                 adev->pg_flags = 0;
1561                 adev->external_rev_id = adev->rev_id + 0x5A;
1562                 break;
1563         case CHIP_POLARIS10:
1564                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1565                         AMD_CG_SUPPORT_GFX_RLC_LS |
1566                         AMD_CG_SUPPORT_GFX_CP_LS |
1567                         AMD_CG_SUPPORT_GFX_CGCG |
1568                         AMD_CG_SUPPORT_GFX_CGLS |
1569                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1570                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1571                         AMD_CG_SUPPORT_SDMA_MGCG |
1572                         AMD_CG_SUPPORT_SDMA_LS |
1573                         AMD_CG_SUPPORT_BIF_MGCG |
1574                         AMD_CG_SUPPORT_BIF_LS |
1575                         AMD_CG_SUPPORT_HDP_MGCG |
1576                         AMD_CG_SUPPORT_HDP_LS |
1577                         AMD_CG_SUPPORT_ROM_MGCG |
1578                         AMD_CG_SUPPORT_MC_MGCG |
1579                         AMD_CG_SUPPORT_MC_LS |
1580                         AMD_CG_SUPPORT_DRM_LS |
1581                         AMD_CG_SUPPORT_UVD_MGCG |
1582                         AMD_CG_SUPPORT_VCE_MGCG;
1583                 adev->pg_flags = 0;
1584                 adev->external_rev_id = adev->rev_id + 0x50;
1585                 break;
1586         case CHIP_POLARIS12:
1587                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1588                         AMD_CG_SUPPORT_GFX_RLC_LS |
1589                         AMD_CG_SUPPORT_GFX_CP_LS |
1590                         AMD_CG_SUPPORT_GFX_CGCG |
1591                         AMD_CG_SUPPORT_GFX_CGLS |
1592                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1593                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1594                         AMD_CG_SUPPORT_SDMA_MGCG |
1595                         AMD_CG_SUPPORT_SDMA_LS |
1596                         AMD_CG_SUPPORT_BIF_MGCG |
1597                         AMD_CG_SUPPORT_BIF_LS |
1598                         AMD_CG_SUPPORT_HDP_MGCG |
1599                         AMD_CG_SUPPORT_HDP_LS |
1600                         AMD_CG_SUPPORT_ROM_MGCG |
1601                         AMD_CG_SUPPORT_MC_MGCG |
1602                         AMD_CG_SUPPORT_MC_LS |
1603                         AMD_CG_SUPPORT_DRM_LS |
1604                         AMD_CG_SUPPORT_UVD_MGCG |
1605                         AMD_CG_SUPPORT_VCE_MGCG;
1606                 adev->pg_flags = 0;
1607                 adev->external_rev_id = adev->rev_id + 0x64;
1608                 break;
1609         case CHIP_VEGAM:
1610                 adev->cg_flags = 0;
1611                         /*AMD_CG_SUPPORT_GFX_MGCG |
1612                         AMD_CG_SUPPORT_GFX_RLC_LS |
1613                         AMD_CG_SUPPORT_GFX_CP_LS |
1614                         AMD_CG_SUPPORT_GFX_CGCG |
1615                         AMD_CG_SUPPORT_GFX_CGLS |
1616                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1617                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1618                         AMD_CG_SUPPORT_SDMA_MGCG |
1619                         AMD_CG_SUPPORT_SDMA_LS |
1620                         AMD_CG_SUPPORT_BIF_MGCG |
1621                         AMD_CG_SUPPORT_BIF_LS |
1622                         AMD_CG_SUPPORT_HDP_MGCG |
1623                         AMD_CG_SUPPORT_HDP_LS |
1624                         AMD_CG_SUPPORT_ROM_MGCG |
1625                         AMD_CG_SUPPORT_MC_MGCG |
1626                         AMD_CG_SUPPORT_MC_LS |
1627                         AMD_CG_SUPPORT_DRM_LS |
1628                         AMD_CG_SUPPORT_UVD_MGCG |
1629                         AMD_CG_SUPPORT_VCE_MGCG;*/
1630                 adev->pg_flags = 0;
1631                 adev->external_rev_id = adev->rev_id + 0x6E;
1632                 break;
1633         case CHIP_CARRIZO:
1634                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1635                         AMD_CG_SUPPORT_GFX_MGCG |
1636                         AMD_CG_SUPPORT_GFX_MGLS |
1637                         AMD_CG_SUPPORT_GFX_RLC_LS |
1638                         AMD_CG_SUPPORT_GFX_CP_LS |
1639                         AMD_CG_SUPPORT_GFX_CGTS |
1640                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1641                         AMD_CG_SUPPORT_GFX_CGCG |
1642                         AMD_CG_SUPPORT_GFX_CGLS |
1643                         AMD_CG_SUPPORT_BIF_LS |
1644                         AMD_CG_SUPPORT_HDP_MGCG |
1645                         AMD_CG_SUPPORT_HDP_LS |
1646                         AMD_CG_SUPPORT_SDMA_MGCG |
1647                         AMD_CG_SUPPORT_SDMA_LS |
1648                         AMD_CG_SUPPORT_VCE_MGCG;
1649                 /* rev0 hardware requires workarounds to support PG */
1650                 adev->pg_flags = 0;
1651                 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1652                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1653                                 AMD_PG_SUPPORT_GFX_PIPELINE |
1654                                 AMD_PG_SUPPORT_CP |
1655                                 AMD_PG_SUPPORT_UVD |
1656                                 AMD_PG_SUPPORT_VCE;
1657                 }
1658                 adev->external_rev_id = adev->rev_id + 0x1;
1659                 break;
1660         case CHIP_STONEY:
1661                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1662                         AMD_CG_SUPPORT_GFX_MGCG |
1663                         AMD_CG_SUPPORT_GFX_MGLS |
1664                         AMD_CG_SUPPORT_GFX_RLC_LS |
1665                         AMD_CG_SUPPORT_GFX_CP_LS |
1666                         AMD_CG_SUPPORT_GFX_CGTS |
1667                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1668                         AMD_CG_SUPPORT_GFX_CGLS |
1669                         AMD_CG_SUPPORT_BIF_LS |
1670                         AMD_CG_SUPPORT_HDP_MGCG |
1671                         AMD_CG_SUPPORT_HDP_LS |
1672                         AMD_CG_SUPPORT_SDMA_MGCG |
1673                         AMD_CG_SUPPORT_SDMA_LS |
1674                         AMD_CG_SUPPORT_VCE_MGCG;
1675                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1676                         AMD_PG_SUPPORT_GFX_SMG |
1677                         AMD_PG_SUPPORT_GFX_PIPELINE |
1678                         AMD_PG_SUPPORT_CP |
1679                         AMD_PG_SUPPORT_UVD |
1680                         AMD_PG_SUPPORT_VCE;
1681                 adev->external_rev_id = adev->rev_id + 0x61;
1682                 break;
1683         default:
1684                 /* FIXME: not supported yet */
1685                 return -EINVAL;
1686         }
1687
1688         if (amdgpu_sriov_vf(adev)) {
1689                 amdgpu_virt_init_setting(adev);
1690                 xgpu_vi_mailbox_set_irq_funcs(adev);
1691         }
1692
1693         return 0;
1694 }
1695
1696 static int vi_common_late_init(void *handle)
1697 {
1698         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1699
1700         if (amdgpu_sriov_vf(adev))
1701                 xgpu_vi_mailbox_get_irq(adev);
1702
1703         return 0;
1704 }
1705
1706 static int vi_common_sw_init(void *handle)
1707 {
1708         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1709
1710         if (amdgpu_sriov_vf(adev))
1711                 xgpu_vi_mailbox_add_irq_id(adev);
1712
1713         return 0;
1714 }
1715
1716 static int vi_common_sw_fini(void *handle)
1717 {
1718         return 0;
1719 }
1720
1721 static int vi_common_hw_init(void *handle)
1722 {
1723         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1724
1725         /* move the golden regs per IP block */
1726         vi_init_golden_registers(adev);
1727         /* enable pcie gen2/3 link */
1728         vi_pcie_gen3_enable(adev);
1729         /* enable aspm */
1730         vi_program_aspm(adev);
1731         /* enable the doorbell aperture */
1732         vi_enable_doorbell_aperture(adev, true);
1733
1734         return 0;
1735 }
1736
1737 static int vi_common_hw_fini(void *handle)
1738 {
1739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1740
1741         /* enable the doorbell aperture */
1742         vi_enable_doorbell_aperture(adev, false);
1743
1744         if (amdgpu_sriov_vf(adev))
1745                 xgpu_vi_mailbox_put_irq(adev);
1746
1747         return 0;
1748 }
1749
1750 static int vi_common_suspend(void *handle)
1751 {
1752         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1753
1754         return vi_common_hw_fini(adev);
1755 }
1756
1757 static int vi_common_resume(void *handle)
1758 {
1759         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1760
1761         return vi_common_hw_init(adev);
1762 }
1763
1764 static bool vi_common_is_idle(void *handle)
1765 {
1766         return true;
1767 }
1768
1769 static int vi_common_wait_for_idle(void *handle)
1770 {
1771         return 0;
1772 }
1773
1774 static int vi_common_soft_reset(void *handle)
1775 {
1776         return 0;
1777 }
1778
1779 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1780                                                    bool enable)
1781 {
1782         uint32_t temp, data;
1783
1784         temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1785
1786         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1787                 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1788                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1789                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1790         else
1791                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1792                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1793                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1794
1795         if (temp != data)
1796                 WREG32_PCIE(ixPCIE_CNTL2, data);
1797 }
1798
1799 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1800                                                     bool enable)
1801 {
1802         uint32_t temp, data;
1803
1804         temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1805
1806         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1807                 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1808         else
1809                 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1810
1811         if (temp != data)
1812                 WREG32(mmHDP_HOST_PATH_CNTL, data);
1813 }
1814
1815 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1816                                       bool enable)
1817 {
1818         uint32_t temp, data;
1819
1820         temp = data = RREG32(mmHDP_MEM_POWER_LS);
1821
1822         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1823                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1824         else
1825                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1826
1827         if (temp != data)
1828                 WREG32(mmHDP_MEM_POWER_LS, data);
1829 }
1830
1831 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1832                                       bool enable)
1833 {
1834         uint32_t temp, data;
1835
1836         temp = data = RREG32(0x157a);
1837
1838         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1839                 data |= 1;
1840         else
1841                 data &= ~1;
1842
1843         if (temp != data)
1844                 WREG32(0x157a, data);
1845 }
1846
1847
1848 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1849                                                     bool enable)
1850 {
1851         uint32_t temp, data;
1852
1853         temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1854
1855         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1856                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1857                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1858         else
1859                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1860                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1861
1862         if (temp != data)
1863                 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1864 }
1865
1866 static int vi_common_set_clockgating_state_by_smu(void *handle,
1867                                            enum amd_clockgating_state state)
1868 {
1869         uint32_t msg_id, pp_state = 0;
1870         uint32_t pp_support_state = 0;
1871         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1872
1873         if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1874                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1875                         pp_support_state = PP_STATE_SUPPORT_LS;
1876                         pp_state = PP_STATE_LS;
1877                 }
1878                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1879                         pp_support_state |= PP_STATE_SUPPORT_CG;
1880                         pp_state |= PP_STATE_CG;
1881                 }
1882                 if (state == AMD_CG_STATE_UNGATE)
1883                         pp_state = 0;
1884                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1885                                PP_BLOCK_SYS_MC,
1886                                pp_support_state,
1887                                pp_state);
1888                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1889         }
1890
1891         if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1892                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1893                         pp_support_state = PP_STATE_SUPPORT_LS;
1894                         pp_state = PP_STATE_LS;
1895                 }
1896                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1897                         pp_support_state |= PP_STATE_SUPPORT_CG;
1898                         pp_state |= PP_STATE_CG;
1899                 }
1900                 if (state == AMD_CG_STATE_UNGATE)
1901                         pp_state = 0;
1902                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1903                                PP_BLOCK_SYS_SDMA,
1904                                pp_support_state,
1905                                pp_state);
1906                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1907         }
1908
1909         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1910                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1911                         pp_support_state = PP_STATE_SUPPORT_LS;
1912                         pp_state = PP_STATE_LS;
1913                 }
1914                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1915                         pp_support_state |= PP_STATE_SUPPORT_CG;
1916                         pp_state |= PP_STATE_CG;
1917                 }
1918                 if (state == AMD_CG_STATE_UNGATE)
1919                         pp_state = 0;
1920                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1921                                PP_BLOCK_SYS_HDP,
1922                                pp_support_state,
1923                                pp_state);
1924                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1925         }
1926
1927
1928         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1929                 if (state == AMD_CG_STATE_UNGATE)
1930                         pp_state = 0;
1931                 else
1932                         pp_state = PP_STATE_LS;
1933
1934                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1935                                PP_BLOCK_SYS_BIF,
1936                                PP_STATE_SUPPORT_LS,
1937                                 pp_state);
1938                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1939         }
1940         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1941                 if (state == AMD_CG_STATE_UNGATE)
1942                         pp_state = 0;
1943                 else
1944                         pp_state = PP_STATE_CG;
1945
1946                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1947                                PP_BLOCK_SYS_BIF,
1948                                PP_STATE_SUPPORT_CG,
1949                                pp_state);
1950                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1951         }
1952
1953         if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1954
1955                 if (state == AMD_CG_STATE_UNGATE)
1956                         pp_state = 0;
1957                 else
1958                         pp_state = PP_STATE_LS;
1959
1960                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1961                                PP_BLOCK_SYS_DRM,
1962                                PP_STATE_SUPPORT_LS,
1963                                pp_state);
1964                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1965         }
1966
1967         if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1968
1969                 if (state == AMD_CG_STATE_UNGATE)
1970                         pp_state = 0;
1971                 else
1972                         pp_state = PP_STATE_CG;
1973
1974                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1975                                PP_BLOCK_SYS_ROM,
1976                                PP_STATE_SUPPORT_CG,
1977                                pp_state);
1978                 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1979         }
1980         return 0;
1981 }
1982
1983 static int vi_common_set_clockgating_state(void *handle,
1984                                            enum amd_clockgating_state state)
1985 {
1986         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1987
1988         if (amdgpu_sriov_vf(adev))
1989                 return 0;
1990
1991         switch (adev->asic_type) {
1992         case CHIP_FIJI:
1993                 vi_update_bif_medium_grain_light_sleep(adev,
1994                                 state == AMD_CG_STATE_GATE);
1995                 vi_update_hdp_medium_grain_clock_gating(adev,
1996                                 state == AMD_CG_STATE_GATE);
1997                 vi_update_hdp_light_sleep(adev,
1998                                 state == AMD_CG_STATE_GATE);
1999                 vi_update_rom_medium_grain_clock_gating(adev,
2000                                 state == AMD_CG_STATE_GATE);
2001                 break;
2002         case CHIP_CARRIZO:
2003         case CHIP_STONEY:
2004                 vi_update_bif_medium_grain_light_sleep(adev,
2005                                 state == AMD_CG_STATE_GATE);
2006                 vi_update_hdp_medium_grain_clock_gating(adev,
2007                                 state == AMD_CG_STATE_GATE);
2008                 vi_update_hdp_light_sleep(adev,
2009                                 state == AMD_CG_STATE_GATE);
2010                 vi_update_drm_light_sleep(adev,
2011                                 state == AMD_CG_STATE_GATE);
2012                 break;
2013         case CHIP_TONGA:
2014         case CHIP_POLARIS10:
2015         case CHIP_POLARIS11:
2016         case CHIP_POLARIS12:
2017         case CHIP_VEGAM:
2018                 vi_common_set_clockgating_state_by_smu(adev, state);
2019                 break;
2020         default:
2021                 break;
2022         }
2023         return 0;
2024 }
2025
2026 static int vi_common_set_powergating_state(void *handle,
2027                                             enum amd_powergating_state state)
2028 {
2029         return 0;
2030 }
2031
2032 static void vi_common_get_clockgating_state(void *handle, u32 *flags)
2033 {
2034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2035         int data;
2036
2037         if (amdgpu_sriov_vf(adev))
2038                 *flags = 0;
2039
2040         /* AMD_CG_SUPPORT_BIF_LS */
2041         data = RREG32_PCIE(ixPCIE_CNTL2);
2042         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
2043                 *flags |= AMD_CG_SUPPORT_BIF_LS;
2044
2045         /* AMD_CG_SUPPORT_HDP_LS */
2046         data = RREG32(mmHDP_MEM_POWER_LS);
2047         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
2048                 *flags |= AMD_CG_SUPPORT_HDP_LS;
2049
2050         /* AMD_CG_SUPPORT_HDP_MGCG */
2051         data = RREG32(mmHDP_HOST_PATH_CNTL);
2052         if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
2053                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
2054
2055         /* AMD_CG_SUPPORT_ROM_MGCG */
2056         data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
2057         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
2058                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
2059 }
2060
2061 static const struct amd_ip_funcs vi_common_ip_funcs = {
2062         .name = "vi_common",
2063         .early_init = vi_common_early_init,
2064         .late_init = vi_common_late_init,
2065         .sw_init = vi_common_sw_init,
2066         .sw_fini = vi_common_sw_fini,
2067         .hw_init = vi_common_hw_init,
2068         .hw_fini = vi_common_hw_fini,
2069         .suspend = vi_common_suspend,
2070         .resume = vi_common_resume,
2071         .is_idle = vi_common_is_idle,
2072         .wait_for_idle = vi_common_wait_for_idle,
2073         .soft_reset = vi_common_soft_reset,
2074         .set_clockgating_state = vi_common_set_clockgating_state,
2075         .set_powergating_state = vi_common_set_powergating_state,
2076         .get_clockgating_state = vi_common_get_clockgating_state,
2077 };
2078
2079 static const struct amdgpu_ip_block_version vi_common_ip_block =
2080 {
2081         .type = AMD_IP_BLOCK_TYPE_COMMON,
2082         .major = 1,
2083         .minor = 0,
2084         .rev = 0,
2085         .funcs = &vi_common_ip_funcs,
2086 };
2087
2088 void vi_set_virt_ops(struct amdgpu_device *adev)
2089 {
2090         adev->virt.ops = &xgpu_vi_virt_ops;
2091 }
2092
2093 int vi_set_ip_blocks(struct amdgpu_device *adev)
2094 {
2095         switch (adev->asic_type) {
2096         case CHIP_TOPAZ:
2097                 /* topaz has no DCE, UVD, VCE */
2098                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2099                 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
2100                 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
2101                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2102                 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
2103                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2104                 if (adev->enable_virtual_display)
2105                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2106                 break;
2107         case CHIP_FIJI:
2108                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2109                 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
2110                 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
2111                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2112                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2113                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2114                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2115                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2116 #if defined(CONFIG_DRM_AMD_DC)
2117                 else if (amdgpu_device_has_dc_support(adev))
2118                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
2119 #endif
2120                 else
2121                         amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
2122                 if (!amdgpu_sriov_vf(adev)) {
2123                         amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
2124                         amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
2125                 }
2126                 break;
2127         case CHIP_TONGA:
2128                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2129                 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
2130                 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
2131                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2132                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2133                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2134                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2135                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2136 #if defined(CONFIG_DRM_AMD_DC)
2137                 else if (amdgpu_device_has_dc_support(adev))
2138                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
2139 #endif
2140                 else
2141                         amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
2142                 if (!amdgpu_sriov_vf(adev)) {
2143                         amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
2144                         amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
2145                 }
2146                 break;
2147         case CHIP_POLARIS10:
2148         case CHIP_POLARIS11:
2149         case CHIP_POLARIS12:
2150         case CHIP_VEGAM:
2151                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2152                 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
2153                 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
2154                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2155                 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
2156                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2157                 if (adev->enable_virtual_display)
2158                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2159 #if defined(CONFIG_DRM_AMD_DC)
2160                 else if (amdgpu_device_has_dc_support(adev))
2161                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
2162 #endif
2163                 else
2164                         amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
2165                 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
2166                 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
2167                 break;
2168         case CHIP_CARRIZO:
2169                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2170                 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
2171                 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
2172                 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2173                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2174                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2175                 if (adev->enable_virtual_display)
2176                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2177 #if defined(CONFIG_DRM_AMD_DC)
2178                 else if (amdgpu_device_has_dc_support(adev))
2179                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
2180 #endif
2181                 else
2182                         amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2183                 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
2184                 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
2185 #if defined(CONFIG_DRM_AMD_ACP)
2186                 amdgpu_device_ip_block_add(adev, &acp_ip_block);
2187 #endif
2188                 break;
2189         case CHIP_STONEY:
2190                 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2191                 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
2192                 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
2193                 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
2194                 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2195                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2196                 if (adev->enable_virtual_display)
2197                         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2198 #if defined(CONFIG_DRM_AMD_DC)
2199                 else if (amdgpu_device_has_dc_support(adev))
2200                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
2201 #endif
2202                 else
2203                         amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2204                 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
2205                 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
2206 #if defined(CONFIG_DRM_AMD_ACP)
2207                 amdgpu_device_ip_block_add(adev, &acp_ip_block);
2208 #endif
2209                 break;
2210         default:
2211                 /* FIXME: not supported yet */
2212                 return -EINVAL;
2213         }
2214
2215         return 0;
2216 }
2217
2218 void legacy_doorbell_index_init(struct amdgpu_device *adev)
2219 {
2220         adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
2221         adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
2222         adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
2223         adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
2224         adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
2225         adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
2226         adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
2227         adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
2228         adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
2229         adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
2230         adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
2231         adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
2232         adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
2233         adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
2234 }