drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <christian.koenig@amd.com>
  26  */
  27
  28 #include <linux/firmware.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_vce.h"
  32 #include "vid.h"
  33 #include "vce/vce_3_0_d.h"
  34 #include "vce/vce_3_0_sh_mask.h"
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37 #include "gca/gfx_8_0_d.h"
  38 #include "smu/smu_7_1_2_d.h"
  39 #include "smu/smu_7_1_2_sh_mask.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41 #include "ivsrcid/ivsrcid_vislands30.h"
  42
  43
  44 #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT     0x04
  45 #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK       0x10
  46 #define GRBM_GFX_INDEX__VCE_ALL_PIPE            0x07
  47
  48 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616
  49 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617
  50 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618
  51 #define mmGRBM_GFX_INDEX_DEFAULT 0xE0000000
  52
  53 #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK   0x02
  54
  55 #define VCE_V3_0_FW_SIZE        (384 * 1024)
  56 #define VCE_V3_0_STACK_SIZE     (64 * 1024)
  57 #define VCE_V3_0_DATA_SIZE      ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024))
  58
  59 #define FW_52_8_3       ((52 << 24) | (8 << 16) | (3 << 8))
  60
  61 #define GET_VCE_INSTANCE(i)  ((i) << GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT \
  62                                         | GRBM_GFX_INDEX__VCE_ALL_PIPE)
  63
  64 static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
  65 static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  66 static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  67 static int vce_v3_0_wait_for_idle(void *handle);
  68 static int vce_v3_0_set_clockgating_state(void *handle,
  69                                           enum amd_clockgating_state state);
  70 /**
  71  * vce_v3_0_ring_get_rptr - get read pointer
  72  *
  73  * @ring: amdgpu_ring pointer
  74  *
  75  * Returns the current hardware read pointer
  76  */
  77 static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
  78 {
  79         struct amdgpu_device *adev = ring->adev;
  80         u32 v;
  81
  82         mutex_lock(&adev->grbm_idx_mutex);
  83         if (adev->vce.harvest_config == 0 ||
  84                 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
  85                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
  86         else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
  87                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
  88
  89         if (ring->me == 0)
  90                 v = RREG32(mmVCE_RB_RPTR);
  91         else if (ring->me == 1)
  92                 v = RREG32(mmVCE_RB_RPTR2);
  93         else
  94                 v = RREG32(mmVCE_RB_RPTR3);
  95
  96         WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
  97         mutex_unlock(&adev->grbm_idx_mutex);
  98
  99         return v;
 100 }
 101
 102 /**
 103  * vce_v3_0_ring_get_wptr - get write pointer
 104  *
 105  * @ring: amdgpu_ring pointer
 106  *
 107  * Returns the current hardware write pointer
 108  */
 109 static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 110 {
 111         struct amdgpu_device *adev = ring->adev;
 112         u32 v;
 113
 114         mutex_lock(&adev->grbm_idx_mutex);
 115         if (adev->vce.harvest_config == 0 ||
 116                 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
 117                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
 118         else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
 119                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
 120
 121         if (ring->me == 0)
 122                 v = RREG32(mmVCE_RB_WPTR);
 123         else if (ring->me == 1)
 124                 v = RREG32(mmVCE_RB_WPTR2);
 125         else
 126                 v = RREG32(mmVCE_RB_WPTR3);
 127
 128         WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
 129         mutex_unlock(&adev->grbm_idx_mutex);
 130
 131         return v;
 132 }
 133
 134 /**
 135  * vce_v3_0_ring_set_wptr - set write pointer
 136  *
 137  * @ring: amdgpu_ring pointer
 138  *
 139  * Commits the write pointer to the hardware
 140  */
 141 static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 142 {
 143         struct amdgpu_device *adev = ring->adev;
 144
 145         mutex_lock(&adev->grbm_idx_mutex);
 146         if (adev->vce.harvest_config == 0 ||
 147                 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1)
 148                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
 149         else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
 150                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
 151
 152         if (ring->me == 0)
 153                 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
 154         else if (ring->me == 1)
 155                 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
 156         else
 157                 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
 158
 159         WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
 160         mutex_unlock(&adev->grbm_idx_mutex);
 161 }
 162
 163 static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
 164 {
 165         WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0);
 166 }
 167
 168 static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
 169                                              bool gated)
 170 {
 171         u32 data;
 172
 173         /* Set Override to disable Clock Gating */
 174         vce_v3_0_override_vce_clock_gating(adev, true);
 175
 176         /* This function enables MGCG which is controlled by firmware.
 177            With the clocks in the gated state the core is still
 178            accessible but the firmware will throttle the clocks on the
 179            fly as necessary.
 180         */
 181         if (!gated) {
 182                 data = RREG32(mmVCE_CLOCK_GATING_B);
 183                 data |= 0x1ff;
 184                 data &= ~0xef0000;
 185                 WREG32(mmVCE_CLOCK_GATING_B, data);
 186
 187                 data = RREG32(mmVCE_UENC_CLOCK_GATING);
 188                 data |= 0x3ff000;
 189                 data &= ~0xffc00000;
 190                 WREG32(mmVCE_UENC_CLOCK_GATING, data);
 191
 192                 data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
 193                 data |= 0x2;
 194                 data &= ~0x00010000;
 195                 WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
 196
 197                 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
 198                 data |= 0x37f;
 199                 WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
 200
 201                 data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
 202                 data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
 203                         VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
 204                         VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
 205                         0x8;
 206                 WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
 207         } else {
 208                 data = RREG32(mmVCE_CLOCK_GATING_B);
 209                 data &= ~0x80010;
 210                 data |= 0xe70008;
 211                 WREG32(mmVCE_CLOCK_GATING_B, data);
 212
 213                 data = RREG32(mmVCE_UENC_CLOCK_GATING);
 214                 data |= 0xffc00000;
 215                 WREG32(mmVCE_UENC_CLOCK_GATING, data);
 216
 217                 data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
 218                 data |= 0x10000;
 219                 WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
 220
 221                 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
 222                 data &= ~0x3ff;
 223                 WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
 224
 225                 data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
 226                 data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
 227                           VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
 228                           VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |
 229                           0x8);
 230                 WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
 231         }
 232         vce_v3_0_override_vce_clock_gating(adev, false);
 233 }
 234
 235 static int vce_v3_0_firmware_loaded(struct amdgpu_device *adev)
 236 {
 237         int i, j;
 238
 239         for (i = 0; i < 10; ++i) {
 240                 for (j = 0; j < 100; ++j) {
 241                         uint32_t status = RREG32(mmVCE_STATUS);
 242
 243                         if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
 244                                 return 0;
 245                         mdelay(10);
 246                 }
 247
 248                 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
 249                 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
 250                 mdelay(10);
 251                 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
 252                 mdelay(10);
 253         }
 254
 255         return -ETIMEDOUT;
 256 }
 257
 258 /**
 259  * vce_v3_0_start - start VCE block
 260  *
 261  * @adev: amdgpu_device pointer
 262  *
 263  * Setup and start the VCE block
 264  */
 265 static int vce_v3_0_start(struct amdgpu_device *adev)
 266 {
 267         struct amdgpu_ring *ring;
 268         int idx, r;
 269
 270         mutex_lock(&adev->grbm_idx_mutex);
 271         for (idx = 0; idx < 2; ++idx) {
 272                 if (adev->vce.harvest_config & (1 << idx))
 273                         continue;
 274
 275                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
 276
 277                 /* Program instance 0 reg space for two instances or instance 0 case
 278                 program instance 1 reg space for only instance 1 available case */
 279                 if (idx != 1 || adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) {
 280                         ring = &adev->vce.ring[0];
 281                         WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
 282                         WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
 283                         WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
 284                         WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 285                         WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
 286
 287                         ring = &adev->vce.ring[1];
 288                         WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
 289                         WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
 290                         WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
 291                         WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 292                         WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
 293
 294                         ring = &adev->vce.ring[2];
 295                         WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
 296                         WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
 297                         WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
 298                         WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
 299                         WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
 300                 }
 301
 302                 vce_v3_0_mc_resume(adev, idx);
 303                 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);
 304
 305                 if (adev->asic_type >= CHIP_STONEY)
 306                         WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
 307                 else
 308                         WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
 309
 310                 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
 311                 mdelay(100);
 312
 313                 r = vce_v3_0_firmware_loaded(adev);
 314
 315                 /* clear BUSY flag */
 316                 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0);
 317
 318                 if (r) {
 319                         DRM_ERROR("VCE not responding, giving up!!!\n");
 320                         mutex_unlock(&adev->grbm_idx_mutex);
 321                         return r;
 322                 }
 323         }
 324
 325         WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
 326         mutex_unlock(&adev->grbm_idx_mutex);
 327
 328         return 0;
 329 }
 330
 331 static int vce_v3_0_stop(struct amdgpu_device *adev)
 332 {
 333         int idx;
 334
 335         mutex_lock(&adev->grbm_idx_mutex);
 336         for (idx = 0; idx < 2; ++idx) {
 337                 if (adev->vce.harvest_config & (1 << idx))
 338                         continue;
 339
 340                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
 341
 342                 if (adev->asic_type >= CHIP_STONEY)
 343                         WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);
 344                 else
 345                         WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0);
 346
 347                 /* hold on ECPU */
 348                 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
 349
 350                 /* clear VCE STATUS */
 351                 WREG32(mmVCE_STATUS, 0);
 352         }
 353
 354         WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
 355         mutex_unlock(&adev->grbm_idx_mutex);
 356
 357         return 0;
 358 }
 359
 360 #define ixVCE_HARVEST_FUSE_MACRO__ADDRESS     0xC0014074
 361 #define VCE_HARVEST_FUSE_MACRO__SHIFT       27
 362 #define VCE_HARVEST_FUSE_MACRO__MASK        0x18000000
 363
 364 static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
 365 {
 366         u32 tmp;
 367
 368         if ((adev->asic_type == CHIP_FIJI) ||
 369             (adev->asic_type == CHIP_STONEY))
 370                 return AMDGPU_VCE_HARVEST_VCE1;
 371
 372         if (adev->flags & AMD_IS_APU)
 373                 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
 374                        VCE_HARVEST_FUSE_MACRO__MASK) >>
 375                         VCE_HARVEST_FUSE_MACRO__SHIFT;
 376         else
 377                 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
 378                        CC_HARVEST_FUSES__VCE_DISABLE_MASK) >>
 379                         CC_HARVEST_FUSES__VCE_DISABLE__SHIFT;
 380
 381         switch (tmp) {
 382         case 1:
 383                 return AMDGPU_VCE_HARVEST_VCE0;
 384         case 2:
 385                 return AMDGPU_VCE_HARVEST_VCE1;
 386         case 3:
 387                 return AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
 388         default:
 389                 if ((adev->asic_type == CHIP_POLARIS10) ||
 390                     (adev->asic_type == CHIP_POLARIS11) ||
 391                     (adev->asic_type == CHIP_POLARIS12) ||
 392                     (adev->asic_type == CHIP_VEGAM))
 393                         return AMDGPU_VCE_HARVEST_VCE1;
 394
 395                 return 0;
 396         }
 397 }
 398
 399 static int vce_v3_0_early_init(void *handle)
 400 {
 401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 402
 403         adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
 404
 405         if ((adev->vce.harvest_config &
 406              (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) ==
 407             (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
 408                 return -ENOENT;
 409
 410         adev->vce.num_rings = 3;
 411
 412         vce_v3_0_set_ring_funcs(adev);
 413         vce_v3_0_set_irq_funcs(adev);
 414
 415         return 0;
 416 }
 417
 418 static int vce_v3_0_sw_init(void *handle)
 419 {
 420         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 421         struct amdgpu_ring *ring;
 422         int r, i;
 423
 424         /* VCE */
 425         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
 426         if (r)
 427                 return r;
 428
 429         r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE +
 430                 (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2);
 431         if (r)
 432                 return r;
 433
 434         /* 52.8.3 required for 3 ring support */
 435         if (adev->vce.fw_version < FW_52_8_3)
 436                 adev->vce.num_rings = 2;
 437
 438         r = amdgpu_vce_resume(adev);
 439         if (r)
 440                 return r;
 441
 442         for (i = 0; i < adev->vce.num_rings; i++) {
 443                 ring = &adev->vce.ring[i];
 444                 sprintf(ring->name, "vce%d", i);
 445                 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
 446                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
 447                 if (r)
 448                         return r;
 449         }
 450
 451         r = amdgpu_vce_entity_init(adev);
 452
 453         return r;
 454 }
 455
 456 static int vce_v3_0_sw_fini(void *handle)
 457 {
 458         int r;
 459         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 460
 461         r = amdgpu_vce_suspend(adev);
 462         if (r)
 463                 return r;
 464
 465         return amdgpu_vce_sw_fini(adev);
 466 }
 467
 468 static int vce_v3_0_hw_init(void *handle)
 469 {
 470         int r, i;
 471         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 472
 473         vce_v3_0_override_vce_clock_gating(adev, true);
 474
 475         amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
 476
 477         for (i = 0; i < adev->vce.num_rings; i++) {
 478                 r = amdgpu_ring_test_helper(&adev->vce.ring[i]);
 479                 if (r)
 480                         return r;
 481         }
 482
 483         DRM_INFO("VCE initialized successfully.\n");
 484
 485         return 0;
 486 }
 487
 488 static int vce_v3_0_hw_fini(void *handle)
 489 {
 490         int r;
 491         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 492
 493         /*
 494          * Proper cleanups before halting the HW engine:
 495          *   - cancel the delayed idle work
 496          *   - enable powergating
 497          *   - enable clockgating
 498          *   - disable dpm
 499          *
 500          * TODO: to align with the VCN implementation, move the
 501          * jobs for clockgating/powergating/dpm setting to
 502          * ->set_powergating_state().
 503          */
 504         cancel_delayed_work_sync(&adev->vce.idle_work);
 505
 506         if (adev->pm.dpm_enabled) {
 507                 amdgpu_dpm_enable_vce(adev, false);
 508         } else {
 509                 amdgpu_asic_set_vce_clocks(adev, 0, 0);
 510                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 511                                                        AMD_PG_STATE_GATE);
 512                 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 513                                                        AMD_CG_STATE_GATE);
 514         }
 515
 516         r = vce_v3_0_wait_for_idle(handle);
 517         if (r)
 518                 return r;
 519
 520         vce_v3_0_stop(adev);
 521         return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
 522 }
 523
 524 static int vce_v3_0_suspend(void *handle)
 525 {
 526         int r;
 527         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 528
 529         r = vce_v3_0_hw_fini(adev);
 530         if (r)
 531                 return r;
 532
 533         return amdgpu_vce_suspend(adev);
 534 }
 535
 536 static int vce_v3_0_resume(void *handle)
 537 {
 538         int r;
 539         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 540
 541         r = amdgpu_vce_resume(adev);
 542         if (r)
 543                 return r;
 544
 545         return vce_v3_0_hw_init(adev);
 546 }
 547
 548 static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
 549 {
 550         uint32_t offset, size;
 551
 552         WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
 553         WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
 554         WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
 555         WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);
 556
 557         WREG32(mmVCE_LMI_CTRL, 0x00398000);
 558         WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
 559         WREG32(mmVCE_LMI_SWAP_CNTL, 0);
 560         WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
 561         WREG32(mmVCE_LMI_VM_CTRL, 0);
 562         WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000);
 563
 564         if (adev->asic_type >= CHIP_STONEY) {
 565                 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
 566                 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
 567                 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
 568         } else
 569                 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
 570         offset = AMDGPU_VCE_FIRMWARE_OFFSET;
 571         size = VCE_V3_0_FW_SIZE;
 572         WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
 573         WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
 574
 575         if (idx == 0) {
 576                 offset += size;
 577                 size = VCE_V3_0_STACK_SIZE;
 578                 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
 579                 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
 580                 offset += size;
 581                 size = VCE_V3_0_DATA_SIZE;
 582                 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
 583                 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
 584         } else {
 585                 offset += size + VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE;
 586                 size = VCE_V3_0_STACK_SIZE;
 587                 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);
 588                 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
 589                 offset += size;
 590                 size = VCE_V3_0_DATA_SIZE;
 591                 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);
 592                 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
 593         }
 594
 595         WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
 596         WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
 597 }
 598
 599 static bool vce_v3_0_is_idle(void *handle)
 600 {
 601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 602         u32 mask = 0;
 603
 604         mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
 605         mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;
 606
 607         return !(RREG32(mmSRBM_STATUS2) & mask);
 608 }
 609
 610 static int vce_v3_0_wait_for_idle(void *handle)
 611 {
 612         unsigned i;
 613         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 614
 615         for (i = 0; i < adev->usec_timeout; i++)
 616                 if (vce_v3_0_is_idle(handle))
 617                         return 0;
 618
 619         return -ETIMEDOUT;
 620 }
 621
 622 #define  VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK  0x00000008L   /* AUTO_BUSY */
 623 #define  VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK   0x00000010L   /* RB0_BUSY */
 624 #define  VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK   0x00000020L   /* RB1_BUSY */
 625 #define  AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \
 626                                       VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK)
 627
 628 static bool vce_v3_0_check_soft_reset(void *handle)
 629 {
 630         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 631         u32 srbm_soft_reset = 0;
 632
 633         /* According to VCE team , we should use VCE_STATUS instead
 634          * SRBM_STATUS.VCE_BUSY bit for busy status checking.
 635          * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE
 636          * instance's registers are accessed
 637          * (0 for 1st instance, 10 for 2nd instance).
 638          *
 639          *VCE_STATUS
 640          *|UENC|ACPI|AUTO ACTIVE|RB1 |RB0 |RB2 |          |FW_LOADED|JOB |
 641          *|----+----+-----------+----+----+----+----------+---------+----|
 642          *|bit8|bit7|    bit6   |bit5|bit4|bit3|   bit2   |  bit1   |bit0|
 643          *
 644          * VCE team suggest use bit 3--bit 6 for busy status check
 645          */
 646         mutex_lock(&adev->grbm_idx_mutex);
 647         WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
 648         if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
 649                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
 650                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
 651         }
 652         WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
 653         if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
 654                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
 655                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
 656         }
 657         WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
 658         mutex_unlock(&adev->grbm_idx_mutex);
 659
 660         if (srbm_soft_reset) {
 661                 adev->vce.srbm_soft_reset = srbm_soft_reset;
 662                 return true;
 663         } else {
 664                 adev->vce.srbm_soft_reset = 0;
 665                 return false;
 666         }
 667 }
 668
 669 static int vce_v3_0_soft_reset(void *handle)
 670 {
 671         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 672         u32 srbm_soft_reset;
 673
 674         if (!adev->vce.srbm_soft_reset)
 675                 return 0;
 676         srbm_soft_reset = adev->vce.srbm_soft_reset;
 677
 678         if (srbm_soft_reset) {
 679                 u32 tmp;
 680
 681                 tmp = RREG32(mmSRBM_SOFT_RESET);
 682                 tmp |= srbm_soft_reset;
 683                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 684                 WREG32(mmSRBM_SOFT_RESET, tmp);
 685                 tmp = RREG32(mmSRBM_SOFT_RESET);
 686
 687                 udelay(50);
 688
 689                 tmp &= ~srbm_soft_reset;
 690                 WREG32(mmSRBM_SOFT_RESET, tmp);
 691                 tmp = RREG32(mmSRBM_SOFT_RESET);
 692
 693                 /* Wait a little for things to settle down */
 694                 udelay(50);
 695         }
 696
 697         return 0;
 698 }
 699
 700 static int vce_v3_0_pre_soft_reset(void *handle)
 701 {
 702         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 703
 704         if (!adev->vce.srbm_soft_reset)
 705                 return 0;
 706
 707         mdelay(5);
 708
 709         return vce_v3_0_suspend(adev);
 710 }
 711
 712
 713 static int vce_v3_0_post_soft_reset(void *handle)
 714 {
 715         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 716
 717         if (!adev->vce.srbm_soft_reset)
 718                 return 0;
 719
 720         mdelay(5);
 721
 722         return vce_v3_0_resume(adev);
 723 }
 724
 725 static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
 726                                         struct amdgpu_irq_src *source,
 727                                         unsigned type,
 728                                         enum amdgpu_interrupt_state state)
 729 {
 730         uint32_t val = 0;
 731
 732         if (state == AMDGPU_IRQ_STATE_ENABLE)
 733                 val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
 734
 735         WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
 736         return 0;
 737 }
 738
 739 static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
 740                                       struct amdgpu_irq_src *source,
 741                                       struct amdgpu_iv_entry *entry)
 742 {
 743         DRM_DEBUG("IH: VCE\n");
 744
 745         WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1);
 746
 747         switch (entry->src_data[0]) {
 748         case 0:
 749         case 1:
 750         case 2:
 751                 amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
 752                 break;
 753         default:
 754                 DRM_ERROR("Unhandled interrupt: %d %d\n",
 755                           entry->src_id, entry->src_data[0]);
 756                 break;
 757         }
 758
 759         return 0;
 760 }
 761
 762 static int vce_v3_0_set_clockgating_state(void *handle,
 763                                           enum amd_clockgating_state state)
 764 {
 765         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 766         bool enable = (state == AMD_CG_STATE_GATE);
 767         int i;
 768
 769         if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
 770                 return 0;
 771
 772         mutex_lock(&adev->grbm_idx_mutex);
 773         for (i = 0; i < 2; i++) {
 774                 /* Program VCE Instance 0 or 1 if not harvested */
 775                 if (adev->vce.harvest_config & (1 << i))
 776                         continue;
 777
 778                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));
 779
 780                 if (!enable) {
 781                         /* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */
 782                         uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);
 783                         data &= ~(0xf | 0xff0);
 784                         data |= ((0x0 << 0) | (0x04 << 4));
 785                         WREG32(mmVCE_CLOCK_GATING_A, data);
 786
 787                         /* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay */
 788                         data = RREG32(mmVCE_UENC_CLOCK_GATING);
 789                         data &= ~(0xf | 0xff0);
 790                         data |= ((0x0 << 0) | (0x04 << 4));
 791                         WREG32(mmVCE_UENC_CLOCK_GATING, data);
 792                 }
 793
 794                 vce_v3_0_set_vce_sw_clock_gating(adev, enable);
 795         }
 796
 797         WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
 798         mutex_unlock(&adev->grbm_idx_mutex);
 799
 800         return 0;
 801 }
 802
 803 static int vce_v3_0_set_powergating_state(void *handle,
 804                                           enum amd_powergating_state state)
 805 {
 806         /* This doesn't actually powergate the VCE block.
 807          * That's done in the dpm code via the SMC.  This
 808          * just re-inits the block as necessary.  The actual
 809          * gating still happens in the dpm code.  We should
 810          * revisit this when there is a cleaner line between
 811          * the smc and the hw blocks
 812          */
 813         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 814         int ret = 0;
 815
 816         if (state == AMD_PG_STATE_GATE) {
 817                 ret = vce_v3_0_stop(adev);
 818                 if (ret)
 819                         goto out;
 820         } else {
 821                 ret = vce_v3_0_start(adev);
 822                 if (ret)
 823                         goto out;
 824         }
 825
 826 out:
 827         return ret;
 828 }
 829
 830 static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags)
 831 {
 832         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 833         int data;
 834
 835         mutex_lock(&adev->pm.mutex);
 836
 837         if (adev->flags & AMD_IS_APU)
 838                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
 839         else
 840                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
 841
 842         if (data & CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) {
 843                 DRM_INFO("Cannot get clockgating state when VCE is powergated.\n");
 844                 goto out;
 845         }
 846
 847         WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
 848
 849         /* AMD_CG_SUPPORT_VCE_MGCG */
 850         data = RREG32(mmVCE_CLOCK_GATING_A);
 851         if (data & (0x04 << 4))
 852                 *flags |= AMD_CG_SUPPORT_VCE_MGCG;
 853
 854 out:
 855         mutex_unlock(&adev->pm.mutex);
 856 }
 857
 858 static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 859                                   struct amdgpu_job *job,
 860                                   struct amdgpu_ib *ib,
 861                                   uint32_t flags)
 862 {
 863         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 864
 865         amdgpu_ring_write(ring, VCE_CMD_IB_VM);
 866         amdgpu_ring_write(ring, vmid);
 867         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 868         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 869         amdgpu_ring_write(ring, ib->length_dw);
 870 }
 871
 872 static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring,
 873                                    unsigned int vmid, uint64_t pd_addr)
 874 {
 875         amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB);
 876         amdgpu_ring_write(ring, vmid);
 877         amdgpu_ring_write(ring, pd_addr >> 12);
 878
 879         amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB);
 880         amdgpu_ring_write(ring, vmid);
 881         amdgpu_ring_write(ring, VCE_CMD_END);
 882 }
 883
 884 static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring)
 885 {
 886         uint32_t seq = ring->fence_drv.sync_seq;
 887         uint64_t addr = ring->fence_drv.gpu_addr;
 888
 889         amdgpu_ring_write(ring, VCE_CMD_WAIT_GE);
 890         amdgpu_ring_write(ring, lower_32_bits(addr));
 891         amdgpu_ring_write(ring, upper_32_bits(addr));
 892         amdgpu_ring_write(ring, seq);
 893 }
 894
 895 static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
 896         .name = "vce_v3_0",
 897         .early_init = vce_v3_0_early_init,
 898         .late_init = NULL,
 899         .sw_init = vce_v3_0_sw_init,
 900         .sw_fini = vce_v3_0_sw_fini,
 901         .hw_init = vce_v3_0_hw_init,
 902         .hw_fini = vce_v3_0_hw_fini,
 903         .suspend = vce_v3_0_suspend,
 904         .resume = vce_v3_0_resume,
 905         .is_idle = vce_v3_0_is_idle,
 906         .wait_for_idle = vce_v3_0_wait_for_idle,
 907         .check_soft_reset = vce_v3_0_check_soft_reset,
 908         .pre_soft_reset = vce_v3_0_pre_soft_reset,
 909         .soft_reset = vce_v3_0_soft_reset,
 910         .post_soft_reset = vce_v3_0_post_soft_reset,
 911         .set_clockgating_state = vce_v3_0_set_clockgating_state,
 912         .set_powergating_state = vce_v3_0_set_powergating_state,
 913         .get_clockgating_state = vce_v3_0_get_clockgating_state,
 914 };
 915
 916 static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
 917         .type = AMDGPU_RING_TYPE_VCE,
 918         .align_mask = 0xf,
 919         .nop = VCE_CMD_NO_OP,
 920         .support_64bit_ptrs = false,
 921         .no_user_fence = true,
 922         .get_rptr = vce_v3_0_ring_get_rptr,
 923         .get_wptr = vce_v3_0_ring_get_wptr,
 924         .set_wptr = vce_v3_0_ring_set_wptr,
 925         .parse_cs = amdgpu_vce_ring_parse_cs,
 926         .emit_frame_size =
 927                 4 + /* vce_v3_0_emit_pipeline_sync */
 928                 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */
 929         .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */
 930         .emit_ib = amdgpu_vce_ring_emit_ib,
 931         .emit_fence = amdgpu_vce_ring_emit_fence,
 932         .test_ring = amdgpu_vce_ring_test_ring,
 933         .test_ib = amdgpu_vce_ring_test_ib,
 934         .insert_nop = amdgpu_ring_insert_nop,
 935         .pad_ib = amdgpu_ring_generic_pad_ib,
 936         .begin_use = amdgpu_vce_ring_begin_use,
 937         .end_use = amdgpu_vce_ring_end_use,
 938 };
 939
 940 static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {
 941         .type = AMDGPU_RING_TYPE_VCE,
 942         .align_mask = 0xf,
 943         .nop = VCE_CMD_NO_OP,
 944         .support_64bit_ptrs = false,
 945         .no_user_fence = true,
 946         .get_rptr = vce_v3_0_ring_get_rptr,
 947         .get_wptr = vce_v3_0_ring_get_wptr,
 948         .set_wptr = vce_v3_0_ring_set_wptr,
 949         .parse_cs = amdgpu_vce_ring_parse_cs_vm,
 950         .emit_frame_size =
 951                 6 + /* vce_v3_0_emit_vm_flush */
 952                 4 + /* vce_v3_0_emit_pipeline_sync */
 953                 6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */
 954         .emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */
 955         .emit_ib = vce_v3_0_ring_emit_ib,
 956         .emit_vm_flush = vce_v3_0_emit_vm_flush,
 957         .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync,
 958         .emit_fence = amdgpu_vce_ring_emit_fence,
 959         .test_ring = amdgpu_vce_ring_test_ring,
 960         .test_ib = amdgpu_vce_ring_test_ib,
 961         .insert_nop = amdgpu_ring_insert_nop,
 962         .pad_ib = amdgpu_ring_generic_pad_ib,
 963         .begin_use = amdgpu_vce_ring_begin_use,
 964         .end_use = amdgpu_vce_ring_end_use,
 965 };
 966
 967 static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
 968 {
 969         int i;
 970
 971         if (adev->asic_type >= CHIP_STONEY) {
 972                 for (i = 0; i < adev->vce.num_rings; i++) {
 973                         adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs;
 974                         adev->vce.ring[i].me = i;
 975                 }
 976                 DRM_INFO("VCE enabled in VM mode\n");
 977         } else {
 978                 for (i = 0; i < adev->vce.num_rings; i++) {
 979                         adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs;
 980                         adev->vce.ring[i].me = i;
 981                 }
 982                 DRM_INFO("VCE enabled in physical mode\n");
 983         }
 984 }
 985
 986 static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = {
 987         .set = vce_v3_0_set_interrupt_state,
 988         .process = vce_v3_0_process_interrupt,
 989 };
 990
 991 static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev)
 992 {
 993         adev->vce.irq.num_types = 1;
 994         adev->vce.irq.funcs = &vce_v3_0_irq_funcs;
 995 };
 996
 997 const struct amdgpu_ip_block_version vce_v3_0_ip_block =
 998 {
 999         .type = AMD_IP_BLOCK_TYPE_VCE,
1000         .major = 3,
1001         .minor = 0,
1002         .rev = 0,
1003         .funcs = &vce_v3_0_ip_funcs,
1004 };
1005
1006 const struct amdgpu_ip_block_version vce_v3_1_ip_block =
1007 {
1008         .type = AMD_IP_BLOCK_TYPE_VCE,
1009         .major = 3,
1010         .minor = 1,
1011         .rev = 0,
1012         .funcs = &vce_v3_0_ip_funcs,
1013 };
1014
1015 const struct amdgpu_ip_block_version vce_v3_4_ip_block =
1016 {
1017         .type = AMD_IP_BLOCK_TYPE_VCE,
1018         .major = 3,
1019         .minor = 4,
1020         .rev = 0,
1021         .funcs = &vce_v3_0_ip_funcs,
1022 };